KR20020034464A - Polycrystalline Silicon Thin Film Transistor and Manufacturing process the same - Google Patents
Polycrystalline Silicon Thin Film Transistor and Manufacturing process the same Download PDFInfo
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- KR20020034464A KR20020034464A KR1020000064780A KR20000064780A KR20020034464A KR 20020034464 A KR20020034464 A KR 20020034464A KR 1020000064780 A KR1020000064780 A KR 1020000064780A KR 20000064780 A KR20000064780 A KR 20000064780A KR 20020034464 A KR20020034464 A KR 20020034464A
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- 239000010409 thin film Substances 0.000 title claims abstract description 48
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 34
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 238000000034 method Methods 0.000 claims abstract description 39
- 239000011229 interlayer Substances 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 239000011521 glass Substances 0.000 claims abstract description 7
- 239000010408 film Substances 0.000 claims description 39
- 238000000151 deposition Methods 0.000 claims description 17
- 238000005530 etching Methods 0.000 claims description 16
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 14
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 150000002500 ions Chemical class 0.000 claims description 4
- 238000005224 laser annealing Methods 0.000 claims description 4
- 230000003213 activating effect Effects 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims description 2
- 230000001681 protective effect Effects 0.000 claims description 2
- 239000007943 implant Substances 0.000 claims 1
- 239000000126 substance Substances 0.000 claims 1
- 238000007740 vapor deposition Methods 0.000 claims 1
- 239000012808 vapor phase Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 abstract description 14
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 abstract description 10
- 238000005468 ion implantation Methods 0.000 abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 3
- 238000009413 insulation Methods 0.000 abstract 1
- 230000005684 electric field Effects 0.000 description 13
- 238000001039 wet etching Methods 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000006356 dehydrogenation reaction Methods 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- 229910017855 NH 4 F Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- -1 Phosphorous ions Chemical class 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical group [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000000116 mitigating effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 238000003949 trap density measurement Methods 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78609—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing leakage current
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78663—Amorphous silicon transistors
- H01L29/78666—Amorphous silicon transistors with normal-type structure, e.g. with top gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
- H01L21/02686—Pulsed laser beam
Abstract
Description
본 발명은 다결정 실리콘 박막 트랜지스터 및 그 제조방법에 관한 것으로써, 특히 다결정 실리콘 박막 트랜지스터의 누설전류를 억제하기 위해 게이트 절연막의 가장자리에 에어-캐비티(air-cavity)를 형성하여 드레인 접합에 유도되는 수직 전계를 완화시키는 구조를 갖는 다결정 실리콘 박막 트랜지스터 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a polycrystalline silicon thin film transistor and a method of manufacturing the same. In particular, in order to suppress leakage current of a polycrystalline silicon thin film transistor, an air-cavity is formed at the edge of the gate insulating film to induce a drain junction. The present invention relates to a polycrystalline silicon thin film transistor having a structure that relaxes an electric field and a method of manufacturing the same.
저온 다결정 실리콘 박막 트랜지스터(Polycrystalline Silicon Thin Film Transistor;poly-Si TFT)를 이용한 능동 행렬 구동 액정 디스플레이(Active Matrix Liquid Crystal Display ; AMLCD)는 현재 노트북 및 개인용 컴퓨터의 모니터에 응용되고 있는 비정질 실리콘 박막 트랜지스터(Amorphous silicon Thin Film Transistor; a-Si TFT)에 비해 구동능력과 집적도가 우수하여 고정세(High Resolution) 액정 디스플레이에 채용될 것으로 기대되고 있다.Active Matrix Liquid Crystal Display (AMLCD) using low-temperature polycrystalline silicon thin film transistor (poly-Si TFT) is an amorphous silicon thin film transistor currently used in monitors of notebooks and personal computers. It is expected to be adopted in high resolution liquid crystal displays because of its excellent driving ability and integration degree compared to Amorphous silicon Thin Film Transistor (a-Si TFT).
그러나 다결정 실리콘 박막 트랜지스터는 누설전류가 상대적으로 크고 구동시에 다결정 실리콘 박막의 결정립(grain) 경계(boundary)에서의 트랩밀도 증가로 인해 소자의 열화(degradation)가 심각하게 일어나는 것으로 알려져 있다.However, polycrystalline silicon thin film transistors are known to have a relatively high leakage current and serious degradation of devices due to an increase in trap density at grain boundaries of the polycrystalline silicon thin film.
상기한 누설전류와 구동 시에 발생하는 소자의 열화는 드레인 접합에 유도되는 수직 및 수평 전계를 완화함으로써 억제될 수 있는데, 최근까지는 수평 전계 완화를 위해 저농도 도핑 드레인(Lightly Doped Drain, LDD)과 같은 오프셋( offset) 구조가 제안되었고 저농도 도핑 드레인은 최근 널리 사용되고 있는 구조이다. (IEEE Electron Device Letters, Vol. EDL8, No.9, September 1987) 수직 전계를감소시키기 위해서 제안된 구조로는 T-게이트 구조의 소자가 제안된 바 있으며 이 경우에는 게이트 산화막의 가장자리가 두껍게 형성되어 소스/드레인 주변에 유도되는 수직전계가 완화될 수 있다.The leakage current and deterioration of the device generated during driving can be suppressed by mitigating the vertical and horizontal electric fields induced in the drain junction. Offset structures have been proposed and low concentration doped drains have been widely used in recent years. (IEEE Electron Device Letters, Vol. EDL8, No.9, September 1987) As a proposed structure for reducing the vertical electric field, a device having a T-gate structure has been proposed. In this case, the edge of the gate oxide film is formed thick. The vertical field induced around the source / drain can be relaxed.
그러나, 상기한 기존의 LDD나 오프셋 구조는 추가의 마스크 공정이나 이온 주입 공정이 요구되며 제작 후 소자의 구동전류가 LDD나 오프셋 구조에 의해 감소되는 단점이 있다. 또한 T-게이트 구조도 산화(Oxidation)와 같은 고온 공정을 이용하거나 추가의 마스크 공정이 요구되는 문제점이 있다.However, the conventional LDD or offset structure requires an additional mask process or an ion implantation process, and the driving current of the device after manufacturing is reduced by the LDD or offset structure. In addition, the T-gate structure also has a problem of using a high temperature process such as oxidation or an additional mask process is required.
본 발명은 상기한 종래 기술의 문제점을 해결하기 위해 제안된 것으로써, 본 발명의 목적은 드레인 접합부의 강한 수직 전계로 인해 발생하는 누설전류를 감소시키고 소자의 신뢰도를 향상시키기 위하여 에어-캐비티를 게이트 절연막의 일부로 사용함으로써, 드레인 접합에 유도되는 수직 전계를 완화시키고 종래의 소자와 동일한 구동전류를 나타내며 전계효과 이동도를 증가시킬 수 있는 다결정 실리콘 박막 트랜지스터 및 그 제조방법을 제공하는 것이다.The present invention has been proposed to solve the above-mentioned problems of the prior art, and an object of the present invention is to gate the air-cavity in order to reduce the leakage current generated by the strong vertical electric field of the drain junction and to improve the reliability of the device. The present invention provides a polycrystalline silicon thin film transistor capable of alleviating the vertical electric field induced by the drain junction, exhibiting the same drive current as a conventional device, and increasing field effect mobility, and a method of manufacturing the same.
도 1은 본 발명에 의한 다결정 실리콘 박막 트랜지스터 구조의 단면도.1 is a cross-sectional view of a polycrystalline silicon thin film transistor structure according to the present invention.
도 2는 본 발명 및 종래의 다결정 실리콘 박막 트랜지스터의 드레인 접합에 유도되는 수직전계의 분포를 모의실험한 결과를 나타내는 그래프.2 is a graph showing the results of simulation of the distribution of the vertical electric field induced in the drain junction of the present invention and the conventional polycrystalline silicon thin film transistor.
도 3은 게이트 산화막의 습식 식각후의 구조를 전자주사현미경을 이용하여 관찰한 사진.3 is a photograph observing the structure after the wet etching of the gate oxide film using an electron scanning microscope.
도 4는 상압화학기상증착을 이용하여 층간절연막을 형성한 후의 구조를 전자주사현미경을 이용하여 관찰한 사진.Figure 4 is a photograph observing the structure after the formation of the interlayer insulating film using atmospheric pressure chemical vapor deposition using an electron scanning microscope.
도 5는 본 발명 및 종래의 다결정 실리콘 박막 트랜지스터의 드레인 전류-게이트 전압 관계를 나타내는 그래프.5 is a graph showing the drain current-gate voltage relationship of the present invention and the conventional polycrystalline silicon thin film transistor.
도 6은 본 발명 및 종래의 다결정 실리콘 박막 트랜지스터의 스트레스 시간에 따른 문턱전압이동을 나타낸 그래프.Figure 6 is a graph showing the threshold voltage shift with stress time of the present invention and the conventional polycrystalline silicon thin film transistor.
도 7은 전기적 스트레스 전후에 측정한 본 발명 및 종래의 다결정 실리콘 박막 트랜지스터의 드레인 전류를 나타낸 그래프.7 is a graph showing the drain current of the present invention and the conventional polycrystalline silicon thin film transistor measured before and after the electrical stress.
상기한 목적을 달성하기 위해 본 발명은 산화막이 증착된 유리기판 위에 형성되는 다결정 실리콘과, 상기의 다결정 실리콘 박막 위에 형성되는 실리콘 산화막(SiO2)의 가장자리에 에어-캐비티가 존재하는 게이트 절연막과, 이온주입으로 형성되는 게이트, 소스, 드레인을 포함하여 구성되는 것을 특징으로 하는 다결정실리콘 박막 트랜지스터를 제공한다.In order to achieve the above object, the present invention provides a polycrystalline silicon formed on a glass substrate on which an oxide film is deposited, a gate insulating film having an air-cavity at the edge of a silicon oxide film (SiO 2 ) formed on the polycrystalline silicon thin film, Provided is a polysilicon thin film transistor comprising a gate, a source, and a drain formed by ion implantation.
또한, 본 발명은 (1) 산화막이 증착된 유리기판 위에 비정질 실리콘을 증착하는 단계와, (2) 상기의 비정질 실리콘 박막을 엑시머 레이저 어닐링하여 결정화한 후 다결정 실리콘 박막을 패터닝하는 단계와, (3) 상기의 다결정 실리콘 박막위에 게이트 산화막을 증착하고 게이트 전극으로 사용될 비정질 실리콘 박막을 증착하는 단계와, (4) 상기의 비정질 실리콘 박막과 게이트 산화막을 연속적으로 식각한 다음 인이온을 주입한 후 레이저 어닐링하여 주입된 이온을 활성화하여 소오스와 드레인을 형성하는 단계와, (5) 상기의 이온주입이 완료된 기판의 게이트 산화막을 습식방법 또는 건식방법으로 식각하는 단계와, (6) 상기의 게이트 산화막을 식각한 후 상압화학기상증착방법으로 층간절연막을 증착하여 에어 캐비티를 형성하는 단계와, (7) 상기의 층간절연막을 증착한 후 컨택홀을 형성한 다음 금속박막을 증착하는 단계와, (8) 상기의 증착된 금속박막을 사진공정 및 식각 공정을 이용하여 식각하여 금속배선을 형성한 후 보호막을 증착하는 단계로 이루어짐을 특징으로 하는 다결정 실리콘 박막 트랜지스터의 제조방법을 제공한다.In addition, the present invention (1) depositing amorphous silicon on the glass substrate on which the oxide film is deposited, (2) crystallizing the amorphous silicon thin film by excimer laser annealing and patterning the polycrystalline silicon thin film, (3 A) depositing a gate oxide film on the polycrystalline silicon thin film and depositing an amorphous silicon thin film to be used as a gate electrode; Activating the implanted ions to form a source and a drain, (5) etching the gate oxide film of the substrate where the ion implantation is completed by a wet method or a dry method, and (6) etching the gate oxide film. And then forming an air cavity by depositing an interlayer insulating film by an atmospheric pressure chemical vapor deposition method, and (7) the above interlayer. Depositing an insulating film, forming a contact hole, and then depositing a metal thin film; and (8) forming the metal wiring by etching the deposited metal thin film using a photo process and an etching process, and then depositing a protective film. Provided is a method of manufacturing a polycrystalline silicon thin film transistor, characterized in that consisting of.
이하, 첨부한 도면을 참조하여 본 발명에 따른 바람직한 실시예를 상세하게 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1에 본 발명에 의한 다결정 실리콘 박막 트랜지스터 구조의 단면도를 나타내었다. 도 1은 에어-캐비티를 게이트 전극의 가장자리 아래에 형성하여 드레인 접합에 유도되는 수직 전계를 완화시키는 구조를 갖는다. 드레인 접합 위에 에어 캐비티가 형성될 경우 드레인 접합에 유도되는 수직 전계는 에어-캐비티가 없는 경우에 비해 이론적으로 1/3.9 정도의 값을 갖는다. 이는 다음과 같은 [수학식 1] 로 표현이 가능하다. 실리콘과 공기의 표면에 자유전하가 없다고 가정할 때 전속밀도는1 is a cross-sectional view of a polycrystalline silicon thin film transistor structure according to the present invention. 1 has a structure to form an air-cavity under the edge of the gate electrode to mitigate the vertical electric field induced in the drain junction. When an air cavity is formed over the drain junction, the vertical electric field induced in the drain junction is theoretically about 1 / 3.9 as compared with the absence of the air-cavity. This can be expressed as the following [Equation 1]. Assuming no free charge on the surface of silicon and air, the flux density
이다. 실리콘 산화막의 유전상수(dielectric constant)는 3.9임에 비해 공기의 유전상수는 1이다. 따라서 완화된 수직 전계는 공기의 유전상수가 산화막의 유전상수에 비해 낮은 값을 가지기 때문이다. 그러나 실제 소자의 구조에서는 에어-캐비티 주변의 게이트 전극에 의한 주변 전계(fringing field)로 인해 에어-캐비티가 없는 구조에서의 수직전계에 비해 1/3.9배만큼 감소되지는 않는다. 이는 2-D 시뮬레이터인 ATLAS(SILVACO)에 의해 검증된 결과로서 도 2에 나타내었다. 도 2는 에어-캐비티의 길이가 드레인 접합으로부터 0.5㎛의 길이를 가지고 형성되었을 경우에 드레인 접합에 유도되는 수직 전계를 나타난 것이다. 에어-캐비티가 없는 종래의 구조에 비해 수직 전계가 완화되었음이 모의실험(simulation)에 의해 확인되었으며 모의실험 결과 본 발명에 의한 구조의 수직전계는 약 20%정도 감소한 값을 보이고 있다.to be. The dielectric constant of the silicon oxide film is 3.9, whereas the dielectric constant of air is 1. Therefore, the relaxed vertical electric field is because the dielectric constant of air has a lower value than that of the oxide film. However, in the actual device structure, the fringing field by the gate electrode around the air cavity does not reduce by 1 / 3.9 times compared to the vertical field in the structure without the air cavity. This is shown in FIG. 2 as a result verified by ATLAS (SILVACO) which is a 2-D simulator. Figure 2 shows the vertical electric field induced in the drain junction when the length of the air-cavity is formed with a length of 0.5 mu m from the drain junction. The simulation confirmed that the vertical electric field was relaxed compared to the conventional structure without the air-cavity, and the simulation shows that the vertical electric field of the structure according to the present invention is reduced by about 20%.
게이트 산화막의 가장자리에 에어 캐비티를 형성하는 과정에 대해서 살펴보면 다음과 같다.The process of forming the air cavity at the edge of the gate oxide film is as follows.
에어 캐비티는 게이트 산화막의 등방성 식각(isotropic etch)을 이용하여 제작되며 식각 방법은 습식 식각과 건식 식각이 모두 가능하다. 상기의 방법을 이용하여 게이트 산화막의 가장자리 일부만을 제거하고 후속 공정으로는 상압화학기상증착(Atmospheric pressure chemical vapor deposition, APCVD)방법을 이용하여 캐비티가 산화막으로 채워지는 것을 방지함으로써 에어-캐비티를 형성할 수 있다. 상압화학기상증착은 공정이 상압에서 이루어지므로 반응 기체들의 평균자유행로(mean free path)가 짧아져 게이트 전극의 아래 부분에 반응 기체의 유입이 억제되어 산화막의 형성이 억제될 수 있다.The air cavity is manufactured using an isotropic etch of the gate oxide layer, and the etching method may be both wet etching and dry etching. The air cavity can be formed by removing only a portion of the edge of the gate oxide film using the above method and preventing the cavity from filling with the oxide film by using an Atmospheric Pressure Chemical Vapor Deposition (APCVD) method. Can be. Atmospheric pressure chemical vapor deposition is the process is carried out at normal pressure, the mean free path of the reaction gases is shortened to inhibit the flow of the reaction gas to the lower portion of the gate electrode can be suppressed the formation of the oxide film.
도 3과 도 4는 게이트 산화막의 일부를 식각한 후 산화막을 증착하기 전과 후의 구조를 관찰한 것이다. 도 3은 게이트 산화막의 습식 식각후의 구조를 보여주는 것으로 게이트 산화막의 가장자리가 부분적으로 식각되어 있음을 확인할 수 있다. 도 4는 습식 식각 후 상압화학기상증착을 이용하여 층간절연막을 형성한 후의 구조를 보여주는 것으로 에어-캐비티가 형성되어 있음을 확인할 수 있다. 게이트 산화막의 습식 식각은 NH4F과 HF을 7 대 1의 비율로 섞은 산화막 식각액을 사용하였으며 습식 식각 시간이 3분일 때 식각된 산화막의 길이는 300nm이다.3 and 4 illustrate a structure before and after depositing an oxide layer after etching a part of the gate oxide layer. 3 shows the structure after the wet etching of the gate oxide layer, and it can be seen that the edge of the gate oxide layer is partially etched. Figure 4 shows the structure after the formation of the interlayer insulating film using atmospheric pressure chemical vapor deposition after wet etching, it can be seen that the air-cavity is formed. The wet etching of the gate oxide layer was performed using an oxide etchant containing NH 4 F and HF in a ratio of 7 to 1, and the length of the etched oxide layer was 300 nm when the wet etching time was 3 minutes.
본 발명에 따른 다결정 실리콘 박막트랜지스터의 제조방법을 실시예에 의거하여 상세히 설명하면 다음과 같은 바, 본 발명이 실시예에 한정되는 것은 아니다.Referring to the method of manufacturing a polycrystalline silicon thin film transistor according to the present invention in detail as follows, the present invention is not limited to the embodiment.
산화막이 증착된 유리 또는 수정(quartz) 웨이퍼에 비정질 실리콘 800Å을 플라즈마화학기상증착법(Plasma Enhanced Chemical Vapor Deposition, PECVD) 또는 저압화학기상증착법(Low pressure Chemical Vapor Deposition, LPCVD)을 이용하여증착한다. 플라즈마화학기상증착법을 이용한 경우에는 노(furnace)에서 450℃의 온도에서 3시간동안 탈수소를 시행한다. 저압화학기상증착법을 이용한 경우에는 박막 내에 수소의 함량이 극히 적으므로 탈수소를 시행할 필요가 없다.Amorphous silicon 800 Å is deposited on the glass or quartz wafer on which the oxide film is deposited using Plasma Enhanced Chemical Vapor Deposition (PECVD) or Low Pressure Chemical Vapor Deposition (LPCVD). In the case of plasma chemical vapor deposition, dehydrogenation is carried out in a furnace at a temperature of 450 ° C. for 3 hours. When the low pressure chemical vapor deposition method is used, the hydrogen content in the thin film is extremely low, so it is not necessary to perform dehydrogenation.
비정질 실리콘 박막을 재결정화하기 위해 XeCl (λ= 308nm) 엑시머 레이저 어닐링 공정을 하고 사진식각공정을 이용하여 다결정 실리콘 박막을 패터닝한다.In order to recrystallize the amorphous silicon thin film, an XeCl (λ = 308 nm) excimer laser annealing process is performed and the polycrystalline silicon thin film is patterned using a photolithography process.
게이트 산화막으로 사용될 TEOS (tetraethoxysilane) 산화막 1000Å을 증착하고 이어서 3000Å두께의 비정질 실리콘 박막을 증착한다. 플라즈마 화학기상증착(PECVD)으로 증착한 경우에는 노(furnace)에서 450℃의 온도에서 3시간동안 탈수소를 진행한다. 사진공정을 이용하여 게이트 전극모양의 패턴을 형성하고, 비정질 실리콘 박막과 TEOS 산화막을 연속적으로 식각한다.1000 μs of a TEOS (tetraethoxysilane) oxide film to be used as a gate oxide film is deposited and then an amorphous silicon thin film having a thickness of 3000 μs is deposited. In the case of deposition by plasma chemical vapor deposition (PECVD), dehydrogenation is performed for 3 hours at a temperature of 450 ° C. in a furnace. A gate electrode pattern is formed by using a photolithography process, and the amorphous silicon thin film and the TEOS oxide film are continuously etched.
소스/드레인을 형성하기 위해 인(Phosphorous) 이온의 주입을 시행하고 레이저 빔을 조사하여 주입된 이온을 활성화한다. 이온 주입의 공정 조건은 30keV, 5 × 1015#/cm2이다.Phosphorous ions are implanted to form the source / drain and the laser beam is irradiated to activate the implanted ions. The process conditions for ion implantation are 30 keV, 5 x 10 15 # / cm 2 .
에어 캐비티를 형성하기 위해 이온 주입이 완료된 박막 트랜지스터(TFT) 기판을 NH4F과 HF을 7 대 1의 비율로 섞은 산화막 식각액 (Buffered Oxide etchants, BOE)에 투입하여 게이트 산화막의 가장자리만을 부분적으로 식각해낸다. 식각 후 상압화학기상증착방법으로 층간절연막인 실리카(SiO2) 산화막을 증착하면 증착과정에서 도 4와 같은 에어 캐비티가 형성된다.In order to form an air cavity, a thin film transistor (TFT) substrate in which ion implantation is completed is partially injected into buffered oxide etchants (BOE) mixed with NH 4 F and HF in a ratio of 7 to 1 to partially etch only edges of the gate oxide layer. Do it. After etching, the silica (SiO 2 ) oxide film, which is an interlayer insulating film, is deposited by atmospheric pressure chemical vapor deposition (CVD) to form an air cavity as illustrated in FIG. 4.
산화막 형성 후 사진공정 및 산화막 식각 공정을 이용하여 외부 회로와의 연결을 위해 컨택홀(contact hole)을 형성한다. 알루미늄 금속박막을 증착한 후 사진공정 및 식각 공정을 이용하여 패턴하여 금속배선을 형성한 다음 소자 보호용 산화막을 증착하여 소자를 최종적으로 완성한다.After forming the oxide layer, a contact hole is formed to connect to an external circuit using a photolithography process and an oxide layer etching process. After the deposition of the aluminum metal thin film to form a metal wiring by using a photo process and an etching process, and then the oxide film for protecting the device is deposited to finally complete the device.
본 발명에서 이용된 공정의 최고온도는 플라즈마 화학기상증착을 이용할 경우, 450℃로서 유리 기판을 이용하는 TFT-LCD에 적용이 가능한 저온공정이며, 추가의 열공정이 요구되지 않는다.The maximum temperature of the process used in the present invention is a low temperature process that can be applied to a TFT-LCD using a glass substrate at 450 ° C. when plasma chemical vapor deposition is used, and no additional thermal process is required.
상기와 같이 제조된 다결정 실리콘 박막 트랜지스터의 전류-전압 전달곡선을 도 5에 나타내었으며 도 5로부터 에어 캐비티가 없는(Lcavity= 0㎛) 종래의 소자와 비교하여 누설전류가 감소되었음을 확인할 수 있다. 에어 캐비티의 길이가 증가할수록 누설전류는 더욱 감소하며 본 실험에서는 0.4㎛의 에어 캐비티가 형성되었을 때 가장 효과적으로 누설전류가 억제되었다.The current-voltage transfer curve of the polycrystalline silicon thin film transistor manufactured as described above is shown in FIG. 5, and it can be seen from FIG. 5 that the leakage current is reduced in comparison with a conventional device having no air cavity (L cavity = 0 μm). As the length of the air cavity increases, the leakage current decreases further. In this experiment, the leakage current was most effectively suppressed when the 0.4 μm air cavity was formed.
소자의 구동전류는 종래의 구조와 거의 동일하며 종래의 구조에 비해 전계효과 이동도가 향상된 결과를 보여준다. 도 5의 전류특성 곡선으로부터 추출한 전계효과 이동도는 종래의 소자가 23.5cm2/Vs이고 본 발명에 의한 소자가 31.9cm2/Vs이다. 이는 완화된 수직 전계로 인해 전하들이 에어 캐비티의 하부를 지날 때 전하와 실리콘/공기 계면과의 충돌회수가 감소하여 전하의 전도특성이 향상되기 때문이다.The driving current of the device is almost the same as that of the conventional structure, and the field effect mobility is improved compared to the conventional structure. Fig field effect mobility is extracted from the current characteristic curve of FIG. 5 is the device according to the present invention the conventional element 23.5cm 2 / Vs and 31.9cm 2 / Vs. This is because the relaxed vertical electric field reduces the number of collisions between the charge and the silicon / air interface as it passes through the bottom of the air cavity, thereby improving the conduction characteristics of the charge.
본 발명에 의한 다결정 실리콘 박막 트랜지스터 소자의 스트레스 특성을 도 6 및 도 7에 나타내었다.6 and 7 show stress characteristics of the polycrystalline silicon thin film transistor device according to the present invention.
도 6은 스트레스 시간에 따른 문턱전압이동을 나타낸 것으로서, 바이어스스트레스 조건이 VG=40V, VD=5V이고 스트레스 시간은 최대 90분으로 하였을 때의 측정 결과이다. 본 발명에 의한 소자(air-cavity TFT)의 문턱전압 이동은 90분이 지난 후에도 0.5V 이내로 측정되었으나 종래의 소자(Conventional TFT)에서는 1.4V이상의 문턱전압이동이 나타났다. 따라서 본 발명에 의한 소자의 문턱전압이동은 종래의 소자에 비해 현저히 억제되었다.Figure 6 shows the threshold voltage shift according to the stress time, the bias stress conditions are V G = 40V, V D = 5V and the stress time is the measurement results when the maximum 90 minutes. The threshold voltage shift of the device (air-cavity TFT) according to the present invention was measured within 0.5V even after 90 minutes, but the threshold voltage shift of 1.4V or more was observed in the conventional TFT. Therefore, the threshold voltage shift of the device according to the present invention is significantly suppressed compared to the conventional device.
도 7의 특성곡선은 전기적 스트레스 전후의 드레인 전류의 변화를 나타낸 것으로 스트레스 후에도 발명된 소자의 누설전류(VGS< 0V)는 종래의 소자(conv.:Lcavity= 0㎛) 에 비해 현저히 낮다. 또한 구동전류(VGS> 0)도 본 발명의 소자에서는 스트레스 후에 거의 변화가 없으나 종래의 소자는 현저히 낮은 전류가 흐름을 확인할 수 있다. 결과적으로 발명된 소자의 온-오프 전류비는 종래의 소자에 비해 향상되었음을 확인할 수 있다.The characteristic curve of FIG. 7 shows the change of the drain current before and after the electrical stress, and the leakage current (V GS <0 V) of the device invented after the stress is significantly lower than that of the conventional device (conv.:L cavity = 0 µm). In addition, the driving current (V GS > 0) is almost unchanged after the stress in the device of the present invention, but in the conventional device it can be seen that a significantly low current flow. As a result, it can be seen that the on-off current ratio of the invented device is improved compared to the conventional device.
상술한 바와 같이, 본 발명에 의한 에어캐비티를 게이트 산화막의 가장자리에 가지는 다결정 실리콘 박막 트랜지스터는 누설전류를 효과적으로 억제하고 전기적 스트레스 후의 소자의 신뢰도를 향상시켜 고품질의 액정 디스플레이를 구현할 수 있다. 또한 본 발명의 제조방법은 추가의 마스크 공정없이 등방성 식각공정과 상압화학기상증착(APCVD)을 이용한 층간절연막 형성공정으로 간단히 에어-캐비티를 형성할 수 있고 450℃이하의 저온 공정에서 제작이 가능하다는 장점이 있다.As described above, the polycrystalline silicon thin film transistor having the air cavity at the edge of the gate oxide film according to the present invention can effectively suppress the leakage current and improve the reliability of the device after the electrical stress to implement a high quality liquid crystal display. In addition, the manufacturing method of the present invention can form an air cavity simply by forming an interlayer insulating film using an isotropic etching process and atmospheric chemical vapor deposition (APCVD) without an additional mask process, and can be manufactured in a low temperature process below 450 ° C. There is an advantage.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20030091644A (en) * | 2002-05-23 | 2003-12-03 | 엘지.필립스 엘시디 주식회사 | poly silicon thin film transistor and fabrication method of the same |
| KR100479266B1 (en) * | 2002-11-26 | 2005-03-28 | 한국전자통신연구원 | Semiconductor device having T-gate electrode and method of manufacturing the same |
| KR100780855B1 (en) * | 2005-07-13 | 2007-11-30 | 세이코 엡슨 가부시키가이샤 | Semiconductor device and method for manufacturing the same |
| KR101051810B1 (en) * | 2004-12-30 | 2011-07-25 | 매그나칩 반도체 유한회사 | Cells of Nonvolatile Memory Devices and Manufacturing Method Thereof |
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| KR102300595B1 (en) | 2021-02-22 | 2021-09-10 | 주식회사 다인 | Dust collector for painting |
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| KR20030091644A (en) * | 2002-05-23 | 2003-12-03 | 엘지.필립스 엘시디 주식회사 | poly silicon thin film transistor and fabrication method of the same |
| KR100479266B1 (en) * | 2002-11-26 | 2005-03-28 | 한국전자통신연구원 | Semiconductor device having T-gate electrode and method of manufacturing the same |
| KR101051810B1 (en) * | 2004-12-30 | 2011-07-25 | 매그나칩 반도체 유한회사 | Cells of Nonvolatile Memory Devices and Manufacturing Method Thereof |
| KR100780855B1 (en) * | 2005-07-13 | 2007-11-30 | 세이코 엡슨 가부시키가이샤 | Semiconductor device and method for manufacturing the same |
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