JP3252997B2 - Thin film transistor and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor using a polycrystalline silicon thin film and a method of manufacturing the same, and more particularly to a thin film transistor suitably used as a switching element of a liquid crystal display and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, a thin film transistor (hereinafter, referred to as a TFT) using a semiconductor layer made of a polycrystalline silicon thin film has been developed.
Are used for a pixel switching element for switching pixels of a liquid crystal display device (hereinafter referred to as LCD) and a peripheral driving circuit. However, in this polycrystalline silicon TFT, since many trap levels are localized at the crystal grain boundaries of the polycrystalline silicon thin film, a large amount of leak current flows during off-time via these trap levels. There was a disadvantage. In particular, when a polycrystalline silicon TFT is used as a pixel switching element of a TFT-LCD, the above disadvantage is serious.

In order to overcome this drawback, conventionally, an offset gate structure or an LDD (Lightly) is conventionally used.
A method of relaxing the electric field concentration at the drain end by adopting a Doped Drain structure or the like has been proposed (Japanese Patent Publication No. 3-38755 or Japanese Patent Application Laid-Open No. 5-136418).
issue).

By the way, there are roughly the following two types of leakage current when a polycrystalline silicon TFT is turned off. The Vg-Id curve of the TFT shown in FIG.
As can be understood from the Vds-Id curve of the TFT shown in (b), when the gate voltage Vg and the drain voltage are low, the ohmic leakage current with respect to the source-drain voltage Vds and the gate voltage Vg and the drain voltage are high. In the case of voltage, it is a non-linear leak current with respect to the source-drain voltage Vds.

[0005] The above-mentioned non-linear leakage current can be reduced by providing an offset region between the channel region and the drain region. However, the ohmic leakage current cannot be reduced even by providing an offset region.
In addition, since the ohmic leakage current increases as the thickness of the intrinsic semiconductor layer increases, a method of reducing the ohmic leakage current by reducing the thickness of the intrinsic semiconductor layer can be considered.

For the above reasons, a TFT is formed by combining a method of reducing the thickness of an intrinsic semiconductor layer used as a channel region to about 20 nm to 30 nm and a method of forming an offset region having an offset length of 1 μm or more. That is being done.

[0007]

However, when the polycrystalline silicon thin film is formed at a low temperature, if the intrinsic semiconductor layer used as the channel region is formed thin, the film quality of the polycrystalline silicon film deteriorates. For this reason, although the ohmic leakage current can be reduced with respect to the source-drain voltage by making the intrinsic semiconductor layer thinner, the gate voltage and the drain voltage at which a non-linear leakage current appears are reduced. In order to prevent this, it is necessary to increase the offset length, and as a result, there is a problem that the on-current decreases.

SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art, and provides a thin film transistor capable of reducing a leak current at the time of off without lowering an on current, and a method of manufacturing the same. With the goal.

[0009]

According to the present invention, there is provided a thin film transistor in which a semiconductor layer comprising a polycrystalline silicon thin film, a gate insulating film and a gate electrode are formed on a substrate in this order from the substrate side. Has a source region and a drain region with a channel region interposed therebetween, and a high-resistance layer having an insulating function is formed on the substrate side of the source region and the drain region of the semiconductor layer, whereby the object is achieved. .

In the thin film transistor according to the present invention, the thickness of the channel region may be larger than the thickness of the source region and the drain region.

[0011]

In the thin film transistor according to the present invention, the high resistance layer may be formed of a polycrystalline silicon thin film into which nitrogen or carbon is mixed.

The method for manufacturing a thin film transistor according to the present invention comprises:
On a substrate, a semiconductor layer made of a polycrystalline silicon thin film, a gate insulating film, and a gate electrode are formed in this order from the substrate side, and the semiconductor layer has a source region and a drain region across a channel region. Forming a semiconductor layer, a gate insulating film, and a gate electrode on a substrate in this order, and injecting nitrogen or carbon into the semiconductor layer using the gate electrode as a mask to provide an insulating function in a portion of the semiconductor layer near the substrate. Forming a high-resistance layer having a source region and a drain region by implanting impurities into the semiconductor layer using the gate electrode as a mask and performing an activation process. Forming a region, whereby the object is achieved.

In the method of manufacturing a thin film transistor according to the present invention, when nitrogen or carbon is implanted into the semiconductor layer, nitrogen or carbon is implanted into a portion where the high-resistance layer is formed at 10 ^{21 at.}
ms / cm ³ or more, and nitrogen or carbon is added to the portion where the source region and the drain region are formed at 10 ²¹ atoms / cm ^3.
/ Cm ³ .

[0015]

In the method of manufacturing a thin film transistor according to the present invention, when an impurity is implanted into the semiconductor layer to form the source region and the drain region, an insulating film formed on a surface of the gate electrode in addition to the gate electrode May also be used as a mask.

[0017]

According to the present invention, since the high resistance layer formed on the substrate side of the source region and the drain region has an insulating function, the leakage current with respect to the source-drain voltage is reduced. In addition, the high-resistance layer that reduces the leakage current
It is preferable to form not only on the substrate side of the source region and the drain region but also on the substrate side of the channel region. By doing so, the leak current with respect to the source-drain voltage can be further reduced. However, like the former,
When a high-resistance layer is formed on the substrate side of the source region and the drain region, the channel region is thicker than the source region and the drain region and protrudes toward the substrate side, so that the channel region flows on the back gate side of the channel region. For the reason that the current is reduced, this can also reduce the leakage current with respect to the source-drain voltage.

As such a high resistance layer, a polycrystalline silicon thin film mixed with nitrogen or carbon can be used.

When the high-resistance layer is formed on the substrate side of the source region and the drain region, nitrogen or carbon is implanted into the semiconductor layer using the gate electrode as a mask, so that the high-resistance layer is self-aligned to the portion of the semiconductor layer near the substrate. Forming a resistance layer,
A source region and a drain region can be formed on the high resistance layer. At this time, the implantation is performed so that nitrogen or carbon is mixed into the high resistance layer at 10 ²¹ atoms / cm ³ or more, and nitrogen or carbon is mixed into the source region and the drain region at less than 10 ²¹ atoms / cm ^3. It is desirable. When nitrogen or carbon mixed into the high resistance layer is less than 10 ²¹ atoms / cm ³ , a desired high resistance cannot be obtained. On the other hand, when nitrogen or carbon is mixed into the source region and the drain region at a concentration of 10 ²¹ atoms / cm ³ or more, the transistor does not operate.

When the high resistance layer is formed not only on the substrate side of the source and drain regions but also on the substrate side of the channel region, the channel region and the source are formed after the high resistance layer is formed on the substrate. A semiconductor layer forming the region and the drain region is preferably formed. In this case, the high resistance layer is formed by forming a polycrystalline silicon thin film (or non-single-crystal silicon) mixed with nitrogen or carbon, or by forming a polycrystalline silicon thin film (or non-single-crystal silicon). This can be done later by injecting nitrogen or carbon.

When impurities are implanted into the semiconductor layer to form a source region and a drain region, an insulating film formed on the surface of the gate electrode in addition to the gate electrode (for example, used in the following embodiments) When an anodic oxide film is used as a mask, an offset region corresponding to the thickness of the insulating film protruding from the gate electrode along the substrate surface can be formed. This offset region contributes to the reduction of non-linear leakage current.

[0022]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 2 (j) shows the TF of this embodiment.
1 shows a sectional view of T. In this TFT, a semiconductor layer 2 made of polycrystalline silicon is formed on an insulating substrate 1.
This semiconductor layer 2 is a channel region 2 which is an intrinsic semiconductor layer.
a, It is divided into a source region 7 and a drain region 7 in which an impurity is implanted to form an n ⁺ layer or a p ⁺ layer.
Below the source region 7 and the drain region 7, a high resistance layer 6 made of polycrystalline silicon mixed with nitrogen or carbon is formed. Channel region 2 of the semiconductor layer 2
On a, a gate insulating film 3 and a gate electrode 4 are formed in this order. An anodized film 5 is formed on the surface of the gate electrode 4.

On the substrate in this state, an interlayer insulating film 8 is formed so as to cover the anodic oxide film 5 and the like, and on the source region 7 and the drain region 7 in the interlayer insulating film 8, , Source region 7 and drain region 7
Is formed. A source electrode 9 and a drain electrode 9 are formed on the interlayer insulating film 8 in a state where the contact holes are partially filled, and a protective film 10 is further formed thereon.

Next, a method of manufacturing the TFT will be described.

First, as shown in FIG. 1A, low pressure CVD (Chemi) is applied on a transparent insulating substrate 1 made of glass or the like.
An amorphous silicon film is formed using a cal vapor deposition (apparatus) apparatus or a plasma CVD apparatus.

Next, this amorphous silicon film is
A semiconductor layer 2 is obtained by forming a polycrystalline silicon film by PC (Solid Phase Crystaization) or excimer laser annealing or a combination of SPC and excimer laser and processing it into a predetermined shape. Note that the thickness of the polycrystalline silicon film is preferably about 20 nm to 100 nm in order to obtain good film quality. The channel region 2, the source region 7, the drain region 7, and the high-resistance layer 6 are formed in the semiconductor layer 2.

Next, as shown in FIG. 1B, a 100 nm-thick SiO ₂ film is formed so as to cover the semiconductor layer 2 using, for example, a plasma TEOS device. This SiO ₂ film is used as the gate insulating film 3 by an etching process described later.

Next, on the SiO ₂ film, an Al film containing Ti is formed to a thickness of 3 using, for example, a sputtering apparatus.
The gate electrode 4 is formed to a thickness of
To form

Next, as shown in FIG. 1 (c), 3% ammonium tartrate and ethylene glycol were added to the former: the latter =
The gate electrode 4 is formed using a solution mixed at a ratio of 1: 9.
Is anodized, so that 0.2
An anodic oxide film 5 having a thickness of not more than μm is formed. This anodic oxide film 5
Is the offset length.

Next, as shown in FIG. 1D, the SiO ₂ film is etched into a predetermined shape using the gate electrode 4 and the anodic oxide film 5 as a mask, whereby a gate insulating film 3 is obtained.

Next, as shown in FIG. 1E, using the gate electrode 4 and the anodic oxide film 5 as a mask, nitrogen or carbon is implanted into the semiconductor layer 2 by a mass separation type ion implantation apparatus or an ion shower doping apparatus. . Thus, the high resistance layer 6 is formed. In this implantation, nitrogen or carbon is mixed into the high-resistance layer 6 in an amount of 10 ²¹ atoms / cm ³ or more, and a portion above the high-resistance layer 6, that is, a source region 7 and a drain region 7 are formed in a later step. The semiconductor layer 2 contains 10 ²¹ atoms of nitrogen or carbon.
It is desirable to perform the mixing so as to be less than s / cm ³ .

Next, as shown in FIG. 1F, using the gate electrode 4 and the anodic oxide film 5 as a mask, the semiconductor layer 2 on the high resistance layer 6 is separated by a mass separation type ion implantation apparatus or an ion shower doping apparatus. Phosphorus or boron is implanted into the portion, for example, at least 10 ²⁰ atoms / cm ³ .

Next, impurity ions are activated by performing thermal annealing or laser annealing. As a result, a source region 7 and a drain region 7 which are n ⁺ layers or p ⁺ layers are formed (see FIG. 2G). Therefore, the portion of the semiconductor layer 2 below the anodic oxide film 5 becomes an offset region.

Next, as shown in FIG. 2H, for example, a SiO ₂ film having a thickness of 400 nm is formed by using a plasma TEOS device.
An interlayer insulating film 8 made of is formed.

Next, as shown in FIG. 2I, two contact holes are opened in the interlayer insulating film 8 so as to reach the source region 7 and the drain region 7. Is formed to a thickness of 350 nm and partially filled in the contact holes to form the source electrode 9 and the drain electrode 9.

Finally, as shown in FIG.
A silicon nitride film is formed using a plasma CVD apparatus on the upper surface of the silicon nitride film to form a protective film 10.

(Embodiment 2) FIG. 4 (i) shows the TF of this embodiment.
1 shows a sectional view of T.

In this TFT, a high-resistance layer 12 made of polycrystalline silicon mixed with nitrogen or carbon and a semiconductor layer 13 made of polycrystalline silicon are formed on an insulating substrate 11 in this order. The semiconductor layer 13 has a channel region 13a, which is an intrinsic semiconductor layer, and n ⁺
It is divided into a source region 17 and a drain region 17 which are layers or p ⁺ layers.

A gate insulating film 14 and a gate electrode 15 are formed in this order on the channel region 13 a of the semiconductor layer 13, and the anodic oxide film 1 is formed on the surface of the gate electrode 15.
6 are formed.

On the substrate in this state, an interlayer insulating film 18 is formed so as to cover anodic oxide film 16 and the like, and a contact hole reaching source region 17 and drain region 17 is formed in interlayer insulating film 18. I have. A source electrode 19 and a drain electrode 19 are formed on the interlayer insulating film 18 so as to partially fill the contact holes, and a protective film 20 is further formed thereon.

Next, a method of manufacturing this TFT will be described.

First, as shown in FIG. 3A, an amorphous silicon film is formed on a transparent insulating substrate 11 made of glass or the like by using a low pressure CVD apparatus or a plasma CVD apparatus. Nitrogen or carbon is implanted into this amorphous silicon film by a mass separation type ion implantation apparatus or an ion shower doping apparatus, and the high resistance layer 12 is formed. This implantation is performed by adding nitrogen or carbon to the high resistance layer 12.
^It is desirable that the mixing be performed so that the concentration is ²¹ atoms / cm ³ or more.

Next, as shown in FIG. 3B, an amorphous silicon film is formed on the high resistance layer 12 by using a low pressure CVD apparatus or a plasma CVD apparatus. This amorphous silicon film is converted into a polycrystalline silicon film by SPC or excimer laser annealing or a combination of SPC and excimer laser, and processed into a predetermined shape to obtain a semiconductor layer 13. Note that the thickness of the polycrystalline silicon film is preferably about 20 nm to 100 nm in order to obtain good film quality.

Next, as shown in FIG. 3C, a 100 nm-thick SiO ₂ film is formed on the substrate in this state by using, for example, a plasma TEOS device so as to cover the semiconductor layer 13.
The gate insulating film 14 made of is formed.

Next, an Al film containing Ti is formed to a thickness of 300 nm on the gate insulating film 14 by using, for example, a sputtering apparatus, and processed into a predetermined shape to form a gate electrode 15.

Next, as shown in FIG. 3D, 3% ammonium tartrate and ethylene glycol were added to the former: the latter =
Using a solution mixed at a ratio of 1: 9, the gate electrode 1
5 is anodically oxidized to form an anodic oxide film 16 of 0.2 μm or less on the surface of the gate electrode 15. The thickness of the anodic oxide film 16 is an offset length.

Next, as shown in FIG. 3E, the gate insulating film 14 is etched into a predetermined shape using the gate electrode 15 and the anodic oxide film 16 as a mask.

Next, as shown in FIG. 3F, using the gate electrode 15 and the anodic oxide film 16 as a mask, phosphorus or boron is applied to the semiconductor layer 13 by a mass separation type ion implantation apparatus or an ion shower doping apparatus. 10
Inject more than ²⁰ atoms / cm ³ . Thereafter, impurity ions are activated by performing thermal annealing or laser annealing. As a result, a source region 17 and a drain region 17 which are n ⁺ layers or p ⁺ layers are formed. At this time, the semiconductor layer below the anodic oxide film 16 becomes an offset region (not shown).

Next, as shown in FIG. 4G, a 400 nm-thick SiO ₂ film is formed by using, for example, a plasma TEOS device.
An interlayer insulating film 18 made of is formed.

Next, as shown in FIG. 4H, two contact holes are opened in the interlayer insulating film 18 so as to reach the source region 17 and the drain region 17. Is formed to a thickness of 350 nm and partially filled in contact holes to form a source electrode 19 and a drain electrode 19.

Finally, as shown in FIG.
A protective film 20 is formed by forming a silicon nitride film on the upper portion using a plasma CVD apparatus.

(Embodiment 3) FIG. 6 (i) shows the TF of this embodiment.
1 shows a sectional view of T.

In this TFT, a high-resistance layer 22 made of polycrystalline silicon mixed with nitrogen or carbon and a semiconductor layer 23 made of polycrystalline silicon are formed on an insulating substrate 21 in this order. The semiconductor layer 23 includes a channel region 23a, which is an intrinsic semiconductor layer, and n ⁺
It is divided into a source region 27 and a drain region 27 which are layers or p ⁺ layers.

On the channel region 23a of the semiconductor layer 23, a gate insulating film 24 and a gate electrode 25 are formed in this order, and on the surface of the gate electrode 25, the anodic oxide film 2 is formed.
6 are formed.

On the substrate in this state, an interlayer insulating film 28 is formed so as to cover anodic oxide film 26 and the like, and a contact hole reaching source region 27 and drain region 27 is formed in interlayer insulating film 28. I have. Interlayer insulating film 2
On top of 8, a source electrode 29 and a drain electrode 29 are formed in a state where the contact holes are partially filled, and a protective film 30 is further formed thereon.

Next, a method of manufacturing this TFT will be described.

First, as shown in FIG. 5A, a high-resistance layer made of non-single-crystal silicon containing nitrogen or carbon is formed on a transparent insulating substrate 21 made of glass or the like by using a plasma CVD apparatus or a sputtering apparatus. 22 is formed. The high resistance layer 22 contains 10 ²¹ atoms / cm of nitrogen.
^It is desirable that ^three or more be mixed.

Next, as shown in FIG. 5B, an amorphous silicon film is formed on the high resistance layer 22 by using a low pressure CVD apparatus or a plasma CVD apparatus. continue,
By subjecting this amorphous silicon film to heat treatment by SPC or excimer laser annealing or a combination of SPC and excimer laser, a polycrystalline silicon film is formed and processed into a predetermined shape to obtain the semiconductor layer 23. The thickness of the semiconductor layer 23 is 20 nm in order to obtain good film quality.
It is preferably about 100 nm. The high-resistance layer 22 made of non-single-crystal silicon containing nitrogen or carbon is used.
Becomes polycrystalline silicon by the above heat treatment. In order to function as a high-resistance layer, non-single-crystal silicon containing nitrogen or carbon may be used as it is. In this embodiment, when the semiconductor layer 23 is formed, and when a source region and a drain region described later are formed. The non-single-crystal silicon undergoes a structural change in the polycrystalline silicon due to the heat treatment performed in step (1).

Next, as shown in FIG. 5C, a 100 nm-thick SiO ₂ film is formed by using, for example, a plasma TEOS device.
Is formed to cover the semiconductor layer 23. An Al film containing Ti is formed thereon to a thickness of 300 nm by using, for example, a sputtering apparatus.
The gate electrode 25 is formed by processing into a predetermined shape.

Next, as shown in FIG. 5 (d), 3% ammonium tartrate and ethylene glycol were added to the former: the latter =
The gate electrode 2 was prepared using a solution mixed at a ratio of 1: 9.
5 is anodized to form an anodic oxide film 26 having a thickness of 0.2 μm or less on the surface of the gate electrode 25. The thickness of the anodic oxide film 26 is an offset length.

Next, as shown in FIG. 5E, the gate insulating film 24 is etched into a predetermined shape using the gate electrode 25 and the anodic oxide film 26 as a mask.

Next, as shown in FIG. 5F, using the gate electrode 25 and the anodic oxide film 26 as a mask, phosphorus or boron is added to the semiconductor layer 23 by a mass separation type ion implantation apparatus or an ion shower doping apparatus. 10
Inject more than ²⁰ atoms / cm ³ . After that, impurity ions are activated by performing thermal annealing or laser annealing to form the source region 27 which is an n ⁺ layer or ap ⁺ layer.
And a drain region 27 are formed. At this time, the semiconductor layer below the anodic oxide film 26 is in an offset region (not shown).
become.

Next, as shown in FIG. 6G, a 400 nm-thick SiO ₂ film is formed by using, for example, a plasma TEOS device.
Is formed.

Next, as shown in FIG. 6H, two contact holes are opened in the interlayer insulating film 28 so as to reach the source region 27 and the drain region 27. Is formed to a thickness of 350 nm and partially filled in contact holes to form a source electrode 29 and a drain electrode 29.

Finally, as shown in FIG.
A silicon nitride film is formed on the upper portion using a plasma CVD device, and a protective film 30 is formed.

[0067]

As is apparent from the above description, according to the present invention, the polycrystalline silicon T which can reduce the off-state leakage current without substantially reducing the on-state current.
The FT can be manufactured by a simple manufacturing process.
In a TFT-LCD, a TFT having a sufficiently high on-state current as a driver element of a peripheral driving circuit and a sufficiently low off-state current as a pixel switching element can be realized, so that the driver element and the pixel switching element are formed by the same process and the same structure. A manufacturing process that can be manufactured and has excellent productivity becomes possible.

[Brief description of the drawings]

FIGS. 1A to 1F are cross-sectional views illustrating steps for manufacturing a TFT of Example 1. FIGS.

2 (g) to 2 (j) are cross-sectional views illustrating steps for manufacturing the TFT of Example 1. FIG.

FIGS. 3A to 3F are cross-sectional views illustrating steps of manufacturing a TFT of Example 2. FIGS.

FIGS. 4 (g) to 4 (i) are cross-sectional views illustrating steps for manufacturing a TFT of Example 2. FIGS.

FIGS. 5A to 5F are cross-sectional views illustrating steps of manufacturing a TFT of Example 3. FIGS.

FIGS. 6G to 6I are cross-sectional views illustrating steps of manufacturing a TFT according to a third embodiment.

FIG. 7A is a Vg-Id curve of a TFT,
(B) is a Vds-Id curve of the TFT.

[Explanation of symbols]

 1, 11, 21 Insulating substrate 2, 13, 23 Semiconductor layer made of polycrystalline silicon 3, 14, 24 Gate insulating film 4, 15, 25 Gate electrode 5, 16, 26 Anodized film 6, 12, 22 High resistance Layers 7, 17, 27 Source and drain regions 8, 18, 28 Interlayer insulating films 9, 19, 29 Source and drain electrodes 10, 20, 30 Protective film

Claims (5)

(57) [Claims] 1. A thin film transistor in which a semiconductor layer made of a polycrystalline silicon thin film, a gate insulating film, and a gate electrode are formed on a substrate in this order from the substrate side, wherein the semiconductor layer has a source region and a drain sandwiching a channel region. It has an area, and the high-resistance layer is formed with an insulating function to the substrate side of said source and drain regions of the semiconductor layer, the thickness of the channel region the source region and the drain
A thin film transistor formed to be thicker than the thickness of the transistor region . 2. A thin film transistor in which a semiconductor layer made of a polycrystalline silicon thin film, a gate insulating film and a gate electrode are formed on a substrate in this order from the substrate side, wherein the semiconductor layer has a source region and a drain sandwiching a channel region. has an area, to the substrate side of said source and drain regions of the semiconductor layer and the high resistance layer is formed having an insulating function, the high resistance layer is polycrystalline nitrogen or carbon is mixed Shi
Thin film transistor made of Recon thin film. 3. A semiconductor layer comprising a polycrystalline silicon thin film, a gate insulating film and a gate electrode are formed on a substrate in this order from the substrate side, and the semiconductor layer has a source region and a drain region with a channel region interposed therebetween. In the method for manufacturing a thin film transistor, a step of forming a semiconductor layer, a gate insulating film, and a gate electrode on a substrate in this order; implanting nitrogen or carbon into the semiconductor layer using the gate electrode as a mask; Forming a high-resistance layer having an insulating function in the portion; and implanting an impurity into the semiconductor layer using the gate electrode as a mask and performing an activation process, thereby forming a semiconductor layer portion above the high-resistance layer. Forming a source region and a drain region in the thin film transistor. 4. When nitrogen or carbon is implanted into the semiconductor layer, nitrogen or carbon is implanted into a portion where the high resistance layer is formed.
²¹ atoms / cm ³ or more, and nitrogen or carbon is added to a portion where the source region and the drain region are formed at 10 ²¹ a / cm ^3.
4. The method for manufacturing a thin film transistor according to claim 3 , wherein the mixing is performed so as to be less than toms / cm ³ . 5. The method according to claim 1, wherein when implanting an impurity into the semiconductor layer to form the source and drain regions, an insulating film formed on the surface of the gate electrode is used as a mask in addition to the gate electrode. 5. The method for manufacturing a thin film transistor according to 3 or 4 .