KR20020047746A - wire bonding method and semiconductor package using it - Google Patents
wire bonding method and semiconductor package using it Download PDFInfo
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- KR20020047746A KR20020047746A KR1020000076328A KR20000076328A KR20020047746A KR 20020047746 A KR20020047746 A KR 20020047746A KR 1020000076328 A KR1020000076328 A KR 1020000076328A KR 20000076328 A KR20000076328 A KR 20000076328A KR 20020047746 A KR20020047746 A KR 20020047746A
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- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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Abstract
Description
본 발명은 와이어본딩 방법 및 이를 이용한 반도체패키지에 관한 것으로, 더욱 상세하게 설명하면 반도체칩이 수직방향으로 다수개로 적층되어 탑 와이와 바텀 와이어의 접속에 의해 상호 신호 교환이 이루어지는 반도체 패키지에서 상기 탑 와이어와 바터 와이어의 갭을 최대한 확보하는 것에 의해, 몰딩 공정시 스위핑에 의한 와이어 쇼트를 방지할 수 있는 와이어 본딩 방법 및 이를 이용한 반도체 패키지에 관한 것이다.The present invention relates to a wire bonding method and a semiconductor package using the same. More specifically, in the semiconductor package, a plurality of semiconductor chips are stacked in a vertical direction to exchange signals with each other by connecting a top wire and a bottom wire. The present invention relates to a wire bonding method capable of preventing wire shorting due to sweeping during a molding process by ensuring a maximum gap between the wire and the batter wire, and a semiconductor package using the same.
통상 인쇄회로기판, 리드프레임 또는 써킷필름(이하 인쇄회로기판에 한하여 설명함) 등에 다수의 반도체칩이 적층되어(이를 Multi Chip Module이라고도 함) 봉지재로 봉지된 반도체패키지를 적층형 반도체패키지, 또는 MCM(Multi Chip Module)이라고 한다.In general, a plurality of semiconductor chips stacked on a printed circuit board, a lead frame or a circuit film (hereinafter, only described as a printed circuit board) (hereinafter referred to as a multi chip module), and a semiconductor package encapsulated with an encapsulant, a multilayer semiconductor package, or an MCM It is called (Multi Chip Module).
이러한 반도체패키지는 통상 봉지재 내측의 적층형성된 반도체칩이 인쇄회로기판의 회로패턴에 탑 와이어(상부쪽의 와이어) 및 바텀 와이어(하부쪽의 와이어)로 연결되어 있다.Such a semiconductor package is typically formed by stacking a semiconductor chip inside an encapsulant with a top wire (upper wire) and a bottom wire (lower wire) to a circuit pattern of a printed circuit board.
이러한 반도체패키지중에서 인쇄회로기판(20)을 이용한 적층형 반도체패키지(100') 및 봉지되기 전의 상태를 도1a 및 도1b에 도시하였다.1A and 1B illustrate the stacked semiconductor package 100 'using the printed circuit board 20 and the state before the semiconductor package is encapsulated.
도1a 및 도1b에 도시된 바와 같이 상면에 다수의 열(예를 들면 2열)로 입출력패드(2a)가 구비된 제1반도체칩(2)이 구비되어 있고, 상기 제1반도체칩(2)의 상면에는 역시 다수의 입출력패드(4a)가 구비된 제2반도체칩(4)이 접착수단(6)으로 접착되어 있다.1A and 1B, a first semiconductor chip 2 having an input / output pad 2a in a plurality of rows (for example, two rows) is provided on an upper surface thereof, and the first semiconductor chip 2 is provided. The second semiconductor chip 4, which is also provided with a plurality of input / output pads 4a, is bonded to the upper surface of the "
상기 제1반도체칩(2)의 저면에는 접착수단(6)으로 인쇄회로기판(20)이 접착되어 있다.The printed circuit board 20 is bonded to the bottom surface of the first semiconductor chip 2 by an adhesive means 6.
주지된 바와 같이 상기 인쇄회로기판(20)은 수지층(22)을 중심으로 그 상,하면에 다수의 회로패턴(24)이 형성되어 있다. 즉, 상기 제1반도체칩(2)을 중심으로 그 외주연에 다수의 본드핑거(24a)를 포함하는 회로패턴(24)이 방사상으로 형성되어 있고, 상기 회로패턴(24)은 비어홀(25)을 통하여 수지층(22) 저면의 볼랜드(24b)를 포함하는 회로패턴(24)에 연결되어 있다. 상기 수지층(22) 상면에는 상기 본드핑거(24a)를 제외한 회로패턴(24)이 커버코트(26) 등으로 코팅되어 있고, 상기 수지층(22) 저면의 볼랜드(24b)를 제외한 회로패턴(24) 역시 커버코트(26) 등으로 코팅되어 있다. 상기 제1반도체칩(2)은 바텀 와이어(8b)에 의해 인쇄회로기판(20)의 본드핑거(24a)에 전기적으로 접속되어 있고, 상기 제2반도체칩(4)의 입출력패드(4a)는 다른 도전성와이어 즉, 탑 와이어 (8a)에 의해 인쇄회로기판(20)의 다른 본드핑거(24a)에 전기적으로 접속되어 있다.As is well known, the printed circuit board 20 has a plurality of circuit patterns 24 formed on and under the resin layer 22. That is, a circuit pattern 24 including a plurality of bond fingers 24a around the first semiconductor chip 2 is formed radially, and the circuit pattern 24 includes a via hole 25. It is connected to the circuit pattern 24 containing the ball land 24b of the bottom face of the resin layer 22 through the sintering layer. The circuit pattern 24 except for the bond finger 24a is coated on the upper surface of the resin layer 22 with a cover coat 26 or the like, and the circuit pattern except for the ball land 24b on the bottom surface of the resin layer 22 ( 24) is also coated with a cover coat 26 or the like. The first semiconductor chip 2 is electrically connected to the bond finger 24a of the printed circuit board 20 by the bottom wire 8b, and the input / output pad 4a of the second semiconductor chip 4 is The other conductive wires, that is, the top wires 8a, are electrically connected to the other bond fingers 24a of the printed circuit board 20.
참고로, 상기와 같이 제1반도체칩(2)과 제2반도체칩(4)을 연결하는 도전성와이어(8a,8b)는 주로 접지용 또는 파워용이다.For reference, the conductive wires 8a and 8b connecting the first semiconductor chip 2 and the second semiconductor chip 4 are mainly for grounding or power.
한편, 상기 제1반도체칩(2), 제2반도체칩(4) 및 탑 와이어, 바텀 도전성와이어(8a,8b) 등은 외부 환경으로부터 보호되도록 봉지재(30)로 봉지되어 있다.Meanwhile, the first semiconductor chip 2, the second semiconductor chip 4, the top wire, the bottom conductive wires 8a and 8b, and the like are encapsulated with the encapsulant 30 so as to be protected from the external environment.
또한, 상기 인쇄회로기판(20) 저면의 볼랜드(24b)에도 도전성볼(40)이 융착되어 입출력 단자로 사용될 수 있도록 되어 있다.In addition, the conductive ball 40 is also fused to the ball land 24b of the bottom surface of the printed circuit board 20 to be used as an input / output terminal.
하지만, 종래에는 상기와 같은 적층형 반도체 패키지에 있어서는, 상기 탑 와이어(8a)와 바텀 와이어(8b)사이의 갭(gab)이 충분히 확보가 되지 않아서,몰딩시 용융수지충진압에 의해 상기 도전성 와이어의 스위핑(sweeping) 불량의 발생가능성이 증가되고, 이에 의해 와이어가 쇼트될 우려가 있다.However, in the conventional stacked semiconductor package, the gap gab between the top wire 8a and the bottom wire 8b is not sufficiently secured, and thus the conductive wire is formed by the melt filling pressure during molding. The likelihood of a sweeping defect is increased, thereby causing the wire to short.
따라서 본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출한 것으로, 본 발명의 목적은 반도체칩이 수직방향으로 다수개로 적층되어 탑 와이와 바텀 와이어의 접속에 의해 상호 신호 교환이 이루어지는 반도체 패키지에서 상기 탑 와이어를 바텀 와이어 보다 강성이 크고 두께를 뚜껍게 형성하여 상기 탑 와이어와 바텀 와이어의 갭을 최대한 확보하는 것에 의해, 몰딩 공정시 스위핑에 의한 와이어 쇼트를 방지할 수 있는 와이어 본딩 방법 및 이를 이용한 반도체 패키지의 제공에 있다.Accordingly, the present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to provide a semiconductor package in which a plurality of semiconductor chips are stacked in a vertical direction to exchange signals by connecting top wires and bottom wires. By forming the top wire to be rigid and thicker than the bottom wire to secure the gap between the top wire and the bottom wire to the maximum, a wire bonding method capable of preventing wire shorting by sweeping during molding process and using the same A semiconductor package is provided.
도1a 및 도1b는 종래 반도체칩과 반도체칩이 도전성와이어로 본딩되어 봉지된 반도체패키지의 일례를 도시한 단면도 및 봉지되기 전의 상태를 도시한 평면도이다.1A and 1B are cross-sectional views showing an example of a semiconductor package in which a conventional semiconductor chip and a semiconductor chip are bonded and encapsulated with a conductive wire, and a plan view showing a state before encapsulation.
도2a 내지 도2c는 본 발명에 와이어본딩 방법을 도시한 설명도이다.2A to 2C are explanatory diagrams showing a wire bonding method according to the present invention.
도3a 및 도 3b는 본 발명에 의한 와이어본딩 방법이 적용된 반도체패키지의 일례와 봉지되기 전의 패키지의 상태를 도시한 평면도이다.3A and 3B are plan views showing an example of a semiconductor package to which the wire bonding method according to the present invention is applied and the state of the package before being sealed.
- 도면중 주요 부호에 대한 설명 --Description of the main symbols in the drawings-
100; 본 발명에 의한 반도체패키지100; Semiconductor package according to the present invention
2; 제1반도체칩2a,4a; 제1반도체칩의 입출력패드2; First semiconductor chips 2a and 4a; I / O pad of the first semiconductor chip
4; 제2반도체칩6; 접착수단4; Second semiconductor chip 6; Adhesive means
8a,8b; 탑 와이어, 바텀 와이어20; 인쇄회로기판8a, 8b; Top wire, bottom wire 20; Printed circuit board
22; 수지층24; 회로패턴22; Resin layer 24; Circuit pattern
24a; 본드핑거 24b; 볼랜드24a; Bondfinger 24b; Borland
25; 비어홀26; 커버코트25; Via-hole 26; Cover coat
30; 봉지재40; 도전성볼30; Encapsulant 40; Conductive ball
50; 캐필러리50; Capillary
상기한 목적을 달성하기 위한 본 발명의 와이어 본딩방법은 회로기판의 중앙부에 각각 다수의 입출력 패드가 구비된 제 1 반도체 칩과 제 2 반도체칩이 차례로 수직방향으로 적층형성되고, 상기 반도체 칩 외주연에 다수의 회로 패턴이 형성되어 상기 제 1 반도체 칩과 제 2 반도체 칩의 입출력 패드와 상기 회로패턴을 도전성 와이어로 본딩하여 상호 신호 교환이 이루어지도록 도전성와이어로 본딩하는 방법에 있어서, 상기 하부쪽의 제 1 반도체 칩의 입출력패드와 회로 패턴을 접속하는 바텀 와이어가 상부쪽의 제 2 반도체 칩의 입출력 패드와 회로 패턴을 접속하는 탑 와이어 보다 두께가 얇게 형성시키는 것을 특징으로 한다.In the wire bonding method of the present invention for achieving the above object, a first semiconductor chip and a second semiconductor chip each having a plurality of input and output pads are sequentially stacked in a vertical direction in a central portion of the circuit board, and the outer peripheral edge of the semiconductor chip is formed. A plurality of circuit patterns are formed on the first semiconductor chip and the input and output pads of the second semiconductor chip and the circuit pattern by bonding a conductive wire to bond the conductive wires so that mutual signal exchange is performed, the method of the lower side The bottom wire connecting the input / output pads of the first semiconductor chip and the circuit pattern is formed to be thinner than the top wire connecting the input / output pads of the second semiconductor chip and the circuit pattern.
또한, 상기 와이어 본딩 방법에 있엇, 상기 바텀 와이어의 두께는 바람직하게는 1.0 mil 이하이고. 상기 탑 와이어의 두께는 1.2 mil 이상인 것이 바람직하다.Further, in the wire bonding method, the thickness of the bottom wire is preferably 1.0 mil or less. The thickness of the top wire is preferably 1.2 mil or more.
또한, 상기 목적을 달성하기 위한 본 발명의 반도체 패키지는 수직 방향으로 차례로 적층형성되는 각각 다수의 입출력 패드가 구비된 제 1 반도체 칩과 제 2 반도체칩과; 상기 제 1반도체 칩의 저면에 접착수단으로 접착되어 있되, 수지층을 중심으로 상기 적층형성된 제 1 반도체칩 및 제 2 반도체 칩의 외주연에 다수의 회로패턴이 형성되어 있으며, 상기 수지층의 상면 또는 저면에는 상기 회로패턴과 연결된 다수의 볼랜드를 포함하여 이루어진 회로기판과;상기 제1반도체칩의 입출력패드와 상기 회로 패턴을 전기적으로 접속시키는 바텀와이어 및 상기 제2반도체칩의 입출력패드와 상기 회로패턴을 전기적으로 접속시키는 탑 와이어와; 상기 제1반도체칩, 제2반도체칩, 도전성와이어 등을 외부환경으로부터 보호하기 위해 감싸는 봉지재와; 상기 회로기판의 볼랜드에 융착된 다수의 도전성볼을 포함하여 이루어지되, 상기 하부쪽의 제 1 반도체 칩의 입출력패드와 회로 패턴을 접속하는 바텀 와이어가 상부쪽의 제 2 반도체 칩의 입출력 패드와 회로 패턴을 접속하는 탑 와이어 보다 두께가 얇게 형성시키는 것을 특징으로 한다.In addition, the semiconductor package of the present invention for achieving the above object comprises: a first semiconductor chip and a second semiconductor chip each having a plurality of input and output pads are sequentially formed in a vertical direction; A plurality of circuit patterns are formed on the outer circumferences of the first semiconductor chip and the second semiconductor chip, which are attached to the bottom surface of the first semiconductor chip by adhesive means, and are formed around the resin layer. Or a bottom surface of the circuit board including a plurality of ball lands connected to the circuit pattern; a bottom wire electrically connecting the input / output pad of the first semiconductor chip and the circuit pattern, the input / output pad of the second semiconductor chip and the circuit; A top wire for electrically connecting the pattern; An encapsulant for encapsulating the first semiconductor chip, the second semiconductor chip, the conductive wire, and the like in an external environment; It includes a plurality of conductive balls fused to the ball land of the circuit board, the bottom wire connecting the circuit pattern and the input and output pads of the first semiconductor chip of the lower side is the input and output pads and circuit of the second semiconductor chip of the upper side It is characterized by forming a thickness thinner than the top wire which connects a pattern.
또한, 본 발명의 반도체 패키지에 있어, 상기 바텀 와이어의 두께는 1.0 mil이하이고. 상기 탑 와이어의 두께는 1.2 mil 이상인 것이 바람직하다.In the semiconductor package of the present invention, the bottom wire has a thickness of 1.0 mil or less. The thickness of the top wire is preferably 1.2 mil or more.
이하 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 용이하게 실시할 수 있을 정도로 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세하게 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings such that those skilled in the art can easily implement the present invention.
도2a 내지 도2c는 본 발명에 의한 와이어 본딩 방법의 일례를 도시한 설명도이다.2A to 2C are explanatory views showing an example of the wire bonding method according to the present invention.
먼저, 회로기판상에 다수의 반도체칩이 적층된 반도체패키지 자재(또는 평면상에 다수의 반도체칩이 분포된 반도체패키지 자재)를 구비하되, 상기 반도체칩의 외주연에는 다수의 본더 핑거(24a)가 형성된 회로패턴이 구비된 회로기판을 구비한다. 여기서 상기 반도체칩은 편의상 제1반도체칩(2) 및 제2반도체칩(4)으로 구분한다.First, a semiconductor package material having a plurality of semiconductor chips stacked on a circuit board (or a semiconductor package material having a plurality of semiconductor chips distributed on a plane) is provided, and a plurality of bonder fingers 24a are formed on the outer circumference of the semiconductor chip. A circuit board is provided with a circuit pattern formed thereon. The semiconductor chip is divided into a first semiconductor chip 2 and a second semiconductor chip 4 for convenience.
다음, 와이어본더(도시되지 않음)의 캐필러리(50)를 이용하여 제1반도체칩(2)의 입출력패드(2a)에 대략 1.0 mil 이하의 얇은 두께를 갖는 바텀 와이어(8b)의 일단을 본딩한 후 타단을 본드 핑거(24a)에 본딩한다.(도2a)Next, one end of the bottom wire 8b having a thin thickness of about 1.0 mil or less is formed on the input / output pad 2a of the first semiconductor chip 2 using the capillary 50 of the wire bonder (not shown). After bonding, the other end is bonded to the bond finger 24a (FIG. 2A).
계속해서, 대략 1.2 mil 이상의 비교적 두꺼운 두께를 갖는 탑 와이어(8a)의 일단을 제2반도체칩(4)의 입출력패드(4a)에 본딩한 후 타단을 상기 다른 본드 핑거(24a)에 본딩한다.(도2b)Subsequently, one end of the top wire 8a having a relatively thick thickness of about 1.2 mil or more is bonded to the input / output pad 4a of the second semiconductor chip 4 and then the other end is bonded to the other bond finger 24a. (Fig. 2b)
따라서, 제1반도체칩(2) 및 제2반도체칩(4))의 전기적 신호는 각각 탑 및 바텀 와이어(8a)(8b)를 통해 회로패턴으로 전달된다.Thus, the electrical signals of the first semiconductor chip 2 and the second semiconductor chip 4 are transmitted to the circuit pattern through the top and bottom wires 8a and 8b, respectively.
여기서, 본 발명에서는 바텀 와이어(8b)부터 본딩하고 그 후, 탑 와이어(8a)를 본딩하였으나, 그 순서를 바꾸어도 무방하다.Here, in the present invention, the bottom wire 8b is bonded and then the top wire 8a is bonded. However, the order may be changed.
도3a 및 도 3b는 본 발명에 의한 와이어본딩 방법이 적용된 반도체패키지(100)의 일례와 봉지되기 전의 반도체 패키지의 상태를 도시한 평면도이다.3A and 3B are plan views showing an example of the semiconductor package 100 to which the wire bonding method according to the present invention is applied and the state of the semiconductor package before being sealed.
먼저 상면에 다수의 열로 입출력패드(2a)가 형성된 제1반도체칩(2)이 구비되어 있다. 상기 제1반도체칩(2)의 상면에는 역시 상부에 입출력패드(4a)가 형성된 제2반도체칩(4)이 접착수단(6)으로 접착되어 있다.First, a first semiconductor chip 2 having a plurality of rows of input / output pads 2a formed thereon is provided on an upper surface thereof. On the upper surface of the first semiconductor chip 2, a second semiconductor chip 4, on which an input / output pad 4a is formed, is attached to the upper surface of the first semiconductor chip 2.
상기 제1반도체칩(2)의 저면에는 접착수단(6)으로 회로기판(20)이 접착되어 있다. 상기 회로기판(20)은 주지된 바와 같이 수지층(22)을 중심으로 상기 제1반도체칩(2)의 외주연에 본드핑거(24a)를 포함하는 다수의 도전성 회로패턴(24)이 방사상으로 형성되어 있다. 또한 상기 수지층(22) 저면에는 볼랜드(24b)를 포함하는 다수의 도전성 회로패턴(24)이 형성되어 있다. 상기 본드핑거(24a)에는 차후 도전성 와이어와의 본딩력을 향상시키기 위해 은(Ag) 또는 금(Au)이 도금되어 있고, 상기 볼랜드(24b)에는 차후 도전성볼(40)과의 융착력을 향상시키기 위해 은(Ag), 니켈(Ni) 및 팔라디엄(Pd) 등이 도금되어 있다. 또한, 상기 본드핑거(24a) 및 볼랜드(24b)를 포함하는 회로패턴(24)은 구리(Cu) 또는 얼로이(alloy) 42 등으로 형성되어 있다. 또한, 상기 본드핑거(24a) 및 볼랜드(24b)를 제외한 회로패턴(24)은 커버코트(26) 등으로 코팅되어 외부 환경으로부터 보호되도록 되어 있다.The circuit board 20 is bonded to the bottom surface of the first semiconductor chip 2 by the bonding means 6. As is well known, the circuit board 20 includes a plurality of conductive circuit patterns 24 including bond fingers 24a on the outer circumference of the first semiconductor chip 2 about the resin layer 22. Formed. Further, a plurality of conductive circuit patterns 24 including the ball lands 24b are formed on the bottom surface of the resin layer 22. The bond finger 24a is plated with silver (Ag) or gold (Au) to improve bonding strength with the conductive wire later, and the bonding force with the conductive ball 40 is further improved with the ball land 24b. Silver (Ag), nickel (Ni), palladium (Pd), and the like are plated for the purpose. In addition, the circuit pattern 24 including the bond finger 24a and the borland 24b is formed of copper (Cu), alloy 42, or the like. In addition, the circuit pattern 24 except for the bond finger 24a and the borland 24b is coated with a cover coat 26 or the like so as to be protected from the external environment.
여기서, 상기 본드핑거(24a)를 포함하는 회로패턴(24)과 볼랜드(24b)를 포함하는 회로패턴(24)은 수지층(22)을 관통하는 도전성 비어홀(25)에 의해 상호 연결되어 있다.Here, the circuit pattern 24 including the bond finger 24a and the circuit pattern 24 including the borland 24b are connected to each other by conductive via holes 25 passing through the resin layer 22.
계속해서, 상기 제1반도체칩(2)의 입출력패드(2a)와 상기 본드 핑거(24a)는 대략 1.0 mil 이하의 비교적 작은 두께를 갖는 바텀 와이어(8b)에 의해 상호 전기적으로 접속되어 있다. 또한, 상기 제2반도체칩(4)의 입출력패드(2a,4a)는 대략 1.2 mil 이상의 상기 바텀 와이어보다는 두꺼운 두께를 갖는 탑 와이어(8a)에 의해 본드핑거(24a)에 접속되어 있다.Subsequently, the input / output pad 2a of the first semiconductor chip 2 and the bond finger 24a are electrically connected to each other by a bottom wire 8b having a relatively small thickness of about 1.0 mil or less. In addition, the input / output pads 2a and 4a of the second semiconductor chip 4 are connected to the bond finger 24a by a top wire 8a having a thickness thicker than that of the bottom wire of about 1.2 mil or more.
계속해서, 상기 제1반도체칩(2), 제2반도체칩(4) 및 다수의 탑 및 바텀 와이어(8a,8b)와 본드핑거(24a) 등을 포함하는 회로기판(20)의 일면은 에폭시 몰딩 컴파운드 또는 액상 봉지재 등의 봉지재(30)로 봉지되어 있다.Subsequently, one surface of the circuit board 20 including the first semiconductor chip 2, the second semiconductor chip 4, and a plurality of top and bottom wires 8a and 8b, a bond finger 24a, and the like is epoxy. It is sealed by the sealing material 30, such as a molding compound or a liquid sealing material.
또한, 상기 회로기판(20)의 저면에 구비된 회로패턴(24)중 볼랜드(24b)에 솔더볼과 같은 다수의 도전성볼(40)이 융착되어 차후 마더보드에 실장가능하게 되어 있다.In addition, a plurality of conductive balls 40 such as solder balls are fused to the ball lands 24b of the circuit patterns 24 provided on the bottom surface of the circuit board 20 to be mounted on the motherboard later.
여기서, 본 발명의 실시예에 있어서는, 제 1 및 제 2 반도체 칩을 수직으로 적층한 구조에 대해서만 설명하였지만, 2개 이상의 반도체 칩을 수직으로 적층할 수 있음은 물론이다.Here, in the embodiment of the present invention, only the structure in which the first and second semiconductor chips are vertically stacked is described, but it goes without saying that two or more semiconductor chips can be vertically stacked.
따라서, 상술한 바와 같이, 바텀 와이어(8b)를 1.0 mil의 비교적 얇은 두께로 와이어 본딩함으로써 바텀 와이어의 루프(loop)의 높이를 낮게함과 동시에, 탑 와이어(8a)의 두께를 1.2 mil 이상의 비교적 두꺼운 두께로 와이어 본딩함으로써 스위핑에 좋은 강도를 가지면서 그 루프 높이를 높임으로써 탑 와이어와 바텀와이의 갭(gab)을 최대한 확보하게 되어, 제조공정시, 특히 몰딩고정의 몰드 주입시에상부의 탑 몰드가 몰딩 주입력에 의한 스위핑에 견고히 지탱될 수 있고, 이것에 의해 와이어 쇼트를 방지할 수가 있게 된다.Therefore, as described above, the bottom wire 8b is wire-bonded to a relatively thin thickness of 1.0 mil, thereby lowering the height of the loop of the bottom wire and at the same time, the top wire 8a having a thickness of 1.2 mil or more. By thick wire bonding, it has good strength for sweeping and increases the loop height to maximize the gap between the top wire and the bottom wire.In the manufacturing process, especially during mold injection of molding fixing, The mold can be firmly supported by sweeping by the molding injection force, thereby making it possible to prevent wire shorting.
여기서, 상기 반도체패키지는 일반적인 인쇄회로기판이 포함된 것에 한하여 설명하였지만 이것으로 한정되는 것은 아니다. 즉, 상기 회로기판은 수지층과 회로패턴 등으로 구성되는 써킷필름을 이용할 수도 있고 심지어 리드프레임을 이용할 수도 있다.Here, the semiconductor package has been described as long as a general printed circuit board is included, but is not limited thereto. That is, the circuit board may use a circuit film composed of a resin layer, a circuit pattern, or the like, or may even use a lead frame.
이상에서와 같이 본 발명은 비록 상기의 실시예에 한하여 설명하였지만 여기에만 한정되지 않으며, 본 발명의 범주 및 사상을 벗어나지 않는 범위내에서 여러가지로 변형된 실시예도 가능할 것이다.As described above, although the present invention has been described with reference to the above embodiments, the present invention is not limited thereto, and various modified embodiments may be possible without departing from the scope and spirit of the present invention.
이와 같이 하여 본 발명에 의한 와이어 본딩 방법 및 이를 이용한 반도체패키지에 의하면, 반도체칩이 수직방향으로 다수개로 적층되어 탑 와이와 바텀 와이어의 접속에 의해 상호 신호 교환이 이루어지는 반도체 패키지에서 상기 탑 와이어를 바텀 와이어 보다 강성이 크고 두께를 뚜껍게 형성하여 상기 탑 와이어와 바터 와이어의 갭을 최대한 확보하는 것에 의해, 몰딩 공정시 스위핑에 의한 와이어 쇼트를 방지할 수 있는 효과가 있다.As described above, according to the wire bonding method and the semiconductor package using the same according to the present invention, a plurality of semiconductor chips are stacked in a vertical direction, and the top wire is bottomed in a semiconductor package in which signal exchange is performed by connecting top wires and bottom wires. By forming a rigidity thicker than the wire and making the thickness thicker to secure the gap between the top wire and the barter wire as much as possible, there is an effect of preventing wire shorting due to sweeping during the molding process.
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| KR10-2000-0076328A KR100394775B1 (en) | 2000-12-14 | 2000-12-14 | wire bonding method and semiconductor package using it |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100871709B1 (en) * | 2007-04-10 | 2008-12-08 | 삼성전자주식회사 | Chip stack package and method of fabricating the same |
| CN108878408A (en) * | 2017-05-10 | 2018-11-23 | 叶秀慧 | It is thinned the encapsulating structure that splices of dual chip |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04221837A (en) * | 1990-12-21 | 1992-08-12 | Mitsubishi Electric Corp | Semiconductor device |
| KR930011182A (en) * | 1991-11-13 | 1993-06-23 | 김광호 | Semiconductor device and manufacturing method thereof |
| JPH0697218A (en) * | 1992-09-14 | 1994-04-08 | Hitachi Ltd | Semiconductor device |
| JPH10135399A (en) * | 1996-10-31 | 1998-05-22 | Hitachi Ltd | Semiconductor device, manufacture thereof and lead frame using it |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100871709B1 (en) * | 2007-04-10 | 2008-12-08 | 삼성전자주식회사 | Chip stack package and method of fabricating the same |
| US7948089B2 (en) | 2007-04-10 | 2011-05-24 | Samsung Electronics Co., Ltd. | Chip stack package and method of fabricating the same |
| CN108878408A (en) * | 2017-05-10 | 2018-11-23 | 叶秀慧 | It is thinned the encapsulating structure that splices of dual chip |
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| Publication number | Publication date |
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| KR100394775B1 (en) | 2003-08-19 |
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