KR20020043671A - Warpage reduction structure of heat sink for manufacturing semiconductor package - Google Patents

Warpage reduction structure of heat sink for manufacturing semiconductor package Download PDF

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Publication number
KR20020043671A
KR20020043671A KR1020000072715A KR20000072715A KR20020043671A KR 20020043671 A KR20020043671 A KR 20020043671A KR 1020000072715 A KR1020000072715 A KR 1020000072715A KR 20000072715 A KR20000072715 A KR 20000072715A KR 20020043671 A KR20020043671 A KR 20020043671A
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South Korea
Prior art keywords
heat sink
warpage
semiconductor package
laser
occurs
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KR1020000072715A
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Korean (ko)
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조응산
이재진
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마이클 디. 오브라이언
앰코 테크놀로지 코리아 주식회사
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Priority to KR1020000072715A priority Critical patent/KR20020043671A/en
Publication of KR20020043671A publication Critical patent/KR20020043671A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3736—Metallic materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

PURPOSE: A structure for reducing warpage of a heat sink for fabricating a semiconductor package is provided to prevent a defect of the semiconductor package caused by warpage of the heat sink, by preventing a delamination phenomenon between the heat sink and an adhesive unit or between semiconductor chips. CONSTITUTION: A surface hardening layer is formed on the surface of the heat sink(10) where the warpage occurs, by a laser hardening method. Heterogeneous metal(16) of which the thermal expansion coefficient is low is claded on a portion where the warpage of the heat sink occurs, by a laser clading method.

Description

반도체 패키지 제조용 히트싱크의 워피지 감소 구조{Warpage reduction structure of heat sink for manufacturing semiconductor package}Warpage reduction structure of heat sink for manufacturing semiconductor package

본 발명은 반도체 패키지 제조용 히트싱크의 워피지 감소 구조에 관한 것으로서, 더욱 상세하게는 히트싱크가 적용된 패키지에서 히트싱크와 반도체 칩과 이들을 부착시키고 있는 접착수단등의 열팽창계수가 서로 달라서 발생하는 박리현상을 방지할 수 있도록 한 반도체 패키지 제조용 히트싱크의 워피지 감소 구조에 관한 것이다.The present invention relates to a warpage reduction structure of a heat sink for manufacturing a semiconductor package, and more particularly, a peeling phenomenon caused by different thermal expansion coefficients of a heat sink, a semiconductor chip, and an adhesive means for attaching them to the heat sink package. The present invention relates to a warpage reducing structure of a heat sink for manufacturing a semiconductor package.

일반적으로 반도체 패키지는 리드프레임, 인쇄회로기판, 회로필름등의 각종부재를 사용하여, 열방출 성능을 향상시킬 수 있고, 칩의 크기에 가깝게 경박단소화를 실현할 수 있으며, 입출력 단자수를 증가시킬 수 있는 등 여러가지 형태로 성능 향상에 기여할 수 있는 구조로 제조되고 있다.In general, a semiconductor package uses various members such as a lead frame, a printed circuit board, and a circuit film to improve heat dissipation performance, to realize light and thin shortening close to the size of a chip, and to increase the number of input / output terminals. It is manufactured in a structure that can contribute to performance improvement in various forms.

상기 열방출 성능을 극대화하기 위한 패키지로서, 소정의 면적과 두께를 갖는 동재질의 히트싱크상에 반도체 칩을 접착수단으로 직접 실장한 구조의 반도체 패키지가 있다.As a package for maximizing the heat dissipation performance, there is a semiconductor package having a structure in which a semiconductor chip is directly mounted by an adhesive means on a heat sink of the same material having a predetermined area and thickness.

여기서, 상기 히트싱크를 이용한 반도체 패키지의 일례를 첨부한 도 2를 참조로 설명하면 다음과 같다.Here, an example of a semiconductor package using the heat sink will be described with reference to FIG. 2.

소정의 크기와 두께를 갖으며 상면 중앙에는 칩 부착용 홈(34)이 에칭 처리에 의하여 형성된 동재질의 히트싱크(10)와; 상기 칩 부착용 홈(34)을 제외한 히트싱크(10)의 표면에 접착수단(22)으로 부착된 회로필름(18)과; 상기 히트싱크(10)의 칩 부착용 홈(34)에 접착수단(22)에 의하여 부착된 반도체 칩(20)과; 상기 반도체 칩(20)의 본딩패드와 상기 회로필름(18)의 와이어 본딩용 전도성패턴간에 연결된 와이어(24)와; 상기 반도체 칩(20)과, 와이어(24)와, 와이어 본딩용 전도성패턴등을 인캡슐레이션 하고 있는 코팅재(26)와; 상기 회로필름(18)의 인출단자 부착용 전도성패턴에 융착된 전도성의 솔더볼(32)로 구성되어 있다.A heat sink 10 of the same material having a predetermined size and thickness and having a chip attaching groove 34 formed in the center of the upper surface by etching; A circuit film 18 attached to the surface of the heat sink 10 except for the chip attaching groove 34 by an adhesive means 22; A semiconductor chip 20 attached to the chip attaching groove 34 of the heat sink 10 by an adhesive means 22; A wire 24 connected between the bonding pad of the semiconductor chip 20 and the conductive pattern for wire bonding of the circuit film 18; A coating material 26 encapsulating the semiconductor chip 20, the wire 24, and a conductive pattern for wire bonding; Consists of a conductive solder ball 32 fused to the conductive pattern for attaching the lead terminal of the circuit film 18.

이때, 상기 회로필름(18)은 베이스층으로서 절연체인 수지필름(28)과; 이 수지필름(28)상에 에칭 처리된 전도성패턴(30)과; 이 전도성패턴(30)들중 와이어 본딩용과 인출단자 부착용 전도성패턴을 노출시키면서 수지필름(28)상에 도포된 커버코트(36)로 구성되어 있다.At this time, the circuit film 18 includes a resin film 28 which is an insulator as a base layer; A conductive pattern 30 etched on the resin film 28; The conductive pattern 30 is composed of a cover coat 36 coated on the resin film 28 while exposing a conductive pattern for wire bonding and a lead terminal attachment.

상기와 같이, 히트싱크를 이용한 반도체 패키지(100)는 그 열방출 성능이 우수하지만, 다음과 같은 문제점을 발생시켜 왔다.As described above, the semiconductor package 100 using the heat sink is excellent in heat dissipation performance, but has caused the following problems.

대개, 상기 히트싱크와 주변의 회로필름과 접착수단등은 반도체 패키지 제조공정시 제조장비들로부터 열을 전달받게 되고, 또한 완성된 반도체 패키지를 전자기기의 마더보드에 실장 후, 전기적인 작동을 의하여 발생되는 반도체 칩의 높은 열을 전달받게 된다.Usually, the heat sink and the surrounding circuit film and the adhesive means receive heat from the manufacturing equipment during the semiconductor package manufacturing process, and after mounting the completed semiconductor package on the motherboard of the electronic device, The high heat of the semiconductor chip is generated.

이때, 상기 히트싱크와, 반도체 칩과, 이것들을 부착하고 있는 접착수단과, 회로필름등은 서로간의 열팽창계수(CTE: Coefficient of Thermal Expantion)가 달라서, 서로 다른 열적 팽창과 수축을 반복하며 워피지(Warpage:휨)와 같은 변형을 일으키게 된다.At this time, the heat sink, the semiconductor chip, the bonding means attaching them, the circuit film, and the like have different coefficients of thermal expansion (CTE), so that the thermal expansion and contraction are repeated differently. (Warpage) will cause deformation.

특히, 상기 히트싱크의 열팽창계수가 가장 크기 때문에, 워피지 변형이 가장 심하게 일어나는데, 첨부한 도 3a,3b에 도시한 바와 같이 모서리 부분에서 워피지가 가장 심하게 일어난다.In particular, since the thermal expansion coefficient of the heat sink is the largest, warpage deformation occurs most severely, and warpage occurs most severely in the corner portion as shown in FIGS. 3A and 3B.

상기 히트싱크의 워피지는 제조공정시 인캡슐레이션 불량등 기타 공정상의불량을 초래하는 원인이 되어 왔고, 또한 반도체 칩을 부착하고 있는 접착수단과 서로 박리되는 현상을 일으킴에 따라, 결국 반도체 패키지의 불량을 초래하는 문제점이 있었다.The warpage of the heat sink has been a cause of other process defects such as poor encapsulation during the manufacturing process, and also causes a phenomenon in which the semiconductor package is separated from the adhesive means to which the semiconductor chip is attached. There was a problem that caused.

따라서, 본 발명은 상기와 같은 문제점을 감안하여, 히트싱크의 워피지 현상을 현격히 감소시킬 수 있도록 한 반도체 패키지 제조용 히트싱크의 워피지 감소 구조를 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a warpage reduction structure of a heat sink for manufacturing a semiconductor package in which the warpage phenomenon of the heat sink can be significantly reduced in view of the above problems.

도 1a,1b는 본 발명에 따른 히트싱크상에 워피지 감소 영역을 형성하는 방법과, 이 방법에 의하여 히트싱크상의 위피지 감소 구조가 형성된 상태를 나타내는 일부 단면 사시도,1A and 1B are partial cross-sectional perspective views showing a method of forming a warpage reducing region on a heat sink according to the present invention, and a state in which a stomach paper reducing structure is formed on a heat sink by the method;

도 2는 본 발명이 적용되는 반도체 패키지를 나타내는 단면도,2 is a cross-sectional view showing a semiconductor package to which the present invention is applied;

도 3a,3b는 종래에 히트싱크의 워피지가 발생하는 것을 보여주는 도면.3a and 3b show that warpage of a heat sink occurs in the related art.

<도면의 주요 부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>

10 : 히트싱크12 : 레이져 가공수단10 heat sink 12 laser processing means

14 : 표면경화층16 : 이종금속14 surface hardening layer 16 dissimilar metal

18 : 회로필름20 : 반도체 칩18: circuit film 20: semiconductor chip

22 : 접착수단100 : 반도체 패키지22: bonding means 100: semiconductor package

상기한 목적을 달성하기 위한 본 발명은:The present invention for achieving the above object is:

반도체 패키지 제조용 히트싱크에 있어서,In the heat sink for manufacturing a semiconductor package,

상기 히트싱크의 워피지가 일어나는 표면에 레이져 하드닝에 의한 표면 경화층을 형성한 것을 특징으로 한다.A surface hardened layer formed by laser hardening is formed on the surface where warpage of the heat sink occurs.

바람직한 구현예로서, 상기 히트싱크의 워피지가 일어나는 부분에 열팽창계수가 낮은 이종금속을 레이져 크래딩으로 입혀준 것을 특징으로 한다.In a preferred embodiment, a dissimilar metal having a low coefficient of thermal expansion is coated with a laser cladding on a part of the heat sink in which the warpage occurs.

여기서 본 발명의 실시예를 첨부한 도면에 의거하여 보다 상세하게 설명하면 다음과 같다.Hereinafter, the embodiments of the present invention will be described in detail with reference to the accompanying drawings.

상기 히트싱크(10)는 반도체 패키지의 열방출 성능을 향상시키기 위하여 적용된 부재의 일종으로 소정의 면적과 두께를 갖도록 성형된 것으로서, 상술한 바와같이, 상기 히트싱크(10)는 열적 요인에 의하여 모서리부분에서 워피지가 가장 크게 발생하고 있다.The heat sink 10 is a member applied to improve the heat dissipation performance of the semiconductor package and is molded to have a predetermined area and thickness. As described above, the heat sink 10 has a corner due to thermal factors. In the part, warpage occurs the most.

따라서, 본 발명은 상기 히트싱크(10)의 워피지가 가장 심하게 일어나는 모서리 부분을 워피지가 감소될 수 있는 구조로 변경함에 그 목적이 있는 것이다.Therefore, an object of the present invention is to change the corner portion where the warpage of the heat sink 10 occurs most severely into a structure in which the warpage can be reduced.

이에, 첨부한 도 1a에 도시한 바와 같이 레이져 하드닝 방법을 사용하여, 워피지가 심하게 일어나는 히트싱크의 모서리 부분에 표면 경화층을 형성하여, 경도를 높여주게 된다.Thus, by using the laser hardening method as shown in Fig. 1A, a surface hardened layer is formed on the edge portion of the heat sink in which warpage occurs badly, thereby increasing the hardness.

좀 더 상세하게는, 워피지가 일어나는 히트싱크(10)의 표면 위에 레이져 가공수단(12)을 위치시키고, 레이져를 조사하여 줌으로써, 일종의 열처리 효과에 의하여 단단한 조직을 갖는 표면경화층(14)이 형성된다.More specifically, by placing the laser processing means 12 on the surface of the heat sink 10 where warpage occurs and irradiating the laser, the surface hardening layer 14 having a hard structure by a kind of heat treatment effect is formed. Is formed.

일반적으로 금속의 경도를 높여주게 되면, 열팽창계수가 낮아지기 때문에, 상기와 같이 히트싱크(10)의 모서리 부분에 대한 경도를 높여줌에 따라, 열적 변형에 의한 히트싱크(10)의 워피지를 크게 감소시킬 수 있게 된다.In general, when the hardness of the metal is increased, the coefficient of thermal expansion is lowered. As the hardness of the edge of the heat sink 10 is increased as described above, the warpage of the heat sink 10 due to thermal deformation is greatly reduced. You can do it.

또 다른 실시예로서, 첨부한 도 1b에 도시한 바와 같이 레이져 크래딩 방법을 사용하여, 워피지가 가장 심하게 일어나는 히트싱크(10)의 모서리 부분에 대하여 이종(異種)금속(16)을 입혀주게 된다.As another example, using a laser cladding method as shown in FIG. 1B to attach dissimilar metals 16 to the edge portions of the heat sink 10 where warpage occurs most severely. do.

보다 상세하게는, 상기 워피지가 심하게 일어나는 히트싱크(10)의 표면에 레이져 가공수단(12)을 위치시키는 동시에 그 옆으로 이종금속 분말을 제공하는 수단(미도시됨)과 연결된 노즐(38)을 위치시킨 다음, 이 노즐(38)을 통하여 이종금속 분말을 제공하는 동시에 레이져을 조사함으로써, 이종금속(16)이 용융되면서 히트싱크(10)의 표면에 입혀지게 된다More specifically, the nozzle 38 is connected to a means (not shown) for placing the laser processing means 12 on the surface of the heat sink 10 in which the warpage is severely generated and at the same time providing dissimilar metal powder. And then irradiate the laser while simultaneously providing the dissimilar metal powder through the nozzle 38, the dissimilar metal 16 is melted and coated on the surface of the heat sink 10.

상기 이종금속(16)은 동 재질의 히트싱크(10)가 보유한 열팽창계수보다 휠씬 낮은 열팽창계수를 갖으며, 열전도성이 우수한 것중 어느 하나를 선택하여 사용함이 바람직하다.The dissimilar metal 16 has a thermal expansion coefficient that is much lower than that of the heat sink 10 of the copper material, and is preferably selected from one of those having excellent thermal conductivity.

따라서, 상기 히트싱크(10)의 모서리 부분에 열팽창계수가 보다 낮은 이종금속(16)을 입혀줌으로써, 히트싱크(10)의 워피지를 크게 감소시킬 수 있게 된다.Therefore, by applying a dissimilar metal 16 having a lower coefficient of thermal expansion to the edge portion of the heat sink 10, the warpage of the heat sink 10 can be greatly reduced.

한편, 상기 히트싱크(10)의 전체적인 형상이 변경되지 않도록 상기 이종금속을 입힐 때는 히트싱크(10)면을 레이져로 파내는 가공을 한 후, 이종금속(16)을 입혀줌으로써, 이종금속(16)이 히트싱크의 표면과 평행을 이루도록 함이 바람직하다.On the other hand, when the dissimilar metal is coated so that the overall shape of the heat sink 10 is not changed, after digging the surface of the heat sink 10 with a laser, the dissimilar metal 16 is coated by coating a dissimilar metal 16. It is preferable to make it parallel with the surface of this heat sink.

이에따라, 상기 표면경화층(14)이 형성되거나 또는 이종금속(16)이 입혀진 히트싱크(10)가 반도체 패키지에 적용되면, 상기 히트싱크(10)의 워피지가 크게 감소함에 따라, 반도체 칩과 접착수단과의 박리현상을 방지할 수 있게 된다.Accordingly, when the surface hardening layer 14 is formed or the heat sink 10 coated with the dissimilar metal 16 is applied to the semiconductor package, as the warpage of the heat sink 10 is greatly reduced, the semiconductor chip and Peeling phenomenon with the bonding means can be prevented.

이상에서 본 바와 같이, 본 발명에 따른 반도체 패키지 제조용 히트싱크의 워피지 감소 구조에 의하면, 히트싱크의 워피지가 가장 심하게 일어나는 부분의 표면에 레이져 하드닝 방법에 의한 표면경화층을 형성하여 경도를 높여주거나, 열팽창계수가 낮은 이종금속을 레이져 크래딩 방법으로 입혀줌으로써, 히트싱크의 워피지를 감소시킬 수 있고, 그에따라 히트싱크와 접착수단 또는 반도체 칩간의 박리현상을 방지시킬 수 있어, 결국 히트싱크의 워피지에 의한 반도체 패키지의 불량을배제시킬 수 있는 장점이 있다.As described above, according to the warpage reduction structure of the heat sink for semiconductor package manufacture according to the present invention, the surface hardening layer is formed on the surface of the portion where the warpage of the heat sink occurs most severely by the laser hardening method to improve hardness. Increasing or coating a dissimilar metal with a low coefficient of thermal expansion using a laser cladding method can reduce the warpage of the heat sink, thereby preventing the peeling phenomenon between the heat sink and the adhesive means or the semiconductor chip. There is an advantage that can be eliminated the defect of the semiconductor package by the warpage of the sink.

Claims (2)

반도체 패키지 제조용 히트싱크에 있어서,In the heat sink for manufacturing a semiconductor package, 상기 히트싱크의 워피지가 일어나는 표면에 레이져 하드닝에 의한 표면 경화층을 형성한 것을 특징으로 하는 반도체 패키지 제조용 히트싱크의 워피지 감소 구조.A surface hardening layer formed by laser hardening is formed on a surface on which the warpage of the heat sink occurs, wherein the warpage reducing structure of the heat sink for manufacturing a semiconductor package is used. 제 1 항에 있어서, 상기 히트싱크의 워피지가 일어나는 부분에 열팽창계수가 낮은 이종금속을 레이져 크래딩으로 입혀준 것을 특징으로 하는 반도체 패키지 제조용 히트싱크의 워피지 감소 구조.2. The warpage reducing structure of a heat sink for manufacturing a semiconductor package according to claim 1, wherein a dissimilar metal having a low coefficient of thermal expansion is coated with a laser cladding on the warpage portion of the heat sink.
KR1020000072715A 2000-12-02 2000-12-02 Warpage reduction structure of heat sink for manufacturing semiconductor package KR20020043671A (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54152865A (en) * 1978-05-23 1979-12-01 Toshiba Corp Manufacture of semiconductor device
JPH04155945A (en) * 1990-10-19 1992-05-28 Nec Kyushu Ltd Lead frame for semiconductor device
KR950007041A (en) * 1993-08-18 1995-03-21 황인길 Reduction of warpage of integrated circuit packages
KR19980044241A (en) * 1996-12-06 1998-09-05 황인길 Bending prevention structure of semiconductor package

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54152865A (en) * 1978-05-23 1979-12-01 Toshiba Corp Manufacture of semiconductor device
JPH04155945A (en) * 1990-10-19 1992-05-28 Nec Kyushu Ltd Lead frame for semiconductor device
KR950007041A (en) * 1993-08-18 1995-03-21 황인길 Reduction of warpage of integrated circuit packages
KR19980044241A (en) * 1996-12-06 1998-09-05 황인길 Bending prevention structure of semiconductor package

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