KR20020038250A - Method of manufacturing a capacitor in semiconductor device - Google Patents
Method of manufacturing a capacitor in semiconductor device Download PDFInfo
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- KR20020038250A KR20020038250A KR1020000068355A KR20000068355A KR20020038250A KR 20020038250 A KR20020038250 A KR 20020038250A KR 1020000068355 A KR1020000068355 A KR 1020000068355A KR 20000068355 A KR20000068355 A KR 20000068355A KR 20020038250 A KR20020038250 A KR 20020038250A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by physical means, e.g. sputtering, evaporation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
Abstract
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로서, 특히 MIM(Metal-Insulator-Metal)구조의 캐패시터 제조시 하부전극으로 금속계열의 물질을 사용할 경우, 콘택플러그를 구성하는 확산방지막을 형성하기 전에 확산방지막과 오믹콘택층 간에 형성된 산화물을 NH3가스를 이용한 급속 열처리 공정으로 질화시켜 질화물로 변화시키고 그 상에 확산방지막을 층작함으로써, 확산방지막과 오믹콘택층의 계면 접촉저항을 감소시킴과 아울러 콘택플러그의 접촉저항을 감소시켜 캐패시터의 전기적 특성을 개선시킬 수 있는 반도체 소자의 캐패시터 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, when a metal-based material is used as a lower electrode when manufacturing a capacitor having a metal-insulator-metal (MIM) structure, the diffusion barrier layer is formed before forming a diffusion barrier layer constituting a contact plug. Oxide formed between the ohmic contact layer and the ohmic contact layer was nitrided by a rapid heat treatment process using NH 3 gas to convert into a nitride, and the diffusion barrier layer was deposited thereon, thereby reducing the interfacial contact resistance between the diffusion barrier layer and the ohmic contact layer. The present invention relates to a method for manufacturing a capacitor of a semiconductor device capable of reducing the contact resistance to improve the electrical characteristics of the capacitor.
통상, DRAM 소자에 이용되는 캐패시터의 유전체 박막으로는 SiO2/Si3N4/SiO2적층구조가 많이 이용되고 있다. 그러나, 최근에는 고유전율과 저누설전류의 캐패시터를 구현함과 아울러 캐패시터 제조공정의 단순화를 들어 Ta2O5를 이용한 단층구조로 바뀌고 있는 추세이다.In general, a SiO 2 / Si 3 N 4 / SiO 2 stacked structure is widely used as a dielectric thin film of a capacitor used in a DRAM device. However, in recent years, a capacitor having a high dielectric constant and low leakage current and a simplified capacitor manufacturing process have been shifting to a single layer structure using Ta 2 O 5 .
Ta2O5를 이용한 캐패시터는 급속열처리공정(RTN)으로 표면처리된 폴리실리콘(Poly-Si)을 하부전극으로 사용하고 있다. 여기서, Ta205를 이용한 캐패시터가 안정되게 동작되기 위해서는 하부전극으로 사용되는 폴리실리콘이 30Å 정도의 두께로 형성되어야만 한다. 그러나, 반도체 소자가 고집적화 됨에 따라 안정된 반도체 소자의 동작을 위해 큰 정전용량이 필요한 반면에 캐패시터의 크기는 소형화되어야 한다. 이로 인해, Ta2O5를 이용한 캐패시터의 하부전극은 폴리실리콘 대신 금속계물질을 도입하여 유효산화막의 두께를 줄이는 방법이 시도되고 있다.The capacitor using Ta 2 O 5 uses polysilicon (Poly-Si) surface-treated by a rapid heat treatment (RTN) as a lower electrode. Here, in order for the capacitor using Ta 2 0 5 to be stably operated, polysilicon used as the lower electrode should be formed to a thickness of about 30 μs. However, as semiconductor devices are highly integrated, large capacitances are required for stable operation of semiconductor devices, while capacitors must be miniaturized. For this reason, a method of reducing the thickness of the effective oxide film by introducing a metal-based material instead of polysilicon for the lower electrode of the capacitor using Ta 2 O 5 has been attempted.
캐패시터의 하부전극으로 금속계물질를 사용할 경우에는 하부전극의 열처리 공정시 발생하는 콘택플러그의 산화를 방지하기 위해 하부전극과 콘택플러그 간에 산화방지막을 형성하는 공정이 필요하게 된다. 이와 같은 이유로, 금속계 하부전극을 사용하는 반도체 소자의 콘택플러그로는 폴리실리콘, TiSi2로 구성된 오믹콘택층, TiN으로 구성된 확산방지막이 순차적으로 형성된 구조로 이루어진다.In the case of using a metal-based material as the lower electrode of the capacitor, a process of forming an anti-oxidation film between the lower electrode and the contact plug is required to prevent oxidation of the contact plug generated during the heat treatment process of the lower electrode. For this reason, the contact plug of the semiconductor device using the metal-based lower electrode has a structure in which polysilicon, an ohmic contact layer composed of TiSi 2 , and a diffusion barrier formed of TiN are sequentially formed.
이러한 반도체 소자의 제조 공정을 간략하게 설명하면, 우선 콘택플러그를 형성하는 폴리실리콘은 반도체 기판 상부의 소정 부위에 화학기상증착법에 의해 증착된 후, 화학적기계연마법(CMP) 또는 에치백(Etch Back)을 이용한 평탄화공정에 의해 패터닝되어 반도체 기판 상부에 소정 형태로 형성된다. 이어서, 폴리실리콘을 포함한 전체 구조 상부에는 Ti가 물리기상증착법(PVD) 또는 화학기상증착법(CVD)에 의해 증착된 후, 급속열처리공정(RTN) 또는 퍼니스(furnace)를 이용한 열처리공정에 의해 열처리된다. 이때, 폴리실리콘 상부에는 자신의 상부에 증착된 Ti와 반응하여 TiSi2의 오믹콘택층이 형성됨과 아울러 오믹콘택층 상부에는 산소와 Ti가 반응한 산화물(TiO, TiO2)과 미반응된 Ti가 형성된다. 또한, 폴리실리콘이 형성된 부위를 제외한 반도체 기판 상부(예를 들면, SiO2로 구성된 층간절연막)에는 산소와 Ti가 반응하여 산화물(TiO, TiO2)이 형성됨과 아울러 미반응된 Ti가 잔재하게 된다.Briefly describing the manufacturing process of the semiconductor device, first, the polysilicon forming the contact plug is deposited by chemical vapor deposition on a predetermined portion of the upper surface of the semiconductor substrate, followed by chemical mechanical polishing (CMP) or etch back (Etch Back). It is patterned by a planarization process using the semiconductor substrate to form a predetermined shape on the semiconductor substrate. Subsequently, Ti is deposited on the entire structure including polysilicon by physical vapor deposition (PVD) or chemical vapor deposition (CVD), followed by heat treatment using a rapid thermal treatment (RTN) or a furnace (furnace). . At this time, an ohmic contact layer of TiSi 2 is formed by reacting with Ti deposited on the upper portion of the polysilicon, and an oxide (TiO, TiO 2 ) and unreacted Ti react with oxygen and Ti on the ohmic contact layer. Is formed. In addition, oxygen and Ti react to form oxides (TiO, TiO 2 ) and remain unreacted Ti on the upper portion of the semiconductor substrate (for example, an interlayer insulating layer composed of SiO 2 ) except for the portion where polysilicon is formed. .
이는, 전체 구조 상부에 Ti를 증착한 후, 시행하는 열처리공정중 미량의 산소(O)에 의해 생성되기 때문이다. 즉, 이 산소에 의해 오믹콘택층 상부 표면에는 Ti와 산소가 반응하여 산화물(TiO, TiO2)이 형성되고, 층간절연막 상부에는 자신과 산소가 반응하여 산화물(SiO, SiO2)이 형성된다.This is because a small amount of oxygen (O) is generated during the heat treatment process performed after depositing Ti on the entire structure. That is, the oxygen (TiO, TiO 2 ) is formed by reacting Ti and oxygen on the upper surface of the ohmic contact layer by the oxygen, and the oxides (SiO, SiO 2 ) are formed by reacting oxygen with itself on the interlayer insulating film.
이어서, 오믹콘택층 상부에 잔재하는 산화물(TiO, TiO2)과 층간절연막 상부에 잔재하는 미반응 Ti 및 산화물(SiO, SiO2)을 제거하기 위한 소정의 세정공정이 시행된다. 그러나, 지금의 세정공정후 확산방지막 TiN을 증착하는 공정으로는 오믹콘택층 상부에 잔재하는 산화물(TiO, TiO2)을 모두 제거하기란 거의 불가능하다. 이로 인해, 오믹콘택층 상부에 TiN의 확산방지막을 증착할 경우, 오믹콘택층과 확산방지막 간에 산화물(TiO, TiO2)이 잔재하게 되어 그 부분의 접촉저항이 증가하게 된다.Subsequently, a predetermined cleaning process is performed to remove oxides (TiO, TiO 2 ) remaining on the ohmic contact layer and unreacted Ti and oxides (SiO, SiO 2 ) remaining on the interlayer insulating film. However, it is almost impossible to remove all the oxides (TiO, TiO 2 ) remaining on the ohmic contact layer in the process of depositing the diffusion barrier TiN after the current cleaning process. Therefore, when TiN diffusion barrier is deposited on the ohmic contact layer, oxides (TiO, TiO 2 ) remain between the ohmic contact layer and the diffusion barrier and the contact resistance of the portion is increased.
이를, 도 1을 결부하여 설명하면, 다음과 같다.This will be described with reference to FIG. 1.
도 1은 콘택플러그(폴리실리콘, 오믹콘택층, 확산방지막)를 형성한 다음, 콘택플러그 내의 깊이 방향 원자함유량(%)을 AES(Auger Electron Spectroscopy)를 이용하여 측정한 결과를 도시한 그래프이다.FIG. 1 is a graph illustrating a result of measuring contact depth (polysilicon, ohmic contact layer, diffusion barrier), and measuring the depth direction atomic content (%) in the contact plug using AES (Auger Electron Spectroscopy).
우선, 도시된 바와 같이 콘택플러그의 최하단부에 형성되는 폴리실리콘(Poly Si)은 Si로 구성되며, 오믹콘택층(TiSi2)과 폴리실리콘 계면에서 폴리실리콘 내부로 들어가며 Ti의 확산에 의한 Ti의 트래스(trace)가 나타나며 깊이에 따라 감소한다.First, as shown, the polysilicon (Poly Si) formed at the lowermost end of the contact plug is composed of Si, and enters into the polysilicon at the interface between the ohmic contact layer (TiSi 2 ) and the polysilicon and the diffusion of Ti by diffusion of Ti. A trace appears and decreases with depth.
이에 반해, 오믹콘택층(TiSi2)은 200Å 이하의 얇은 박막을 형성함으로 깊이 방향의 위치에 따라 원자함유량(%)이 다르게 나타난다. 즉, 폴리실리콘(Poly Si)과 근접한 부위의 오믹콘택층(TiSi2) 내에는 대부분 폴리실리콘(Poly Si)과 동일한 원자인 Si와 Ti로 형성되고, 확산방지막(TiN)과 근접한 부위의 오믹콘택층(TiSi2) 내에는 Si, N, Ti 및 O로 형성된다. 그 구성비는 Ti가 40%, Si가 25%, N가 25%, O가 10%정도의 함유량으로 구성된다. 이와 같이, 확산방지막(TiN)에 근접한 부위의 오믹콘택층(TiSi2) 내에 다량으로 함유된 O는 Ti와 반응하여 산화물(TiO, TiO2)을 형성하게 된다. 이 산화물(TiO, TiO2)은 후속공정인 세정공정에 의해 완전히 제거되지 않고 도시된 바와 같이 확산방지막(TiN)과 오믹콘택층(TiSi2) 간에 다량이 잔재하게 된다.In contrast, the ohmic contact layer TiSi 2 forms a thin film having a thickness of 200 GPa or less, and thus the atomic content (%) is different depending on the position in the depth direction. That is, in the ohmic contact layer (TiSi 2 ) of the region close to the polysilicon (Poly Si) is formed of Si and Ti which are mostly the same atoms as the polysilicon (Poly Si), and the ohmic contact of the region close to the diffusion barrier (TiN) In the layer TiSi 2 , it is formed of Si, N, Ti and O. The composition ratio is 40% of Ti, 25% of Si, 25% of N, and 10% of O. As such, O contained in a large amount in the ohmic contact layer TiSi 2 near the diffusion barrier layer TiN reacts with Ti to form oxides TiO and TiO 2 . The oxides (TiO, TiO 2 ) are not completely removed by a subsequent cleaning process, and a large amount of residues remain between the diffusion barrier layer TiN and the ohmic contact layer TiSi 2 as shown.
이런, 산화물(TiO, TiO2)에 의해 콘택플러그 내의 접촉저항이 증가하게 되어 그 부위의 콘택저항이 증가됨과 아울러 콘택플러그 내의 콘택저항의 증가로 인해 캐패시터와 접합영역(예를 들면, 소오스전극, 드레인전극, 셀영역)간의 도전성이감소하게 된다. 또한, 콘택플러그 내에 형성되는 산화물(TiO, TiO2)로 인해 오믹콘택층과 산화방지막을 전극으로 하는 또 다른 캐패시터가 형성되어 반도체 소자의 전기적특성에 영향을 미치게 된다.The contact resistance in the contact plug is increased by oxides (TiO, TiO 2 ), and the contact resistance of the site is increased and the contact resistance in the contact plug is increased, so that the capacitor and the junction region (for example, source electrode, The conductivity between the drain electrode and the cell region is reduced. In addition, due to the oxides (TiO, TiO 2 ) formed in the contact plug, another capacitor having an ohmic contact layer and an anti-oxidation layer as an electrode is formed to affect the electrical characteristics of the semiconductor device.
따라서, 본 발명은 콘택플러그를 구성하고 있는 오믹콘택층과 확산방지막 간에 형성되는 산화물을 제거하여 콘택플러그의 접촉저항을 감소시키기 위한 반도체 소자의 캐패시터 제조 방법을 제공함에 있다.Accordingly, the present invention provides a method of manufacturing a capacitor of a semiconductor device for reducing the contact resistance of the contact plug by removing the oxide formed between the ohmic contact layer constituting the contact plug and the diffusion barrier.
본 발명의 또 다른 목적은 콘택플러그를 구성하는 확산방지막을 형성하기 전에 확산방지막과 오믹콘택층 간에 형성된 산화물을 NH3가스를 이용한 급속 열처리 공정으로 질화시켜 질화물로 변화시키고 그 상에 확산방지막을 층작함으로써, 확산방지막과 오믹콘택층의 계면 접촉저항을 감소시킴과 아울러 콘택플러그의 접촉저항을 감소시켜 캐패시터의 전기적 특성을 개선시킬 수 있는 반도체 소자의 캐패시터 제조 방법을 제공하는데 있다.Another object of the present invention is to nitrate the oxide formed between the diffusion barrier and the ohmic contact layer by the rapid heat treatment process using NH 3 gas before forming the diffusion barrier constituting the contact plug into a nitride and layering the diffusion barrier thereon Accordingly, the present invention provides a method of manufacturing a capacitor of a semiconductor device capable of reducing the interface contact resistance between the diffusion barrier layer and the ohmic contact layer and reducing the contact resistance of the contact plug to improve the electrical characteristics of the capacitor.
도 1은 콘택플러그 내의 깊이 방향 원자함유량(%)을 AES(Auger Electron Spectroscopy)를 이용하여 측정한 결과를 도시한 그래프.1 is a graph showing the results of measuring the depth direction atomic content (%) in the contact plug using Auger Electron Spectroscopy (AES).
도 2(a) 내지 도 2(c)는 본 발명의 일 실시예에 따른 반도체 소자의 캐패시터 제조 방법을 순서적으로 설명하기 위해 도시한 반도체 소자의 단면도.2 (a) to 2 (c) are cross-sectional views of a semiconductor device shown in order to explain a method of manufacturing a capacitor of a semiconductor device according to an embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
2 : 반도체 기판 3 : 필드산화막2: semiconductor substrate 3: field oxide film
4 : 제 1 접합영역 5 : 게이트전극4: first junction region 5: gate electrode
6 : 게이트산화막 7 : 제 2 접합영역6 gate oxide film 7 second junction region
8 : 도전층 10 : 제 1 층간 절연막8 conductive layer 10 first interlayer insulating film
12 : 비트라인 13 :제 2 층간 절연막12 bit line 13: second interlayer insulating film
14 : 콘택홀 15 : 매립층14 contact hole 15 landfill layer
16 : 오믹콘택층 17 : 질화물16: ohmic contact layer 17: nitride
18 : 확산방지막 19 : 콘택플러그18: diffusion barrier 19: contact plug
20 : 패턴층 21 : 하부전극20: pattern layer 21: lower electrode
22 : 유전체막 23 : 상부전극22 dielectric film 23 upper electrode
본 발명은 소정의 구조가 형성된 반도체 기판 상부에 절연막을 증착한 후 상기 절연막의 소정 영역을 식각하여 상기 반도체 기판의 소정 영역을 노출시키는 콘택홀을 형성하는 단계와; 상기 콘택홀을 소정의 깊이로 매립하도록 매립층을 형성하는 단계와; 상기 매립층 상에 오믹콘택층을 형성하는 단계와; 상기 오믹콘택층을 NH3가스를 이용하여 열처리하는 단계와; 상기 오믹콘택층 상에 확산방지막을 형성하여 상기 콘택홀을 완전히 매립하는 단계와; 상기 전체 구조 상부에 하부전극, 유전체 박막 및 상부전극을 순차적으로 형성하는 단계를 포함한다.The present invention provides a method for manufacturing a semiconductor device, the method comprising: forming a contact hole for exposing a predetermined region of a semiconductor substrate by etching an insulating layer on the semiconductor substrate on which a predetermined structure is formed; Forming a buried layer to fill the contact hole to a predetermined depth; Forming an ohmic contact layer on the buried layer; Heat treating the ohmic contact layer using NH 3 gas; Forming a diffusion barrier on the ohmic contact layer to completely fill the contact hole; And sequentially forming a lower electrode, a dielectric thin film, and an upper electrode on the entire structure.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 2(a) 내지 도 2(c)는 본 발명의 일 실시예에 따른 반도체 소자의 캐패시터 제조 방법을 순서적으로 도시한 단면도이다. 여기서는, 실린더형 캐패시터의 제조 방법에 관해서만 도시하였다.2 (a) to 2 (c) are cross-sectional views sequentially illustrating a method of manufacturing a capacitor of a semiconductor device according to an embodiment of the present invention. Here, only the manufacturing method of a cylindrical capacitor is shown.
도 2(a)를 참조하면, 우선 반도체 기판(2) 상의 소정 영역에 액티브영역과 필드영역을 확정하기 위한 필드산화막(3)이 형성된다. 필드산화막(3)을 포함한 전체 구조 상부에 게이트절연막(6) 및 도전층(8)이 순차적으로 적층된 후, 패터닝되어 게이트전극(5)이 형성된다. 이어서, 이온 주입공정에 의해 반도체 기판(2)의 소정 영역에 제 1 및 제 2 접합영역(4,7)이 형성된다.Referring to FIG. 2A, first, a field oxide film 3 for defining an active region and a field region is formed in a predetermined region on the semiconductor substrate 2. The gate insulating film 6 and the conductive layer 8 are sequentially stacked on the entire structure including the field oxide film 3, and then patterned to form the gate electrode 5. Subsequently, first and second junction regions 4 and 7 are formed in predetermined regions of the semiconductor substrate 2 by an ion implantation process.
전체 구조 상부에 제 1 층간절연막(10)이 형성된 후, 제 1 층간절연막(10)은 제 2 접합영역(7)이 노출되도록 패터닝된다. 제 2 접합영역(7)이 노출되도록 패터닝된 제 1 층간절연막(10)을 매립하도록 전도성 물질이 증착된 후, 패터닝되어 비트라인(12)이 형성된다. 이 비트라인(12)을 포함한 전체 구조 상부에 제 2 층간절연막(13)이 형성된다. 이어서, 소정의 에칭공정을 통해 제 1 접합영역(4)이 제 1및 제 2 층간절연막(10,13)의 소정 부위에 2500∼10000Å의 두께로 콘택홀(14)이 형성된다.After the first interlayer insulating film 10 is formed over the entire structure, the first interlayer insulating film 10 is patterned to expose the second junction region 7. A conductive material is deposited to fill the first interlayer insulating film 10 patterned to expose the second junction region 7, and then patterned to form a bit line 12. The second interlayer insulating film 13 is formed over the entire structure including the bit line 12. Subsequently, a contact hole 14 is formed in the first junction region 4 in a predetermined portion of the first and second interlayer insulating films 10 and 13 with a thickness of 2500 to 10000 kPa through a predetermined etching process.
도 2(b)를 참조하면, 콘택홀(14)을 덮도록 폴리실리콘이 증착된 후, 순차적인 마스크공정과 에치공정에 의해 콘택홀(14)의 상단에서 500∼2000Å의 깊이로 패터닝되어 매립층(15)이 형성된다.Referring to FIG. 2B, after the polysilicon is deposited to cover the contact hole 14, the buried layer is patterned to a depth of 500 to 2000 μs at the upper end of the contact hole 14 by a sequential mask process and an etch process. (15) is formed.
이어서, 매립층(15) 상부에 Ti가 증착된 후, 급속 열처리 공정에 의해 매립층(15)의 폴리실리콘과 Ti가 반응하여 TiSi2의 오믹콘택층(16)이 형성된다. 여기서, 급속 열처리 공정은 N2가스가 100∼1000sccm로 유입된 상태에서 650∼800℃ 온도와 0.2∼1 Torr정도의 압력으로 10∼120초 동안 실시된다.Subsequently, after Ti is deposited on the buried layer 15, polysilicon and Ti of the buried layer 15 react by a rapid heat treatment process to form an ohmic contact layer 16 of TiSi 2 . Here, the rapid heat treatment process is carried out for 10 to 120 seconds at a temperature of 650 ~ 800 ℃ and a pressure of about 0.2 to 1 Torr in the state in which the N 2 gas flowed into 100 ~ 1000sccm.
이런 급속 열처리 공정에 의해 오믹콘택층(16)을 포함한 전체 구조 상부에는 산화물(TiO, TiO2, SiO, SiO2)과 미반응된 Ti의 잔재물이 남게 된다. 이 잔재물은 SC-1 용액을 이용한 세정공정에 의해 소정 양이 제거된다.By such a rapid heat treatment process, oxides (TiO, TiO 2 , SiO, SiO 2 ) and unreacted Ti residues remain on the entire structure including the ohmic contact layer 16. This residue is removed by a washing step using an SC-1 solution.
이때, 세정공정에 의해 제거되지 않은 잔재물및 세정된 TiSi2표면의 대기중 산소(O)와 결합을 방지하기 위해 급속 열처리 공정에 의해 열처리된다. 여기서, 급속 열처리 공정은 NH3가스가 100∼1000sccm으로 유입된 상태에서 600∼850℃ 온도와 0.2∼1Torr 정도의 압력으로 10∼120초 동안 실시된다.At this time, it is heat-treated by a rapid heat treatment process to prevent bonding with the residues not removed by the cleaning process and oxygen (O) in the atmosphere of the cleaned TiSi 2 surface. Here, the rapid heat treatment process is carried out for 10 to 120 seconds at a temperature of 600 ~ 850 ℃ and a pressure of 0.2 ~ 1 Torr in the state in which the NH 3 gas flowed into 100 ~ 1000sccm.
이런 급속 열처리 공정에 의해 잔재물 및 TiSi2표면은 NH3와 반응하여 질화물(17)로 변화하여 오믹콘택층(16) 상부에 형성된다.By the rapid heat treatment process, the residue and the TiSi 2 surface react with NH 3 to be converted into nitride 17 to be formed on the ohmic contact layer 16.
도 2(c)를 참조하면, 질화물(17)를 포함한 전체 구조 상부에는 TiN이 PVD 또는 CVD에 의해 증착된 후, 패터닝되어 500∼2000Å의 두께로 확산방지막(18)이 형성된다. 여기서, 매립층(15), 오믹콘택층(16), 질화물(17) 및 확산방지막(18)은 캐패시터와 제 1 접합영역(4)을 전기적으로 접속하기 위한 콘택플러그(19)로 이용된다.Referring to FIG. 2 (c), TiN is deposited on the entire structure including the nitride 17 by PVD or CVD, and then patterned to form a diffusion barrier film 18 having a thickness of 500 to 2000 mW. Here, the buried layer 15, the ohmic contact layer 16, the nitride 17, and the diffusion barrier 18 are used as a contact plug 19 for electrically connecting the capacitor and the first junction region 4.
이어서, 확산방지막(18)을 포함한 전체 구조 상부에는 하나 이상의 홀을 가진 패턴층(20)이 형성됨과 아울러 패턴층(20)을 덮도록 하부전극(21), 유전체막(22) 및 상부전극(23)이 순차적으로 형성된다. 여기서, 상/하부전극(26,22)은 Pt, Ru 및 Ir과 같은 금속계물질과 IrO2및 TiN과 같은 전도성 산화막중 어느 하나로 설정된다.Subsequently, a pattern layer 20 having one or more holes is formed on the entire structure including the diffusion barrier 18, and the lower electrode 21, the dielectric film 22, and the upper electrode (ie, to cover the pattern layer 20). 23 is formed sequentially. Here, the upper and lower electrodes 26 and 22 are set to any one of a metal-based material such as Pt, Ru, and Ir, and a conductive oxide film such as IrO 2 and TiN.
전술한 바와 같이 본 발명의 일 실시예는 콘택플러그를 구성하는 확산방지막을 형성하기 전에 확산방지막과 오믹콘택층 간에 형성된 산화물을 NH3가스를 이용한 급속 열처리 공정으로 질화시켜 질화물로 변화시키고 그 상에 확산방지막을 층작함으로써, 확산방지막과 오믹콘택층의 계면 접촉저항을 감소시킴과 아울러 콘택플러그의 접촉저항을 감소시켜 캐패시터의 전기적 특성을 개선시킬 수 있다.As described above, in one embodiment of the present invention, an oxide formed between the diffusion barrier layer and the ohmic contact layer is nitrided by a rapid heat treatment process using NH 3 gas before forming the diffusion barrier layer constituting the contact plug, and the nitride is changed to nitride. By layering the diffusion barrier, the contact resistance of the diffusion barrier and the ohmic contact layer can be reduced, and the contact resistance of the contact plug can be reduced to improve the electrical characteristics of the capacitor.
상술한 바와 같이 본 발명은 MIM(Metal-Insulator-Metal)구조의 캐패시터 제조시 하부전극으로 금속계열의 물질을 사용할 경우, 콘택플러그를 구성하는 확산방지막을 형성하기 전에 확산방지막과 오믹콘택층 간에 형성된 산화물을 NH3가스를 이용한 급속 열처리 공정으로 질화시켜 질화물로 변화시키고 그 상에 확산방지막을 층작함으로써, 확산방지막과 오믹콘택층의 계면 접촉저항을 감소시킴과 아울러 콘택플러그의 접촉저항을 감소시켜 캐패시터의 전기적 특성을 개선시킬 수 있다.As described above, when the metal-based material is used as the lower electrode when manufacturing a capacitor having a metal-insulator-metal (MIM) structure, the present invention is formed between the diffusion barrier and the ohmic contact layer before forming the diffusion barrier constituting the contact plug. The oxide is nitrided by a rapid heat treatment process using NH 3 gas to change into a nitride, and the diffusion barrier layer is deposited thereon, thereby reducing the interface contact resistance between the diffusion barrier layer and the ohmic contact layer and reducing the contact resistance of the contact plug. Can improve the electrical properties of the.
Claims (7)
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