KR20020028005A - Structure of wire and method for manufacturing the wire, and thin film transistor substrate and method for manufacturing the substrate using the same - Google Patents

Abstract

PURPOSE: A method for fabricating a thin-film-transistor(TFT) substrate is provided to prevent an injection signal or image signal from being delayed, by forming a gate interconnection or data interconnection while using an Ag-based metal material layer having lower resistance than that of an Al-based metal material layer. CONSTITUTION: The gate interconnection(22,24,26) of a dual layer structure including the Ag-based metal material layer is formed on a substrate(10). A gate insulation layer(30) covering the gate interconnection is formed. A semiconductor layer is formed on the gate insulation layer. A data line crosses the gate line. A source electrode is in contact with one portion of the semiconductor layer. A drain electrode is in contact with the other portion of the semiconductor layer, corresponding to the source electrode. The drain interconnection includes the data line, the source electrode and the drain electrode. A passivation layer(70) covering the data interconnection(64,65,66) and the semiconductor layer is formed. A contact hole(72,74,76) exposing the drain electrode is formed in the passivation layer. A pixel electrode connected to the drain electrode is formed.

Description

STRUCTURE OF WIRE AND METHOD FOR MANUFACTURING THE WIRE, AND THIN FILM TRANSISTOR SUBSTRATE AND METHOD FOR MANUFACTURING THE SUBSTRATE USING THE SAME}

The present invention relates to a structure of a wiring, a method of manufacturing the same, a thin film transistor substrate using the same, and a method of manufacturing the same.

In general, the wiring in the semiconductor device is used as a means for transmitting a signal, it is required to minimize the signal delay.

In particular, in thin film transistor substrates used in liquid crystal display devices, the need for low resistance wiring has become important due to the large area and high definition. Currently, in order to prevent signal delay, a metal material having a low resistance, particularly an Al-based metal material such as Al or Al alloy, is used as the wiring material of the device.

However, since the Al-based wiring is weak in physical or chemical properties, corrosion occurs in the process of connecting to other conductive materials at the contact portion, and thus has a problem of degrading device characteristics.

The technical problem to be achieved by the present invention is to form a wiring having excellent physical or chemical properties and having a low resistance, and to apply the same to a thin film transistor substrate to prevent signal delay due to large area.

1 is a simplified cross-sectional view of the structure of a wiring according to the present invention,

2 is a layout view of a thin film transistor substrate according to a first exemplary embodiment of the present invention;

3 is a cross-sectional view taken along the line II-II ′ of FIG. 2;

4A to 7B are manufacturing process diagrams of the thin film transistor substrate according to the first embodiment of the present invention,

8 is a layout view of a thin film transistor substrate according to a second exemplary embodiment of the present invention.

9 and 10 are cross-sectional views of the thin film transistor substrate illustrated in FIG. 8 along cut lines VII- ′ and VII- ′ ′, respectively.

11A through 17C are manufacturing process diagrams of the thin film transistor substrate according to the second embodiment of the present invention.

In order to solve this problem, in the present invention, the wiring located on the substrate is formed of an Ag series having a lower resistance characteristic than Al, and the wiring is applied to the gate wiring or the data wiring of the thin film transistor substrate.

Specifically, in the structure of the wiring according to the present invention, a buffer conductive layer is formed on a substrate, and an Ag-based conductive layer is formed on the buffer conductive layer.

In this case, the buffer conductive layer may be formed of one of Mo-based, Si-based, and ITO-based, and the Ag-based conductive layer may be formed to have a taper profile of 30 degrees or less.

In order to manufacture such a wiring structure, a buffer conductive layer is deposited on a substrate, an Ag-based conductive layer is deposited on the buffer conductive layer, and the buffer conductive layer and the Ag-based conductive layer are etched.

In this case, the buffer conductive layer may be formed of a Mo-based material, and the buffer conductive layer and the Ag-based conductive layer may be simultaneously etched. A mixed solution of phosphoric acid + nitric acid + acetic acid + DI is preferably used for the etching process. .

In the thin film transistor substrate according to the present invention, a gate wiring including a gate electrode and a gate line formed in a double layer structure including an Ag-based metal layer is formed on the substrate, and a gate insulating film covering the gate wiring is formed. . A semiconductor layer is formed on the gate insulating layer, and includes a data line intersecting the gate line to be insulated, a data line extending from the data line to contact the semiconductor layer, and a drain electrode corresponding to the source electrode and contacting the semiconductor layer. Is formed, and the protective film which covers a data wiring and a semiconductor layer is formed. A contact hole for exposing the drain electrode is formed in the protective film, and the pixel electrode is connected to the drain electrode. At this time, it is preferable that the other metal layer is formed of one of Mo-based, Si-based, and ITO-based gate wirings in a double layer structure.

The data line may be formed in a double layer structure including an Ag-based metal layer, or may be formed in a single layer structure including one of Ag, Cr, Mo, Ta, and Ti.

The thin film transistor substrate according to the present invention includes a gate pad connected to an end of a gate line, a data pad connected to an end of a data line, a first contact hole for exposing the gate pad to a passivation layer and a gate insulating layer, and a data pad exposed to the passivation layer. The display device may further include a second contact hole, an auxiliary gate pad covering the gate pad through the first contact hole, and an auxiliary data pad covering the data pad through the second contact hole.

Further, the gate wiring further includes a storage electrode formed in parallel with the gate line to form one conductive layer of the storage accumulator, and the data wiring overlaps the storage electrode to form another conductive layer of the storage accumulator. It may further include.

In order to manufacture the thin film transistor substrate according to the present invention, a gate wiring having a double layer structure including an Ag-based metal material layer is formed on the substrate, and a gate insulating film covering the gate wiring is formed. Next, a semiconductor layer is formed on the gate insulating layer, and a data line including a data line intersecting the gate line, a source electrode in contact with a portion of the semiconductor, and a drain electrode corresponding to the source electrode is in contact with another portion of the semiconductor layer. Then, a protective film covering the data wiring and the semiconductor layer is formed. Subsequently, a contact hole for exposing the drain electrode is formed in the protective film, and a pixel electrode connected to the drain electrode is formed.

Here, the gate wiring may be formed by continuously depositing a lower metal layer consisting of Mo-based and an upper metal layer formed of Ag-based on the substrate, and simultaneously etching the metal layer and the lower metal layer using a mixed etchant of phosphoric acid + nitric acid + acetic acid + DI. Can be.

The data wiring may be formed in a single layer structure made of Ag series or in a double layer structure including an Ag based metal material layer. In this case, the lower metal layer made of Mo series and the upper metal layer made of Ag series may be continuously formed. After deposition, the metal layer and the lower metal layer may be simultaneously etched using a mixed etchant of phosphoric acid + nitric acid + acetic acid + DI.

The semiconductor layer and the data line may be formed together by a photolithography process using photoresist patterns having different thicknesses. In this case, the photoresist pattern may include a first part having a first thickness, a second part thicker than the first thickness, and a third part having no thickness and excluding the first and second parts, and the photoresist pattern may include the first part. It can be formed using an optical mask including a region, a second region having a lower transmittance than the first region, and a third region having a higher transmittance than the first region. In the photoresist pattern, the first part may be formed between the source electrode and the drain electrode, and the second part may be positioned above the data wiring, and the translucent film or the exposure machine may be applied to the photomask to differently control the transmittance of the first to third areas. A slit pattern smaller than the resolution of can be formed. In addition, in the photosensitive film pattern, the thickness of the first portion may be formed to be 1/2 or less with respect to the thickness of the second portion.

The method of manufacturing a thin film transistor substrate according to the present invention may further include forming an ohmic contact layer between the semiconductor layer and the data wiring, wherein the data wiring, the ohmic contact layer and the semiconductor layer are combined together using one photosensitive film pattern. Can be formed.

Next, a structure of a wiring according to an exemplary embodiment of the present invention, a method of manufacturing the same, a thin film transistor substrate using the same, and a method of manufacturing the same will be described in detail with reference to the accompanying drawings.

In the display device, an Al-based metal material having a low specific resistance is commonly used to minimize signal delay in a wiring for transmitting a signal. In the case of Al alloys currently in use, the specific resistance is as low as 4.7 μΩcm, but about twice as high as that of Ag or Cu. Therefore, a metal such as Ag or Cu is needed at a time when a wiring having a lower specific resistance is required.

Cu has a low specific resistance but is difficult to apply due to poor resistance to corrosion. On the other hand, Ag series such as Ag or Ag alloy has better corrosion resistance than Al series. Therefore, Ag series is required after Al series as next generation low resistance wiring material.

On the other hand, the Ag-based has poor adhesion properties with glass, and when the Ag-based wiring is formed on the glass substrate, as shown in FIG. 1, rather than a single layer structure, between the glass substrate 10 and the Ag-based wiring 202. It is preferable to form a double layer structure formed through the buffer film 201.

In particular, since the Mo-based and Ag-based etching can be simultaneously etched by the Ag-based etching solution, there is an advantage in that when the Mo-based buffer film is used, wiring of a double layer structure can be formed by one etching process.

A method of forming such a wiring will be briefly described with reference to FIG. 1 as follows.

First, a Mo-based metal layer 201 such as Mo or Mo alloy is deposited on the glass substrate 10 to a thickness of about 500 GPa, and an Ag-based metal layer 202 such as Ag or Ag alloy to about 1500 GPa on it. Laminate. Subsequently, the two metal layers 201 and 202 are dry or wet etched by a photolithography process using a mask.

In this case, when a mixed solution of phosphoric acid + nitric acid + acetic acid + D.I, which is an Ag-based etching solution, the Mo-based metal layer 201 and the Ag-based metal layer 202 can be etched simultaneously, the manufacturing process can be simplified.

On the other hand, the mixed solution of phosphoric acid + nitric acid + acetic acid + DI, which is an Ag-based etchant, etches the Ag-based metal layer 202 faster than the Mo-based metal layer 201 and thus has a good taper profile as shown in the drawing. You can get it. At this time, the taper profile of the Ag-based metal layer 202 can also be formed at 30 degrees or less, so that subsequent film deposition can be made favorable.

On the other hand, in addition to the Mo-based, as a buffer film, the glass substrate 10 and the Ag-based metal layer may be formed using one of the Si-based and ITO-based adhesive properties with good adhesion properties, in this case, by the Ag-based etching solution Since it is difficult to etch a series or an ITO series, a double layer wiring is formed by two etching processes.

However, when the Ag-based wiring is formed on a material layer other than a glass substrate, for example, a Si-based semiconductor layer, the wiring can be formed even in a single layer structure without intervening the buffer film.

Next, a thin film transistor substrate employing such Ag-based wiring will be described.

First, the structure of the thin film transistor substrate according to the first embodiment of the present invention will be described in detail with reference to FIGS. 2 and 3.

2 is a layout view of a thin film transistor substrate according to a first exemplary embodiment of the present invention, and FIG. 3 is a cross-sectional view of the thin film transistor substrate taken along the cutting line III-III ′ of FIG. 2. Five masks are used to manufacture the thin film transistor according to the first embodiment of the present invention.

The gate wiring 22 having a double layer structure formed of an Mo-based lower metal layer 201 such as Mo or Mo alloy and an Ag-based upper metal layer 202 such as Ag or Ag alloy having low resistance on the insulating substrate 10. 24, 26) are formed.

The gate wires 22, 24, and 26 are connected to gate lines 22 and gate lines 22 extending in the horizontal direction, and the gate pads receive the scan signals from the outside and transmit them to the gate lines 22 ( 24 and the gate electrode 26 of the thin film transistor which is part of the gate line 22.

As described above, since the gate wires 22, 24, and 26 are formed of an Ag-based metal material having excellent low resistance, scan signals can be quickly transmitted.

In the case where the insulating substrate 10 is a glass substrate, in the case where the Ag-based wiring is formed on the glass substrate, the Ag-based glass and the Ag-based glass are considered as in this embodiment in consideration of poor adhesion properties with the glass substrate. It is good to employ the wiring of the double layer structure in which Ag and a glass substrate and the buffer film with a favorable adhesive property were interposed between board | substrates. In this embodiment, although the Mo series is used as the material of the buffer layer, that is, the lower metal layer 201 of the gate lines 22, 24, and 26, an Si series or an ITO series may also be used.

On the insulating substrate 10, a gate insulating film 30 made of an insulating material such as silicon nitride or silicon oxide covers the gate wirings 22, 24, and 26.

A semiconductor pattern 42 made of a semiconductor material such as hydrogenated amorphous silicon overlapping with the gate electrode 26 is formed on the gate insulating layer 30, and the n-type impurity is formed on the semiconductor pattern 42 at a high concentration. Ohmic contact layers 55 and 56 are formed of a semiconductor material layer doped with impurities such as doped amorphous silicon.

On the ohmic contact layers 55 and 56 and the gate insulating layer 30, a Mo-based lower metal layer 601 such as Mo or Mo alloy and an Ag-based upper metal layer 602 such as Ag or Ag alloy having low resistance properties are provided. The double-layered data wirings 62, 64, 65, and 66 are formed. As such, the data wires 62, 64, 65, and 66 may be formed in a double layer structure of an Ag-based metal layer and another metal layer, such as the gate wires 22, 24, and 26. It may be formed of a series or ITO-based material.

The data wires 62, 64, 65, and 66 are connected to one end of the data line 62 and the data line 62, which are formed in the vertical direction, to receive image signals from the outside, and to the data pad 64 and the data line. Protruding from 62 and contacting one ohmic contact layer 55 to correspond to the source electrode 65 and the source electrode 65 forming a part of the thin film transistor, and contacting the other ohmic contact layer 56. A drain electrode 66 constituting part of the thin film transistor is included.

The data wires 62, 64, 65, and 66 are also made of Ag, which has lower resistance than Al, like the gate wires 22, 24, and 26, so that image signals can be transmitted quickly.

The data wires 62, 64, 65, and 66 may be formed in a single layer structure made of Ag, which is a glass substrate 10 in which the data wires 62, 64, 65, and 66 have poor adhesion properties with the Ag series. This is because the semiconductor substrate 42 is formed of a semiconductor pattern 42 made of Ag-based silicon and good adhesion-type silicon or a gate insulating film 30 made of silicon nitride. In this case, in addition to Ag-based, it may be formed using a metal material such as Cr-based, Mo-based, Ta-based, or Ti-based. However, it is advantageous to form Ag based for low resistance data wiring.

The passivation layer 70 made of an insulating material such as silicon nitride or silicon oxide is formed on the data lines 62, 64, 65, and 66.

The protective film 70 is provided with a contact hole 72 for exposing the drain electrode 66 and a contact hole 76 for exposing the data pad 64. Further, contact holes 74 exposing the gate pads 24 are formed in the protective film 70 and the gate insulating film 30.

On the passivation layer 70, a pixel electrode 82 that receives an image signal from a thin film transistor and generates an electric field together with an electrode (not shown) on the upper plate is formed. The pixel electrode 82 is made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), and is connected to the drain electrode 66 through the contact hole 72 to receive an image signal.

In the drawing, the pixel electrode 82 overlaps with the neighboring gate line 22 and the data line 62 to increase the aperture ratio, but may not overlap.

Meanwhile, an auxiliary gate pad 84 connected to the gate pad 24 is formed on the passivation layer 70 through a contact hole 74 exposing the gate pad 24, and the contact exposing the data pad 64. An auxiliary data pad 86 is formed that connects to the data pad 64 through the hole 76. These auxiliary pads 84 and 86 complement the adhesion to external circuit devices and protect the gate pads 24 and the data pads 64, and are not essential, and their application is optional.

Next, a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 3A to 7B and FIGS. 1 and 2.

First, as shown in FIGS. 4A to 4B, a lower Mo-based lower metal layer 201 such as Mo or Mo alloy is deposited to a thickness of about 500 kPa on the substrate 10, and an Ag-based upper part such as Ag or Ag alloy is deposited thereon. The metal layer 202 is laminated to a thickness of about 1500 kPa. Subsequently, the two metal layers 201 and 202 are etched by a photolithography process using a mask, and a gate including a double-layered gate line 22, a gate pad 24, and a gate electrode 26 is formed on the substrate 10. The wirings 22, 24, and 26 are formed.

In this case, when a mixed solution of phosphoric acid + nitric acid + acetic acid + DI which is an Ag-based etching solution is used, the lower metal layer 201 of Mo-based and the upper metal layer 202 of Ag-based can be simultaneously etched, which is advantageous in simplifying the process. . At this time, the tapered profile of the Ag-based metal layer can be formed to 30 degrees or less by Ag-based etching solution, so that subsequent film deposition can be improved.

On the other hand, the lower metal layer 201 of the gate wiring is formed of a material having a good adhesive property with the substrate 10 and the Ag-based upper metal layer 202. In addition to the Mo-based as shown in the embodiment, It can be formed by ITO series. However, since the Si-based or ITO-based etched with respect to the Ag-based etchant is slow, it is difficult to form a double gate wiring by etching simultaneously with the Ag-based. Therefore, when the lower metal layer is to be formed of Si-based or ITO-based, an etching process using an Ag-based etchant and an etching process using an Si-based or ITO-based etchant are performed respectively to form a gate wiring having a double layer structure. .

Next, as shown in FIGS. 5A to 5B, the gate insulating layer 30, the hydrogenated amorphous silicon layer, and the amorphous silicon layer heavily doped with n-type impurities are sequentially stacked, and impurities are formed by a photolithography process using a mask. The doped amorphous silicon layer and the amorphous silicon layer are sequentially patterned to form an island-shaped semiconductor pattern 42 and an ohmic contact layer pattern 52.

6A to 6B, a Mo-based lower metal layer 601 such as Mo or Mo alloy is deposited to a thickness of about 500 GPa, and Ag-based upper metal layer 602 such as Ag or Ag alloy is deposited thereon. Laminate to a thickness of about 1500Å. Subsequently, the two metal layers 601 and 602 are etched by a photolithography process using a mask to include a double layer data line 62, a data pad 64, a source electrode 65, and a drain electrode 66. Data wirings 62, 64, 65, and 66 are formed.

In this case, when a mixed solution of phosphoric acid + nitric acid + acetic acid + DI which is an Ag-based etching solution is used, the lower metal layer 601 of the Mo series and the upper metal layer 602 of the Ag series can be simultaneously etched, which is advantageous in simplifying the process. .

In addition, the lower metal layer 601 constituting the data lines 62, 64, 65, and 66 may be formed of a material having excellent adhesive properties with Ag-based such as Si-based or ITO-based instead of Mo-based.

In addition, the data lines 62, 64, 65, and 66 may be formed as a single layer. In this case, the data lines 62, 64, 65, and 66 may be formed using a metal material such as Ag, Cr, Mo, Ta, Ti, or the like. Can be. However, it is advantageous to form Ag based for low resistance data wiring.

Subsequently, the resistive contact layer pattern 52 which is not separated using the source electrode 65 and the drain electrode 66 as a mask is etched to contact the source electrode 65 and the resistive contact layer 55 and the drain electrode ( And the other ohmic contact layer 56 in contact with 66).

Referring to FIGS. 7A and 7B, an inorganic insulating material such as silicon nitride or silicon oxide is deposited to form a protective film 70 on the entire surface of the substrate, and then patterned together with the gate insulating film 30 by a photolithography process using a mask. The contact hole 72 exposing the drain electrode 66, the contact hole 74 exposing the gate pad 24, and the contact hole 76 exposing the data pad 64 are formed.

Subsequently, referring again to FIGS. 2 and 3, a layer of a transparent conductive material made of a transparent conductive material such as ITO or IZO is deposited and patterned by a photolithography process using a mask to form a drain electrode (through the contact hole 72). The auxiliary gate pad 84 and the auxiliary data pad 86 respectively connected to the gate pad 24 and the data pad 64 through the pixel electrode 82 and the contact holes 74 and 76 connected to the 66 are respectively. Form.

Since the thin film transistor substrate according to the first embodiment of the present invention is formed of the Ag wiring having the lower resistance characteristics than the Al series, the gate wiring or the data wiring can be quickly transferred to the scan signal or the image signal, thereby displaying a large area. Applicable to the device. On the other hand, in the case of forming a wiring with an Ag-based metal layer on the glass substrate, it is advantageous to form a Si-based, ITO-based material layer as a buffer film for the stable adhesion of the two layers between the glass substrate and the Ag-based metal layer.

This method can be similarly applied to the method of manufacturing a thin film transistor substrate using four masks. This will be described in detail with reference to the drawings.

First, the unit pixel structure of the thin film transistor substrate completed by using the four masks according to the second embodiment of the present invention will be described in detail with reference to FIGS. 8 to 10.

8 is a layout view of a thin film transistor substrate according to a second exemplary embodiment of the present invention, and FIGS. 9 and 10 are each cut along the cutting lines IX-IX 'and VII-VII', respectively. One cross section.

First, on the insulating substrate 10 as the Ag-based upper metal layer 202 such as Ag or Ag alloy having a low resistance on the Mo-based lower metal layer 201, such as Mo or Mo alloy, as in the first embodiment The gate line portions 22, 24, and 26 including the gate line 22, the gate pad 24, and the gate electrode 26 having a double layer structure formed thereon are parallel to the gate line 22 on the substrate 10. Gate wirings 22, 24, 26, and 28 are formed to include sustain electrodes 28 for a storage capacitor that receive a voltage such as a common electrode voltage input to the common electrode from the outside.

The storage electrode 28 for the storage capacitor overlaps with the conductive pattern 68 for the storage capacitor connected to the pixel electrode 82 to be described later to form a storage capacitor that improves the charge retention capability of the pixel, and the pixel electrode 82 to be described later. ) And may not be formed when the storage capacitance generated by the overlap of the gate line 22 is sufficient.

As described above, the gate lines 22, 24, and 26 have an Ag-based metal material layer having excellent low resistance characteristics, so that the scan signal can be quickly transmitted.

In the case where the insulating substrate 10 is a glass substrate, in the case where the Ag-based wiring is formed on the glass substrate, the Ag-based glass and the Ag-based glass are considered as in this embodiment in consideration of poor adhesion properties with the glass substrate. It is good to employ the wiring of the double layer structure in which Ag and a glass substrate and the buffer film with a favorable adhesive property were interposed between board | substrates. In this embodiment, although the Mo series is used as a material of the buffer layer, that is, the lower metal layer 201 of the gate lines 22, 24, 26, and 28, an Si series or an ITO series may also be used.

A gate insulating film 30 made of silicon nitride (SiNx) is formed on the gate wirings 22, 24, 26, and 28 to cover the gate wirings 22, 24, 26, and 28.

Semiconductor patterns 42 and 48 made of a semiconductor material such as hydrogenated amorphous silicon are formed on the gate insulating layer 30, and n-type impurities such as phosphorus (P) are formed on the semiconductor patterns 42 and 48. An ohmic contact layer pattern 55, 56, 58 made of a semiconductor material doped with impurities such as amorphous silicon that is heavily doped is formed. The semiconductor patterns 42 and 48 include the thin film transistor semiconductor pattern 42 and the storage capacitor semiconductor pattern 48.

On the ohmic contact layer patterns 55, 56, and 58, a bilayer structure consisting of an Mo-based lower metal layer 601 such as Mo or Mo alloy and an Ag-based upper metal layer 602 such as Ag or Ag alloy having low resistance properties Data wirings 62, 64, 65, 66, and 68 are formed. As such, the data wires 62, 64, 65, 66, and 68 may be formed in a double layer structure of an Ag-based metal layer and another metal layer, such as the gate wires 22, 24, and 26. It may be formed of a material of Si, or ITO series.

The data wires 62, 64, 65, 66, and 68 are connected to one end of the data line 62, the data line 62 formed in the vertical direction, to receive image signals from the outside, and And a data line portion 62, 64, 65, 66 including a source electrode 65 protruding from the data line 62, a drain electrode 66 corresponding to the source electrode 65, and a storage electrode 28 for a storage capacitor. And a conductor pattern 68 for the storage capacitor.

The data wires 62, 64, 65, 66, and 68 are made of Ag, which has lower resistance than Al, like the gate wires 22, 24, and 26, so that image signals can be transmitted quickly.

The data wires 62, 64, 65, 66, and 68 can be formed in a single layer structure made of Ag series, which means that the data wires 62, 64, 65, 66, and 68 have poor adhesion properties with the Ag series. This is because the semiconductor substrates 42 and 48 are formed on the gate insulating film 30 made of silicon nitride or the semiconductor patterns 42 and 48 made of Ag-based and silicon-based silicon.

The data wires 62, 64, 65, 66, and 68 may be formed in a single layer structure composed of Ag series. The data wires 62, 64, 65, 66, and 68 may be formed of a glass substrate having poor adhesion characteristics with the Ag series. This is because the semiconductor substrates 42 and 48 are made of Ag-based and silicon-based semiconductors having good adhesion characteristics or gate insulating films 30 made of silicon nitride. In this case, in addition to Ag-based, it may be formed using a metal material such as Cr-based, Mo-based, Ta-based, or Ti-based. However, it is advantageous to form Ag based for low resistance data wiring.

The ohmic contact layer patterns 55, 56, and 58 lower the contact resistance between the semiconductor patterns 42 and 48 below and the data lines 62, 64, 65, 66, and 68 above them. It has the same form as the wirings 62, 64, 65, 66 and 68.

The semiconductor patterns 42 and 48 have the same shape as the data lines 62, 64, 65, 66, and 68 and the ohmic contact layer patterns 55, 56, and 58 except for the channel portion C of the thin film transistor. Doing. Specifically, the semiconductor capacitor 48 for the storage capacitor, the conductor pattern 68 for the storage capacitor, and the contact layer pattern 58 for the storage capacitor have the same shape, but the semiconductor pattern 42 for the thin film transistor has a data line 62. ), The same as the data line portions 62, 68, 65, 66 including the data pad 68, the source electrode 65, and the drain electrode 66, but between the source electrode 65 and the drain electrode 66. The semiconductor device further includes a region defined as a channel of the thin film transistor positioned at.

A protective film 70 made of silicon nitride is formed on the data lines 62, 64, 65, 66, and 68.

In the protective film 70, a contact hole 72 exposing the drain electrode 66, a contact hole 76 exposing the data pad 64, and a contact hole 78 exposing the conductor pattern 68 for the storage capacitor are formed. Moreover, the contact hole 74 which exposes the gate pad 24 with the gate insulating film 30 is formed.

On the passivation layer 70, a pixel electrode 82 that receives an image signal from a thin film transistor and generates an electric field together with the electrode of the upper plate is formed. The pixel electrode 82 is made of a transparent conductive material such as indium tin oxide (IZO), and is physically and electrically connected to the drain electrode 66 through the contact hole 72 to receive an image signal. 82 is also connected with the conductor pattern 68 for the storage capacitor through the contact hole 78 to transmit an image signal to the conductor pattern 68. In this case, the pixel electrode 82 overlaps with the neighboring gate line 22 and the data line 62 to increase the aperture ratio, but may not overlap.

On the other hand, an auxiliary gate pad 84 and an auxiliary data pad 86 are formed on the passivation layer 70 through the contact holes 74 and 76, respectively, and these pads 24 and 64 and the external circuit device are formed. It is not essential to play a role of complementing the adhesion to the pad and to protect the pad, and their application is optional.

Next, a method of manufacturing a thin film transistor substrate for a liquid crystal display device having the structure of FIGS. 8 to 10 using four masks will be described in detail with reference to FIGS. 8 to 10 and FIGS. 10A to 17C. .

First, as shown in FIGS. 11A to 11C, a lower Mo-based lower metal layer 201 such as Mo or Mo alloy is deposited to a thickness of about 500 kPa on the substrate 10, and Ag-based Ag such as Ag or Ag alloy is deposited thereon. The upper metal layer 202 is laminated to a thickness of about 1500 kPa.

Subsequently, the two metal layers 201 and 202 are etched by a photolithography process using a mask, and the gate line portion having the double layer structure gate line 22, gate electrode 26, and gate pad 24 is formed on the substrate 10. And the gate wirings 22, 24, 26, 28 including the sustain electrode 28.

At this time, in the case of using a mixture of phosphoric acid + nitric acid + acetic acid + DI, which is an Ag-based etching solution, the lower metal layer 201 of the Mo series and the upper metal layer 202 of the Ag series can be simultaneously etched, which is advantageous in simplifying the process. . At this time, the tapered profile of the Ag-based metal layer can be formed to 30 degrees or less by Ag-based etching solution, so that subsequent film deposition can be improved.

On the other hand, the lower metal layer 201 of the gate wiring is formed of a material having a good adhesive property with the substrate 10 and the Ag-based upper metal layer 202. In addition to the Mo-based as shown in the embodiment, It can be formed by ITO series. However, since the Si-based or ITO-based etched with respect to the Ag-based etchant is slow, it is difficult to form a double gate wiring by etching simultaneously with the Ag-based. Therefore, when the lower metal layer is to be formed of Si-based or ITO-based, an etching process using an Ag-based etchant and an etching process using an Si-based or ITO-based etchant are performed respectively to form a gate wiring having a double layer structure. .

Next, as shown in FIGS. 12A to 12C, an insulating material such as gate silicon nitride is deposited on the gate lines 22, 24, 26, 28, and the substrate 10 to form the gate insulating layer 30.

Subsequently, the data lines 62, 64, 65, and 66 including the data line 62, the data pad 64, the source electrode 65, and the drain electrode 66 are disposed on the gate insulating film 30, and the conductive capacitors are electrically conductive. Data wirings 62, 64, 65, 66, and 68 including the sieve pattern 68, and ohmic contact layers 55 disposed under the same and in the same pattern as the data wirings 62, 64, 65, 66, and 68. , Which is defined between the source electrode 65 and the drain electrode 66 in the same pattern as the data lines 62, 64, 65, 66, and 68, and defined as the channel C of the thin film transistor. The semiconductor patterns 42 and 48 thus formed are formed.

Here, one ohmic contact layer 56 is in contact with the bottom of the drain electrode 66, and the other ohmic contact layer 55 is the source electrode 65, the data line 62, and the data pad 64. The other contact layer 58 is in contact with the storage capacitor 58 for the storage capacitor, and is in contact with the conductor pattern 68 for the storage capacitor.

The data wires 62, 64, 65, 66, 68, the ohmic contact layers 55, 56, 58, and the semiconductor patterns 42, 48 are formed using one mask, which is illustrated in FIGS. 13A through 17B. This will be described in detail with reference.

First, as shown in FIGS. 13A and 13B, a gate insulating film 30 made of silicon nitride, a semiconductor layer 40, and impurities are doped with an exposed front surface including the gate wirings 22, 24, 26, and 28. The semiconductor layer 50 is continuously deposited to a thickness of 1,500 kPa to 5,000 kPa, 500 kPa to 2,000 kPa, and 300 kPa to 600 kPa using chemical vapor deposition.

Subsequently, a Mo-based lower metal layer 601 such as Mo or Mo alloy is continuously deposited to a thickness of about 500 GPa, and an Ag-based upper metal layer 602 such as Ag or Ag alloy is deposited to a thickness of about 1500 GPa thereon. . And a photosensitive film is apply | coated on it in thickness of 1 micrometer-2 micrometers.

Subsequently, light is irradiated to the photoresist film through a mask, and then developed to form the photoresist patterns 112 and 114. In this case, the photoresist patterns 112 and 114 may have a first portion 112 of the photoresist layer positioned at the data line portion A between the channel portion C of the thin film transistor, that is, between the source electrode 65 and the drain electrode 66. It is formed to be thicker than the second portion 114 of the positioned photosensitive film, and the other portion (B) is formed so as not to remain. The ratio of the thickness of the first portion 112 of the photosensitive film of the second portion 114 of the photosensitive film should be different depending on the process conditions in the etching process, which will be described later, but the thickness of the second portion 114 is determined by the first portion 112. It is preferable to make into 1/2 or less of thickness.

As such, photoresist patterns having partially different thicknesses are formed using one mask having partially different transmittance. In order to control the light transmission, a slit or lattice pattern or a mask with a translucent film is used. In this case, the line width of the pattern located between the slits, or the interval between the patterns, that is, the width of the slits, is preferably smaller than the resolution of the exposure apparatus used for exposure. A thin film having a thickness or a thin film may be used.

When the photosensitive film is irradiated with light through such a mask, the polymers are completely decomposed at the portion (C) directly exposed to the light, and the polymers are completely decomposed because the amount of light is less at the portion (B) corresponding to the slit pattern or the translucent film. The polymer is hardly decomposed in the part A covered by the light shielding film. In this case, if the exposure time is extended, all molecules are decomposed, so it should not be so.

When the selective exposed photoresist is developed, only portions where polymer molecules are not decomposed remain, and a photoresist having a thickness thinner than a portion that is not irradiated with light is left in the central portion irradiated with little light.

Next, as shown in FIGS. 14A and 14B, the Ag-based upper conductive layer 602 and the Mo-based lower conductive layer (exposed to the other portions B using the photosensitive film patterns 112 and 114 as masks). 601 is removed to expose the semiconductor layer 50 doped with impurities thereunder.

In this way, only the conductor patterns 67 and 68 in the channel portion C and the data wiring portion A remain, and the conductive layer in the other portion B is removed, and the semiconductor layer doped with impurities located thereunder. 50 is revealed. The conductor pattern 68 is a conductor pattern for the storage capacitor, and the conductor pattern 67 is a data wiring metal layer in which the source electrode 65 and the drain electrode 66 are not separated yet and exist in an integrated state.

Next, as shown in FIGS. 15A and 15B, the semiconductor layer 50 doped with the exposed impurities of the other portion B and the semiconductor layer 40 thereunder together with the second portion 114 of the photoresist film. Simultaneously removed by dry etching. The etching may be performed under the condition that the photoresist patterns 112 and 114, the semiconductor layer 50 and the semiconductor layer 40 doped with impurities are simultaneously etched, and the gate insulating layer 30 is not etched. It is preferable to etch under the conditions in which the etching ratio with respect to (112, 114) and the semiconductor layer 40 is substantially the same. For example, by using a mixed gas of SF ₆ and HCl or a mixed gas of SF ₆ and O ₂ , the two films can be etched to almost the same thickness.

When the etch ratios of the photoresist patterns 112 and 114 and the semiconductor layer 40 are the same, the thickness of the second portion 114 of the photoresist layer is the sum of the thicknesses of the semiconductor layer 40 and the semiconductor layer 50 doped with impurities. It must be less than or equal to

In this case, the second portion 114 of the photoresist film positioned in the channel portion C is removed to expose the conductor pattern 67 of the channel portion C, and the semiconductor layer 50 doped with impurities in the other portion B. ) And the semiconductor layer 40 are removed to reveal the gate insulating film 30 thereunder. On the other hand, since the first portion 112 of the photosensitive film of the data wiring portion A is also etched, the thickness becomes thin.

In this step, the semiconductor patterns 42 and 48 including the thin film transistor semiconductor pattern 42 and the storage capacitor semiconductor pattern 48 are completed.

The ohmic contact layer 57 is formed on the thin film transistor semiconductor pattern 42 in the same pattern as the semiconductor pattern 42. The ohmic contact layer 58 is also formed on the semiconductor capacitor 48 for the storage capacitor. It is formed in the same pattern as 48).

Subsequently, ashing removes residues of the second portion of the photoresist film remaining on the surface of the conductor pattern 67 of the channel portion C.

Next, as shown in FIGS. 16A and 16B, the double layer conductor pattern 67 positioned in the channel portion C using the first portion 112 of the remaining photoresist pattern as a mask and the ohmic contact layer thereunder. The pattern 57 is removed by etching.

In this case, a portion of the semiconductor pattern 42 may be removed to reduce the thickness, and the first portion 112 of the photoresist pattern may also be etched to a certain thickness. At this time, the etching must be performed under the condition that the gate insulating layer 30 is not etched, and the first portion 112 of the photoresist pattern is etched to expose the lower data lines 62, 64, 65, 66, and 68. It is a matter of course that the photosensitive film pattern is thick so that there is no.

In this way, the source electrode 65 and the drain electrode 66 are separated from the conductor pattern 67 to complete the data line 62, the source electrode 65, and the drain electrode 68. The patterns 55, 56 and 58 are completed.

Finally, when the first portion 112 of the photosensitive film pattern remaining in the data wiring portion A is removed by an ashing operation, a cross-sectional structure as shown in FIGS. 12B and 12C can be obtained.

Next, as shown in FIGS. 17A to 17C, the silicon nitride is deposited on the data lines 62, 64, 65, 66, and 68 by CVD to form a protective film 70.

Subsequently, the protective layer 70 is etched together with the gate insulating layer 30 by a photolithography process using a mask to form the drain electrode 66, the gate pad 24, the data pad 68, and the conductive pattern 64 for the storage capacitor. Contact holes 72, 74, 76, and 78, respectively.

Next, again, as shown in FIGS. 8, 9, and 10, an IZO or ITO layer having a thickness of 400 kV to 500 kV is deposited and etched using a mask to etch the drain electrode 66 and the storage capacitor. The pixel electrode 82 connected to the pattern 68, the auxiliary gate pad 84 connected to the gate pad 24 through the contact hole 74, and the auxiliary data connected to the data pad 64 through the contact hole 76. The pad 86 is formed.

Since the thin film transistor substrate according to the second exemplary embodiment of the present invention is formed of an Ag series having a lower resistance than that of Al, the thin film transistor substrate can transfer a scan signal or an image signal quickly so that the large-area display device Applicable to On the other hand, in the case of forming a wiring with an Ag-based metal layer on the glass substrate, it is advantageous to form a Si-based, ITO-based material layer as a buffer film for the stable adhesion of the two layers between the glass substrate and the Ag-based metal layer.

In the present invention, since the gate wiring or the data wiring is formed using the Ag series having a lower resistance than the Al series, the delay of the scan signal or the video signal due to the large area can be prevented. In addition, when the lower metal layer is formed of a metal material, for example, Mo-based, and is etched by an Ag-based etchant, and the upper metal layer is formed thereon on the glass substrate, the upper metal layer and the lower metal layer are formed on the glass substrate. Can be simultaneously etched to form a double-sided wiring, which is advantageous in simplifying the process.

Claims (25)

Board, A buffer conductive layer formed on the substrate, Ag-based conductive layer formed on the buffer conductive layer, Structure of the wiring comprising a. The method according to claim 1, The buffer conductive layer is a wiring structure formed of one of Mo-based, Si-based, ITO-based. The method according to claim 1, The Ag-based conductive layer has a tapered profile of 30 degrees or less. Depositing a buffer conductive layer on the substrate, Depositing an Ag-based conductive layer on the buffer conductive layer; And etching the buffer conductive layer and the Ag-based conductive layer to form a wiring structure. The method according to claim 4, The buffer conductive layer is formed of a Mo-based material, and forming a structure of a wiring for etching the buffer conductive layer and the Ag-based conductive layer at the same time. The method according to claim 5, And forming a wiring structure using a mixture of phosphoric acid + nitric acid + acetic acid + D.I in the etching process. Substrate, A gate wiring including a gate electrode and a gate line formed in a double layer structure including an Ag-based metal layer on the substrate; A gate insulating film covering the gate wiring, A semiconductor layer formed on the gate insulating film, A data line including a data line crossing the gate line insulated from the gate line, a source electrode extending from the data line to contact the semiconductor layer, and a drain electrode corresponding to the source electrode and contacting the semiconductor layer; A protective film covering the data line and the semiconductor layer, A contact hole exposing the drain electrode to the protective film, And a pixel electrode connected to the drain electrode. The method according to claim 7, The thin film transistor substrate of which the other metal layer is formed of one of Mo-based, Si-based, and ITO-based gate wirings. The method according to claim 7, The data line is a thin film transistor substrate having a double layer structure including an Ag-based metal layer. The method according to claim 7, The data line is a thin film transistor substrate having a single layer structure made of one metal material of Ag-based, Cr, Mo, Ta, Ti. The method according to claim 7, A gate pad connected to an end of the gate line, A data pad connected to an end of the data line; A first contact hole exposing the gate pad to the passivation layer and the gate insulating layer; A second contact hole exposing the data pad to the passivation layer, An auxiliary gate pad covering the gate pad through the first contact hole, An auxiliary data pad covering the data pad through the second contact hole Thin film transistor substrate further comprising. The method according to claim 7, The gate wiring further includes a storage electrode formed in parallel with the gate line to form a conductive layer of the storage accumulator, The data line further includes a conductor pattern for a storage capacitor overlapping the storage electrode to form another conductive layer of the storage accumulator. Forming a gate wiring having a double layer structure including an Ag-based metal material layer on a substrate, Forming a gate insulating film covering the gate wiring; Forming a semiconductor layer on the gate insulating film, Forming a data line including a data line crossing the gate line, a source electrode in contact with a portion of the semiconductor, and a drain electrode corresponding to the source electrode and in contact with another portion of the semiconductor layer; Forming a protective film covering the data line and the semiconductor layer; Forming a contact hole in the passivation layer to expose the drain electrode; Forming a pixel electrode connected to the drain electrode. The method of claim 13, wherein the gate wiring is formed, Continuously depositing a lower metal layer made of Mo-based and an upper metal layer made of Ag-based on the substrate, And etching the upper metal layer and the lower metal layer simultaneously using a mixed etchant of phosphoric acid + nitric acid + acetic acid + D.I. The method according to claim 13, A method for manufacturing a thin film transistor substrate, in which the data wiring is formed in a single layer structure composed of Ag series. The method according to claim 13, A method of manufacturing a thin film transistor substrate, wherein the data line is formed in a double layer structure including an Ag-based metal material layer. The method of claim 16, wherein the data wiring is formed, Continuously depositing a lower metal layer made of Mo-based and an upper metal layer made of Ag-based, And etching the upper metal layer and the lower metal layer simultaneously using a mixed etchant of phosphoric acid + nitric acid + acetic acid + D.I. The method according to claim 13, And the semiconductor layer and the data line are formed together by a photolithography process using a photoresist pattern having a different thickness. The method according to claim 18, The photoresist pattern may include a first portion having a first thickness, a second portion thicker than the first thickness, and a third portion having no thickness and excluding the first and second portions. The method according to claim 18, In the photolithography process, the photoresist pattern is formed using a photomask including a first region, a second region having a lower transmittance than the first region, and a third region having a higher transmittance than the first region. Method of manufacturing a substrate. The method according to claim 19, In the photolithography process, the first portion is formed between the source electrode and the drain electrode, and the second portion is formed to be positioned above the data wiring. The method of claim 20, And a slit pattern smaller than the resolution of the translucent film or the exposure machine is formed in the photomask to differently control the transmittance of the first to third regions. The method according to claim 19, And the thickness of the first portion is less than 1/2 of the thickness of the second portion. The method according to claim 13, Forming a ohmic contact layer between the semiconductor layer and the data line. The method according to claim 22, And the data wiring, the ohmic contact layer and the semiconductor layer are formed together using one photosensitive film pattern.