KR20020002987A - Wafer level package - Google Patents

Abstract

PURPOSE: A wafer level package is provided to maintain a size of solder ball and a size of pitch through a size of a semiconductor chip is reduced. CONSTITUTION: A protective layer(12) is formed on an active wafer(10). A bond pad(11) is exposed by etching the protective layer(12). An auxiliary junction layer is deposited on the protective layer(12). A photo-resist layer is formed on the auxiliary junction layer. A trench is formed by patterning the photo-resist layer. A solder bump is grown within the trench. The trench is buried by growing the solder bump. The photo-resist is removed. The auxiliary junction layer is removed from a surface of the protective layer(12). A solder ball(41) is formed by using the solder bump. The active wafer(10) is divided into each semiconductor chip by cutting the active wafer(10). An auxiliary junction layer(21) is deposited on a dummy wafer. A photo-resist pattern is formed on the auxiliary junction layer(21). A metal trace(22) is grown on the exposed auxiliary junction layer(21). The photo-resist pattern is removed. Each metal trace(22) is insulated by removing the auxiliary junction layer(21) between the metal traces(22). Each semiconductor chip(10) is mounted on the dummy wafer. The solder ball(41) is mounted on the auxiliary junction layer(21). The whole surface of the dummy wafer is encapsulated by an encapsulant(60). The metal trace(22) exposed by grinding the dummy wafer. A solder resist(70) is applied on the metal trace(22) and the encapsulant(60). The metal trace(22) is exposed by etching the solder resist(70). A solder ball(42) is mounted on a ball land. A wafer level package is completed by cutting the encapsulant(60) between each semiconductor chip(10).

Description

Wafer Level Package {WAFER LEVEL PACKAGE}

The present invention relates to a wafer level package, and more particularly to a package in which a packaging process is performed in a wafer state.

Existing packages are manufactured by first cutting a wafer along a scribe line, separating the wafer into individual semiconductor chips, and then performing various packaging processes for each semiconductor chip.

However, since the conventional package described above requires many unit processes to be performed for each semiconductor chip, considering the semiconductor chips manufactured from one wafer, there is a problem that the number of processes is too large.

Therefore, in recent years, a method of manufacturing a package by first performing the above-described packaging process in a wafer state without cutting the wafer first and finally cutting along the scribe line has been proposed. A package manufactured in this manner is called a wafer level package, and its structure is briefly described with reference to FIG. 1 as follows.

The protective film 7 which is a silicon nitride film is coated on the wafer 1 surface. The bond pads 2 of the semiconductor chip formed on the wafer 1 surface are exposed through grooves formed in the protective film by etching. In this state, the lower insulating layer 3 is applied to the entire surface of the protective film. A portion of the lower insulating layer 3 positioned on the bond pad 2 is etched to expose the bond pad 2 to the outside. A metal film of copper material is vacuum deposited on the entire structure surface, wherein the metal film is also deposited on the bond pads. The metal film is partially etched so that one end of the metal pattern 4 is electrically connected to the bond pad 2. An upper insulating layer 5 is applied to the entire structure surface, and a portion of the upper insulating layer 5 positioned on the other end of the metal pattern 4 is etched to expose the other end of the metal pattern 4. The other end of the exposed metal pattern 4 becomes a ball land on which solder balls are mounted. A bonding auxiliary layer (not shown) is formed in the ball land, and the solder balls 6 are mounted on the bonding auxiliary layer.

Each of the above components is carried out in a wafer state, and the wafer 1 is cut along the scribe line and separated into individual semiconductor chips, thereby completing a wafer level package.

2 is a bottom perspective view of the finally completed wafer level package. As shown, a total of 52 solder balls 6 are arranged in a 4 × 13 matrix.

However, as the number of semiconductor chips that can be manufactured in one wafer gradually increases, the size of the wafer is limited, so that the size of the semiconductor chips gradually decreases. For example, as shown in FIG. 2, when the size of the semiconductor chip is reduced to the size shown by the dotted line, the total of sixteen solder balls 6 arranged on both sides of the dotted line are separated from the semiconductor chip.

As a countermeasure for this, as shown in FIG. 3, the size and pitch of the solder balls 6a may be reduced. However, this method introduces the following new problem.

First of all, it is almost impossible to standardize a package. The reason is that whenever the size of the semiconductor chip is changed, the size and pitch of the solder balls must also be changed. Since the solder balls must be mounted at fixed positions on the substrate, the substrate pattern must be changed as well. However, since the substrate pattern is standardized worldwide for common use, it is not possible to change only the size and pitch of the solder balls.

Moreover, since the technique of manufacturing a board | substrate pattern has a limit, the pitch of a solder ball cannot be reduced infinitely.

In addition, as the pitch of the solder balls decreases, the size of the solder balls also needs to be reduced. If the size of the solder balls is too small, the joint reliability with the substrate becomes very weak.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object thereof is to provide a wafer level package in which the size or pitch of solder balls can correspond to a standardized substrate pattern even if the size of a semiconductor chip is reduced.

Another object of the present invention is to allow the size of the semiconductor chip to be arbitrarily reduced while maintaining the pitch or size of the solder ball to the standard.

Another object of the present invention is to keep the size of the solder ball intact, to prevent the joint reliability is weak.

1 is a cross-sectional view showing a conventional wafer level package.

2 and 3 are exemplary diagrams for explaining the problem of the conventional wafer level package.

4 to 25 are cross-sectional views showing wafer level packages according to Embodiment 1 of the present invention in the order of manufacturing process;

26 to 30 are cross-sectional views illustrating a wafer level package according to a second embodiment of the present invention in the order of manufacturing process.

-Explanation of symbols for the main parts of the drawing-

10; Active semiconductor chip 11; Bond pad

21; Metal trace 41; Solder Balls for Connection Parameters

42; Mounting solder balls 60; Encapsulant

70; Solder resist

In order to achieve the above object, the wafer level package according to the present invention has the following configuration.

A bonding auxiliary layer is deposited on the bond pad of the semiconductor chip. The solder ball for the connection medium is mounted on the bonding auxiliary layer. The underside of the metal traces extending beyond the outside of the semiconductor chip is contacted on the solder balls for the connection medium. The entire product is encapsulated with an encapsulant so that only the surface of the metal traces are exposed. Solder resists are formed on the metal traces and the encapsulant surfaces to locally expose the ball lands, which are part of the surface of the metal traces located at the inner and outer sides of the semiconductor chip. Mounting solder balls are mounted on the ball lands exposed from the solder resist.

According to the above-described configuration of the present invention, a semiconductor chip having a reduced size is connected to a metal trace through a solder ball for connection, and the solder ball is mounted on the metal trace, so that the solder ball is arranged at a predetermined standard pitch while having the original size. Therefore, it is not necessary to reduce the size or pitch of the solder balls as the size of the semiconductor chip is reduced.

Best Mode for Carrying Out the Invention Preferred embodiments of the present invention will now be described based on the accompanying drawings.

Example 1

4 to 25 are cross-sectional views illustrating wafer level packages according to Embodiment 1 of the present invention in the order of manufacturing process.

First, the present invention will be described taking as an example a semiconductor chip having a size smaller than that of an existing semiconductor chip. As will be described in detail below, the present invention can maintain the pitch and size of the solder ball as it is, even for a semiconductor chip having such a small size.

As shown in FIG. 4, a protective layer 12, which is a silicon nitride film, is coated on a surface of an active wafer 10 including a plurality of semiconductor chips having a reduced size than before, and then etched to bond bond pads of each semiconductor chip ( 11).

Next, as shown in FIG. 5, the bonding auxiliary layer 20 is deposited on the surface of the protective layer 12. Bonding auxiliary layer 20 is a three-layer structure, the lower layer is a layer having excellent adhesion to the bond pad 11, the middle layer is a layer to prevent the diffusion of tin components of the solder ball, the upper layer is to strengthen the bonding strength with the solder ball It is a layer having wettability. The bonding auxiliary layer of this three-layer structure may be selected from the group consisting of aluminum / nickel / copper, aluminum / titanium / copper, aluminum / chrome / copper, titanium / titanium + tungsten / copper and chrome / chromium + copper / copper. .

Thereafter, as shown in FIG. 6, the photoresist 30 is spin coated on the bonding auxiliary layer 20. Subsequently, the photoresist 30 is patterned to form a trench 31 in the photoresist 30 that exposes the bonding auxiliary layer 20 as shown in FIG. 7.

Then, the active wafer 10 is immersed in a solder plating bath, so that the solder bumps 40 shown in FIG. 8 are grown in the trench 31. That is, the solder bumps 40 in contact with the bonding auxiliary layer 20 are grown by using the electroplating method, and the trench 31 is filled with the solder bumps 40.

Subsequently, after stripping and removing the photoresist 30 as shown in FIG. 9, only the bonding auxiliary layer 20 positioned on the surface of the protective layer 12 is etched and removed. In this manner, the portion of the bonding auxiliary layer 20 that shortens the respective bond pads 11 is removed, so that the respective bond pads 11 and the solder bumps 40 are insulated.

Then, a cylindrical solder bump 40 is formed into a spherical solder ball 41, that is, a connection ball solder ball 41, as shown in FIG. 11 through a reflow process, which is a heating process using infrared rays. . Next, the active wafer 10 is cut along the scribe line and separated into individual semiconductor chips.

Meanwhile, the dummy wafer 50 shown in FIG. 12 is prepared. As shown in FIG. 13, another bonding auxiliary layer 21 having the same structure as the bonding auxiliary layer 20 formed on the active wafer 10 is deposited on the dummy wafer 50 surface.

Subsequently, as shown in FIG. 14, a photoresist pattern 32 is formed on the bonding auxiliary layer 21. A portion of the bonding auxiliary layer 21 is locally exposed through the photoresist pattern 32, wherein a portion which does not expose the bonding auxiliary layer 21, that is, a portion having the photoresist pattern 32 is immediately described below. It becomes land.

Next, as shown in FIG. 15, the metal traces 22 are grown on the exposed bonding auxiliary layer 21 using the electroplating method. Subsequently, when the photoresist pattern 32 is stripped and removed, as shown in FIG. 16, only the metal traces 22 remain on the surface of the bonding auxiliary layer 21.

Then, each of the metal traces 22 is insulated by etching and removing portions of the bonding auxiliary layer 21 located between the metal traces 22.

The individual semiconductor chips 10 separated from the active wafer 10 are mounted on the dummy wafer 50 having the above-described structure. That is, as shown in FIG. 18, the solder balls 41 for connecting the individual semiconductor chips are mounted on the metal traces 22 of the dummy wafer 50, specifically, the bonding auxiliary layer 21. As shown in FIG. . Here, as clearly shown in FIG. 18, each metal trace 22 has a length that extends beyond the outside of the semiconductor chip, for this reason the length of the metal trace 22 is relatively longer than the conventional This is because the size of the semiconductor chip itself is reduced.

Subsequently, as shown in FIG. 19, the entire upper region of the dummy wafer 50 is sealed with the encapsulant 60. Then, when the dummy wafer 50 is ground and removed, only the metal traces 22 are exposed from the encapsulant 60 as shown in FIG.

Next, as shown in FIG. 21, the solder resist 70 is applied to the surface of the metal trace 22 and the encapsulant 60 that form the same plane while the whole resultant is inverted by 180 °. The solder resist 70 is etched to expose the metal traces 22 locally from the solder resist 70. The locally exposed portion of the metal trace 22 is the ball land, as shown in FIG. 22, the ball land is disposed not only inside the semiconductor chip but also beyond the periphery thereof.

Then, as shown in Fig. 23, mounting solder balls 42 are mounted on the ball lands. As shown in FIG. 23, the mounting solder balls 42 remain in their original size while maintaining their pitch. That is, only the size of the semiconductor chip is reduced, and the size and pitch of the mounting solder balls 42 are maintained as before.

Finally, the portion of the encapsulant 60 interposed between the semiconductor chips as shown in FIG. 24 is cut to complete the wafer level package according to the first embodiment shown in FIG. 25.

Example 2

26 to 30 are cross-sectional views illustrating a wafer level package according to a second embodiment of the present invention in the order of manufacturing process.

In the second embodiment, another structure of the dummy wafer will be disclosed. In the second embodiment, an expensive wafer is not used, and glass 80 is used instead. As shown in FIG. 26, the pattern tape is adhered to the surface of the glass 80 via the adhesive 81. The pattern tape has a structure in which the metal traces 22 made of copper are arranged on the silver polymer tape 82, so that the metal traces 22 are adhered to the surface of the glass 80 via an adhesive 81. On the other hand, the adhesive 81 is ultraviolet curable and has a property that its adhesive strength is significantly reduced by curing when exposed to ultraviolet rays.

On the premise of such conditions, as shown in FIG. 27, the individual semiconductor chips completed in Example 1 are mounted on the pattern tape surface, and the connection medium solder balls 41 are brought into contact with the metal traces 22.

Subsequently, when the upper region of the glass 80 is sealed with the encapsulant 60 and irradiated with ultraviolet rays, the adhesive 81 is cured, so that the glass 80 is easily detached from the pattern tape. Therefore, as shown in FIG. 30, the entire result of removing the glass 80 is the same as that of FIG. 20 except for the polymer tape 82. In addition, since a subsequent process is also the same as that of Example 1, repeated description is abbreviate | omitted.

As described above, according to the present invention, since the reduced size of the active semiconductor chip is electrically connected to the metal traces formed from the dummy wafer, the size and pitch of the solder balls do not have to be reduced as the size of the active semiconductor chip is reduced. Therefore, packaging of a semiconductor chip whose size is reduced to a standardized package specification is realized.

In particular, since the size of the solder balls is not reduced, the bonding force between the solder balls and the substrate is prevented from becoming weak.

Although the preferred embodiments of the present invention have been illustrated and described above, the present invention is not limited to the above-described embodiments, and the present invention is not limited to the above-described claims, and the present invention is not limited to the scope of the present invention. Anyone with knowledge will be able to make various changes.

Claims (3)

A semiconductor chip having a bond pad disposed on a surface thereof; A connection medium solder ball mounted on a bond pad of the semiconductor chip; A metal trace whose bottom surface is electrically connected to the connection medium solder ball and extends beyond the periphery of the semiconductor chip; An encapsulant encapsulating the entire resultant so that only the surface of the metal trace is exposed; A solder resist formed on the encapsulant and the metal trace surface to expose only ball lands that are part of the surface of the metal trace; And And a mounting solder ball mounted on the ball land exposed from the solder resist. The wafer level package according to claim 1, wherein a bonding auxiliary layer is deposited on the bond pad, and a connection medium solder ball is mounted on the bonding auxiliary layer. The method of claim 2, wherein the bonding auxiliary layer is selected from the group consisting of aluminum / nickel / copper, aluminum / titanium / copper, aluminum / chromium / copper, titanium / titanium + tungsten / copper and chrome / chromium + copper / copper Wafer level package, characterized in that any one of the three-layer structure.