KR20010004546A - wafer level package and method of fabricating the same - Google Patents

Abstract

PURPOSE: A wafer level package and a method for making the same are provided to prevent that a crack is formed on interfacial surface between a junction auxiliary layer and an insulating layer by maximally suppressing a side stress on the junction auxiliary layer. CONSTITUTION: A wafer level package includes a semiconductor chip having many bonding pads(11), a lower insulating layer(20), a metal pattern(30), a junction auxiliary layer(40), an upper insulating layer(61) and a solder ball(70). The lower insulating layer is deposited on the semiconductor chip in order to expose a bonding pad of the semiconductor chip. The metal pattern is connected its one end to the bonding pad, and a via hole is formed to the other end positioned on the lower insulating layer. The junction auxiliary layer is deposited on the via hole, is positioned on the same plane as the metal pattern. The bottom of the junction auxiliary layer is contacted with the lower insulating layer, a side of which is contacted with the metal pattern, and edge of which is contacted with the metal pattern surface. The upper insulating layer is deposited on a total structure in order to expose the junction auxiliary layer. The solder ball is mounted to the junction auxiliary layer.

Description

Wafer level package and method of fabricating the same

TECHNICAL FIELD The present invention relates to a wafer level package and a method for manufacturing the same, and more particularly, to a package in which a packaging process is performed in a wafer state.

Existing packages are manufactured by first cutting a wafer along a scribe line, separating the wafer into individual semiconductor chips, and then performing various packaging processes for each semiconductor chip.

However, since the conventional package described above requires many unit processes to be performed for each semiconductor chip, considering the semiconductor chips manufactured from one wafer, there is a problem that the number of processes is too large.

Therefore, in recent years, a method of manufacturing a package by first performing the above-described packaging process in a wafer state without cutting the wafer first and finally cutting along the scribe line has been proposed. Packages manufactured in this manner are referred to as wafer level packages, in which a conventional wafer level package is shown in cross section.

As shown in FIG. 1, a lower insulating layer 2 made of a polymer is coated on a surface of a wafer 1 including a plurality of semiconductor chips having bonding pads 1a. The lower insulating layer 2 is etched to expose the bonding pads 1a. A metal pattern 3 having one end connected to the bonding pad 1a is deposited on the lower insulating layer 2. The upper insulating layer 4, which is also a polymer material, is coated on the entire structure, and the portion of the upper insulating layer 4 located on the other end of the metal pattern 3 is etched to expose the other end of the metal pattern 3, , A ball land is formed. The bonding auxiliary layer 5 which is a multilayer metal film is deposited on the other end of the exposed metal pattern 3, and the solder ball 6 is mounted on the bonding auxiliary layer 5. After the solder balls 6 are mounted, the wafer 1 is cut along the scribe line, so that the wafer level package is completed by being separated into individual semiconductor chips.

However, in the conventional package shown in FIG. 1, since the lower end of the bonding auxiliary layer 5 is bonded to the metal pattern 3 made of a metal material, there is no problem, but the side surface of the bonding auxiliary layer 5 is undercut to form an inclined surface. Since they are in contact with the etching surface of 4), problems arise between their interfaces.

That is, since the bonding auxiliary layer 5 is a metal and the upper insulating layer 4 is a polymer, the thermal expansion coefficient also differs severely because of their material difference. For this reason, stress is applied to the inclined surface of the upper insulating layer 4, making the joint strength weak. If the bond strength is weakened, a serious situation arises in which a problem occurs in the flow of the electrical signal. Even if there is no great obstacle in the flow of the electrical signal, the phenomenon of lifting occurs between the interfaces due to the difference in the coefficient of thermal expansion, and water penetrates through them, which is very likely to corrode the metal pattern 3. When the metal pattern 3 is corroded, a crack phenomenon occurs.

In addition, conventionally, the material of the upper and lower insulating layers 4 and 2 is the same as the polymer. Therefore, the lower insulating layer 2 applied first is cured, and then the upper insulating layer 4 is applied and then cured. However, if the lower insulating layer 2 is not completely cured, residual moisture or solvent may explode when the upper insulating layer 4 is cured, thereby forming a wrinkle in the upper insulating layer 4.

In particular, in the related art, the bonding auxiliary layer 5 is not disposed on the same plane as the metal pattern 3 but is positioned on the metal pattern 3. For this reason, in order for the electrons to transmit the electrical signal to reach the solder balls 6, the electrons must move along the metal pattern 3 and then turn to 90 ° under the bonding auxiliary layer 5. Therefore, there is also a problem that the movement flow of the charge is not smooth.

In addition, the bonding auxiliary layer 5 is also placed on the surface of the upper insulating layer 4, the solder ball 6 is not in contact with the portion of the bonding auxiliary layer 5 placed on the surface of the upper insulating layer (4). Therefore, there is a problem in the bonding strength of the solder balls 6.

Accordingly, the present invention has been made to solve the problem of the conventional wafer-level package, to minimize the application of side stress to the bonding auxiliary layer, so that a gap is formed at the interface between the bonding auxiliary layer and the insulating layer. It is an object of the present invention to provide a wafer-level package and a method of manufacturing the same, which can be prevented.

Another object of the present invention is to make it possible to solve the problem caused in the upper insulating layer by causing the lower insulating layer is not completely cured by different materials of the upper and lower insulating layers.

Still another object of the present invention is to facilitate the flow of electrons for transmitting an electrical signal by placing the metal pattern and the bonding auxiliary layer on the same plane.

It is still another object of the present invention to further strengthen the bonding strength of the solder ball by making the edge surface portion of the bonding auxiliary layer also contact the solder ball.

1 is a cross-sectional view showing a conventional wafer level package.

2 to 5 are cross-sectional views of wafer level packages according to the present invention in the order of manufacturing process.

Description of symbols for the main parts of the drawings

10; Wafer 11; Bonding pads

20; Lower insulating layer 30; Metal pattern

40; Bonding auxiliary layer 50; Protective layer

60,61; Upper insulating layer 70; Solder ball

In order to achieve the above object, the wafer level package according to the present invention has the following configuration.

The lower insulating layer is applied to the surface of the semiconductor chip on which the plurality of bonding pads are disposed so that the bonding pads are exposed. A metal pattern, one end of which is connected to the exposed bonding pads, is deposited on the lower insulating layer. The other end of the metal pattern is etched to form a via hole. A bonding auxiliary layer made of a metal is deposited in the via hole. The bottom of the bonding auxiliary layer is in contact with the lower insulating layer, and the side is in contact with the metal pattern so that it is coplanar with the metal pattern, and the edge is on the surface of the metal pattern. Is in contact with. An upper insulating layer is applied over the entire structure to expose the bonding auxiliary layer, and the material of the upper insulating layer is different from that of the lower insulating layer. Solder balls are mounted to the bonding auxiliary layer exposed from the upper insulating layer, which is also bonded to the edge surface of the bonding auxiliary layer.

A method of manufacturing a wafer level package having the above-described configuration is as follows.

A lower insulating layer made of a silicon nitride film is applied to a wafer surface on which a plurality of semiconductor chips having bonding pads are formed. The lower insulating layer is etched to expose the bonding pads. A metal layer is deposited on the entire structure and then patterned to form a metal pattern, one end of which is connected to the bonding pad. The other end of the metal pattern is etched to form a via hole. After the deposition auxiliary metal layer is deposited on the entire structure, the metal layer is patterned so as to remain only in the via hole to form the bonding auxiliary layer. After applying the upper insulating layer of polyimide on the entire structure, the upper insulating layer is etched to expose the bonding auxiliary layer. After mounting the solder balls on the exposed bonding auxiliary layer, the wafer is cut along the scribe line and separated into individual semiconductor chips.

According to the above-described configuration of the present invention, since the bonding auxiliary layer is located on the same plane as the metal pattern, the side stress is not applied to the interfaces between each other and the formation of gaps at the interfaces is also suppressed. In particular, since the junction auxiliary layer and the metal pattern are located on the same plane, the electric charges that transfer the electric signal are linearly moved, and the electric flow is very smooth. Since the solder ball is also bonded to the edge surface of the bonding auxiliary layer, the bonding strength of the solder ball is enhanced by that amount. In addition, since the material of the lower insulating layer is a silicon nitride film, it is also prevented that uncured moisture or solvent penetrates into the upper insulating layer and forms wrinkles in the upper insulating layer.

Best Mode for Carrying Out the Invention Preferred embodiments of the present invention will now be described based on the accompanying drawings.

2 to 5 are cross-sectional views showing the wafer level package according to the present invention in the order of manufacturing process.

First, referring to FIG. 2, a lower insulating layer 20 is coated on a surface of a wafer 10 including a plurality of semiconductor chips having bonding pads 11. Subsequently, the lower insulating layer 20 is etched by dry etching to expose the bonding pads 11. Here, the lower insulating layer 20 is a silicon nitride film instead of the conventional polymer.

Then, as shown in FIG. 3, a metal film is deposited on the entire structure, and then the metal film is patterned, so that one end is connected to the bonding pad 11 and the other end is positioned on the lower insulating layer 20. 30). As the material of the metal pattern 30, one of aluminum, tungsten silicide, titanium, titanium silicide, cobalt silicide or copper may be used.

Subsequently, the other end of the metal pattern 30 is etched to form via holes (two in the example). The bonding auxiliary metal layer is deposited on the entire structure and patterned to form the bonding auxiliary layer 40 remaining only in the via hole. Here, the bonding auxiliary layer 40 has a bottom thereof in contact with the lower insulating layer 20, a side in contact with the metal pattern 30, and an edge thereof in contact with the surface of the metal pattern 30. As such, the bonding auxiliary layer 40 is coplanar with the metal pattern 30. Therefore, the charges moved along the metal pattern 30 can be moved to the junction auxiliary layer 40 in a straight line without turning to 90 °. In addition, since the side surface of the bonding auxiliary layer 40 is in contact with the metal pattern 30 of the same metal series having a large difference in coefficient of thermal expansion as described above, the side stress is suppressed from being applied to the interface, and a gap is formed in the interface. To be suppressed.

On the other hand, the bonding auxiliary layer 40 is generally a three-layer metal multilayer structure, and is composed of a conductive layer, a diffusion barrier layer, and a solder wet layer from the bottom. The conductive layer is a layer electrically connected to the metal pattern 30. The diffusion barrier layer is a layer for preventing the tin component of the solder ball from penetrating into the metal pattern 30 to form an intermetallic compound that weakens the bonding force. The solder wetting layer is a layer that is soluble to enhance bonding with the solder balls. Aluminum / nickel / copper, aluminum / titanium / copper, aluminum / chromium / copper, titanium / titanium + tungsten / copper or chrome / chromium + copper / copper may be selected as the bonding auxiliary layer 40 of the three-layer structure. Can be.

Subsequently, as shown in FIG. 4A, in order to protect the metal pattern 30 and the bonding auxiliary layer 40, the planarization process is performed after applying the protective layer 50 and the upper insulating layer 60 over the entire structure. Is carried out. Here, the material of the upper insulating layer 60 is a polyimide polymer different from the lower insulating layer 20. Then, the upper insulating layer 60 and the protective layer 50 are etched to expose the bonding auxiliary layer 40.

On the other hand, if a material having a property that can replace the role of the protective layer 50 is used as the upper insulating layer, the upper insulating layer 61 of the material having the above characteristics without applying a protective layer as shown in Figure 4b It can also be applied directly.

Subsequently, the solder balls 70 are mounted on the exposed bonding auxiliary layer 40 as shown in FIG. 5. At this time, the solder ball 70 is bonded not only to the bottom and side surfaces of the bonding auxiliary layer 30 but also to the edge surface. Therefore, the bonding strength of the solder balls 70 is further enhanced. Finally, when the wafer 10 is cut along the scribe line and separated into individual semiconductor chips, the wafer level package according to the present invention is completed.

As described above, according to the present invention, the bonding auxiliary layer is located on the same plane as the metal pattern. Therefore, since the flow of electric charge is not converted to 90 degrees as in the prior art and continues in a straight line, the electric charge flow becomes very smooth. In addition, since the side surfaces of the joining auxiliary layers come into contact with metal patterns of the same metal series, the application of side stresses to the interfaces between each other is suppressed, and the formation of gaps in the interfaces is also suppressed. As a result, the situation in which moisture penetrates through the gap formed in the interface and corrodes the metal pattern as in the prior art is prevented.

Since the solder ball is also bonded to the edge surface of the bonding auxiliary layer, the bonding strength of the solder ball is enhanced by that amount. In addition, since the material of the lower insulating layer is a silicon nitride film rather than a polymer, it is also prevented that uncured moisture or solvent penetrates into the upper insulating layer and forms wrinkles in the upper insulating layer.

Although the preferred embodiments of the present invention have been illustrated and described above, the present invention is not limited to the above-described embodiments, and the present invention is not limited to the above-described claims, and the present invention is not limited to the scope of the present invention. Anyone with knowledge will be able to make various changes.

Claims (8)

A semiconductor chip having a plurality of bonding pads on a surface thereof; A lower insulating layer applied to the surface of the semiconductor chip so that the bonding pads of the semiconductor chip are exposed; A metal pattern having one end connected to the bonding pad and a via hole formed at the other end of the lower insulating layer; A bonding auxiliary layer deposited on the via hole and coplanar with the metal pattern, a bottom surface of which is in contact with the lower insulating layer, a side surface of which is in contact with the metal pattern, and an edge of which is in contact with the surface of the metal pattern; An upper insulating layer applied over the entire structure to expose the bonding auxiliary layer; And And a solder ball mounted to the bonding auxiliary layer. The wafer level package of claim 1, wherein the solder balls are bonded to the bottom, side, and edge surfaces of the bonding auxiliary layer. The wafer level package of claim 1, wherein the material of the lower insulating layer is a silicon nitride film, and the material of the upper insulating layer is a polymer. The wafer level package of claim 1, wherein the metal pattern is made of aluminum, tungsten silicide, titanium, titanium silicide, cobalt silicide, or copper. The method of claim 1, wherein the bonding auxiliary layer is made of aluminum / nickel / copper, aluminum / titanium / copper, aluminum / chromium / copper, titanium / titanium + tungsten / copper or chrome / chromium + copper / copper. Featured wafer level package. Applying a lower insulating layer to a wafer surface on which a plurality of semiconductor chips having bonding pads are formed, and then etching the lower insulating layer to expose a bonding pad; Depositing a metal film over the entire structure, and patterning the metal film so that one end is connected to a bonding pad and the other end is formed with a metal pattern located on the lower insulating layer; Etching the other end of the metal pattern to form a via hole; Depositing a bonding auxiliary metal film on the entire structure and patterning the bonding auxiliary metal film so as to remain only in the via hole to form a bonding auxiliary layer on the same plane as the metal pattern; Applying an upper insulating layer over the entire structure, and then etching the upper insulating layer to expose the junction auxiliary layer; Mounting a solder ball on the bonding auxiliary layer; And Cutting the wafer along a scribe line and separating the wafer into individual semiconductor chips. 7. The method of claim 6, wherein the solder balls are mounted to bond to the bottom, side, and edge surfaces of the bonding auxiliary layer. The method of claim 6, wherein the lower insulating layer is formed of a silicon nitride film, and the upper insulating layer is formed of a polymer.