KR20020094472A - Method for fabricating Solder Bump for semiconductor packaging - Google Patents

Method for fabricating Solder Bump for semiconductor packaging Download PDF

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Publication number
KR20020094472A
KR20020094472A KR1020010032702A KR20010032702A KR20020094472A KR 20020094472 A KR20020094472 A KR 20020094472A KR 1020010032702 A KR1020010032702 A KR 1020010032702A KR 20010032702 A KR20010032702 A KR 20010032702A KR 20020094472 A KR20020094472 A KR 20020094472A
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South Korea
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solder
ubm
bump
forming
wiring
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KR1020010032702A
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Korean (ko)
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윤중림
고영필
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삼성전자 주식회사
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Priority to KR1020010032702A priority Critical patent/KR20020094472A/en
Publication of KR20020094472A publication Critical patent/KR20020094472A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/10125—Reinforcing structures
    • H01L2224/10126—Bump collar
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
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    • H01L2224/1147—Manufacturing methods using a lift-off mask
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/11912—Methods of manufacturing bump connectors involving a specific sequence of method steps the bump being used as a mask for patterning other parts
    • H—ELECTRICITY
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
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    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys

Abstract

PURPOSE: A method for forming a solder bump for semiconductor package is provided to improve a cutting mode of a bump and reliability of the semiconductor package by filling robust material such as polyimide into an undercut portion between a solder and a polyimide layer. CONSTITUTION: A final Cu line(14) instead of an insulating layer(12) is formed on an insulating substrate(10) by performing a damascene process. A protective layer(16) is formed thereon in order to expose a part of a surface of the final Cu line(14). An Al pad(20) is formed on the protective layer(16) by inserting a metal barrier(18). A polyimide layer(24) is formed on the above structure in order to expose a surface of the Al pad(20) of an upper side of the final Cu line(14). An UBM(Under Bump Metal)(26) is deposited thereon by using a sputtering method. The UBM(26) is formed with Cr(26a), phased Cr/Cu(26b), and Cu(26c). A resist pattern is formed on the UBM(26) in order to open a solder bump formation portion. A solder is plated on an open portion by using an electro-plating method. The unnecessary UBM(26) is etched. A polyimide layer is coated thereon. A hemispheric bump(28a) is formed by performing a reflow process.

Description

반도체 패키지용 솔더 범프 형성방법{Method for fabricating Solder Bump for semiconductor packaging}Method for fabricating solder bumps for semiconductor packaging

본 발명은 패키지 공정후 실시되는 풀 테스트시 Al 패드와 범프 간이 덕타일 모드로 즉, 솔더 범프의 일부에서 절단되도록 하여 범프의 파단 모드를 개선하고, 패키지의 신뢰성 향상을 이룰 수 있도록 한 반도체 패키지용 솔더 범프 형성방법에 관한 것이다.The present invention is a semiconductor package for improving the fracture mode of the bump and improve the reliability of the package in the ductile mode between the Al pad and the bump during the full test performed after the package process, that is, to cut in a part of the solder bump It relates to a solder bump forming method.

범프 공정이 완료된 상태에서는 통상, 패키지의 신뢰성을 확보할 목적으로 패키지 작업후 풀 테스트를 진행하고 있다. 이때, 패스(pass)의 기준은 덕트 모드로서, Pb/Sn 재질의 솔더 범프 일부에서 절단이 되는 것이다.In the state where the bump process is completed, the full test is normally performed after package operation in order to ensure the reliability of a package. At this time, the reference of the pass (duct) is a duct mode, which is cut from a part of the solder bump of Pb / Sn material.

그러나 현재의 노말 범프 공정에서는 스퍼터법으로 UBM(Under Bump Metal)을 증착한 후, 범프 포토 공정을 진행하고, 일렉트로-플레이팅(electro-plating)법으로 솔더-리드를 도금한 다음, 범프와 범프 사이의 불필요한 UBM을 습식식각법으로 제거해 주는 방식으로 공정 진행을 이루고 있어, 습식식각 과정에서 UBM이 솔더 범프 안쪽으로 치고 들어가 식각되는 즉, 언더 컷(under cut)되는 취약 구조가 만들어지게 된다.However, in the current normal bump process, UBM (Under Bump Metal) is deposited by sputtering, followed by a bump photo process, and solder-lead plating by electro-plating, followed by bump and bump. The process is performed by removing the unnecessary UBM in the wet etching method, which creates a vulnerable structure in which the UBM is etched into the solder bumps and etched, that is, the undercut.

도 1 및 도 2에는 이해를 돕기 위하여 노말 범프 공정에 의해 범프 제작이 완료된 상태의 소자 구조를 보인 단면도와, 도 1과 같이 범프를 제조했을 때 ⓐ 부분에 유발되는 불량 발생 형태를 도시한 요부상세도가 제시되어 있다.1 and 2 are cross-sectional views showing the device structure in the state in which the bump fabrication is completed by the normal bump process for the sake of understanding, and the main part showing the defect generation form caused in the ⓐ part when the bump is manufactured as shown in FIG. The figure is presented.

여기서 미설명 참조번호 10은 최종 Cu 배선(12)이 구비된 절연기판을, 18은 장벽금속막을, 20은 Al 패드를, 26은 "Cr(26a)/Phased (Cr/Cu)(26b)/Cu(26c)" 적층 구조의 UBM을, 28a는 Pb/Sn 재질의 솔더 범프를, 24는 폴리이미드막을, 16은 보호막을, 그리고 12는 절연막을 각각 나타낸다.Here, reference numeral 10 denotes an insulating substrate having a final Cu wiring 12, 18 a barrier metal film, 20 an Al pad, and 26 “Cr (26a) / Phased (Cr / Cu) (26b) / UBM having a Cu (26c) " laminated structure, 28a represents a solder bump made of Pb / Sn, 24 represents a polyimide film, 16 represents a protective film, and 12 represents an insulating film.

따라서, 이 상태에서 패키지 공정 후 풀 테스트 작업을 실시하면 UBM의 취약 구조로 인해 Al 패드(20)와 솔더 범프(28a) 간이 Pb/Sn 덕타일 모드로 절단되지 않고 UBM에서 떨어지는 불량이 발생된다. 이처럼 UBM 관련 불량이 발생할 경우, 패키지의 신뢰성 저하가 초래되므로 이에 대한 개선책이 시급하게 요구되고 있다.Therefore, if the full test operation is performed after the package process in this state, the defective structure of the UBM may cause a defect that falls between the Al pad 20 and the solder bumps 28a in the Pb / Sn ductile mode without falling into the UBM. As such, UBM-related defects cause deterioration of package reliability, and an improvement for this problem is urgently required.

본 발명의 목적은, 범프와 범프 사이의 UBM 식각후 폴리이미드와 같이 접착력이 강한 물질을 솔더(Pb/Sn)와 폴리이미드막 사이의 언더 컷된 부분에 채워서 UBM을 기존대비 강한(robust) 구조로 만들어주므로써, 풀 테스트시 덕타일 모드로 절단이 되도록 함과 아울러 패키지의 신뢰성을 높일 수 있도록 한 반도체 패키지용 솔더 범프 형성방법을 제공함에 있다.The object of the present invention is to fill the undercut portion between the solder (Pb / Sn) and the polyimide layer with a strong adhesive material such as polyimide after etching the UBM between the bumps and the bumps, thereby making the UBM a more robust structure. The present invention provides a method of forming solder bumps for a semiconductor package that allows cutting in ductile mode during a full test and increases the reliability of the package.

도 1은 종래기술로서, 노말 공정에 의해 제조된 범프 구조를 도시한 단면도,1 is a cross-sectional view showing a bump structure manufactured by a normal process according to the prior art;

도 2는 도 1과 같이 범프를 제조했을 때 야기되는 불량 발생 형태를 도시한 요부상세도,FIG. 2 is a detailed view of a main part of a defect generation form caused when a bump is manufactured as shown in FIG. 1;

도 3은 본 발명에서 제안된 범프 공정에 의해 제조된 범프 구조를 도시한 단면도,3 is a cross-sectional view showing a bump structure manufactured by the bump process proposed in the present invention;

도 4 내지 도 9는 도 3의 소자 제조방법을 보인 공정순서도이다.4 to 9 are process flowcharts showing the device manufacturing method of FIG.

상기 목적을 달성하기 위하여 본 발명에서는, Cu 배선이 구비된 절연기판 상에, 상기 Cu 배선의 표면이 일부 노출되도록 보호막을 형성하는 단계; 상기 Cu 배선과 접하도록 장벽금속막을 개재해서 상기 보호막 상에 Al 패드를 형성하는 단계; 상기 Cu 배선 상측의 상기 Al 패드 표면이 일부 노출되도록 상기 결과물 상에 폴리이미드막을 형성하는 단계; 상기 Al 배선의 표면 노출부를 포함한 상기 폴리이미드막 상에 스퍼터링법으로 UBM을 형성하는 단계; 솔더 범프 형성부의 상기 UBM 표면이 오픈되도록 상기 결과물 상에 레지스트 패턴을 형성하는 단계; 상기 오픈 부위에 일렉트로-플레이팅법으로 솔더를 도금하는 단계; 상기 레지스트 패턴을 제거하여 솔더 범프 형성부에만 선택적으로 솔더를 남기는 단계; 상기 솔더를 마스크로해서 상기 UBM을 식각하는 단계; 상기 UBM 식각 과정에서 발생된 상기 솔더와 상기 폴리이미드막 사이의 언더 컷된 부분에 접착성 물질을 채우는 단계; 및 리플로우 공정으로 상기 솔더를 반구 형상의 범프로 만드는 단계를 포함하는 반도체 패키지용 솔더 범프 형성방법이 제공된다.In order to achieve the above object, in the present invention, a step of forming a protective film on the insulating substrate provided with Cu wiring so that the surface of the Cu wiring is partially exposed; Forming an Al pad on the protective film via a barrier metal film so as to contact the Cu wiring; Forming a polyimide film on the resultant portion to partially expose the Al pad surface above the Cu wiring; Forming UBM on the polyimide film including the surface exposed portion of the Al wiring by sputtering; Forming a resist pattern on the resultant to open the UBM surface of a solder bump forming portion; Plating a solder on the open portion by an electro-plating method; Removing the resist pattern to selectively leave solder only on solder bump forming portions; Etching the UBM using the solder as a mask; Filling an adhesive material in an undercut portion between the solder and the polyimide layer generated during the UBM etching process; And forming a solder into a hemispherical bump in a reflow process.

이때, 상기 접착성 물질은 폴리이미드 재질로 형성하는 것이 바람직하다.At this time, the adhesive material is preferably formed of a polyimide material.

상기와 같이 범프 공정을 진행할 경우, 솔더(Pb/Sn)와 폴리이미드막 사이의 언더 컷 부위에 접착력이 강한 폴리이미드막을 별도 더 형성한 상태에서 패키징을 실시하는 방식으로 후속 공정이 진행되므로, 풀 테스트시 Al 패드와 범프 간을 Pb/Sn 덕타일 모드로 절단할 수 있게 된다.When the bump process is performed as described above, the subsequent process is performed by packaging in a state in which a polyimide film having a strong adhesive strength is further formed in the undercut portion between the solder (Pb / Sn) and the polyimide film. During testing, the Al pads and bumps can be cut in Pb / Sn ductile mode.

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

도 3은 본 발명에서 제안된 범프 공정에 의해 제조된 범프 구조를 도시한 단면도이도, 도 4 ~ 도 9는 도 3의 소자 제조방법을 보인 공정순서도이다. 이를 참조하여 그 제조방법을 제 6 단계로 구분하여 설명하면 다음과 같다.3 is a cross-sectional view illustrating a bump structure manufactured by the bump process proposed in the present invention, and FIGS. 4 to 9 are process flowcharts showing the device manufacturing method of FIG. 3. Referring to this, the manufacturing method is described by dividing into six steps.

제 1 단계로서, 도 4와 같이 절연기판(10) 상의 절연막(12) 내에 다마신 공정을 적용해서 최종(final) Cu 배선(14)을 형성한 후, 상기 결과물 상에 Cu 배선(14) 표면이 일부 노출되도록 보호막(16)을 형성한다.As a first step, after the damascene process is applied to the insulating film 12 on the insulating substrate 10 to form a final Cu wiring 14 as shown in FIG. 4, the surface of the Cu wiring 14 is formed on the resultant. The protective film 16 is formed to partially expose this.

제 2 단계로서, 도 5와 같이 상기 Cu 배선(14)과 접하도록 장벽금속막(18)을 개재해서 보호막(16) 상에 Al 패드(20)를 형성한다.As a second step, an Al pad 20 is formed on the protective film 16 via the barrier metal film 18 so as to contact the Cu wiring 14 as shown in FIG.

제 3 단계로서, 도 6과 같이 Cu 배선(14) 상측의 Al 패드(20) 표면이 일부 노출되도록 상기 결과물 상에 폴리이미드막(24)을 형성하고, 그 위에 스퍼터법으로 "Cr(26a)/Phased (Cr/Cu)(26b)/Cu(26c)" 적층 구조의 UBM(26)을 증착한다. 이때, 상기 UBM(26)을 이루는 Cr(26a)은 500Å 두께로 형성하는 것이 바람직하고, Phased(Cr/Cu)(26b)은 1500Å의 두께로 형성하는 것이 바람직하며, Cu(26c)는 6000Å의 두께로 형성하는 것이 바람직하다.As a third step, as shown in Fig. 6, a polyimide film 24 is formed on the resultant so that the surface of the Al pad 20 above the Cu wiring 14 is partially exposed, and on it, " Cr (26a) " UBM 26 in a / Phased (Cr / Cu) 26b / Cu (26c) stacked structure is deposited. At this time, the Cr (26a) constituting the UBM (26) is preferably formed to a thickness of 500Å, Phased (Cr / Cu) (26b) is preferably formed to a thickness of 1500Å, Cu (26c) of 6000Å It is preferable to form in thickness.

제 4 단계로서, 도 7과 같이 상기 UBM(26) 상에 솔더 범프 형성부만이 오픈되도록 레지스트 패턴(미 도시)을 형성하고, 일렉트로-플레이팅법으로 상기 오픈 부위에 솔더(28)를 도금한 다음, 상기 레지스트 패턴을 제거한다. 이어, 상기 솔더(28)를 마스크로해서 솔더와 솔더 사이의 불필요한 UBM(26)을 습식식각한다. 이 과정에서 UBM(26)이 솔더(28) 하단쪽으로도 일부 치고 들어가 식각되므로, 솔더(28)와 폴리이미드막(24) 사이에는 도시된 형태의 언더 컷이 존재하게 된다.As a fourth step, a resist pattern (not shown) is formed on the UBM 26 so that only solder bump forming portions are opened as shown in FIG. 7, and the solder 28 is plated on the open portion by an electro-plating method. Next, the resist pattern is removed. Subsequently, the unnecessary UBM 26 between the solder and the solder is wet-etched using the solder 28 as a mask. In this process, since the UBM 26 is partially etched into the lower side of the solder 28, there is an undercut of the illustrated shape between the solder 28 and the polyimide film 24.

제 5 단계로서, 도 8과 같이 상기 결과물 상에 적정 두께의 폴리이미드막을 코팅한 후, 노광 및 현상 공정을 실시하여 언더 컷 부위에만 선택적으로 폴리이미드막(30)을 남긴다. 이와 같이 언더 컷된 부분에 접착성 물질인 폴리이미드막을 별도 더 형성한 것은 이 부분의 접착(adesion) 특성을 개선하여 UBM을 기존대비 강한 구조로 만들어주므로써, 후속 풀 테스트 작업시 Al 패드(20)와 범프(28a) 간이 Pb/Sn 덕타일 모드로 절단되도록 하기 위함이다.As a fifth step, after coating a polyimide film of a suitable thickness on the resultant as shown in Figure 8, the exposure and development process is performed to leave the polyimide film 30 selectively only in the undercut portion. The additional formation of the polyimide film, which is an adhesive material, on the undercut portion further improves the adhesion characteristics of the portion, thereby making the UBM structure stronger than before, and thus, the Al pad 20 during the subsequent full test operation. This is to allow the space between the bumps 28a to be cut in the Pb / Sn ductile mode.

제 6 단계로서, 도 9와 같이 리플로우 공정을 실시하여 솔더(28)를 반구 형상의 범프(28a)로 만들어 주므로써, 본 공정 진행을 완료한다.As a sixth step, the reflow process is performed as shown in FIG. 9 to make the solder 28 into a hemispherical bump 28a, thereby completing the present process.

이와 같이 공정을 진행할 경우, 솔더(Pb/Sn)와 폴리이미드막 사이의 언더 컷 부위에 접착력이 강한 폴리이미드막을 별도 더 형성한 상태에서 후단 패키징 공정을 실시하는 방식으로 범프 공정이 진행되므로, UBM(26)을 기존대비 강한 구조로 만들 수 있게 된다.When the process proceeds as described above, the bump process proceeds by performing a post-packaging process in a state in which a polyimide film having strong adhesion is further formed in the undercut portion between the solder (Pb / Sn) and the polyimide film. (26) can be made stronger than before.

그 결과, 패키징 공정후 실시되는 풀 테스트 작업시 Pb/Sn 덕타일 모드를 만들 수 있게 되므로 범프의 파단 모드를 개선할 수 있게 될 뿐 아니라 패키지의 신뢰성 또한 향상시킬 수 있게 된다.As a result, the Pb / Sn ductile mode can be created during the full test operation after the packaging process, so that not only the break mode of the bump can be improved but also the reliability of the package can be improved.

이상에서 살펴본 바와 같이 본 발명에 의하면, UBM 식각후 폴리이미드와 같이 접착력이 뛰어난 물질을 솔더와 폴리이미드막 사이의 언더 컷된 부분에 별도 더 채워주므로써, 풀 테스트시 Al 패드와 범프 간을 Pb/Sn 덕타일 모드로 절단시킬 수 있게 되므로 범프의 파단 모드를 개선할 수 있게 될 뿐 아니라 패키지의 신뢰성을 높일 수 있게 된다.As described above, according to the present invention, by additionally filling the undercut portion between the solder and the polyimide layer with an excellent adhesive force such as polyimide after UBM etching, the Al pad and the bump are separated between the Al pad and the bump during the full test. The ability to cut in ductile mode not only improves the breaking mode of the bumps, but also improves package reliability.

Claims (5)

Cu 배선이 구비된 절연기판 상에, 상기 Cu 배선의 표면이 일부 노출되도록 보호막을 형성하는 단계;Forming a protective film on the insulating substrate provided with Cu wiring to partially expose the surface of the Cu wiring; 상기 Cu 배선과 접하도록 장벽금속막을 개재해서 상기 보호막 상에 Al 패드를 형성하는 단계;Forming an Al pad on the protective film via a barrier metal film so as to contact the Cu wiring; 상기 Cu 배선 상측의 상기 Al 패드 표면이 일부 노출되도록 상기 결과물 상에 폴리이미드막을 형성하는 단계;Forming a polyimide film on the resultant portion to partially expose the Al pad surface above the Cu wiring; 상기 Al 배선의 표면 노출부를 포함한 상기 폴리이미드막 상에 스퍼터링법으로 UBM을 형성하는 단계;Forming UBM on the polyimide film including the surface exposed portion of the Al wiring by sputtering; 솔더 범프 형성부의 상기 UBM 표면이 오픈되도록 상기 결과물 상에 레지스트 패턴을 형성하는 단계;Forming a resist pattern on the resultant to open the UBM surface of a solder bump forming portion; 상기 오픈 부위에 일렉트로-플레이팅법으로 솔더를 도금하는 단계;Plating a solder on the open portion by an electro-plating method; 상기 레지스트 패턴을 제거하여 솔더 범프 형성부에만 선택적으로 솔더를 남기는 단계;Removing the resist pattern to selectively leave solder only on solder bump forming portions; 상기 솔더를 마스크로해서 상기 UBM을 식각하는 단계; 상기 UBM 식각 과정에서 발생된 상기 솔더와 상기 폴리이미드막 사이의 언더 컷된 부분에 접착성 물질을 채우는 단계; 및Etching the UBM using the solder as a mask; Filling an adhesive material in an undercut portion between the solder and the polyimide layer generated during the UBM etching process; And 리플로우 공정으로 상기 솔더를 반구 형상의 범프로 만드는 단계를 포함하는 것을 특징으로 하는 반도체 패키지용 솔더 범프 형성방법.The solder bump forming method for a semiconductor package comprising the step of making the solder into a hemispherical bump in a reflow process. 제 1항에 있어서, 상기 UBM은 "Cr/Phased (Cr/Cu)/Cu" 적층 구조로 형성하는 것을 특징으로 하는 반도체 패키지용 솔더 범프 형성방법.The method of claim 1, wherein the UBM is formed in a “Cr / Phased (Cr / Cu) / Cu” stacked structure. 제 1항에 있어서, 상기 솔더는 Pb/Sn 재질로 형성하는 것을 특징으로 하는 반도체 패키지용 솔더 범프 형성방법.The method of claim 1, wherein the solder is formed of a Pb / Sn material. 제 1항에 있어서, 상기 UBM은 습식식각법으로 식각하는 것을 특징으로 하는 반도체 패키지용 솔더 범프 형성방법.The method of claim 1, wherein the UBM is etched by a wet etching method. 제 1항에 있어서, 상기 접착성 물질은 폴리이미드 재질로 형성하는 것을 특징으로 하는 반도체 패키지용 솔더 범프 형성방법.The method of claim 1, wherein the adhesive material is formed of a polyimide material.
KR1020010032702A 2001-06-12 2001-06-12 Method for fabricating Solder Bump for semiconductor packaging KR20020094472A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030058627A (en) * 2001-12-31 2003-07-07 주식회사 하이닉스반도체 Method for manufacturing semiconductor device
US20120007233A1 (en) * 2010-07-12 2012-01-12 Siliconware Precision Industries Co., Ltd. Semiconductor element and fabrication method thereof
CN103474407A (en) * 2013-09-29 2013-12-25 南通富士通微电子股份有限公司 Semiconductor package structure
US8865586B2 (en) 2012-01-05 2014-10-21 Taiwan Semiconductor Manufacturing Company, Ltd. UBM formation for integrated circuits

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030058627A (en) * 2001-12-31 2003-07-07 주식회사 하이닉스반도체 Method for manufacturing semiconductor device
US20120007233A1 (en) * 2010-07-12 2012-01-12 Siliconware Precision Industries Co., Ltd. Semiconductor element and fabrication method thereof
US8865586B2 (en) 2012-01-05 2014-10-21 Taiwan Semiconductor Manufacturing Company, Ltd. UBM formation for integrated circuits
CN103474407A (en) * 2013-09-29 2013-12-25 南通富士通微电子股份有限公司 Semiconductor package structure

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