KR100416614B1 - Semiconductor device for reinforcing a under structure of bonding pad and method for fabricating the same - Google Patents
Semiconductor device for reinforcing a under structure of bonding pad and method for fabricating the same Download PDFInfo
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- KR100416614B1 KR100416614B1 KR10-2002-0015149A KR20020015149A KR100416614B1 KR 100416614 B1 KR100416614 B1 KR 100416614B1 KR 20020015149 A KR20020015149 A KR 20020015149A KR 100416614 B1 KR100416614 B1 KR 100416614B1
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- Prior art keywords
- bonding pad
- substructure
- metal layer
- interlayer insulating
- insulating film
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- 238000000034 method Methods 0.000 title claims abstract description 78
- 239000004065 semiconductor Substances 0.000 title claims abstract description 66
- 230000003014 reinforcing effect Effects 0.000 title claims abstract description 22
- 239000010410 layer Substances 0.000 claims abstract description 81
- 229910052751 metal Inorganic materials 0.000 claims abstract description 63
- 239000002184 metal Substances 0.000 claims abstract description 63
- 239000011229 interlayer Substances 0.000 claims abstract description 54
- 230000008569 process Effects 0.000 claims abstract description 52
- 238000004519 manufacturing process Methods 0.000 claims abstract description 21
- 238000005530 etching Methods 0.000 claims abstract description 16
- 238000011161 development Methods 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims description 21
- 239000004020 conductor Substances 0.000 claims description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims description 7
- 238000000059 patterning Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 5
- 239000002356 single layer Substances 0.000 claims description 5
- 238000002161 passivation Methods 0.000 claims description 4
- 230000001681 protective effect Effects 0.000 claims description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 239000011241 protective layer Substances 0.000 claims description 2
- 238000001465 metallisation Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000012858 packaging process Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
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Abstract
본딩패드의 하부구조를 보강하기 위한 반도체 소자 및 그 제조방법에 관해 개시한다. 이를 위해 본 발명은 본딩패드용 금속층 하부에, 노광 공정에서는 서로 연결되지 않고 일정간격으로 이격된 점(dot)들이 전체적으로 메쉬(mesh) 형태를 이루고, 현상 및 식각 공정에서 상기 이격된 점(dot)들이 서로 연결되어 전체적으로 메쉬 형태를 이루는 트랜치 콘택부가 형성된 층간 절연막이 있는 반도체 소자 및 그 제조방법을 제공한다. 따라서, 현재의 포토공정으로는 형성할 수 없는 미세한 선폭의 매쉬형 트랜치 콘택부를 구현하여 수율을 향상시키고, 본딩능력(bondability) 및 반도체 소자의 신뢰성을 개선할 수 있다.A semiconductor device and a method of manufacturing the same for reinforcing a lower structure of a bonding pad are disclosed. To this end, the present invention is a lower portion of the bonding pad metal layer, the dots (dots) that are not connected to each other in the exposure process but spaced at a predetermined interval as a whole form a mesh (mesh), and the spaced apart (dot) in the development and etching process A semiconductor device having an interlayer insulating film having trench contact portions connected to each other to form a mesh shape as a whole and a method of manufacturing the same are provided. Therefore, the mesh type trench contact portion having a fine line width, which cannot be formed by the current photo process, may be implemented to improve the yield, and the bonding ability and the reliability of the semiconductor device may be improved.
Description
본 발명은 반도체 소자 및 그 제조방법에 관한 것으로, 더욱 상세하게는 반도체 소자 중에서 본딩패드 하부에 형성되는 층간 절연막(inter-layer dielectic)의 구조 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a structure of an inter-layer dielectic film formed under a bonding pad among semiconductor devices and a method of manufacturing the same.
반도체 소자를 제조하는 공정기술이 발달하면서 반도체 칩의 집적도는 증가하고, 그 크기는 점차 작아지고 있다. 따라서 일정 면적에 형성해야 하는 금속 배선의 수는 증가하는 경향을 나타내고 있다. 이러한 경향은 금속배선의 폭(line width)과 금속배선간의 간격(space)으로 표현되는 피치(pitch)를 감소시키는 결과를 초래하고, 금속배선의 두께 역시 감소하게 만든다.As the process technology for manufacturing a semiconductor device is developed, the degree of integration of a semiconductor chip is increasing and its size is gradually decreasing. Therefore, the number of metal wirings to be formed in a predetermined area tends to increase. This tendency results in a decrease in pitch, expressed as the line width of the metal wires and the space between the metal wires, and also in the thickness of the metal wires.
특히 반도체 소자의 제조공정중 금속배선 공정에서 최종 금속배선의 두께 감소는 후속으로 진행되는 반도체 패키징(packaging) 공정시, 와이어 본딩 공정의 불량을 증대시키는 결과를 낳는다. 본딩패드(bonding pad)란, 최종 금속배선이 노출된 부분으로서 반도체 칩 내부에 집적화된 회로패턴들을 반도체 칩 외부로 연결하기 위한 통로(path)로서의 단자를 말하며, 통상 본딩패드는 반도체 패키징 공정시 금선(gold wire), 솔더 볼(solder ball) 및 솔더 범프(solder bump)를 이용하여 외부로 연결된다.In particular, the reduction of the thickness of the final metallization in the metallization process of the semiconductor device manufacturing process may result in an increase in defects in the wire bonding process in the subsequent semiconductor packaging process. A bonding pad refers to a terminal that is a path for connecting circuit patterns integrated inside the semiconductor chip to the outside of the semiconductor chip as a portion where the final metal wiring is exposed. In general, the bonding pad is a gold wire in a semiconductor packaging process. (gold wire), solder balls, and solder bumps to connect to the outside.
일반적으로 반도체 패키지 공정중 와이어 본딩 공정의 불량률을 억제하기 위해서는, 본딩패드가 형성되는 최종 금속배선의 두께를 증가시키거나, 혹은 본딩패드의 하부구조를 보강하여야 한다. 그러나, 최종 금속배선의 두께를 증가시키는 방법은 반도체 칩의 집적화에 역행하는 방법이기 때문에 채택이 용이하지 않으며, 본딩패드의 하부구조, 즉 금속층간 절연막(inter Metallic Dielectric layer)를 보강하는 방법이 와이어 본딩의 불량률을 억제하기 위한 대안으로서 주류를 이룬다.In general, in order to suppress the defect rate of the wire bonding process during the semiconductor package process, the thickness of the final metal wiring on which the bonding pad is formed should be increased or the substructure of the bonding pad should be reinforced. However, the method of increasing the thickness of the final metal wiring is not easy to adopt because it is a method that is inverse to the integration of the semiconductor chip, and the method of reinforcing the underlying structure of the bonding pad, that is, the intermetallic dielectric layer, is used. It is mainstream as an alternative to suppress the failure rate of bonding.
상기 금속층간 절연막의 구조를 보강하기 위한 방법은, 금속층간 절연막 내에 형성되는 콘택부를 플러그(plug) 형태가 아닌 라인(line) 형태, 즉 메쉬(mesh) 형상으로 만들어 본딩패드의 기계적 강도를 증대시키고, 와이어가 본딩될 때에 내구성을 갖도록 하는 방법이 제시되고 있다.The method for reinforcing the structure of the interlayer dielectric layer may increase the mechanical strength of the bonding pad by forming a contact portion formed in the interlayer dielectric layer in a line form, that is, in a mesh form, instead of a plug form. A method of making a wire durable when bonded is proposed.
이를 위하여 상기 메쉬 형태의 콘택부는, 라인의 선폭은 가급적 미세하게 만들고, 라인형 콘택간의 간격(space)은 가급적 크게 할수록 메쉬 형상을 잘 구현할 수 있다고 할 수 있다.To this end, the contact portion of the mesh form, the line width of the line to be as small as possible, the space (space) between the line contact as possible as possible can be said to implement the mesh shape better.
도 1은 종래 기술에 의한 반도체 소자의 본딩패드 하부구조 및 그 제조방법을 설명하기 위해 도시한 단면도이다.1 is a cross-sectional view illustrating a bonding pad substructure of a semiconductor device and a method of manufacturing the same according to the related art.
도 1을 참조하면, 종래 기술에 의한 반도체 소자는, 일반적으로 반도체 기판(100) 위에 트랜지스터를 포함하는 하부구조(102), 예컨대 트랜지스터나 비트라인(bit line)과 같은 반도체 소자의 고유의 기능을 수행하는 회로패턴을 형성한 후, 절연막(104)을 상기 하부구조(102) 위에 형성한다. 이어서 상기 절연막(104) 위에 하부금속층(106)을 형성하고, 상기 하부금속층(106) 위에 금속층간절연막(108)을 증착한다.Referring to FIG. 1, a semiconductor device according to the related art generally has inherent functions of a semiconductor device, such as a transistor 102 or a bit line, including a substructure 102 including a transistor on a semiconductor substrate 100. After forming a circuit pattern to be performed, an insulating film 104 is formed on the substructure 102. Subsequently, a lower metal layer 106 is formed on the insulating film 104, and an intermetallic insulating film 108 is deposited on the lower metal layer 106.
계속해서 상기 금속층간 절연막(108)에 본딩패드(114) 하부구조를 보강하기 위한 패터닝을 수행한다. 상기 금속층간 절연막(108)에 행해지는 패터닝에 의해, 메쉬 형태의 트랜치 콘택부가 금속층간 절연막(108)에 형성된다. 상기 결과물에 콘택 플러그로 사용될 도전물질을 적층하되, 상기 도전물질이 상기 트랜치를 채우고 상기 반도체 기판 위를 덮도록 한다. 그 후, 화학기계적 연마(CMP)나 에치백(etch back)과 같은 평탄화 공정을 진행하여 메쉬 형태의 트랜치 콘택부를 채우는 콘택 플러그(110)를 형성한다. 상기 콘택 플러그(110)가 형성된 결과물 위에 최종 금속배선(112)을 적층한 후 패터닝한다. 계속해서, 상기 최종 금속배선(112) 위에 최종 보호막(116)을 증착한 다음, 패터닝을 진행하여 와이어 본딩이 수행되는 본딩패드(114)를 노출시킨다.Subsequently, patterning is performed on the interlayer insulating layer 108 to reinforce the underlying structure of the bonding pad 114. By patterning performed on the interlayer insulating film 108, a trench contact portion in the form of a mesh is formed in the interlayer insulating film 108. A conductive material to be used as a contact plug is stacked on the resultant, so that the conductive material fills the trench and covers the semiconductor substrate. Thereafter, a planarization process such as chemical mechanical polishing (CMP) or etch back is performed to form the contact plug 110 filling the trench contact in the form of a mesh. The final metal wiring 112 is laminated on the resultant formed contact plug 110 and then patterned. Subsequently, the final passivation layer 116 is deposited on the final metallization 112, and then patterning is performed to expose the bonding pad 114 on which wire bonding is performed.
도 2 및 도 3은 도1의 금속층간 절연막(IMD) 제조공정을 설명하기 위한 평면도들로서, 도 2는 노광 공정전 마스크의 단면도이고, 도 3은 현상 및 식각 공정 후의 단면도이다.2 and 3 are plan views illustrating a manufacturing process of the interlayer insulating film IMD of FIG. 1, FIG. 2 is a cross-sectional view of a mask before an exposure process, and FIG. 3 is a cross-sectional view after a developing and etching process.
도 2를 참조하면, 금속층간 절연막(108)에 형성된 메쉬 형태의 트랜치 콘택부(110)는 미세한 선폭으로 설계되고, 메쉬 형태의 트랜치 콘택부(110)에서 각각의 라인간의 거리는 가급적 떨어지도록 설계된 것을 보여준다. 이러한 설계의 목적은 후속 공정에서 메쉬 형상의 트랜치 콘택이 메쉬 형태를 그대로 유지할 수 있도록 하기 위함이다.Referring to FIG. 2, the meshed trench contact portion 110 formed in the interlayer insulating film 108 is designed to have a fine line width, and the distance between each line in the meshed trench contact portion 110 is designed to fall as far as possible. Shows. The purpose of this design is to allow the mesh-shaped trench contacts to maintain the mesh shape in subsequent processes.
그러나 상기 노광 공정은 본딩패드 하부에 있는 금속층간 절연막(108)에 대해서만 수행되는 것이 아니고, 본딩패드 하부 영역을 포함하는 반도체 기판 전체에 대하여 수행된다. 이때 본딩패드 하부에 형성되는 메쉬 형태의 트랜치 콘택부(110)는 공정 진행에 따라 메쉬 형상이 유지될 수 있도록 선폭이 가늘지만, 이에 비하여 본딩패드 하부영역을 제외한 영역, 예컨대 반도체 메모리 소자의 경우 메인 셀 영역에서 형성되는 콘택홀은 크기가 상기 메쉬 형태의 트랜치 콘택부와 비교하여 상대적으로 크다. 즉, 본딩패드가 형성될 영역은 메인 셀 영역의 콘택홀 크기보다 상대적으로 작은 선폭의 트랜치가 형성된다.However, the exposure process is not only performed on the interlayer insulating film 108 under the bonding pad, but on the entire semiconductor substrate including the bonding pad lower region. In this case, the trench contact portion 110 having a mesh shape formed under the bonding pad has a thin line width so that the mesh shape can be maintained as the process proceeds. However, in contrast to the bonding pad lower region, for example, a semiconductor memory device has a main line width. The contact hole formed in the cell region is relatively larger in size than the trench contact portion having the mesh shape. In other words, a trench having a line width relatively smaller than the contact hole size of the main cell region is formed in the region where the bonding pad is to be formed.
도 3을 참조하면, 이렇게 상대적으로 크기를 달리하는 트랜치 및 콘택홀을 본딩패드 하부 영역 및 나머지 반도체 기판 영역에서 형성하기 때문에, 현상 및 식각 공정을 거치면서 메쉬 형태의 트랜치 콘택부(109)는 점차 확장되어 커지기 때문에 원하는 형태 및 치수(dimension)를 실현하는 것이 거의 힘들다. 또한, 원하는 메쉬 형상이 형성되었다 하더라도, 후속되는 에치백 공정과, 본딩패드용 금속층을 형성한 후, 본디패드용 금속층 표면에 굴곡이 발생하는 문제가 발생한다.Referring to FIG. 3, since trenches and contact holes having relatively different sizes are formed in the bonding pad lower region and the remaining semiconductor substrate region, the trench contact portions 109 in the form of mesh gradually develop during the development and etching process. Because it expands and grows, it is almost difficult to achieve the desired shape and dimensions. In addition, even if the desired mesh shape is formed, a problem occurs in that bending occurs on the surface of the metal layer for bonding pads after the etch back process and the bonding pad metal layer are formed.
이러한 이유로 본딩패드 하부의 층간 절연막(108)에 메쉬 형태의 콘택부(110)를 형성하는 기술은 현실적으로 실제공정에 적용이 쉽지 않은 실정이다.For this reason, the technology of forming the mesh contact portion 110 in the interlayer insulating film 108 under the bonding pad is not practical to apply to the actual process in reality.
본 발명이 이루고자 하는 기술적 과제는 메쉬 형태의 트랜치 콘택부를 형성할 때에 식각 마진(etching margin)에 크게 제한됨 없이 원하는 모양 및 치수를 구현할 수 있는 본딩패드 하부구조를 보강하기 위한 반도체 소자를 제공하는데 있다.An object of the present invention is to provide a semiconductor device for reinforcing a bonding pad substructure that can implement a desired shape and dimensions without being significantly limited to an etching margin when forming a trench contact in a mesh form.
본 발명이 이루고자 하는 다른 기술적 과제는 상기 본딩패드 하부구조를 보강하기 위한 반도체 소자의 제조방법을 제공하는데 있다.Another object of the present invention is to provide a method of manufacturing a semiconductor device to reinforce the bonding pad substructure.
도 1은 종래 기술에 의한 반도체 소자의 본딩패드 하부구조 및 그 제조방법을 설명하기 위해 도시한 단면도이다.1 is a cross-sectional view illustrating a bonding pad substructure of a semiconductor device and a method of manufacturing the same according to the related art.
도 2 및 도 3은 도1의 금속층간 절연막(IMD)에 대한 제조공정을 설명하기 위한 평면도들이다.2 and 3 are plan views illustrating a manufacturing process of the interlayer insulating layer IMD of FIG. 1.
도 4 내지 도 11는 본 발명에 의한 본딩패드 하부구조를 보강하기 위한 반도체 소자의 구조 및 제조방법을 설명하기 위해 도시한 도면들이다.4 to 11 are diagrams for explaining the structure and manufacturing method of a semiconductor device for reinforcing a bonding pad substructure according to the present invention.
도 12는 본 발명에 의한 본딩패드 하부구조를 보강하기 위한 반도체 소자의 변형된 제조방법을 설명하기 위해 도시한 단면도이다.12 is a cross-sectional view illustrating a modified method of manufacturing a semiconductor device for reinforcing a bonding pad substructure according to the present invention.
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
200: 반도체 기판, 202: 하부구조,200: semiconductor substrate, 202: substructure,
204: 절연막, 206: 하부금속층,204: insulating film, 206: lower metal layer,
208: 층간 절연막, 210: 메쉬 형태의 트랜치 콘택부,208: interlayer insulating film, 210: trench contact portion in the form of a mesh,
210A: 일정간격 이격된 점들이 메쉬 형태를 이루는 전사패턴,210A: a transfer pattern in which meshes having a predetermined distance form a mesh shape,
212: 포토레지스트막, 214: 콘택 플러그,212: photoresist film, 214: contact plug,
216: 본딩패드용 금속층, 218: 최종보호막,216: metal layer for bonding pads, 218: final protective film,
220: 본딩 패드.220: bonding pads.
상기 기술적 과제를 달성하기 위하여 본 발명은, 반도체 기판과, 상기 반도체 기판 위에 형성된 하부구조와, 상기 하부구조 위에 형성되되, 노광 공정에서는 서로 연결되지 않고 일정간격으로 이격된 점(dot)들이 전체적으로 메쉬(mesh) 형태를 이루고, 현상 및 식각 공정에서 상기 이격된 점(dot)들이 서로 연결되어 전체적으로 메쉬 형태를 이루는 메쉬 형태의 트랜치 콘택부를 포함하는 층간 절연막과, 상기 층간 절연막의 메쉬 형태의 트랜치 콘택부를 채우는 콘택 플러그와, 상기 층간 절연막 위에 형성된 본딩패드용 금속층을 구비하는 것을 특징으로 하는 본딩패드 하부구조를 보강하기 위한 반도체 소자를 제공한다.In order to achieve the above technical problem, the present invention provides a semiconductor substrate, a substructure formed on the semiconductor substrate, and a dot formed on the substructure, which are not connected to each other in the exposure process and spaced apart at regular intervals. An interlayer insulating layer including a trench contact portion having a mesh shape and forming a mesh shape as a whole, wherein the spaced dots are connected to each other in a developing and etching process to form a mesh, and a trench contact portion having a mesh shape of the interlayer insulating film is formed. A semiconductor device for reinforcing a bonding pad substructure comprising a filling contact plug and a bonding pad metal layer formed on the interlayer insulating film.
본 발명의 바람직한 실시예에 의하면, 상기 하부구조는, 트랜지스터를 포함하는 회로부와, 상기 회로부 위에 형성된 절연막과, 상기 절연막 위에 형성된 하부 금속층을 구비하는 것이 적합하고, 이때 상기 절연막은 평탄화가 완료된 막질인 것이 바람직하다.According to a preferred embodiment of the present invention, it is preferable that the substructure includes a circuit portion including a transistor, an insulating film formed on the circuit portion, and a lower metal layer formed on the insulating film, wherein the insulating film has a planarization film quality. It is preferable.
상기 본딩패드용 금속층은 그 상부에 본딩패드는 노출시키면서 나머지 반도체 기판 전체를 덮는 최종보호막을 더 구비하는 것이 적합하고, 상기 서로 연결되지 않고 일정간격으로 이격된 점(dot)에서 이격된 거리는 점의 직경의 5 ~ 95% 범위로 이격된 것이 적합하다.The bonding pad metal layer may further include a final passivation layer covering the entire remaining semiconductor substrate while exposing the bonding pads thereon, and the distance between the bonding pad metal layers and the dots spaced apart from each other at regular intervals. Suitably spaced in the range of 5 to 95% of the diameter.
바람직하게는, 상기 콘택 플러그는 텅스텐이 재질 혹은 본딩패드용 금속층과동일한 재질인 것이 적합하다. 상기 본딩패드용 금속층은 단일층(single layer) 혹은 다층막(multi-layer)일 수 있다.Preferably, the contact plug is preferably made of tungsten material or the same material as the metal layer for the bonding pad. The bonding pad metal layer may be a single layer or a multi-layer.
또한, 본 발명의 바람직한 실시예에 의하면, 상기 하부구조와 상기 층간 절연막 사이에 상기 층간 절연막, 콘택 플러그 및 본딩패드용 금속층과 동일한 구조를 갖는 또 다른 층간 절연막, 콘택 플러그 및 본딩패드용 금속층을 더 구비할 수도 있다.According to a preferred embodiment of the present invention, there is further provided between the substructure and the interlayer insulating film another interlayer insulating film, contact plug and bonding pad metal layer having the same structure as the metal layer for the interlayer insulating film, contact plug and bonding pad. It may be provided.
상기 다른 기술적 과제를 달성하기 위하여 본 발명은, 반도체 기판 위에 회로부를 포함하는 하부구조를 형성하는 제1 공정과, 상기 하부구조 위에 층간 절연막을 증착하는 제2 공정과, 상기 층간 절연막 위에 포토레지스트막을 도포하고 노광 공정을 진행하되, 서로 연결되지 않고 일정간격으로 이격된 점들이 메쉬 형태를 이루는 패턴이 상기 포토레지스트막 위에 전사(transcription)되도록 노광을 진행하는 제3 공정과, 상기 노광이 이루어진 층간 절연막에 현상(development) 및 식각 공정을 진행하되, 상기 일정간격으로 이격된 점들이 확장되어 서로 연결된 메쉬 형태를 이루는 트랜치 콘택부가 형성되도록 현상 및 식각을 진행하는 제4 공정과, 상기 층간 절연막의 메쉬 형태의 트랜치 콘택부에 도전물질을 채워 콘택 플러그를 형성하는 제5 공정과, 상기 콘택 플러그가 채워진 층간 절연막 위에 본딩패드용 금속층을 증착하는 제6 공정을 구비하는 것을 특징으로 하는 본딩패드 하부구조를 보강하기 위한 반도체 소자의 제조방법을 제공한다.In order to achieve the above technical problem, the present invention provides a first process of forming a substructure including a circuit portion on a semiconductor substrate, a second process of depositing an interlayer insulating film on the substructure, and a photoresist film on the interlayer insulating film. Coating and performing an exposure process, wherein a third process of performing exposure is performed such that a pattern forming a mesh shape of dots spaced at regular intervals without being connected to each other is transferred onto the photoresist film; And a fourth process of developing and etching a trench contact portion forming a mesh connected to each other by expanding the spaced points at a predetermined interval to form a mesh connected to each other, and a mesh form of the interlayer insulating film. A fifth process of forming a contact plug by filling a conductive material in a trench contact portion of the trench; And a sixth step of depositing a bonding pad metal layer on an interlayer insulating film filled with a tack plug.
본 발명의 바람직한 실시예에 의하면, 상기 제6 공정후, 상기 본딩패드용 금속막 위에 최종보호막을 적층하는 공정과, 상기 최종보호막을 패터닝하여 상기 본딩패드용 금속층에서 본딩패드를 노출시키는 공정을 더 진행하는 것이 적합하다.According to a preferred embodiment of the present invention, after the sixth process, the step of laminating a final protective film on the bonding pad metal film, and the step of patterning the final protective film to expose the bonding pad in the bonding pad metal layer It is appropriate to proceed.
또한, 상기 제1 공정 후에, 또 다른 층간 절연막, 콘택 플러그 및 본딩패드용 금속층을 형성하기 위한 제2 공정 내지 제6 공정을 추가로 진행할 수도 있다.Further, after the first step, the second to sixth steps for forming another interlayer insulating film, the contact plug and the metal layer for the bonding pad may be further performed.
본 발명에 따르면, 본딩패드 하부의 층간 절연막에 메쉬 형태의 트랜치 콘택부를 형성함으로써 본딩패드의 기계적 강도 및 내구성을 증대시켜 와이어 본딩 공정에서 수율을 향상시키고 반도체 소자의 신뢰성을 개선할 수 있다.According to the present invention, by forming a trench contact portion in the form of a mesh in the interlayer insulating film below the bonding pad, it is possible to increase the mechanical strength and durability of the bonding pad to improve the yield in the wire bonding process and improve the reliability of the semiconductor device.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하기로 한다. 그러나, 아래의 상세한 설명에서 개시되는 실시예는 본 발명을 한정하려는 의미가 아니라, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자에게, 본 발명의 개시가 실시 가능한 형태로 완전해지도록 발명의 범주를 알려주기 위해 제공되는 것이다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the embodiments disclosed in the following detailed description are not meant to limit the present invention, but to those skilled in the art to which the present invention pertains, the disclosure of the present invention may be completed in a form that can be implemented. It is provided to inform the category.
본 발명은 그 정신 및 필수의 특징을 이탈하지 않고 다른 방식으로 실시할 수 있다. 예를 들면, 아래의 바람직한 실시예에 있어서는 층간 절연막에 형성된 메쉬 형태의 트랜치 콘택부가 메쉬형(Mesh type)이지만, 이는 다른 모양으로 얼마든지 변형이 가능하다. 가령 메쉬 형태는 사각형의 링(ring) 형태로 변경해도 무방하다. 따라서, 아래의 바람직한 실시예에서 기재한 내용은 예시적인 것이며 한정하는 의미가 아니다.The invention can be practiced in other ways without departing from its spirit and essential features. For example, in the following preferred embodiment, the trench contact portion in the form of a mesh formed on the interlayer insulating film is a mesh type, but this can be modified to any other shape. For example, the mesh shape may be changed to a rectangular ring shape. Therefore, the content described in the following preferred embodiments is exemplary and not intended to be limiting.
도 4 내지 도 11는 본 발명에 의한 본딩패드 하부구조를 보강하기 위한 반도체 소자의 구조 및 제조방법을 설명하기 위해 도시한 도면들이다.4 to 11 are diagrams for explaining the structure and manufacturing method of a semiconductor device for reinforcing a bonding pad substructure according to the present invention.
도 4를 참조하면, 반도체 기판(200)에 일반적인 하부구조(202), 예컨대 반도체 소자의 고유기능을 수행하는 트랜지스터와 비트라인과 같은 회로부를 통상의 방법에 따라 형성한다. 이어서 상기 하부구조(202) 위에 절연막(204)을 증착하고, 평탄화 공정을 진행하여 상기 절연막(204)을 평탄화시킨다.Referring to FIG. 4, a circuit portion, such as a transistor and a bit line, which performs the inherent function of a general substructure 202, for example, a semiconductor device, is formed on a semiconductor substrate 200 according to a conventional method. Subsequently, an insulating film 204 is deposited on the substructure 202, and a planarization process is performed to planarize the insulating film 204.
이러한 평탄화 공정으로 화학기계적 연마(Chemical Mechanical Polishing) 공정 혹은 에치백(etchbach) 공정을 사용할 수 있다. 계속해서, 상기 절연막(204) 위에 하부 금속층(206)을 알루미늄이나 폴리실리콘과 같은 도전물질을 사용하여 형성한다.Such a planarization process may use a chemical mechanical polishing process or an etchbach process. Subsequently, the lower metal layer 206 is formed on the insulating film 204 by using a conductive material such as aluminum or polysilicon.
도 5를 참조하면, 상기 하부 금속층(206)이 형성된 결과물 위에 층간 절연막(208), 예컨대 산화막 혹은 산화막을 포함하는 다층막을 증착한다. 그 후, 본 발명에 의해 제시되는 특별한 방법에 의하여 상기 층간 절연막(208)에 패터닝을 진행하여 메쉬 형태의 트랜치 콘택부(210)를 형성한다.Referring to FIG. 5, an interlayer insulating layer 208, for example, an oxide layer or a multilayer layer including an oxide layer, is deposited on a resultant material on which the lower metal layer 206 is formed. Thereafter, patterning is performed on the interlayer insulating film 208 by a special method proposed by the present invention to form the trench contact portion 210 in the form of a mesh.
도 6을 참조하면, 상기 층간 절연막(208)에 형성된 메쉬 형태의 트랜치 콘택부(210)를 보여주는 평면도로서, 상기 메쉬 형태의 트랜치 콘택부(210)는 층간 절연막(208)에 미세한 선폭으로 형성되고, 메쉬 형태의 트랜치 콘택부(210) 라인간의 간격이 멀리 떨어져 있지만, 이를 확대하여 보면 점(dot)들이 서로 연결된 형태이다. 도면의 참조부호 206은 하부 금속층을 가리킨다.Referring to FIG. 6, a plan view showing a trench contact portion 210 having a mesh shape formed on the interlayer insulating layer 208, and the trench contact portion 210 having a mesh shape having a fine line width is formed on the interlayer insulating layer 208. Although the distance between the lines of the mesh contact trenches 210 is far apart, when the magnified view thereof is enlarged, the dots are connected to each other. Reference numeral 206 in the figure indicates the lower metal layer.
도 7을 참조하면, 도 6의 A부분에 대한 노광 공정시의 확대도로서 층간 절연막 위에는 노광을 위한 포토레지스트막(212)이 도포(coating)되고, 상기 포토레지스트막(212)에는 일정간격 이격된 점들이 메쉬 형태를 이루는 전사패턴(210A)이 노광된다.Referring to FIG. 7, an enlarged view of the exposure process of part A of FIG. 6 is applied to the photoresist film 212 for exposure on the interlayer insulating film, and spaced apart from the photoresist film 212 by a predetermined interval. The transfer pattern 210A in which the dots form a mesh is exposed.
즉, 즉 메쉬 형태의 트랜치 콘택부를 형성하기 위해 사용되는 노광 패턴이 종래 기술과 같이 라인 형태가 아니고, 일정간격으로 이격된 점들이 서로 연결되지 않은 상태로 라인 형태로 배열된다. 이러한 노광 패턴은 현상 및 식각 공정을 거치면서 메쉬 형태의 트랜치 콘택부가 확장되는 문제점을 고려하여 설계된 것이다.That is, the exposure pattern used to form the trench contact portion in the form of a mesh is not in the form of a line as in the prior art, but is arranged in the form of a line without the points spaced apart at regular intervals from each other. The exposure pattern is designed in consideration of the problem that the trench contact portion in the form of a mesh is expanded during the development and etching process.
이때, 일정간격으로 이격된 점들은 점의 직경의 5~95% 거리로 서로 이격시킬 수 있으며, 식각 마진(etching margin)이 크면 클수록 상기 이격된 거리는 커지게 된다. 본 발명에서는 이를 30~40%의 거리로 서로 이격시켜 후속되는 현상 및 식각 공정에서 개개의 점들이 서로 연결되어 라인 형태가 되도록 하였다.At this time, the points spaced at a predetermined interval may be spaced apart from each other by a distance of 5 ~ 95% of the diameter of the point, the larger the etching margin (etching margin) the larger the spaced distance. In the present invention, it is separated from each other by a distance of 30 to 40% so that the individual points are connected to each other in a line shape in a subsequent phenomenon and etching process.
도 8을 참조하면, 도 7에서 현상 및 식각 공정(development etching process)을 추가로 진행한 후의 평면도로서, 층간 절연막(208) 위에는 서로 이격되어 라인 형태로 배열된 점들이, 이제는 서로 연결되어 라인 형태를 이루는 메쉬 형태의 트랜치 콘택부(210)로 변화되었다.Referring to FIG. 8, which is a plan view after further developing and developing etching processes in FIG. 7, points spaced apart from each other and arranged in line form on the interlayer insulating layer 208 are now connected to each other in a line form. The trench contact portion 210 has a mesh form.
즉, 현상 및 식각 공정을 거치면서 메쉬 형태의 트랜치 콘택부(210)가 확장되는 것을 보상하여 메쉬 형태의 트랜치 콘택부(210)를 만들었기 때문에 종래 기술의 문제점을 해결하고, 원하는 모양, 원하는 치수의 메쉬 형태의 트랜치 콘택부(210)를 구현할 수 있다. 물론 점들이 확장되어 라인형태를 이루는 메쉬 형태의 트랜치 콘택부(210)의 전체적인 모양은 라인을 사용하여 형성할 수 있는 다른 모양, 예컨대 사각링 형태 등의 모양으로 얼마든지 변형이 가능하다.That is, since the trench contact portion 210 in the mesh form is made by compensating for the expansion of the mesh contact trench 210 through the development and etching process, the problem of the prior art is solved, and the desired shape and desired dimension are provided. The trench contact portion 210 may be implemented in the form of a mesh. Of course, the overall shape of the trench contact portion 210 of the mesh form that the points are expanded to form a line can be modified as much as another shape that can be formed using a line, for example, a rectangular ring shape.
도 9를 참조하면, 상기 메쉬 형태의 트랜치 식각부(210)가 형성된 결과물에 콘택 플러그(214)로 사용될 도전물질, 예컨대 텅스텐이나 후속으로 형성될 본딩패드 금속층(216)과 동일 재질의 도전물질을 증착하여 상기 메쉬 형태의 트랜치 식각부(210)를 채우고, 상기 반도체 기판 위를 덮도록 한다. 이어서 화학기계적 연마(CMP)나 에치백과 같은 평탄화 공정을 진행하여 반도체 기판 위에 있는 콘택 플러그(214)로 사용될 도전물질을 제거하여 상기 메쉬 형태의 트랜치 식각부(210)를 채우는 콘택 플러그(214)를 형성한다.Referring to FIG. 9, a conductive material to be used as the contact plug 214, for example, tungsten or a bonding pad metal layer 216 to be formed subsequently, may be formed on a result of forming the trench etch portion 210 having the mesh shape. The deposition process fills the trench etched portion 210 of the mesh shape and covers the semiconductor substrate. Next, a planarization process such as chemical mechanical polishing (CMP) or etch back is performed to remove the conductive material to be used as the contact plug 214 on the semiconductor substrate, thereby filling the contact trench 214 filling the trench etched portion 210 in the mesh form. Form.
만약 필요하다면, 상기 콘택 플러그(214)와 하부금속층(206) 및 본딩패드용 금속층(216)의 경계면에 장벽층(barrier layer)이나 접착층(adhesion layer)을 통상의 방법에 의하여 추가로 형성할 수도 있다.If necessary, a barrier layer or an adhesion layer may be further formed on the interface between the contact plug 214, the lower metal layer 206, and the bonding pad metal layer 216 by a conventional method. have.
도 10을 참조하면, 상기 콘택 플러그(214)가 형성된 반도체 기판 위에 본딩패드용 금속층(216)을 적층한다. 상기 본딩패드용 금속층(216)은 알루미늄이나 구리 등의 금속을 이용한 단일층(single layer), 혹은 다층막(multi-layer)중 어느 하나를 선택할 수 있으며, 반도체 소자의 종류에 따라 다양하게 변형될 수 있다.Referring to FIG. 10, a bonding pad metal layer 216 is stacked on a semiconductor substrate on which the contact plug 214 is formed. The bonding pad metal layer 216 may be selected from a single layer or a multi-layer using a metal such as aluminum or copper, and may be variously modified according to the type of semiconductor device. have.
따라서, 본딩패드용 금속층(216) 하부의 층간 절연막(218)에 있는 메쉬 형태의 트랜치 콘택부를 채우는 콘택 플러그(214)가 후속공정의 와이어 본딩 공정이 수행될 때에 본딩패드에 가해지는 기계적 충격을 완화시키고, 하부금속층(206)과 본딩패드용 금속층(216)의 기계적 결합력을 강화시킨다. 그러므로 와이어 본딩이 수행된 후에 와이어가 본딩패드로부터 떨어지거나, 본딩패드 하부에 있는 절연막이 깨져서 이 부분에서 누설전류가 발생하는 문제점을 개선할 수 있다. 그리고 본드 풀 테스트(BPT: bond Pull Test)와 같은 신뢰성 검사의 결과도 개선할 수 있다.Therefore, the contact plug 214 filling the trench contact portion of the mesh shape in the interlayer insulating layer 218 below the metal layer 216 for the bonding pad mitigates the mechanical shock applied to the bonding pad when the wire bonding process of the subsequent process is performed. The mechanical bonding force between the lower metal layer 206 and the bonding pad metal layer 216 is enhanced. Therefore, after the wire bonding is performed, the wire may be separated from the bonding pad, or the insulating film under the bonding pad may be broken, thereby preventing the leakage current in this portion. And results of reliability tests such as bond pull test (BPT) can be improved.
도 11을 참조하면, 상기 본딩패드용 금속층(216)이 형성된 반도체 기판 위에최종보호막(218)으로 사용될 절연막을 증착하고 사진 및 식각 공정을 진행하여 본딩패드(220) 영역을 노출시킨다.Referring to FIG. 11, an insulating film to be used as the final passivation layer 218 is deposited on the semiconductor substrate on which the bonding pad metal layer 216 is formed, and the bonding pad 220 region is exposed by performing a photo and etching process.
이하, 도 11을 참조하여 본 발명에 따른 본딩패드 하부구조를 보강하기 위한 반도체 소자의 구조에 대하여 설명하기로 한다.Hereinafter, a structure of a semiconductor device for reinforcing a bonding pad substructure according to the present invention will be described with reference to FIG. 11.
본 발명에 의한 본딩패드 하부구조를 보강하기 위한 반도체 소자는 반도체 기판(200)과, 상기 반도체 기판 위에 형성된 하부구조(202, 204, 206)와, 상기 하부구조(202, 204, 206) 위에 형성되되, 노광 공정에서는 서로 연결되지 않고 일정간격으로 이격된 점(dot)들이 전체적으로 메쉬(mesh) 형태를 이루고, 현상 및 식각 공정에서 상기 이격된 점(dot)들이 서로 연결되어 전체적으로 메쉬 형태를 이루는 메쉬 형태의 트랜치 콘택부(도6의 210)를 포함하는 층간 절연막(208)과, 상기 층간 절연막(208)의 메쉬 형태의 트랜치 콘택부를 채우는 콘택 플러그(214)와, 상기 층간 절연막 위에 형성된 본딩패드용 금속층(214) 및 상기 본딩패드 금속층(214) 위에서 형성되고 본딩패드(220)를 노출시키는 최종보호막(218)으로 이루어진다.The semiconductor device for reinforcing the bonding pad substructure according to the present invention is formed on the semiconductor substrate 200, the substructures 202, 204 and 206 formed on the semiconductor substrate, and the substructures 202, 204 and 206. However, in the exposure process, dots that are not connected to each other but spaced at a predetermined interval form a mesh as a whole, and in the developing and etching process, the spaced apart dots are connected to each other to form a mesh as a whole. An interlayer insulating film 208 including a trench contact portion (210 in FIG. 6), a contact plug 214 filling a trench contact portion in a mesh form of the interlayer insulating film 208, and a bonding pad formed on the interlayer insulating film. A final protective layer 218 is formed on the metal layer 214 and the bonding pad metal layer 214 and exposes the bonding pad 220.
여기서 상기 층간절연막(208)의 메쉬 형태의 트랜치 콘택부 및 이 부분을 채우는 콘택 플러그(214)는 본 발명의 목적을 달성하는 주요한 수단이 된다.The trench contact portion in the form of a mesh of the interlayer insulating film 208 and the contact plug 214 filling the portion are the main means for achieving the object of the present invention.
도 12는 본 발명에 의한 본딩패드 하부구조를 보강하기 위한 반도체 소자의 변형된 제조방법을 설명하기 위해 도시한 단면도이다. 상세히 설명하면, 현재까지는 메쉬 형태의 트랜치 콘택부가 있는 층간 절연막(208)막이 하나인 경우의 반도체 소자에 대해서만 설명하였다. 그러나 필요에 따라 하부금속층(206) 및 본딩패드용 금속층(216) 외에 또 다른 금속층을 적용하여 반도체 소자를 만들 수도 있다. 이경우 하부금속층(206)과 층간 절연막(208) 사이에 또 다른 층간 절연막(308), 콘택 플러그(314) 및 금속층(316)을 상술한 본 발명에 의한 방법에 따라 추가로 만들 수 있다.12 is a cross-sectional view illustrating a modified method of manufacturing a semiconductor device for reinforcing a bonding pad substructure according to the present invention. In detail, the semiconductor device in the case where there is only one interlayer insulating film 208 with the trench contact portion in the mesh form has been described so far. However, in addition to the lower metal layer 206 and the bonding pad metal layer 216, another metal layer may be applied to make a semiconductor device, if necessary. In this case, between the lower metal layer 206 and the interlayer insulating film 208, another interlayer insulating film 308, the contact plug 314 and the metal layer 316 may be further made in accordance with the above-described method of the present invention.
본 발명은 상기한 실시예에 한정되지 않으며, 본 발명이 속한 기술적 사상 내에서 당 분야의 통상의 지식을 가진 자에 의해 많은 변형이 가능함이 명백하다.The present invention is not limited to the above embodiments, and it is apparent that many modifications can be made by those skilled in the art within the technical spirit to which the present invention belongs.
따라서, 상술한 본 발명에 따르면, 본딩패드 하부의 층간 절연막에 메쉬 형태의 트랜치 콘택부를 라인형이 아닌 점들이 연결된 라인형으로 형성하여, 본딩패드의 기계적 강도를 높이고, 본딩패드 하부의 접착력 및 완충능력과 같은 내구성을 향상시킴으로써, 첫째, 와이어 본딩 공정에서 수율을 향상시키고, 둘째, 반도체 소자의 신뢰성을 개선할 수 있다.Therefore, according to the present invention described above, the trench contact portion of the mesh form in the interlayer insulating film beneath the bonding pad to form a line connected to the non-linear point, thereby increasing the mechanical strength of the bonding pad, the adhesion and buffering of the bonding pad lower By improving durability, such as capacity, firstly, the yield can be improved in the wire bonding process, and secondly, the reliability of the semiconductor device can be improved.
Claims (20)
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2002-0015149A KR100416614B1 (en) | 2002-03-20 | 2002-03-20 | Semiconductor device for reinforcing a under structure of bonding pad and method for fabricating the same |
| US10/376,110 US6717272B2 (en) | 2002-03-20 | 2003-02-26 | Reinforced bond-pad substructure and method for fabricating the same |
| DE10309998A DE10309998B4 (en) | 2002-03-20 | 2003-02-27 | Semiconductor device having a reinforced substructure of a contact point and associated manufacturing method |
| JP2003070797A JP3923440B2 (en) | 2002-03-20 | 2003-03-14 | Semiconductor device having reinforcing structure under bonding pad and manufacturing method thereof |
| TW092106167A TWI227539B (en) | 2002-03-20 | 2003-03-20 | Reinforced bond-pad substructure and method for fabricating the same |
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| KR10-2002-0015149A KR100416614B1 (en) | 2002-03-20 | 2002-03-20 | Semiconductor device for reinforcing a under structure of bonding pad and method for fabricating the same |
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| KR20030075780A KR20030075780A (en) | 2003-09-26 |
| KR100416614B1 true KR100416614B1 (en) | 2004-02-05 |
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| US (1) | US6717272B2 (en) |
| JP (1) | JP3923440B2 (en) |
| KR (1) | KR100416614B1 (en) |
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| US6960836B2 (en) * | 2003-09-30 | 2005-11-01 | Agere Systems, Inc. | Reinforced bond pad |
| JP2007514312A (en) * | 2003-12-10 | 2007-05-31 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Wire bonded semiconductor components with reinforced interconnect metallization |
| JP4517843B2 (en) * | 2004-12-10 | 2010-08-04 | エルピーダメモリ株式会社 | Semiconductor device |
| JP4522435B2 (en) * | 2007-06-05 | 2010-08-11 | 富士通テン株式会社 | High frequency circuit device and radar device |
| JP5034740B2 (en) | 2007-07-23 | 2012-09-26 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
| CN101796633A (en) * | 2007-07-26 | 2010-08-04 | Nxp股份有限公司 | Reinforced structure for a stack of layers in a semiconductor component |
| CN101765913B (en) * | 2007-07-30 | 2012-10-03 | Nxp股份有限公司 | Reduced bottom roughness of stress buffering element of a semiconductor component |
| JP4953132B2 (en) * | 2007-09-13 | 2012-06-13 | 日本電気株式会社 | Semiconductor device |
| JP5098655B2 (en) * | 2008-01-18 | 2012-12-12 | 富士通セミコンダクター株式会社 | Electronic equipment |
| JP5610905B2 (en) | 2010-08-02 | 2014-10-22 | パナソニック株式会社 | Semiconductor device |
| US8802554B2 (en) * | 2011-02-15 | 2014-08-12 | Marvell World Trade Ltd. | Patterns of passivation material on bond pads and methods of manufacture thereof |
| CN105518865A (en) * | 2013-08-28 | 2016-04-20 | 三菱电机株式会社 | Semiconductor device |
| CN107422610B (en) * | 2017-07-20 | 2019-09-24 | 武汉华星光电技术有限公司 | A kind of motherboard exposure method |
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| KR19980086680A (en) * | 1997-05-01 | 1998-12-05 | 윌리엄 비. 켐플러 | Bond Pad Reinforcement System and Method |
| KR20010073536A (en) * | 2000-01-18 | 2001-08-01 | 윤종용 | Semiconductor chip having mesh type plug below the electro-pad |
| US20010010408A1 (en) * | 1999-03-19 | 2001-08-02 | Ming-Dou Ker | Low-capacitance bonding pad for semiconductor device |
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| US5939790A (en) * | 1996-04-09 | 1999-08-17 | Altera Corporation | Integrated circuit pad structures |
| US5700735A (en) * | 1996-08-22 | 1997-12-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming bond pad structure for the via plug process |
| TW416575U (en) * | 1998-06-03 | 2000-12-21 | United Integrated Circuits Corp | Bonding pad structure |
| US6444295B1 (en) * | 1998-12-29 | 2002-09-03 | Industrial Technology Research Institute | Method for improving integrated circuits bonding firmness |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR19980086680A (en) * | 1997-05-01 | 1998-12-05 | 윌리엄 비. 켐플러 | Bond Pad Reinforcement System and Method |
| US20010010408A1 (en) * | 1999-03-19 | 2001-08-02 | Ming-Dou Ker | Low-capacitance bonding pad for semiconductor device |
| KR20010073536A (en) * | 2000-01-18 | 2001-08-01 | 윤종용 | Semiconductor chip having mesh type plug below the electro-pad |
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| TW200403801A (en) | 2004-03-01 |
| US20030178644A1 (en) | 2003-09-25 |
| US6717272B2 (en) | 2004-04-06 |
| JP3923440B2 (en) | 2007-05-30 |
| KR20030075780A (en) | 2003-09-26 |
| DE10309998A1 (en) | 2003-10-16 |
| DE10309998B4 (en) | 2006-06-14 |
| TWI227539B (en) | 2005-02-01 |
| JP2003282627A (en) | 2003-10-03 |
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