JP5098655B2 - Electronic equipment - Google Patents

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Publication number
JP5098655B2
JP5098655B2 JP2008008753A JP2008008753A JP5098655B2 JP 5098655 B2 JP5098655 B2 JP 5098655B2 JP 2008008753 A JP2008008753 A JP 2008008753A JP 2008008753 A JP2008008753 A JP 2008008753A JP 5098655 B2 JP5098655 B2 JP 5098655B2
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Japan
Prior art keywords
terminal
insulating film
pad
groove
electronic component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2008008753A
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Japanese (ja)
Other versions
JP2009170745A (en
Inventor
政志 加納
文彦 谷口
信勝 斎藤
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Fujitsu Semiconductor Ltd
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Fujitsu Semiconductor Ltd
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Priority to JP2008008753A priority Critical patent/JP5098655B2/en
Publication of JP2009170745A publication Critical patent/JP2009170745A/en
Application granted granted Critical
Publication of JP5098655B2 publication Critical patent/JP5098655B2/en
Expired - Fee Related legal-status Critical Current
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To suppress a metal short between adjacent pads of an electronic device. <P>SOLUTION: The electronic device comprises an electronic component, a first terminal and a second terminal formed on the electronic component, a first insulating film formed on the electronic component and having an opening wherein the first terminal and the second terminal are exposed, a conductive member connected to at least one of the first terminal and the second terminal and containing a material different from the first terminal and the second terminal, and a groove portion formed in the first insulating film between the first terminal and the second terminal. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

本発明は電子装置に関するものであり、特に、半導体チップ等の電子部品に設けるパッドの狭ピッチ化に伴う短絡を防止するための構成に特徴のある電子装置に関するものである。   The present invention relates to an electronic device, and more particularly to an electronic device characterized by a configuration for preventing a short circuit due to a narrow pitch of pads provided on an electronic component such as a semiconductor chip.

従来より半導体チップは実装基板上にワイヤボンディング或いはフリップチップボンディングにより実装されているが、半導体チップの周辺部にはボンディングワイヤと接続するためのパッド或いは実装基板に設けたパッドと接続するためのバンプが設けられている（例えば、特許文献１或いは特許文献２参照）。   Conventionally, a semiconductor chip is mounted on a mounting substrate by wire bonding or flip chip bonding, but a pad for connecting to a bonding wire or a pad provided on the mounting substrate is provided on the periphery of the semiconductor chip. (For example, refer to Patent Document 1 or Patent Document 2).

ここで、図６を参照して、従来のワイヤボンディング構造を説明する。
図６は、従来のワイヤボンディング構造の説明図であり、多層配線構造を形成した半導体基板上の最上部近傍に層間絶縁膜７１に設けた凹部にＴａＮを介してＣｕを埋め込んでＣｕ埋込パッド７２を形成したのち、層間絶縁膜７３を形成し、次いで、Ｃｕ埋込パッド７２に達するビアホールを形成し、このビアホールをＴｉＮを介してＷで埋め込んで複数のＷプラグ７４を形成する。 Here, a conventional wire bonding structure will be described with reference to FIG.
FIG. 6 is an explanatory view of a conventional wire bonding structure, in which Cu is embedded in a recess provided in an interlayer insulating film 71 in the vicinity of the uppermost portion on a semiconductor substrate on which a multilayer wiring structure is formed via TaN, and a Cu embedded pad. After forming 72, an interlayer insulating film 73 is formed, and then a via hole reaching the Cu embedded pad 72 is formed, and the via hole is embedded with W through TiN to form a plurality of W plugs 74.

次いで、Ａｌ膜を堆積させたのち所定の形状にエッチングすることによって、Ａｌパッド７５を形成し、次いで、ＳｉＮ膜からなる保護膜７６を設け、この保護膜７６に開口部７７を設けてボンディング部を露出させる。
このようにパッドを形成した半導体チップを実装基板に実装する場合には、Ａｌパッド７５と実装基板に設けたパッド同士をＡｕワイヤ７８でボンディングする。 Next, an Al film is deposited and then etched into a predetermined shape, thereby forming an Al pad 75. Next, a protective film 76 made of a SiN film is provided, and an opening 77 is provided in the protective film 76 to provide a bonding portion. To expose.
When the semiconductor chip having the pads formed thereon is mounted on the mounting substrate, the Al pad 75 and the pads provided on the mounting substrate are bonded with the Au wire 78.

近年、電子機器の小型化、軽量化、薄型化の要求に伴い、また、半導体チップのコストダウンの要求に伴い半導体チップの縮小化が進んでいる。
このような半導体チップの縮小化に対応するために、半導体チップに設けるパッドの狭ピッチ化への対応が急務になっている。
特開２００４−０５４３０４号公報 特開２００６−２７３９０４号公報 In recent years, along with demands for downsizing, weight reduction, and thinning of electronic devices, and reductions in the cost of semiconductor chips, semiconductor chips are being reduced.
In order to cope with such a reduction in the size of the semiconductor chip, there is an urgent need to cope with a narrow pitch of pads provided on the semiconductor chip.
Japanese Patent Laid-Open No. 2004-054304 JP 2006-273904 A

しかしながら、従来構造を単純に狭パッドピッチ化した場合には、半導体チップを実装基板上に実装したのち、長期高温環境下に放置した場合、Ａｕワイヤを構成するＡｕとＡｌパッドを構成するＡｌとの間の合金反応が進行して、Ａｕ−Ａｌ合金層の成長による隣接パッド間のメタルショートが発生するという問題があるので、図７を参照してこの事情を説明する。   However, when the conventional structure is simply made with a narrow pad pitch, if the semiconductor chip is mounted on a mounting substrate and then left in a high-temperature environment for a long time, Au constituting the Au wire and Al constituting the Al pad There is a problem that a metal short between adjacent pads occurs due to the progress of the alloy reaction between the adjacent pads due to the growth of the Au—Al alloy layer, and this situation will be described with reference to FIG.

図７は従来のワイヤボンディング構造の問題点の説明図であり、半導体チップを長期高温環境下に放置した場合、熱ストレス等によりＡｕ−Ａｌ合金層７９が成長し、このＡｕ−Ａｌ合金層７９の成長により最上層の保護膜７６にクラックが生じ、クラックにより隣接するＡｌパッド７５の間が空洞でつながる。   FIG. 7 is an explanatory diagram of problems of the conventional wire bonding structure. When a semiconductor chip is left in a high temperature environment for a long time, an Au—Al alloy layer 79 grows due to thermal stress or the like, and this Au—Al alloy layer 79 is grown. As a result of the growth, a crack is generated in the uppermost protective film 76, and the adjacent Al pads 75 are connected by a cavity through the crack.

そして、この空洞部にＡｕ−Ａｌ合金層７９が成長しながら進入していくことによって隣接するＡｌパッド７５の間がＡｕ−Ａｌ合金層７９によって接続されてパッドショートが発生することになる。   Then, as the Au—Al alloy layer 79 enters the cavity while growing, the adjacent Al pads 75 are connected by the Au—Al alloy layer 79 and a pad short circuit occurs.

或いは、ボンディングワイヤとしてＡｌを用いて超音波ボンディングした場合にも、半導体チップを長期高温環境下に放置して熱ストレス等により最上層の保護膜７６にクラックが生じた場合、ストレスマイグレーション等によりＡｌが拡散・移動して、隣接するＡｌパッド７５の間がＡｌによって接続されてパッドショートが発生する虞がある。   Alternatively, when ultrasonic bonding is performed using Al as a bonding wire, if the semiconductor chip is left in a high temperature environment for a long time and a crack occurs in the uppermost protective film 76 due to thermal stress or the like, Al may be generated due to stress migration or the like. May diffuse and move, and the adjacent Al pads 75 may be connected by Al to cause a pad short circuit.

さらに、このような事情は、半導体チップを実装基板上にフリップチップボンディングした場合にも同じであり、実装基板に設けたパッドと半導体チップに設けたバンプの間の合金化反応の進行により、メタルショートが発生することになる。   Furthermore, this situation is the same when the semiconductor chip is flip-chip bonded onto the mounting substrate, and the metallization proceeds between the pads provided on the mounting substrate and the bumps provided on the semiconductor chip. A short circuit will occur.

したがって、本発明は、隣接するパッド間のメタルショートを抑制することを目的とする。   Therefore, an object of the present invention is to suppress metal shorts between adjacent pads.

本発明の一観点によれば、電子部品と、前記電子部品上に形成される第１の端子および第２の端子と、前記電子部品上に形成され、前記第１の端子及び前記第２の端子が露出する開口を備えた第１の絶縁膜と、前記第１の端子及び第２の端子の少なくとも一方に接続され、前記第１の端子及び前記第２の端子とは異なる材料を含む導電部材と、前記第１の端子と前記第２の端子との間の前記第１の絶縁膜に形成される溝部と、を備える電子装置が提供される。   According to an aspect of the present invention, an electronic component, a first terminal and a second terminal formed on the electronic component, and a first terminal and the second terminal formed on the electronic component. A first insulating film having an opening through which a terminal is exposed, and a conductive material connected to at least one of the first terminal and the second terminal and including a material different from that of the first terminal and the second terminal There is provided an electronic device including a member and a groove formed in the first insulating film between the first terminal and the second terminal.

本発明によれば、合金層の伸長或いは元素のストレスマイグレーションによる拡散・移動が溝部により遮断されるので、隣接するパッド間でメタルショートが発生することがない。   According to the present invention, since the diffusion / movement due to the elongation of the alloy layer or the stress migration of the element is blocked by the groove portion, the metal short circuit does not occur between the adjacent pads.

ここで図１を参照して、本発明の実施の形態を説明する。
図１は、本発明の実施の形態の構成説明図であり、本発明は、電子部品装置において、電子部品と、電子部品上に形成される第１の端子１および第２の端子２と、電子部品上に形成され、第１の端子１及び第２の端子２が露出する開口を備えた第１の絶縁膜３と、第１の端子１及び第２の端子２の少なくとも一方に接続され、第１の端子１及び第２の端子２とは異なる材料を含む導電部材５と、第１の端子１と第２の端子２との間の第１の絶縁膜３に形成される溝部４とを備えるものである。 An embodiment of the present invention will now be described with reference to FIG.
FIG. 1 is a configuration explanatory diagram of an embodiment of the present invention. The present invention relates to an electronic component, a first terminal 1 and a second terminal 2 formed on the electronic component in an electronic component device, Connected to at least one of the first insulating film 3 formed on the electronic component and having an opening through which the first terminal 1 and the second terminal 2 are exposed, and the first terminal 1 and the second terminal 2. The conductive member 5 containing a material different from that of the first terminal 1 and the second terminal 2 and the groove 4 formed in the first insulating film 3 between the first terminal 1 and the second terminal 2. Are provided.

このように、第１の端子１と第２の端子２との間の第１の絶縁膜３に溝部４を形成することによって、第１の端子１及び第２の端子２と導電部材５との間の合金化が進んでも、溝部４で合金層９の成長が抑制されて隣接する端子に到達することがなく、それによって、メタルショートを抑制することができる。   Thus, by forming the groove 4 in the first insulating film 3 between the first terminal 1 and the second terminal 2, the first terminal 1, the second terminal 2, and the conductive member 5 Even when alloying progresses, the growth of the alloy layer 9 is suppressed in the groove 4 and does not reach the adjacent terminal, thereby suppressing a metal short circuit.

また、合金化が伴わない場合にも、第１の端子１及び第２の端子２を構成する元素がストレスマイグレーションにより拡散・移動しても、溝部４を超えて移動することはないので、メタルショートを抑制することができる。   Further, even when alloying is not accompanied, even if the elements constituting the first terminal 1 and the second terminal 2 are diffused and moved by stress migration, they do not move beyond the groove portion 4. Short circuit can be suppressed.

より具体的には、Ｃｕ埋込層等の下層パッド８の直上にＷプラグ等の導電性ビア７を介してＡｌ等からなるパッドを設け、パッドをＳｉＮ膜等の保護膜となる第１の絶縁膜３で被覆し、保護膜にボンディング用窓部を形成する際に、隣接するパッド間に存在する保護膜に、保護膜の下に設けたビア形成用絶縁膜に達する溝を形成するものである。   More specifically, a pad made of Al or the like is provided directly above a lower layer pad 8 such as a Cu buried layer via a conductive via 7 such as a W plug, and the pad serves as a protective film such as a SiN film. When forming a bonding window on the protective film by covering with the insulating film 3, a groove reaching the via forming insulating film provided under the protective film is formed in the protective film existing between adjacent pads. It is.

この場合の溝は、樹脂等のエポキシ樹脂等の絶縁膜で埋めても良く、ワイヤボンディングの場合には全体を覆う被覆樹脂を利用して埋め込んでも良いし、また、フリップチップボンディングの場合にはアンダーフィル樹脂を利用して埋め込んでも良い。   The groove in this case may be filled with an insulating film such as an epoxy resin such as resin, or may be filled using a covering resin that covers the whole in the case of wire bonding, or in the case of flip chip bonding It may be embedded using an underfill resin.

また、溝部４に第１の絶縁膜３とは異なる材料からなる第２の絶縁膜、特に、第１の絶縁膜３よりも低い硬度を有する第２の絶縁膜、典型的には樹脂膜を設けることが望ましく、第２の絶縁膜は柔らかいのでクラックが発生することがなく、それによって、クラックが繋がって隣接する第１の端子１と第２の端子２が空洞で繋がることがない。   Further, a second insulating film made of a material different from that of the first insulating film 3, particularly a second insulating film having a hardness lower than that of the first insulating film 3, typically a resin film, is formed in the groove 4. Desirably, the second insulating film is soft and does not generate cracks, whereby the cracks are connected and the adjacent first terminal 1 and second terminal 2 are not connected by a cavity.

また、この溝部４は、第１の絶縁膜３の下に設けた第３の絶縁膜６に達するように深く設けることが望ましく、それによって、第３の絶縁膜６にクラックが発生しても隣接する第１の端子１と第２の端子２が空洞で繋がることがない。   Further, it is desirable to provide the groove 4 deeply so as to reach the third insulating film 6 provided under the first insulating film 3, so that even if a crack occurs in the third insulating film 6. Adjacent first terminal 1 and second terminal 2 are not connected by a cavity.

また、第１の端子１及び第２の端子２は、典型的には電子部品の表面に形成されるパッドであり、導電部材５はボンディングワイヤである。   The first terminal 1 and the second terminal 2 are typically pads formed on the surface of the electronic component, and the conductive member 5 is a bonding wire.

また、第２の絶縁膜は溝部４に別途設けても良いが、電子部品、第１の端子１、第２の端子２、及び、導電部材５を封止する第４の絶縁膜を利用して溝部４を埋め込んでも良い。   The second insulating film may be provided separately in the groove 4, but the fourth insulating film that seals the electronic component, the first terminal 1, the second terminal 2, and the conductive member 5 is used. The groove 4 may be embedded.

次に、図２を参照して、本発明の実施例１の半導体装置を説明する。
図２は、本発明の実施例１の半導体装置の構成説明図であり、半導体チップ１０の表面部に設けたシリカ系の層間絶縁膜１１に凹部を形成したのち、ＴａＮを介してＣｕで埋め込むことによって、Ｃｕ埋込パッド１２を形成する。 Next, with reference to FIG. 2, the semiconductor device of Example 1 of this invention is demonstrated.
FIG. 2 is a diagram illustrating the configuration of the semiconductor device according to the first embodiment of the present invention. After a recess is formed in the silica-based interlayer insulating film 11 provided on the surface portion of the semiconductor chip 10, it is embedded with Cu via TaN. Thereby, the Cu embedded pad 12 is formed.

次いで、シリカ系の層間絶縁膜１３を堆積させたのち、Ｃｕ埋込パッド１２の周辺部に達する複数のビアホールを設けたのち、ＴｉＮを介してＷで埋め込むことによってＷプラグ１４を形成し、次いで、Ａｌ膜を堆積させたのち所定の形状にエッチングすることによってＡｌパッド１５を構成する。   Next, after depositing a silica-based interlayer insulating film 13, a plurality of via holes reaching the peripheral portion of the Cu embedded pad 12 are provided, and then a W plug 14 is formed by embedding with W through TiN, Then, after depositing the Al film, the Al pad 15 is formed by etching into a predetermined shape.

次いで、全面にＳｉＮ膜からなる保護膜１６を堆積させたのち、Ａｌパッド１５の中央部が露出するようにボンディング窓１７を形成するとともに、隣接するＡｌパッド１５同士の間にＡｌパッド１５の下面より深い層間絶縁膜１３に達する溝１８を設ける。   Next, after depositing a protective film 16 made of a SiN film on the entire surface, a bonding window 17 is formed so that the central portion of the Al pad 15 is exposed, and the lower surface of the Al pad 15 is disposed between adjacent Al pads 15. A trench 18 reaching the deeper interlayer insulating film 13 is provided.

なお、この溝１８の幅は、例えば、幅が４４μｍのＡｌパッド１５の間隔が２〜１０μｍの場合、１〜５μｍ、例えば、２μｍとし、深さは、例えば、１．１５μｍとする。
また、溝１８の長さは、Ａｌパッド１６の長さの±１０％とする。 The width of the groove 18 is, for example, 1 to 5 μm, for example, 2 μm, and the depth is, for example, 1.15 μm when the interval between the Al pads 15 having a width of 44 μm is 2 to 10 μm.
The length of the groove 18 is ± 10% of the length of the Al pad 16.

次いで、溝１８を形成した半導体チップ１０を表面にパッド２１を形成するとともに裏面にボールグリッド２２を形成した実装回路基板２０上に接着剤２３を用いてマウントしたのち、Ａｕワイヤ２４を用いて、パッド２１とＡｌパッド１５とを接続する。   Next, the semiconductor chip 10 in which the groove 18 is formed is mounted using the adhesive 23 on the mounting circuit board 20 on which the pad 21 is formed on the front surface and the ball grid 22 is formed on the back surface, and then the Au wire 24 is used. The pad 21 and the Al pad 15 are connected.

次いで、半導体チップ１０の表面をエポキシ樹脂からなる被覆樹脂２５で封止することによって、本発明の実施例１の半導体装置が完成する。
この時、溝１８の内部にはエポキシ樹脂が入り込んで溝１８を完全に埋め込むことになる。 Next, the surface of the semiconductor chip 10 is sealed with a coating resin 25 made of an epoxy resin, whereby the semiconductor device of Example 1 of the present invention is completed.
At this time, the epoxy resin enters the inside of the groove 18 and completely fills the groove 18.

このように、本発明の実施例１においては、隣接するＡｌパッド間の保護絶縁膜に深い溝を設けているので、この半導体装置を長期高温環境下に放置した場合に、熱ストレス等によって保護膜にクラックが発生しても溝があるので、クラック同士が繋がって隣接するＡｌパッド間に空洞が形成されることがない。   As described above, in Example 1 of the present invention, since the deep groove is provided in the protective insulating film between adjacent Al pads, when this semiconductor device is left in a long-term high temperature environment, it is protected by thermal stress or the like. Even if cracks occur in the film, there are grooves, so that the cracks are not connected and a cavity is not formed between adjacent Al pads.

したがって、ＡｌパッドとＡｕワイヤが合金反応を起こして合金層がクラックを介して成長したとしても隣接するＡｌパッド間が合金層によりメタルショートを起こすことがない。
また、溝の幅が非常に狭い場合には、溝部の空隙を介して成長した合金層同士が接触する可能性もあるが、溝内には柔らかくてクラックの発生しない樹脂で充填されているので、成長した合金層同士が接触してメタルショートを起こすこともない。 Therefore, even if the Al pad and the Au wire cause an alloy reaction and the alloy layer grows through cracks, the adjacent Al pads do not cause a metal short due to the alloy layer.
In addition, when the width of the groove is very narrow, there is a possibility that the alloy layers grown through the gap in the groove portion may come into contact with each other, but since the groove is filled with a soft resin that does not generate cracks. The grown alloy layers do not contact each other to cause a metal short circuit.

次に、図３を参照して、本発明の実施例２の半導体装置を説明する。
図３は、本発明の実施例２の半導体装置の構成説明図であり、上記実施例１と全く同様に半導体チップ１０の表面部に設けたＡｌパッド１５の周囲を覆う保護膜１６に溝１８を設ける。 Next, with reference to FIG. 3, the semiconductor device of Example 2 of this invention is demonstrated.
FIG. 3 is a diagram for explaining the configuration of the semiconductor device according to the second embodiment of the present invention. In exactly the same manner as in the first embodiment, the groove 18 Is provided.

次いで、溝１８を形成した半導体チップ１０を、内部配線３１を有するとともに、表面にボンディングパッド３２を有し、このボンディングパッド３２にスルービア３３を介して接続する側面電極３４及び底面電極３５を設けた多層セラミックパッケージ３０に接着剤３６を用いてマウントしたのち、Ａｕワイヤ３７を用いて、ボンディングパッド３２ととＡｌパッド１５とを接続する。
なお、内部電極３１の内のいくつかは側面電極３４と繋がっており、側面電極３４を介して底面電極３５から取り出される。 Next, the semiconductor chip 10 in which the groove 18 is formed has an internal wiring 31, a bonding pad 32 on the surface, and a side electrode 34 and a bottom electrode 35 connected to the bonding pad 32 via a through via 33. After the multilayer ceramic package 30 is mounted using the adhesive 36, the bonding pad 32 and the Al pad 15 are connected using the Au wire 37.
Some of the internal electrodes 31 are connected to the side electrode 34 and are taken out from the bottom electrode 35 through the side electrode 34.

次いで、蓋部材３８を蓋部材３８の周辺部に設けたＡｇ−Ｓｎ半田等の封止部材３９を多層セラミックパッケージ３０に当接した状態で加熱処理して封止することによって、本発明の実施例２の半導体装置が完成する。   Next, the lid member 38 is sealed by heat treatment in a state where the sealing member 39 such as Ag—Sn solder provided on the periphery of the lid member 38 is in contact with the multilayer ceramic package 30. The semiconductor device of Example 2 is completed.

このように、本発明の実施例１においては、蓋部材を用いてパッケージを封止しているので、溝に樹脂等の絶縁膜が充填されることがないが、この半導体装置を長期高温環境下に放置した場合に、熱ストレス等によって保護膜にクラックが発生しても溝があるので、クラック同士が繋がって隣接するＡｌパッド間に空洞が形成されることがない。   As described above, in the first embodiment of the present invention, since the package is sealed using the lid member, the groove is not filled with an insulating film such as a resin. When left underneath, even if a crack occurs in the protective film due to thermal stress or the like, there is a groove, so that the cracks are not connected and a cavity is not formed between adjacent Al pads.

したがって、ＡｌパッドとＡｕワイヤが合金反応を起こして合金層がクラックを介して成長したとしても隣接するＡｌパッド間が合金層によりメタルショートを起こすことがない。   Therefore, even if the Al pad and the Au wire cause an alloy reaction and the alloy layer grows through cracks, the adjacent Al pads do not cause a metal short due to the alloy layer.

次に、図４を参照して、本発明の実施例３の半導体装置を説明する。
図４は、本発明の実施例３の半導体装置の構成説明図であり、半導体チップ４０の表面部に設けたシリカ系の層間絶縁膜４１にトレンチを形成したのち、ＴａＮを介してＣｕで埋め込むことによって、最上層のＣｕ埋込パッド４２を形成する。 Next, with reference to FIG. 4, the semiconductor device of Example 3 of this invention is demonstrated.
FIG. 4 is a diagram for explaining the configuration of the semiconductor device according to the third embodiment of the present invention. After a trench is formed in the silica-based interlayer insulating film 41 provided on the surface portion of the semiconductor chip 40, it is filled with Cu via TaN. As a result, the uppermost Cu embedded pad 42 is formed.

次いで、シリカ系の層間絶縁膜４３を堆積させたのち、Ｃｕ埋込パッド４２に達するビアホールを設けたのち、ＴａＮを介してＣｕで埋め込むことによってＷプラグ４４を形成し、次いで、Ａｌ膜を堆積させたのち所定の形状にエッチングすることによってＡｌパッド４５を構成する。   Next, after depositing a silica-based interlayer insulating film 43, a via hole reaching the Cu embedded pad 42 is provided, and then a W plug 44 is formed by filling with Cu via TaN, and then an Al film is deposited. After that, the Al pad 45 is formed by etching into a predetermined shape.

次いで、全面にＳｉＮ膜からなる保護膜４６を堆積させたのち、Ａｌパッド４５の中央部が露出するように開口部４７を形成するとともに、隣接するＡｌパッド４５同士の間にＡｌパッド４５の下面より深い層間絶縁膜４３に達する溝４８を設ける。   Next, after depositing a protective film 46 made of a SiN film on the entire surface, an opening 47 is formed so that the central portion of the Al pad 45 is exposed, and the lower surface of the Al pad 45 is disposed between adjacent Al pads 45. A trench 48 reaching the deeper interlayer insulating film 43 is provided.

なお、この溝４８の幅は、Ａｌパッド４５の間隔が２〜１０μｍの場合、１〜５μｍ、例えば、２μｍとし、深さは、例えば、１．１５μｍとする。
また、溝４８の長さは、Ａｌパッド４５の長さの±１０％とする。
次いで、メッキ法を用いてＡｌパッド４５上にＡｕバンプ４９を形成する。 The width of the groove 48 is 1 to 5 μm, for example 2 μm, and the depth is 1.15 μm, for example, when the interval between the Al pads 45 is 2 to 10 μm.
The length of the groove 48 is ± 10% of the length of the Al pad 45.
Next, an Au bump 49 is formed on the Al pad 45 by using a plating method.

次いで、Ａｕバンプ４９を形成した半導体チップ４０を表面に周囲をソルダーレジスト５２で囲まれたパッド５１を形成するとともに裏面に半田ボール５３を形成した実装回路基板５０に、Ａｕバンプ４９とパッド５１とが対向するように当接させたのち、加熱することによってＡｕバンプ４９とパッド５１とを合金接合する。   Next, the Au bump 49, the pad 51, and the pad 51 are formed on the mounting circuit board 50 in which the pad 51 surrounded by the solder resist 52 is formed on the front surface of the semiconductor chip 40 on which the Au bump 49 is formed and the solder ball 53 is formed on the back surface. After being brought into contact with each other, the Au bump 49 and the pad 51 are alloy-bonded by heating.

次いで、半導体チップ４０と実装回路基板５０との間にアンダーフィル樹脂５４を充填したのち、全体を被覆樹脂５５をポッティングすることによって、本発明の実施例３の半導体装置が完成する。
この場合、アンダーフィル工程において、アンダーフィル樹脂５４が溝４８の内部に入り込んで溝４８を完全に埋め込むことになる。 Next, after filling the underfill resin 54 between the semiconductor chip 40 and the mounting circuit board 50, the whole is potted with the covering resin 55, thereby completing the semiconductor device according to the third embodiment of the present invention.
In this case, in the underfill process, the underfill resin 54 enters the groove 48 and completely fills the groove 48.

このように、本発明の実施例３においては、隣接するＡｕバンプ間の保護絶縁膜に深い溝を設けているので、この半導体装置を長期高温環境下に放置した場合に、熱ストレス等によって保護膜にクラックが発生しても溝があるので、クラック同士が繋がって隣接するＡｕバンプ間に空洞が形成されることがない。   As described above, in Example 3 of the present invention, a deep groove is provided in the protective insulating film between adjacent Au bumps. Therefore, when this semiconductor device is left in a long-term high temperature environment, it is protected by thermal stress or the like. Even if a crack occurs in the film, there is a groove, so that the cracks are not connected and a cavity is not formed between adjacent Au bumps.

また、溝の幅が非常に狭い場合には、溝部の空隙を介して成長した合金層同士が接触する可能性もあるが、溝内には柔らかくてクラックの発生しない樹脂で充填されているので、成長した合金層同士が接触してメタルショートを起こすこともない。   In addition, when the width of the groove is very narrow, there is a possibility that the alloy layers grown through the gap in the groove portion may come into contact with each other, but since the groove is filled with a soft resin that does not generate cracks. The grown alloy layers do not contact each other to cause a metal short circuit.

さらに、ストレスマイグレーションによってＡｌパッドを構成するＡｌが拡散・移動したとしても、溝によって遮られるので、移動したＡｌにより隣接するＡｌパッド間にリーク電流が流れることがない。   Further, even if Al constituting the Al pad diffuses and moves due to stress migration, the groove is blocked by the groove, so that no leak current flows between adjacent Al pads due to the moved Al.

次に、図５を参照して、本発明の実施例４の半導体装置を説明する。
図５は、本発明の実施例４の半導体装置の構成説明図であり、上記実施例３と全く同様に半導体チップ４０の表面部に設けたＡｌパッド４５の周囲を覆う保護膜４６に溝４８を設けるとともに、Ａｌパッド４５上にＡｕバンプ４９を形成する。 Next, with reference to FIG. 5, the semiconductor device of Example 4 of this invention is demonstrated.
FIG. 5 is a diagram for explaining the configuration of the semiconductor device according to the fourth embodiment of the present invention. Like the third embodiment, the groove 48 is formed in the protective film 46 covering the periphery of the Al pad 45 provided on the surface portion of the semiconductor chip 40. And an Au bump 49 is formed on the Al pad 45.

次いで、Ａｕバンプ４９を形成した半導体チップ４０を、内部配線６１を有するとともに、表面にボンディングパッド６２を有し、このボンディングパッド６２にスルービア６３を介して接続する側面電極６４及び底面電極６５を設けた多層セラミックパッケージ６０に、Ａｕバンプ４９とボンディングパッド６２とが対向するように当接したのち、加熱することにより結合する。
なお、内部電極６１の内のいくつかは側面電極６４と繋がっており、側面電極６４を介して底面電極６５から取り出される。 Next, the semiconductor chip 40 on which the Au bumps 49 are formed has an internal wiring 61 and a bonding pad 62 on the surface. A side electrode 64 and a bottom electrode 65 connected to the bonding pad 62 via a through via 63 are provided. The Au bump 49 and the bonding pad 62 are brought into contact with the multilayer ceramic package 60 so as to face each other, and then bonded by heating.
Some of the internal electrodes 61 are connected to the side electrode 64 and are taken out from the bottom electrode 65 via the side electrode 64.

次いで、蓋部材６６を蓋部材６６の周辺部に設けたＡｇ−Ｓｎ半田等の封止部材６７を多層セラミックパッケージ６０に当接した状態で加熱処理して封止することによって、本発明の実施例４の半導体装置が完成する。   Next, the lid member 66 is sealed by heat treatment in a state where the sealing member 67 such as Ag-Sn solder provided on the periphery of the lid member 66 is in contact with the multilayer ceramic package 60, thereby implementing the present invention. The semiconductor device of Example 4 is completed.

このように、本発明の実施例４においては、蓋部材を用いてパッケージを封止しているので、溝に樹脂等の絶縁膜が充填されることがないが、この半導体装置を長期高温環境下に放置した場合に、熱ストレス等によって保護膜にクラックが発生しても溝があるので、クラック同士が繋がって隣接するＡｕパッド間に空洞が形成されることがない。   Thus, in Example 4 of the present invention, since the package is sealed using the lid member, the groove is not filled with an insulating film such as a resin. When left underneath, even if a crack occurs in the protective film due to thermal stress or the like, there is a groove, so that the cracks are not connected and a cavity is not formed between adjacent Au pads.

以上、本発明の各実施例を説明してきたが、本発明は各実施例に記載された構成・条件等に限られるものではなく各種の変更が可能であり、例えば、ワイヤボンディングの際には、Ａｕワイヤを用いているが、Ａｌワイヤを用いて超音波ボンディングする場合にも、有効である。   Although the embodiments of the present invention have been described above, the present invention is not limited to the configurations and conditions described in the embodiments, and various modifications are possible. For example, in wire bonding Although Au wire is used, it is also effective when ultrasonic bonding is performed using Al wire.

以上の実施例１乃至実施例４を含む実施の形態に関し、さらに、以下の付記を開示する。
（付記１） 電子部品と、前記電子部品上に形成される第１の端子および第２の端子と、前記電子部品上に形成され、前記第１の端子及び前記第２の端子が露出する開口を備えた第１の絶縁膜と、前記第１の端子及び第２の端子の少なくとも一方に接続され、前記第１の端子及び前記第２の端子とは異なる材料を含む導電部材と、前記第１の端子と前記第２の端子との間の前記第１の絶縁膜に形成される溝部と、を備えることを特徴とする電子装置。
（付記２） 前記溝部に埋め込まれ、前記第１の絶縁膜とは異なる材料からなる第２の絶縁膜をさらに備えることを特徴とする付記１記載の電子装置。
（付記３） 前記第２の絶縁膜は、前記第１の絶縁膜よりも低い硬度を有することを特徴とする付記２記載の電子装置。
（付記４） 前記第１の端子及び前記第２の端子はＡｌを含み、且つ、前記導電部材はＡｕを含むことを特徴とする付記１乃至３のいずれか１に記載の電子装置。
（付記５） 前記第１の絶縁膜の下にさらに第３の絶縁膜を備え、前記溝部は、前記第３の絶縁膜に到達していることを特徴とする付記１乃至４のいずれか１に記載の電子装置。
（付記６） 前記第１の端子及び前記第２の端子は、前記電子部品の表面に形成されるパッドであり、前記導電部材は、ボンディングワイヤであることを特徴とする付記１乃至５のいずれか１に記載の電子装置。
（付記７） 前記電子部品、前記第１の端子、前記第２の端子、及び、前記導電部材を封止する第４の絶縁膜をさらに備え、前記溝部に埋め込まれる第２の絶縁膜は、前記第４の絶縁膜の一部であることを特徴とする付記１乃至６のいずれか１に記載の電子装置。
（付記８） 前記電子部品を搭載する回路基板をさらに備え、前記第１の端子及び前記第２の端子は、前記電子部品のうちの前記回路基板との対向面に形成されるバンプであり、前記導電部材は前記回路基板の表面に形成されるパッドであることを特徴とする付記１乃至５のいずれか１に記載の電子装置。
（付記９） 前記電子部品と前記回路基板との間にさらに第５の絶縁膜を備え、前記第２の絶縁膜は、前記第５の絶縁膜の一部であることを特徴とする付記８記載の電子装置。
（付記１０） 前記電子部品は半導体素子であることを特徴とする付記１乃至４のいずれか１に記載の電子装置。 The following additional notes are further disclosed with respect to the embodiments including the first to fourth embodiments.
(Supplementary Note 1) An electronic component, a first terminal and a second terminal formed on the electronic component, and an opening formed on the electronic component and exposing the first terminal and the second terminal. A conductive member that is connected to at least one of the first terminal and the second terminal and includes a material different from that of the first terminal and the second terminal; An electronic device comprising: a groove formed in the first insulating film between the first terminal and the second terminal.
(Supplementary note 2) The electronic device according to supplementary note 1, further comprising a second insulating film embedded in the groove and made of a material different from the first insulating film.
(Supplementary note 3) The electronic device according to supplementary note 2, wherein the second insulating film has a lower hardness than the first insulating film.
(Supplementary note 4) The electronic device according to any one of supplementary notes 1 to 3, wherein the first terminal and the second terminal contain Al, and the conductive member contains Au.
(Supplementary Note 5) Any one of Supplementary Notes 1 to 4, further comprising a third insulating film below the first insulating film, wherein the groove portion reaches the third insulating film. An electronic device according to 1.
(Supplementary Note 6) Any one of Supplementary Notes 1 to 5, wherein the first terminal and the second terminal are pads formed on a surface of the electronic component, and the conductive member is a bonding wire. The electronic device according to claim 1.
(Supplementary Note 7) The electronic component, the first terminal, the second terminal, and a fourth insulating film that seals the conductive member are further provided, and the second insulating film embedded in the groove portion is, The electronic device according to any one of appendices 1 to 6, wherein the electronic device is a part of the fourth insulating film.
(Additional remark 8) It is further provided with the circuit board which mounts the said electronic component, The said 1st terminal and the said 2nd terminal are bumps formed in the opposing surface with the said circuit board among the said electronic components, The electronic device according to any one of appendices 1 to 5, wherein the conductive member is a pad formed on a surface of the circuit board.
(Supplementary note 9) A supplementary note 8, further comprising a fifth insulating film between the electronic component and the circuit board, wherein the second insulating film is a part of the fifth insulating film. The electronic device described.
(Additional remark 10) The said electronic component is a semiconductor element, The electronic device of any one of Additional remark 1 thru | or 4 characterized by the above-mentioned.

本発明の活用例としては、半導体装置が典型的なものであるが、実装基板に搭載される電子部品は半導体素子に限られるものではなく、例えば、光偏光素子等の強誘電体デバイスにも適用されるものである。   As a practical example of the present invention, a semiconductor device is typical, but the electronic component mounted on the mounting substrate is not limited to the semiconductor element, and for example, to a ferroelectric device such as a light polarizing element. Applicable.

本発明の実施の形態の構成説明図である。It is a configuration explanatory view of an embodiment of the present invention. 本発明の実施例１の半導体装置の構成説明図である。1 is a configuration explanatory diagram of a semiconductor device according to a first embodiment of the present invention. 本発明の実施例２の半導体装置の構成説明図である。FIG. 6 is a configuration explanatory diagram of a semiconductor device according to a second embodiment of the present invention. 本発明の実施例３の半導体装置の構成説明図である。It is a structure explanatory drawing of the semiconductor device of Example 3 of this invention. 本発明の実施例４の半導体装置の構成説明図である。It is a structure explanatory view of the semiconductor device of Example 4 of the present invention. 従来のワイヤボンディング構造の説明図である。It is explanatory drawing of the conventional wire bonding structure. 従来のワイヤボンディング構造の問題点の説明図である。It is explanatory drawing of the problem of the conventional wire bonding structure.

符号の説明Explanation of symbols

１ 第１の端子
２ 第２の端子
３ 第１の絶縁膜
４ 溝部
５ 導電部材
６ 第３の絶縁膜
７ プラグ
８ 下層パッド
９ 合金層
１０，４０ 半導体チップ
１１，４１ 層間絶縁膜
１２，４２ Ｃｕ埋込パッド
１３，４３ 層間絶縁膜
１４，４４ Ｗプラグ
１５，４５ Ａｌパッド
１６，４６ 保護膜
１７ ボンディング窓
１８，４８ 溝
２０ 実装回路基板
２１ パッド
２２ ボールグリッド
２３ 接着剤
２４ Ａｕワイヤ
２５ 被覆樹脂
３０，６０ 多層セラミックパッケージ
３１，６１ 内部配線
３２，６２ ボンディングパッド
３３，６３ スルービア
３４，６４ 側面電極
３５，６５ 底面電極
３６ 接着剤
３７ Ａｕワイヤ
３８，６６ 蓋部材
３９，６７ 封止部材
４７ 開口部
４９ Ａｕバンプ
５０ 実装回路基板
５１ パッド
５２ ソルダーレジスト
５３ 半田ボール
５４ アンダーフィル樹脂
５５ 被覆樹脂
７１ 層間絶縁膜
７２ Ｃｕ埋込パッド
７３ 層間絶縁膜
７４ Ｗプラグ
７５ Ａｌパッド
７６ 保護膜
７７ 開口部
７８ Ａｕワイヤ
７９ Ａｕ−Ａｌ合金層 DESCRIPTION OF SYMBOLS 1 1st terminal 2 2nd terminal 3 1st insulating film 4 Groove part 5 Conductive member 6 3rd insulating film 7 Plug 8 Lower layer pad 9 Alloy layer 10, 40 Semiconductor chip 11, 41 Interlayer insulating film 12, 42 Cu Embedded pad 13, 43 Interlayer insulating film 14, 44 W plug 15, 45 Al pad 16, 46 Protective film 17 Bonding window 18, 48 Groove 20 Mounted circuit board 21 Pad 22 Ball grid 23 Adhesive 24 Au wire 25 Coating resin 30 , 60 Multilayer ceramic package 31, 61 Internal wiring 32, 62 Bonding pad 33, 63 Through via 34, 64 Side electrode 35, 65 Bottom electrode 36 Adhesive 37 Au wire 38, 66 Lid member 39, 67 Sealing member 47 Opening 49 Au bump 50 Mounting circuit board 51 Pad 52 Solder resist 53 Solder ball 54 Le resin 55 coating resin 71 interlayer insulating film 72 Cu embedded pad 73 interlayer insulating film 74 W plugs 75 Al pad 76 protective film 77 opening 78 Au wire 79 Au-Al alloy layer

Claims (5)

電子部品と、
前記電子部品上に形成される第１の端子および第２の端子と、
前記電子部品上に形成され、前記第１の端子及び前記第２の端子が露出する開口を備えた第１の絶縁膜と、
前記第１の端子及び第２の端子の少なくとも一方に接続され、前記第１の端子及び前記第２の端子とは異なる材料を含む導電部材と、
前記第１の端子と前記第２の端子との間の前記第１の絶縁膜に形成される溝部と、
を備えることを特徴とする電子装置。 Electronic components,
A first terminal and a second terminal formed on the electronic component;
A first insulating film formed on the electronic component and having an opening through which the first terminal and the second terminal are exposed;
A conductive member connected to at least one of the first terminal and the second terminal and including a material different from the first terminal and the second terminal;
A groove formed in the first insulating film between the first terminal and the second terminal;
An electronic device comprising: 前記溝部に埋め込まれ、前記第１の絶縁膜とは異なる材料からなる第２の絶縁膜をさらに備えることを特徴とする請求項１記載の電子装置。 The electronic device according to claim 1, further comprising a second insulating film embedded in the groove portion and made of a material different from that of the first insulating film. 前記第２の絶縁膜は、前記第１の絶縁膜よりも低い硬度を有することを特徴とする請求項２記載の電子装置。 The electronic device according to claim 2, wherein the second insulating film has a hardness lower than that of the first insulating film. 前記第１の端子及び前記第２の端子はＡｌを含み、且つ、前記導電部材はＡｕを含むことを特徴とする請求項１乃至３のいずれか１項に記載の電子装置。 4. The electronic device according to claim 1, wherein the first terminal and the second terminal contain Al, and the conductive member contains Au. 5. 前記電子部品は半導体素子であることを特徴とする請求項１乃至４のいずれか１項に記載の電子装置。 The electronic device according to claim 1, wherein the electronic component is a semiconductor element.
JP2008008753A 2008-01-18 2008-01-18 Electronic equipment Expired - Fee Related JP5098655B2 (en)

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