TWI451545B - Bump pad structure and method for creating the same - Google Patents
Bump pad structure and method for creating the same Download PDFInfo
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- TWI451545B TWI451545B TW099114442A TW99114442A TWI451545B TW I451545 B TWI451545 B TW I451545B TW 099114442 A TW099114442 A TW 099114442A TW 99114442 A TW99114442 A TW 99114442A TW I451545 B TWI451545 B TW I451545B
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- pad
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- bump
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- aluminum
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Description
本申請案主張於2009年5月8日申請之美國臨時專利申請案編號第61/176522號,名稱為「凸塊墊結構(Bump Pad Structure)」的有利條件,在此將此申請案一併列入參考。The present application claims the benefit of the U.S. Provisional Patent Application Serial No. 61/176,522, filed on May 8, 2009, entitled "Bump Pad Structure", which is incorporated herein by reference. Listed for reference.
本發明一般是有關於一種半導體元件之凸塊墊結構,且特別是有關於一種覆晶裝置(Flip Chip Assembly)之凸塊墊結構。BACKGROUND OF THE INVENTION 1. Field of the Invention This invention generally relates to a bump pad structure for a semiconductor device, and more particularly to a bump pad structure for a flip chip assembly.
一覆晶封裝包含面朝下的半導體晶片,此半導體晶片利用銲接凸塊電性與物理性地(mechanically)貼附於基材。因覆晶封裝之可擴縮性(scalability)而可允許覆晶封裝使用在較小之應用中,因此覆晶封裝通常優於其他傳統封裝。但隨著覆晶封裝之尺寸的縮減,以及低介電常數介電質之使用的增加,源自於施加在覆晶封裝上的機械應力,可能導致與凸塊墊金屬和低介電常數介電質有關的問題發生。A flip chip package includes a face down semiconductor wafer that is electrically and physically attached to the substrate using solder bumps. Due to the scalability of flip chip packages, flip chip packages can be used in smaller applications, so flip chip packages are generally superior to other conventional packages. However, as the size of flip chip packages shrinks and the use of low dielectric constant dielectrics increases, the mechanical stresses imposed on the flip chip package may result in bump metal and low dielectric constant. Problems related to electrical quality occur.
第1A圖係繪示銲接凸塊墊及其下方內連線結構之一部分的剖面圖。銲接凸塊2實體地連接至凸塊底層金屬(UBM)墊4,且凸塊底層金屬墊4透過半導體晶片上之外鈍化層6中之開口而與鋁墊8連接。鋁墊8位在內鈍化層10上。內鈍化層10位於未摻雜矽玻璃(USG)層12之上,而未摻雜矽玻璃層12位於低介電常數層14上。未摻雜矽玻璃層12可包含多個包含電路系統之獨立金屬層。鋁線路16電性耦合鋁墊8至內連線結構中之鋁接觸18。介層窗20a、20b與20c經由內鈍化層10,而將鋁接觸18連接至接觸22。接觸22透過數個介層窗24而耦合至另一接觸26。另外的接觸與介層窗可包含如半導體元件所要求之內連線結構。Figure 1A is a cross-sectional view showing a portion of the solder bump pad and its underlying interconnect structure. The solder bump 2 is physically connected to the bump underlayer metal (UBM) pad 4, and the bump underlayer metal pad 4 is connected to the aluminum pad 8 through an opening in the passivation layer 6 on the semiconductor wafer. The aluminum pad 8 is placed on the inner passivation layer 10. The inner passivation layer 10 is over the undoped bismuth glass (USG) layer 12 and the undoped bismuth glass layer 12 is on the low dielectric constant layer 14. The undoped bismuth glass layer 12 can comprise a plurality of individual metal layers comprising circuitry. Aluminum line 16 electrically couples aluminum pad 8 to aluminum contact 18 in the interconnect structure. The vias 20a, 20b and 20c connect the aluminum contacts 18 to the contacts 22 via the inner passivation layer 10. Contact 22 is coupled to another contact 26 through a plurality of vias 24. Additional contact and vias may include interconnect structures as required for semiconductor components.
第1B圖係繪示凸塊底層金屬墊4、鋁墊8、鋁線路16、鋁接觸18、及介層窗20a、20b與20c之布局。外八邊形區域代表鋁墊8。中間之八邊形區域代表凸塊底層金屬墊4。內八邊形區域代表凸塊底層金屬墊4之凹陷部。FIG. 1B illustrates the layout of the under bump metal pad 4, the aluminum pad 8, the aluminum line 16, the aluminum contact 18, and the vias 20a, 20b, and 20c. The outer octagonal area represents the aluminum pad 8. The middle octagonal region represents the under bump metal pad 4. The inner octagonal region represents the depressed portion of the under bump metal pad 4 of the bump.
第1A圖與第1B圖所示之凸塊墊一般應用在覆晶裝置上。因覆晶裝置之可應用在較小科技之可擴縮性,覆晶裝置較適用於最新之科技中。此外,隨著裝至尺寸的縮減,特別是22nm科技,且隨著低介電常數介電質的使用變得更為普遍,特別是當介電常數值低於2.5,來自於凸塊墊之機械應力的衝擊也隨之增加。凸塊墊上的應力,例如半導體元件與附著之封裝基材之間的熱膨脹係數(CTE)的不匹配所造成之剝離或剪應力,可因源自於弱化之凸塊墊而造成之半導體元件的機械故障,例如未摻雜矽玻璃、低介電常數介電質或銲接凸塊的破裂。The bump pads shown in Figs. 1A and 1B are generally applied to a flip chip device. Because the flip chip device can be applied to the scalability of smaller technologies, the flip chip device is more suitable for the latest technology. In addition, as the size is reduced, especially 22nm technology, and with the use of low dielectric constant dielectrics become more common, especially when the dielectric constant value is less than 2.5, the machine from the bump pad The impact of stress also increases. The stress on the bump pad, such as the peeling or shear stress caused by the mismatch of the coefficient of thermal expansion (CTE) between the semiconductor component and the attached package substrate, may be due to the semiconductor component resulting from the weakened bump pad Mechanical failures such as undoped bismuth glass, low dielectric constant dielectric or cracking of solder bumps.
另一常用在覆晶技術中的結構為銅上直凸塊(Direct Bump On Copper;DBOC)結構。在DBOC結構中,凸塊底層金屬與上金屬化層之銅金屬直接接觸。無鋁墊或內鈍化層應用在DBOC結構中。無鋁墊或內鈍化層來作為緩衝,DBOC結構通常具有較低之機械強度,而遭受如同上述之相同問題。因此,習知技術需要一種具有增強之機械強度的凸塊墊,以克服習知技術缺點,Another commonly used structure in flip chip technology is the Direct Bump On Copper (DBOC) structure. In the DBOC structure, the bump underlayer metal is in direct contact with the copper metal of the upper metallization layer. No aluminum pad or inner passivation layer is used in the DBOC structure. Without an aluminum pad or an inner passivation layer as a buffer, DBOC structures typically have lower mechanical strength and suffer from the same problems as described above. Therefore, the prior art requires a bump pad with enhanced mechanical strength to overcome the shortcomings of the prior art.
本發明之目的就是在提供一種凸塊接合墊結構極其製造方法。藉由本發明之實施例通常可解決或防止這些與其他問題,且通常可達到技術優點,其中本發明之實施例增加凸塊接合墊結構之機械強度。因此,可保護未摻雜矽玻璃層與低介電常數介電層之間的界面。SUMMARY OF THE INVENTION It is an object of the present invention to provide an extreme manufacturing method for a bump bond pad structure. These and other problems are generally solved or prevented by embodiments of the present invention, and technical advantages are generally achieved, wherein embodiments of the present invention increase the mechanical strength of the bump bond pad structure. Therefore, the interface between the undoped bismuth glass layer and the low-k dielectric layer can be protected.
根據本發明之一實施例,一種凸塊接合墊結構包含:一基材,包含一上層;一強化墊位於此上層上;一中間層位於上層之上方;一中間連接墊位於中間層上;一外層位於中間層之上方;以及一凸塊底層金屬經由外層中之開口連接至中間連接墊。According to an embodiment of the invention, a bump bond pad structure comprises: a substrate comprising an upper layer; a reinforcing pad on the upper layer; an intermediate layer above the upper layer; and an intermediate connection pad on the intermediate layer; The outer layer is above the intermediate layer; and a bump underlayer metal is connected to the intermediate connection pad via an opening in the outer layer.
根據本發明之另一實施例,一種凸塊接合墊結構包含:一銅墊位於一基材之上層上;一鋁墊位於一內鈍化層上;一介層窗物理性地耦合銅墊至鋁墊;以及一凸塊底層金屬經由外鈍化層中之開口,物理性地且電性耦合至鋁墊。內鈍化層位於基材之上層上。According to another embodiment of the present invention, a bump bond pad structure includes: a copper pad on an upper layer of a substrate; an aluminum pad on an inner passivation layer; and a via window physically coupling the copper pad to the aluminum pad And a bump underlayer metal is physically and electrically coupled to the aluminum pad via an opening in the outer passivation layer. The inner passivation layer is on the upper layer of the substrate.
根據本發明之又一實施例,一種凸塊接合墊結構之製造方法,此方法包含:形成一強化墊於一基材之上層上;形成一中間層於基材之上層上;形成一中間連接墊於中間層上,且一介層窗經由中間層而將中間連接墊耦合至強化墊;形成一外層於基材上;以及形成一凸塊底層金屬於外層之開口中,以將凸塊底層金屬耦合至中間連接墊。According to still another embodiment of the present invention, a method of manufacturing a bump bond pad structure, the method comprising: forming a reinforcing pad on an upper layer of a substrate; forming an intermediate layer on the upper layer of the substrate; forming an intermediate connection Padding on the intermediate layer, and a via window couples the intermediate connection pad to the reinforcement pad via the intermediate layer; forming an outer layer on the substrate; and forming a bump underlayer metal in the opening of the outer layer to bond the under bump metal Coupled to the intermediate connection pad.
本發明之一實施例的優點為,因結構之楊氏係數(Young’s Modulus)的增加而在未摻雜矽玻璃與低介電常數介電層之間的界面上所造成的應力,大致上可獲得縮減。楊氏係數的增加通常會造成整體結構具有更大之機械強度。An advantage of an embodiment of the present invention is that the stress caused at the interface between the undoped bismuth glass and the low-k dielectric layer due to the increase in the Young's Modulus of the structure is substantially Get reduced. An increase in the Young's modulus usually results in a greater mechanical strength of the overall structure.
較佳實施例的製造與應用將詳細討論如下。然而,應該了解的一點是,本發明提供許多可應用的創新概念,這些創新概念可在各種特定背景中加以體現。所討論之特定實施例僅係用以舉例說明製造與應用本發明之特定方式,並非用以限制本發明之範圍。The fabrication and application of the preferred embodiment will be discussed in detail below. However, it should be understood that the present invention provides many applicable and innovative concepts that can be embodied in various specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and are not intended to limit the scope of the invention.
本發明將以特定背景,稱之為覆晶裝置之凸塊墊,的數個實施例來描述。然而,本發明亦可應用在任何使用銲接凸塊墊之封裝裝置,例如DBOC結構。The invention will be described in terms of several embodiments, which are referred to as bump pads of a flip chip device in a particular context. However, the invention can also be applied to any packaged device that uses a solder bump pad, such as a DBOC structure.
第2圖係繪示本發明之第一實施例。銲接凸塊30實體上連接至下凸塊底層金屬墊32,而凸塊底層金屬墊32經由半導體晶片上之外鈍化層34中的開口連接至鋁墊36。鋁墊36設置在內鈍化層38上。內鈍化層38位於未摻雜矽玻璃層42之上方,而未摻雜矽玻璃層42位於低介電常數介電層44上。實心銅墊40位於未摻雜矽玻璃層42上,且位於銅墊36之下方。低介電常數介電層44亦可包含電路系統46。這些層亦可包含任何其他已知配置或材料。舉例而言,低介電常數介電層44可以另一未摻雜矽玻璃層替代。此外,未繪示於第2圖與後續之第3圖和第8圖的是鋁線路,此鋁線路電性耦合內連線結構至鋁墊36。Figure 2 is a diagram showing a first embodiment of the present invention. Solder bumps 30 are physically connected to lower bump underlying metal pads 32, while bump underlayer metal pads 32 are connected to aluminum pads 36 via openings in passivation layer 34 on the semiconductor wafer. An aluminum pad 36 is disposed on the inner passivation layer 38. The inner passivation layer 38 is over the undoped yttrium glass layer 42 and the undoped yttrium glass layer 42 is on the low-k dielectric layer 44. The solid copper pad 40 is located on the undoped bismuth glass layer 42 and is located below the copper pad 36. The low-k dielectric layer 44 can also include circuitry 46. These layers may also comprise any other known configuration or material. For example, the low-k dielectric layer 44 can be replaced with another undoped bismuth glass layer. Further, not shown in FIG. 2 and subsequent FIGS. 3 and 8 are aluminum lines which electrically couple the interconnect structure to the aluminum pad 36.
第3圖描繪另一實施例。第3圖之結構相同於第2圖,除了第3圖之結構具有數個介層窗48,這些介層窗48將鋁墊36連接至銅墊40。Figure 3 depicts another embodiment. The structure of FIG. 3 is the same as that of FIG. 2, except that the structure of FIG. 3 has a plurality of vias 48 which connect the aluminum pads 36 to the copper pads 40.
這些實施例降低施加在未摻雜矽玻璃層42與低介電常數介電層44之應力。第4圖係一曲線圖,其繪示出未摻雜矽玻璃層42與低介電常數介電層44之間的界面處的應力縮減。傳統鋁墊描繪在第1A圖中。具有銅墊之鋁墊繪示於第2圖中,且具有銅墊與介層窗連接之鋁墊繪示在第3圖中。以傳統墊作為基線,來正規化界面上之應力。鋁墊與銅墊結構(第2圖)在剝離應力上具有正規化基線9%的縮減,在剪應力上具有正規化基線12%的縮減。具有介層窗之鋁墊與銅墊結構(第3圖)在剝離應力上具有正規化基線15%的縮減,在剪應力上具有正規化基線22%的縮減。These embodiments reduce the stress applied to the undoped bismuth glass layer 42 and the low-k dielectric layer 44. 4 is a graph depicting stress reduction at the interface between the undoped bismuth glass layer 42 and the low-k dielectric layer 44. A conventional aluminum pad is depicted in Figure 1A. An aluminum pad having a copper pad is shown in Fig. 2, and an aluminum pad having a copper pad and a via window is shown in Fig. 3. The traditional pad is used as a baseline to normalize the stress on the interface. The aluminum pad and copper pad structure (Fig. 2) has a normalized baseline reduction of 9% on the peel stress and a 12% reduction in the normalized baseline on the shear stress. The aluminum pad and copper pad structure with via window (Fig. 3) has a 15% reduction in normalized baseline on the peel stress and a 22% reduction in normalized baseline on shear stress.
在界面上之應力的縮減大致上係由藉增加銅墊40所造成之楊氏係數的增加所造成。低介電常數介電質之楊氏係數約為10GPa,而未摻雜矽玻璃之楊氏係數約為70GPa。然而,銅之楊氏係數約為218GPa。因此,將銅插入結構中將大致上可增加結構之楊氏係數,以增加機械強度,藉以提供界面較佳之保護。The reduction in stress at the interface is generally caused by an increase in the Young's modulus caused by the addition of the copper pad 40. The Young's modulus of the low dielectric constant dielectric is about 10 GPa, and the Young's modulus of the undoped bismuth glass is about 70 GPa. However, the Young's modulus of copper is about 218 GPa. Therefore, inserting copper into the structure will substantially increase the Young's modulus of the structure to increase mechanical strength, thereby providing better protection of the interface.
不僅此型式之結構的應用可影響施加在未摻雜矽玻璃層42上之應力,而且銅墊40之尺寸也可影響這些應力。第5圖係一曲線圖,其繪示出銅墊40之尺寸可如何的影響應力。曲線圖之x軸為差Δ,其單位為微米。差Δ代表第3圖所示之凸塊底層金屬墊32的外接圓半徑與銅墊40之外接圓半徑的差。在第5圖中,根據一基線來正規化未摻雜矽玻璃層42與低介電常數介電層44之間的界面上的應力,此基線係當銅墊40之外接圓半徑等於凸塊底層金屬墊32之外接圓半徑,如此差Δ為零。如第5圖之曲線圖所示,應力隨著差Δ的增加而減少,且一旦差Δ超過5微米,正規化應力的減少相對小。如此,可說差Δ在5微米時變飽和。因此,差Δ較佳為約5微米,雖然差Δ可為任何可能的尺寸。Not only does the application of this type of structure affect the stresses exerted on the undoped bismuth glass layer 42, but the size of the copper pad 40 can also affect these stresses. Fig. 5 is a graph showing how the size of the copper pad 40 can affect the stress. The x-axis of the graph is the difference Δ, which is in microns. The difference Δ represents the difference between the radius of the circumcircle of the under bump metal pad 32 shown in Fig. 3 and the radius of the circumscribed circle of the copper pad 40. In FIG. 5, the stress at the interface between the undoped bismuth glass layer 42 and the low-k dielectric layer 44 is normalized according to a baseline which is equal to the bump radius of the copper pad 40. The bottom metal pad 32 is circumscribed by a circle radius such that the difference Δ is zero. As shown in the graph of Fig. 5, the stress decreases as the difference Δ increases, and once the difference Δ exceeds 5 μm, the decrease in the normalized stress is relatively small. Thus, it can be said that the difference Δ becomes saturated at 5 μm. Therefore, the difference Δ is preferably about 5 microns, although the difference Δ can be any possible size.
此外,用以將鋁墊36連接至銅墊40之介層窗48的佈局,可影響施加在未摻雜矽玻璃層42與低介電常數介電層44上之應力。第6A圖至第6D圖係繪示介層窗48之數種示範性佈局。第6A圖繪示具有實心八邊形介層窗48a。虛線表示凸塊底層金屬墊32之佈局,實線為銅墊40。大體而言,凸塊底層金屬墊32之外接圓半徑介於約75與120微米之間,而鋁墊36(未繪示於圖中)之外接圓半徑約大於凸塊底層金屬墊32之外接圓半徑4微米。第6B圖繪示八邊形環狀介層窗48b,其中介層窗48b之外側的外接圓半徑大於介層窗48b之內側的外接圓半徑10微米。第6C圖繪示八邊形環狀介層窗48c,其中介層窗48c之外側的外接圓半徑大於介層窗48c之內側的外接圓半徑20微米。第6B圖與第6C圖中之介層窗的表面積分別為鋁墊36之表面積的28.4%與52.1%。此外,八邊形環狀介層窗48b與48c之內側與外側外接圓半徑之間的差距可增加或減少,例如至5微米或至25微米。具有5微米之差距時,介層窗之表面積為鋁墊36之14.8%,而具有25微米之差距時,介層窗之表面積為鋁墊36之62.1%。第6D圖繪示5×5陣列之介層窗48b。由第6A圖至第6D圖之示範佈局可知,銅墊40之平面視圖的形狀與凸塊底層金屬墊32之平面視圖的形狀對應。Moreover, the layout of the vias 48 used to connect the aluminum pads 36 to the copper pads 40 can affect the stresses applied to the undoped germanium glass layer 42 and the low-k dielectric layer 44. 6A through 6D illustrate several exemplary layouts of vias 48. Figure 6A illustrates a solid octagonal via 48a. The dashed line indicates the layout of the under bump metal pad 32, and the solid line is the copper pad 40. In general, the outer radius of the under bump metal pad 32 is between about 75 and 120 micrometers, and the outer radius of the aluminum pad 36 (not shown) is greater than the outer diameter of the under bump metal pad 32. The radius of the circle is 4 microns. FIG. 6B illustrates an octagonal annular via window 48b, wherein the radius of the circumcircle of the outer side of the via 48b is greater than the radius of the circumscribed circle of the inner side of the via 48b. FIG. 6C illustrates an octagonal annular via window 48c, wherein the radius of the circumcircle of the outer side of the via 48c is greater than the radius of the circumscribed circle of the inner side of the via 48c. The surface areas of the vias in Figures 6B and 6C are respectively 28.4% and 52.1% of the surface area of the aluminum pad 36. Moreover, the difference between the inner and outer circumscribed circle radii of the octagonal annular vias 48b and 48c can be increased or decreased, for example to 5 microns or to 25 microns. With a gap of 5 microns, the surface area of the via is 14.8% of the aluminum pad 36, and with a gap of 25 microns, the surface area of the via is 62.1% of the aluminum pad 36. Figure 6D shows a 5 x 5 array of vias 48b. As can be seen from the exemplary layout of FIGS. 6A to 6D, the shape of the plan view of the copper pad 40 corresponds to the shape of the plan view of the under bump metal pad 32.
第7圖係一曲線圖,其繪示出這些不同佈局如何影響未摻雜矽玻璃層42與低介電常數介電層44之界面的應力。第6A圖之實心八邊形介層窗48a作為基線,而其他所有佈局根據此基線進行正規化。從此曲線圖中,可看出在經正規化後之應力從基線縮減至第6C圖中之20微米八邊形環狀介層窗48c,繼續縮減至第6D圖中之5×5陣列介層窗48d,再縮減至第6B圖中之10微米八邊形環狀介層窗48b。Figure 7 is a graph depicting how these different layouts affect the stress at the interface of the undoped bismuth glass layer 42 and the low-k dielectric layer 44. The solid octagonal via 48a of Figure 6A serves as a baseline, while all other layouts are normalized according to this baseline. From this graph, it can be seen that the normalized stress is reduced from the baseline to the 20 micron octagonal annular via 48c in Figure 6C, and continues to be reduced to the 5 x 5 array via in Figure 6D. Window 48d is further reduced to the 10 micron octagonal annular via 48b in Figure 6B.
上述實施例之缺點為未摻雜矽玻璃層42中之銅墊40需要更多面積,或者未摻雜矽玻璃層42必須包含一額外金屬層。相較於第1A圖中之凸塊墊,本發明之實施例在未摻雜矽玻璃層42中之上金屬層上需要一區域來放置銅墊40。這樣可能需要在上金屬層上重新設定電路系統的線路,以清出銅墊40之區域。替代性地,可在未摻雜矽玻璃層42中加入額外金屬層,以放置銅墊40。如此將不需要重新設定已存半導體元件設計中之電路系統的線路,但加入此額外金屬層所增加之處理與材料,將會導致花費更多。A disadvantage of the above embodiment is that the copper pad 40 in the undoped bismuth glass layer 42 requires more area, or the undoped yttrium glass layer 42 must contain an additional metal layer. In contrast to the bump pads of FIG. 1A, embodiments of the present invention require a region on the upper metal layer of the undoped germanium glass layer 42 to place the copper pads 40. This may require resetting the circuitry of the circuitry on the upper metal layer to clear the area of the copper pad 40. Alternatively, an additional metal layer can be added to the undoped bismuth glass layer 42 to place the copper pad 40. This would eliminate the need to reset the circuitry of the circuitry in the existing semiconductor component design, but the added processing and materials added to this additional metal layer would result in more expense.
第8圖係繪示類似於第3圖所示之實施例的另一實施例,除了第二銅墊52位於未摻雜矽玻璃層24下方與低介電常數介電層44上。數個介層窗50將銅墊40連接至第二銅墊52。根據第6A圖至第6D圖之介層窗佈局,介層窗50可為一或許多單獨的介層窗,或者可為一介層窗。此外, 可將更多銅墊加入第8圖所示之結構中。這些銅墊可位於包含未摻雜矽玻璃層42之多重金屬層中,或者可位於未摻雜矽玻璃層42與低介電常數介電層44中。多個銅墊可利用介層窗來予以連接,或者可不連接。第二銅墊22的加入可進一步增加結構之楊氏係數,因而可增加結構的整體機械強度。FIG. 8 illustrates another embodiment similar to the embodiment illustrated in FIG. 3 except that a second copper pad 52 is disposed beneath the undoped germanium glass layer 24 and the low-k dielectric layer 44. A plurality of vias 50 connect the copper pads 40 to the second copper pads 52. The via 50 may be one or more separate vias, or may be a via, depending on the via layout of Figures 6A-6D. In addition, More copper pads can be added to the structure shown in Figure 8. These copper pads may be located in multiple metal layers comprising undoped bismuth glass layer 42, or may be located in undoped bismuth glass layer 42 and low-k dielectric layer 44. The plurality of copper pads may be connected by a via window or may not be connected. The addition of the second copper pad 22 can further increase the Young's modulus of the structure, thereby increasing the overall mechanical strength of the structure.
實施例的其他特徵包含較厚之鋁墊36及/或鋁線路、較厚之未摻雜矽玻璃層42、或僅具有數個介層窗48穿過內鈍化層38而不具有下方銅墊。鋁墊36之厚度一般約為1.45微米。將此厚度增加至例如2.5微米,可增加結構之機械強度,而將可提供未摻雜矽玻璃層42與低介電常數介電層44更多的保護。同樣地,增加未摻雜矽玻璃層42之厚度,可增加未摻雜矽玻璃層42之機械強度,藉以愈來愈強地保護未摻雜矽玻璃層42與低介電常數介電層44。可藉由增加未摻雜矽玻璃層42中之已存在之層的厚度、或藉由在未摻雜矽玻璃層42中加入數層新的層的方式,來增加未摻雜矽玻璃層42之厚度。此外,穿過內鈍化層38且不具有下方銅墊之數個介層窗48可增加超越傳統凸塊墊之結構的機械強度。Other features of the embodiment include a thicker aluminum pad 36 and/or aluminum line, a thicker undoped yttrium glass layer 42, or only a plurality of vias 48 passing through the inner passivation layer 38 without a lower copper pad . Aluminum pad 36 is typically about 1.45 microns thick. Increasing this thickness to, for example, 2.5 microns increases the mechanical strength of the structure and provides more protection for the undoped bismuth glass layer 42 and the low-k dielectric layer 44. Similarly, increasing the thickness of the undoped bismuth glass layer 42 increases the mechanical strength of the undoped bismuth glass layer 42, thereby enhancing the undoped bismuth glass layer 42 and the low-k dielectric layer 44 more and more strongly. . The undoped bismuth glass layer 42 can be increased by increasing the thickness of the existing layer in the undoped bismuth glass layer 42 or by adding several new layers to the undoped bismuth glass layer 42. The thickness. In addition, the plurality of vias 48 that pass through the inner passivation layer 38 and have no underlying copper pads can increase the mechanical strength beyond the structure of conventional bump pads.
第9A圖至第9M圖係繪示依照另一實施例之一種製造第3圖之凸塊墊結構的製程。在第9A圖中,形成未摻雜矽玻璃層100於低介電常數介電層(未繪示)上。在第9B圖中,圖案化光阻層102於未摻雜矽玻璃層100上,以暴露出未摻雜矽玻璃層100之將進行數個內連線介層窗開口104之蝕刻處。接著,利用已知的微影技術,蝕刻內連線 介層窗開口104。在第9C圖中,接下來以數個插塞(Plug)106部分填充內連線介層窗開口104,再移除光阻層102。在第9D圖中,形成另一光阻層108於未摻雜矽玻璃層100上,並圖案化此光阻層108,以暴露出未摻雜矽玻璃層100中將形成在內連線介層窗開口104上之內連線接觸之處、與將形成銅墊之處。接著,利用已知的微影技術,將未摻雜矽玻璃層100蝕刻到至少插塞106之頂部的深度。9A through 9M illustrate a process for fabricating the bump pad structure of FIG. 3 in accordance with another embodiment. In Fig. 9A, an undoped germanium glass layer 100 is formed on a low-k dielectric layer (not shown). In FIG. 9B, the patterned photoresist layer 102 is over the undoped bismuth glass layer 100 to expose an etch of the undoped bismuth glass layer 100 where a plurality of interconnect via openings 104 are to be formed. Next, etch the interconnects using known lithography techniques The via window opening 104. In Fig. 9C, the interconnect via window opening 104 is then partially filled with a plurality of plugs 106, and the photoresist layer 102 is removed. In FIG. 9D, another photoresist layer 108 is formed on the undoped germanium glass layer 100, and the photoresist layer 108 is patterned to expose the undoped germanium glass layer 100 to form an interconnect. Where the inner wires on the layer window opening 104 contact, and where the copper pad will be formed. Next, the undoped bismuth glass layer 100 is etched to a depth of at least the top of the plug 106 using known lithography techniques.
在第9E圖中,移除光阻層108與插塞106。接下來,沉積銅110於未摻雜矽玻璃層100上。在沉積銅110之前,可利用物理氣相沉積方式形成擴散阻障層。而且,於形成擴散阻障層之後,但在沉積銅110之前,可形成銅晶種層(Copper Seed Layer),以利電鍍。在第9F圖中,利用例如化學機械研磨移除任何多餘之銅110。這樣形成數個內連線介層窗112、內連線接觸114與銅墊116。替代性地,傳統雙鑲嵌製程步驟可應用來形成內連線介層窗112、內連線接觸114與銅墊116。In FIG. 9E, the photoresist layer 108 and the plug 106 are removed. Next, copper 110 is deposited on the undoped yttrium glass layer 100. A diffusion barrier layer may be formed by physical vapor deposition prior to depositing the copper 110. Moreover, after forming the diffusion barrier layer, but before depositing the copper 110, a copper seed layer may be formed to facilitate electroplating. In Figure 9F, any excess copper 110 is removed using, for example, chemical mechanical polishing. A plurality of interconnect vias 112, interconnect contacts 114 and copper pads 116 are formed in this manner. Alternatively, a conventional dual damascene process step can be applied to form interconnect vias 112, interconnect contacts 114, and copper pads 116.
在第9G圖中,沉積第一鈍化層118於未摻雜矽玻璃層100之上方。在第9H圖中,形成光阻層120於第一鈍化層118上。圖案化光阻層120,以暴露出第一鈍化層118位於內連線接觸114與銅墊116上之數個部分。接著,利用已知微影技術蝕刻第一鈍化層118,而留下數個介層窗開口122與124。在第9I圖中,移除光阻層120,且沉積鋁126。鋁126填充介層窗開口122,而形成鋁內連線介層窗128,且填充介層窗開口124,而形成鋁介層窗130。在第9J圖中,形成光阻層132於鋁126上方,並圖案化此光阻層132, 以形成鋁內連線接觸134、鋁線路136與鋁墊138。接著,蝕刻鋁126之圖案。接著,蝕刻鋁126,而形成這些構件。In FIG. 9G, a first passivation layer 118 is deposited over the undoped bismuth glass layer 100. In FIG. 9H, a photoresist layer 120 is formed on the first passivation layer 118. The photoresist layer 120 is patterned to expose portions of the first passivation layer 118 that are on the interconnect contacts 114 and the copper pads 116. Next, the first passivation layer 118 is etched using known lithography techniques leaving a plurality of via openings 122 and 124. In FIG. 9I, the photoresist layer 120 is removed and aluminum 126 is deposited. Aluminum 126 fills via opening 122 to form aluminum interconnect via 128 and fill via opening 124 to form aluminum via 130. In FIG. 9J, a photoresist layer 132 is formed over the aluminum 126, and the photoresist layer 132 is patterned. To form an aluminum interconnect contact 134, an aluminum line 136 and an aluminum pad 138. Next, the pattern of aluminum 126 is etched. Next, aluminum 126 is etched to form these members.
在第9K圖中,移除光阻層132,再沉積第二鈍化層140於此結構上。在第9L圖中,形成光阻層142於第二鈍化層140上,並圖案化此光阻層142,以暴露出鋁墊138上方之第二鈍化層140的一部分。接著,向下蝕刻第二鈍化層140至鋁墊138,而留下凸塊底層金屬開口144。在第9M圖中,移除光阻層142,再形成凸塊底層金屬墊146於凸塊底層金屬開口144中,此凸塊底層金屬墊146與鋁墊138連接。In FIG. 9K, the photoresist layer 132 is removed and a second passivation layer 140 is deposited over the structure. In FIG. 9L, a photoresist layer 142 is formed on the second passivation layer 140, and the photoresist layer 142 is patterned to expose a portion of the second passivation layer 140 over the aluminum pad 138. Next, the second passivation layer 140 is etched down to the aluminum pad 138 leaving the bump underlying metal opening 144. In FIG. 9M, the photoresist layer 142 is removed, and a bump underlying metal pad 146 is formed in the under bump metal opening 144. The bump underlying metal pad 146 is connected to the aluminum pad 138.
雖然本發明及其優點已詳細描述如上,然應該了解到的一點是,在不偏離后附申請專利範圍所界定之本發明的精神與範圍下,當可在此進行各種改變、取代以及修正。舉例而言,雖然上述實施例的許多特徵已包含銅或鋁,然而每個特徵可包含同來取代上述之鋁,或反之亦然。如另一個例子,熟習此項技藝者將可輕易地了解到,以上所描述之各層,例如鈍化層、未摻雜矽玻璃層與介電層,可無需為依照上述實施例之結構中所描述之層。Although the present invention and its advantages have been described in detail above, it should be understood that various changes, substitutions and modifications can be made herein without departing from the spirit and scope of the invention. For example, while many of the features of the above-described embodiments have included copper or aluminum, each feature may include the same as the aluminum described above, or vice versa. As another example, those skilled in the art will readily appreciate that the various layers described above, such as the passivation layer, the undoped bismuth glass layer, and the dielectric layer, need not be described in the structure in accordance with the above embodiments. Layer.
此外,本申請案之範圍並非限制在說明書所描述之製程、機械、製造、物質成分、手段、方法以及步驟的特定實施例中。任何在此技術領域中具有通常知識者,將可輕易從本發明之揭露中了解到,現存或日後所發展出之可與在此所描述之對應實施例執行實質相同之功能、或達到實質相同之結果的製程、機械、製造、物質成分、手段、方法或步驟,可依據本發明來加以應用。因此,所附之申請 專利範圍係用以將這類製程、機械、製造、物質成分、手段、方法或步驟含括在其範圍內。In addition, the scope of the present application is not limited to the specific embodiments of the process, the machine, the manufacture, the composition of matter, the means, the method and the steps described in the specification. Anyone having ordinary skill in the art will readily appreciate from the disclosure of the present invention that existing or future developments can perform substantially the same functions or substantially the same as the corresponding embodiments described herein. The resulting process, machine, manufacture, material composition, means, method or procedure can be applied in accordance with the present invention. Therefore, the attached application The patentable scope is intended to cover such <RTIgt; </ RTI> <RTIgt; </ RTI> processes, machinery, manufacture, composition, means, methods, or steps.
2‧‧‧銲接凸塊2‧‧‧welding bumps
4‧‧‧凸塊底層金屬墊4‧‧‧Bump bottom metal pad
6‧‧‧外鈍化層6‧‧‧Outer passivation layer
8‧‧‧鋁墊8‧‧‧Aluminum pad
10‧‧‧內鈍化層10‧‧‧Inner passivation layer
12‧‧‧未摻雜矽玻璃層12‧‧‧Undoped glass layer
14‧‧‧低介電常數層14‧‧‧Low dielectric constant layer
16‧‧‧鋁線路16‧‧‧Aluminum line
18‧‧‧鋁接觸18‧‧‧Aluminum contact
20a‧‧‧介層窗20a‧‧‧layer window
20b‧‧‧介層窗20b‧‧‧ via window
20c‧‧‧介層窗20c‧‧‧layer window
22‧‧‧接觸22‧‧‧Contact
24‧‧‧介層窗24‧‧・Intermediate window
26‧‧‧接觸26‧‧‧Contact
30‧‧‧銲接凸塊30‧‧‧welding bumps
32‧‧‧凸塊底層金屬墊32‧‧‧Bump bottom metal pad
34‧‧‧外鈍化層34‧‧‧Outer passivation layer
36‧‧‧鋁墊36‧‧‧Aluminum pad
38‧‧‧內鈍化層38‧‧‧Inner passivation layer
40‧‧‧銅墊40‧‧‧ copper pad
42‧‧‧未摻雜矽玻璃層42‧‧‧Undoped glass layer
44‧‧‧低介電常數介電層44‧‧‧Low dielectric constant dielectric layer
46‧‧‧電路系統46‧‧‧Circuit system
48‧‧‧介層窗48‧‧‧Intermediate window
48a‧‧‧介層窗48a‧‧・Intermediate window
48b‧‧‧介層窗48b‧‧‧layer window
48c‧‧‧介層窗48c‧‧・Intermediate window
48d‧‧‧介層窗48d‧‧‧layer window
50‧‧‧介層窗50‧‧‧Interval window
52‧‧‧銅墊52‧‧‧ copper pad
100‧‧‧未摻雜矽玻璃層100‧‧‧Undoped glass layer
102‧‧‧光阻層102‧‧‧ photoresist layer
104‧‧‧內連線介層窗開口104‧‧‧Internal connection window opening
106‧‧‧插塞106‧‧‧ Plug
108‧‧‧光阻層108‧‧‧Photoresist layer
110‧‧‧銅110‧‧‧ copper
112‧‧‧內連線介層窗112‧‧‧Interconnecting via window
114‧‧‧內連線接觸114‧‧‧Inline contact
116‧‧‧銅墊116‧‧‧ copper pad
118‧‧‧第一鈍化層118‧‧‧First passivation layer
120‧‧‧光阻層120‧‧‧ photoresist layer
122‧‧‧介層窗開口122‧‧‧Interval window opening
124‧‧‧介層窗開口124‧‧‧Interval window opening
126‧‧‧鋁126‧‧‧Aluminium
128‧‧‧鋁內連線介層窗128‧‧‧Aluminum interconnecting via window
130‧‧‧鋁介層窗130‧‧‧Aluminum interlayer window
132‧‧‧光阻層132‧‧‧ photoresist layer
134‧‧‧鋁內連線接觸134‧‧‧Aluminum connection
136‧‧‧鋁線路136‧‧‧Aluminum line
138‧‧‧鋁墊138‧‧‧Aluminum pad
140‧‧‧第二鈍化層140‧‧‧Second passivation layer
142‧‧‧光阻層142‧‧‧ photoresist layer
144‧‧‧凸塊底層金屬開口144‧‧‧Bump bottom metal opening
146‧‧‧凸塊底層金屬墊146‧‧‧Bump bottom metal pad
△‧‧‧差△‧‧‧Poor
為了更完全了解本發明及其優點,現結合所附圖式而參照以上之描述,其中:第1A圖係繪示一種傳統凸塊墊結構與內連線之剖面圖。For a fuller understanding of the present invention and its advantages, reference is made to the above description in conjunction with the drawings, wherein FIG. 1A is a cross-sectional view showing a conventional bump pad structure and interconnect.
第1B圖係繪示一種傳統凸塊墊結構與內連線之平面視圖。Figure 1B is a plan view showing a conventional bump pad structure and interconnect.
第2圖係繪示依照本發明一實施例的一種凸塊墊結構的剖面圖。2 is a cross-sectional view showing a bump pad structure in accordance with an embodiment of the present invention.
第3圖係繪示依照本發明之另一實施例的一種凸塊墊結構的剖面圖。Figure 3 is a cross-sectional view showing a bump pad structure in accordance with another embodiment of the present invention.
第4圖係繪示比較傳統結構與本發明之實施例間之未摻雜矽玻璃層與低介電常數介電層之界面處的應力的曲線圖。Figure 4 is a graph showing the stress at the interface between the undoped bismuth glass layer and the low-k dielectric layer between the conventional structure and the embodiment of the present invention.
第5圖係繪示銅墊尺寸對未摻雜矽玻璃層與低介電常數介電層之界面處之應力的影響的曲線圖。Figure 5 is a graph showing the effect of copper pad size on the stress at the interface of the undoped bismuth glass layer and the low-k dielectric layer.
第6A圖至第6D圖係繪示依照本發明之數個實施例的介層窗與凸塊墊結構的平面視圖。6A through 6D are plan views showing a via window and a bump pad structure in accordance with several embodiments of the present invention.
第7圖係繪示不同介層窗布局如何影響未摻雜矽玻璃層與低介電常數介電層之界面處之應力的曲線圖。Figure 7 is a graph showing how different via window layouts affect the stress at the interface between the undoped bismuth glass layer and the low-k dielectric layer.
第8圖係繪示依照本發明之又一實施例的一種凸塊墊 結構的剖面圖。Figure 8 is a perspective view of a bump pad according to still another embodiment of the present invention. A sectional view of the structure.
第9A圖至第9M圖係繪示依照本發明之一實施例之一種製造凸塊墊結構的製程。9A through 9M are diagrams showing a process for fabricating a bump pad structure in accordance with an embodiment of the present invention.
30...銲接凸塊30. . . Welding bump
32...凸塊底層金屬墊32. . . Bump bottom metal pad
34...外鈍化層34. . . Outer passivation layer
36...鋁墊36. . . Aluminum pad
38...內鈍化層38. . . Inner passivation layer
40...銅墊40. . . Copper pad
42...未摻雜矽玻璃層42. . . Undoped glass layer
44...低介電常數介電層44. . . Low dielectric constant dielectric layer
46...電路系統46. . . electrical system
48...介層窗48. . . Via window
Δ...差Δ. . . difference
Claims (10)
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US17652209P | 2009-05-08 | 2009-05-08 | |
US12/726,449 US8405211B2 (en) | 2009-05-08 | 2010-03-18 | Bump pad structure |
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