KR20010110159A - Circuit board and flat panel display device - Google Patents

Abstract

The circuit board includes an array substrate on which scan lines are formed as capacitive loads, and first and second scan line drivers respectively connected to the scan lines to drive the scan lines in common. Each of the first and second scan line drivers is connected in series between the first and second power supply terminals YGVDD and YGVSS to selectively output the potentials of the first and second power supply terminals YGVDD and YGVSS as control signals. First and second switch circuits (S1, S2) and an output buffer for setting the potential of the scanning line in response to the control signal, wherein the driving capabilities of the first and second switch circuits (S1, S2) are not equal to each other. Is configured.

Description

CIRCUIT BOARD AND FLAT PANEL DISPLAY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a flat panel display device in which a plurality of signal lines are formed in accordance with a plurality of pixel electrodes arranged in a matrix shape, and in particular, connected to an end portion of the signal line for driving a signal line that becomes a capacitive load in the flat display device. It relates to an output circuit.

In recent years, the active matrix liquid crystal display device has been widely used as a monitor display of a notebook PC or a portable terminal device due to the beauty of the display and the high reliability of the product. The liquid crystal display device generally includes an array substrate in which a plurality of pixel electrodes are arranged in a matrix, an opposing substrate on which opposing electrodes are disposed to face the plurality of recovery electrodes, and a liquid crystal layer held between the array substrate and the opposing substrate. It is a flat panel display device. The array substrate includes a plurality of scan lines arranged along the rows of the pixel electrodes in addition to the plurality of pixel electrodes, a plurality of signal lines arranged along the columns of the pixel electrodes, and a plurality of scan lines arranged near the intersection positions of the scan lines and the signal lines. A switch element is provided. Each switch element is connected to apply a signal voltage of the corresponding signal line to the corresponding pixel electrode when driven through the corresponding scanning line. By using this switch element, crosstalk between adjacent pixels is sufficiently reduced, and a high contrast image can be obtained.

The switch element is generally composed of a thin film transistor using an amorphous silicon semiconductor film. In recent years, advances in manufacturing techniques have made it possible to form polysilicon semiconductor thin films having a higher carrier mobility than amorphous silicon on low temperature glass substrates. By using this thin film forming technique, not only the pixel switching element but also the scanning line driver and the signal line driver can be assembled on the array substrate.

However, the screen size of the liquid crystal display device tends to be enlarged at present. If it is about 12 inches as in the related art, a signal driver such as a scan line or a signal line can be sufficiently driven by a single driving circuit. When this driving capability is insufficient due to the increase in the screen size and the increase in the load capacity of the signal wiring, a movement for adopting the two-side driving method in which a pair of drivers are connected to both ends of the signal wiring is first introduced. However, it is difficult to uniformly form polysilicon having good properties on glass substrates by current manufacturing techniques. For this reason, an error tended to occur in the output characteristics of these drivers arranged on the glass substrate.

The conventional scanning line driver includes, for example, an output circuit configured as shown in FIG. 5 for each scanning line. In this output circuit, the NOR circuit 1 selectively outputs the scan signal SEL under the control of the output control signal SHUT. When this scan signal is output from the NOR circuit 1, it is level shifted in the level shifter LS, and is further supplied to one scan line Y1 via the inverters 2 and 3. The level shifter LS shifts the input signal changing between the high level power potential (YVDD) and the low level power potential (YVSS) to become an output signal changing between the high level power potential (YGVDD) and the low level power potential (YGVSS). do. The level shifter LS drives a load connected to an output terminal via a series circuit of two N-channel transistors and one of a single P-channel transistor. Here, since the series circuit of the N-channel transistor and the P-channel transistor are configured to have the same driving capability, it is unclear whether the output terminal is set to the high level power potential YGVDD or the low level power potential YGVSS immediately after the power is turned on.不定). A pair of scanning line drivers are respectively connected to both ends of the scanning line Y1 in the above-described configuration, and the high level power potential YGVDD and the low level power potential YGVSS that are different from each other immediately after the power is turned on due to a characteristic error. When the both ends of the scan line Y1 are set, a short circuit current flows through these scan line drivers and the scan line Y1, causing significant defects in the operation of the liquid crystal display device such as shutting down or destroying the power supply. There is.

This problem can be avoided by, for example, adding a protection circuit composed of the P-channel transistor 3A and the N-channel transistor 3B shown in FIG. 6 to the inverter 3. In this case, the P-channel transistor 3C is connected in series with the P-channel transistor 3A between the power supply terminal YGVDD and the scanning line Y1, and the N-channel transistor 3D is connected to the scanning line Y1 and the power supply terminal YGVSS. Are connected in series with the P-channel transistor 3A. The scan signal SEL is supplied to the level shifter LS without intervening the NOR circuit 1, and the output signal of the level shifter LS is supplied to the gate electrodes of the P-channel transistor 3C and the N-channel transistor 3D. Each is supplied. The output control signal SHUT is directly supplied to the gate electrode of the N-channel transistor 3B and is supplied to the gate electrode of the P-channel transistor 3A via the inverter INV. In such a configuration, the transistors 3A and 3B of the protection circuit are temporarily turned off from the power supply under the control of the output control signal SHUT, and the scan line Y1 is placed in an electrically floating state so that a short circuit current does not flow. . However, the transistors 3A and 3B of the protection circuit need to be the same size as the transistors 3C and 3D of the final inverter 3 which is the largest circuit element among the scan line drivers. For this reason, it is difficult to lay out without increasing the width | variety of the edge which surrounds the display area of a liquid crystal display device.

SUMMARY OF THE INVENTION The present invention has been made in view of the above point, and an object thereof is to provide a circuit board and a flat panel display device which can suppress unwanted charges in the signal wiring after turning on the power supply by reducing layout restrictions.

In addition, an object of the present invention is to provide a circuit board and a flat panel display device capable of preventing a short circuit current flowing in the signal wiring immediately after the power is turned on.

1 is a plan view schematically showing the configuration of a liquid crystal display device according to an embodiment of the present invention, in which FIG. 1A is a plan view thereof, FIG.

FIG. 2 is a circuit diagram showing the configuration of each scan line driver shown in FIG. 1;

3 is a circuit diagram showing the configuration of the NOR circuit shown in FIG.

4 is a plan view illustrating a double gate structure of the transistor illustrated in FIG. 3;

5 is a circuit diagram schematically showing the configuration of an output circuit of a conventional scan line driver;

FIG. 6 is a circuit diagram illustrating a protection circuit added to the final inverter shown in FIG. 5.

1 --- NOR circuit

2 --- inverter

3 --- inverter

3A --- P-Channel Transistor

3B --- N-channel transistor

3C --- P-Channel Transistor

3D --- N-Channel Transistor

10 --- Array Board

20 --- Opposing board

30 --- liquid crystal layer

40 --- Scanline Driver

41 --- NOR circuit

41A --- P-Channel Transistor

41B --- P-Channel Transistor

41C --- N-Channel Transistor

41D --- N-Channel Transistor

42 --- inverter

43 --- Inverter

50 --- signal line driver

SEL --- scan signal

SHUT --- Output Control Signal

LS --- Level Shifter

Y --- scan line

YVDD --- High Level Power Potential

YVSS --- Low Level Power Potential

YGVDD --- High Level Power Potential (Power Terminal)

YGVSS --- Low Level Power Potential (Power Terminal)

INV --- Inverter

EL --- pixel electrode

X --- signal line

SW --- switch element

SR --- shift register

FF1 to FFm --- flip flop

STV --- Vertical Injection Start Pulse

S1 --- switch circuit

S2 --- switch circuit

IN1 --- input

IN2 --- input

G --- gate electrode

PS --- Polysilicon Semiconductor Thin Film

EG --- metal layer

W --- gate width

L --- Gate Length

According to the present invention for achieving the above object, one of the first voltage and the second voltage to the signal wiring based on the signal wiring formed on the insulating substrate, and the external voltage and the timing signal disposed at both ends of the signal wiring. An output circuit is provided, and the output circuit is provided with a circuit board comprising a plurality of circuit elements having a non-uniform driving capability to output the first voltage when the external voltage is input.

Further, according to the present invention, in a display device having first and second substrates and an optical modulation layer disposed between the substrates, the first substrate is substantially perpendicular to the first signal wiring and the first signal wiring. A second signal wiring arranged, a pixel transistor arranged near an intersection of the first signal wiring and the second signal wiring, a pixel electrode electrically connected to the pixel transistor, and at least one of the first and second signal wiring And a driving circuit disposed at an end of the signal wiring line, the output circuit outputting one of a first voltage and a second voltage to the signal wiring based on an external voltage and a timing signal. There is provided a flat panel display device comprising a plurality of circuit elements having a non-uniform driving ability to output the first voltage when a voltage is input.

Further, according to the present invention, there is provided an output circuit for outputting one of a first voltage or a second voltage to the signal wiring based on a signal wiring formed on an insulated substrate and an external voltage and a timing signal disposed at an end of the signal wiring. And the output circuit comprises a plurality of circuit elements having different resistance values to output the first voltage when the external voltage is input.

Furthermore, according to the present invention, there is provided a signal wiring formed on an insulated substrate, and an output circuit for setting a voltage output to the signal wiring based on an external voltage disposed at an end of the signal wiring and a timing signal. Is provided with a plurality of circuit elements having uneven driving capability, and outputs the output of each circuit element to the signal wiring.

In these circuit boards and flat panel display devices, the driving capacities of a plurality of circuit elements are formed unevenly. In this configuration, even when there is an error in the front end of the output circuit, the desired voltage can be output through the signal wiring. In addition, when output circuits are provided on both sides of the signal wiring, high reliability can be prevented from malfunctioning due to a short-circuit current and a decrease in yield. Moreover, since it can be configured without requiring a large circuit element, layout restrictions can be reduced.

(Example)

Hereinafter, a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 schematically shows the configuration of this liquid crystal display, where FIG. 1A is a plan view and FIG. 1B is a sectional view. The liquid crystal display device includes an array substrate 10 in which a plurality of pixel electrodes EL are arranged in a matrix form in a display area of 15 inches diagonally, and an opposite electrode faces the plurality of pixel electrodes EL. A flat panel display comprising a counter substrate 20 disposed thereon and a liquid crystal layer 30 sandwiched between the array substrate 10 and the counter electrode 20. The liquid crystal layer 30 is obtained by injecting and sealing a liquid crystal composition into a cell enclosed by the sealing material with the gap between the array substrate 10 and the counter substrate 20, and each pixel electrode EL and the counter electrode CT. A light modulating layer modulates the transmitted light according to the potential difference therebetween. In addition, the counter substrate 20 includes a counter electrode CT which is commonly provided on all the pixels on an insulating substrate 21 such as glass.

The array substrate 10 includes a plurality of scan lines Y arranged along rows of the pixel electrodes EL in addition to the plurality of pixel electrodes EL, and a plurality of signal lines arranged along the columns of the pixel electrodes EL. X), the plurality of pixel switch elements SW disposed near the intersections of the scan lines Y and the signal lines X, and the first and second scan line drivers 40 driving the plurality of scan lines Y, respectively. And a signal line driver 50 for driving the plurality of signal lines X. FIG. Each switch element SW is connected to apply a potential of the corresponding signal line X to the corresponding pixel electrode EL when driven through the corresponding scanning line Y. FIG. The first and second scan line driver 40 and the signal line driver 50 are disposed in the outer regions of the plurality of pixel electrodes EL adjacent to the ends of the array substrate 10. The first and second scan line driver 40 and the signal line driver 50 are integrally formed on the substrate by using a semiconductor thin film of polysilicon similarly to the switch element SW.

2 shows the configuration of each scan line driver 40. The scan line driver 40 includes a shift register SR, m level shifters LS, m two-input NOR circuits 41, m inverters 42, and m inverters 43. This shift register SR is constituted by m flip-flops FF1 to FFm cascaded, and sequentially shifts the vertical scan start pulse STV in synchronization with a clock signal. These flip-flops FF1 to FFm generate the scan signal SEL from the output terminal when the vertical scan start pulses STV are latched, respectively. Each scan signal SEL is supplied to the corresponding scan line Y via the level shifter LS, the NOR circuit 41, the inverter 42, and the inverter 43. The level shifter LS has a structure similar to that of the conventional art as shown in FIG. 5 and converts the scan signal SEL that is changed between the high level power potential YVDD and the low level power potential YVSS and the high level power potential YGVDD. Level shift is performed so as to become a scanning signal that varies between the low-level power supply potentials (YGVSS). The NOR circuit 41 selectively outputs the scan signal SEL supplied from the level shifter LS based on the output control signal SHUT. This output control signal SHUT is a signal used to reset the circuit elements of the scan line driver 40 before the input of the vertical scan start signal STV.

3 shows the configuration of the NOR circuit 41. The NOR circuit 41 comprises a switch circuit S1 composed of P-channel transistors 41A and 41B connected in series between a high level power supply potential YGVDD and an output terminal OUT, and an output terminal OUT and a low level power supply. A switch circuit S2 composed of the N-channel transistors 41C and 41D connected in parallel to each other between the potentials YGVSS is provided. The gate electrodes of the P-channel transistor 41A and the N-channel transistor 41C are connected to the input terminal IN1 that receives the scan signal SEL, and the gate electrodes of the P-channel transistor 41B and the N-channel transistor 41D are connected to the input terminal IN1. It is connected to the input terminal IN2 which receives the output control signal SHUT. Each of these transistors 41A to 41D extends from the metal layer EG so that two gate electrodes G are orthogonal to the polysilicon semiconductor thin film PS, as shown in FIG. 4, and gates the semiconductor thin film PS. It has a double gate structure overlapping with an insulating film. The gate width W of each gate electrode G is set to 9 mu m, for example, and the gate length L is set to 6 mu m, for example. When the transistors 41A to 41D are connected as described above, the W / L ratio of the N-channel transistors 41C and 41D becomes four times the W / L ratio of the P-channel transistors 41A and 41B. In other words, in the switch circuit S1 in which two transistors are connected in series and the switch circuit S2 in which two transistors are connected in parallel, the W / Ls of the individual transistors constituting the switch circuits S1 and S2 are provided. When the ratio is the same, the on resistance of the switch circuit S1 becomes four times the on resistance of the switch circuit S2.

That is, since the driving capability of the switch circuit S1 becomes 1/4 times the driving capability of the switch circuit S2, the output terminal of the NOR circuit 41 immediately after the power supply of which the potentials of the input terminals IN1 and IN2 are unstable. It becomes easy to become low level power supply potential (YGVSS). Since only inverters 42 and 43 serving as output buffers are interposed between the NOR circuit 41 and the scanning line Y, the potentials at both ends of the scanning line Y are immediately after the power is turned on. Is set to the low level power supply potential (YGVSS) in common, and rises stably without a short circuit current flowing.

In this liquid crystal display device, the first and second scan line drivers 40 are connected to both ends of the signal wiring, respectively, so that the driving capabilities of the switch circuits S1 and S2 are unevenly formed. In this configuration, even when there is an error in the characteristics of the first and second scan line drivers 40, since both ends of the scan line Y serving as signal wiring are not set to different potentials immediately after the power is turned on, the short-circuit current is the first. And the second scan line driver 40 and the scan line Y do not flow. Therefore, high reliability can be obtained which can prevent the malfunction due to such short-circuit current and the decrease in yield. In addition, since the switch circuits S1 and S2 are arranged in front of the output buffers composed of the inverters 42 and 43, it is possible to construct them without requiring a large circuit element. For this reason, layout restrictions can be reduced.

In the conventional example shown in FIG. 5, the level shifter LS is connected to the rear end of the two-input NOR circuit 1. Unlike the two-input NOR circuit 41 of this embodiment, the level shifter LS is easily set to one of the high level power supply potential YGVDD and the low level power supply potential YGVSS immediately after the power supply is turned on. It is not structured. For this reason, there is a possibility that a short-circuit current may flow by being set at different potentials by a pair of scanning line drivers having a characteristic error in the potential at both ends of the scanning line immediately after the power is turned on. In addition, each of the transistors 41A to 41D of the two-input NOR circuit 41 is about 1/10 of the transistors 3A and 3B of the protection circuit provided in the final inverter 3 of the conventional example shown in FIG. As the size of, it is possible to easily perform circuit layout, and it is not necessary to increase the width of the edge outside the display area. The output buffer of the scan line driver 40 needs to be made larger in size, such as making the liquid crystal display device more precise or making it larger. For this reason, the transistors 3A and 3B of the protection circuit shown in Fig. 3 also become large with this. In this case, the liquid crystal display device of this embodiment does not need to enlarge the transistors 41A to 41D of the NOR circuit 41.

Furthermore, in this embodiment, the W / L ratio of the N-channel transistors 41C and 41D is set to four times the W / L ratio of the P-channel transistors 41A and 41B, but in order to raise the liquid crystal display more stably, The value may be larger than four times.

In the present embodiment, the case where the W / L ratios of the transistors constituting the switch circuits S1 and S2 are the same has been described. It is possible. In addition, the ratio of the on resistance of the switch circuit S1 and the switch circuit S2 can also be set appropriately, and in consideration of the error (about 30%) of the transistor characteristics caused by the polysilicon semiconductor thin film, the switch circuit S1 It is preferable that the on-resistance of?) Is three times or more to the on-resistance of the switch circuit S2, and the on-resistance of the switch circuit S1 is set in consideration of the output timing of the scan signal between adjacent scan lines. It is preferable to set it to 10 times or less with respect to the on-resistance of (S2).

In addition, in the present embodiment, the two-side driving method in which the first and second scan line drivers 40 are respectively connected to both ends of the signal wiring has been described, but in the present invention, the first and second signal line drivers are both ends of the signal line X. It is also applicable to the both-side driving method connected to the.

In the present embodiment, the case where a signal is input from both sides of the signal wiring has been described, but the present invention can also be applied to the case of inputting a signal from one end of the signal wiring. Such a structure can reduce layout constraints and prevent unwanted potential from being set on the signal wiring.

In addition, although the present embodiment has been described using a liquid crystal display device, the present invention can be applied to an entire display device such as a self-luminous display device having a light emitting layer as a light modulation layer between opposing electrodes. It is possible to apply to the luminescence display device.

As described above, according to the present invention, it is possible to reduce undesired layout and to prevent unwanted charges from being occupied in the signal wiring immediately after the power supply, and further, after the voltage is output from both sides of the signal wiring at the same time. A circuit board and a flat panel display device capable of preventing a short circuit current flowing in a signal line can be provided.

Claims (19)

A signal wiring formed on an insulating substrate, and an output circuit for outputting one of a first voltage and a second voltage to the signal wiring based on an external voltage and a timing signal disposed at both ends of the signal wiring; And the output circuit is composed of a plurality of circuit elements having an uneven driving capability to output the first voltage when the external voltage is input. The circuit board of claim 1, wherein the output circuit is disposed at both ends of the signal line. The circuit board of claim 1, wherein the output circuit comprises a first circuit element and a second circuit element connected in series between two power supply terminals. 4. The circuit board of claim 3, wherein the first circuit element of the output circuit is composed of a plurality of transistors connected in series, and the second circuit element is composed of a plurality of transistors connected in parallel. The circuit board of claim 4, wherein the plurality of transistors have the same driving capability. 5. The circuit board according to claim 4, wherein a transistor constituting said first circuit element of said output circuit and a transistor constituting said second circuit element have different conductivity types. The circuit board of claim 4, wherein the semiconductor film of the transistor is a polysilicon semiconductor thin film, and the transistor is integrally formed with the insulating substrate. 5. The circuit board according to claim 4, wherein the on resistance of the first circuit element of the output circuit is set to be 3 to 10 times the on resistance of the second circuit element. In a display device having a first and a second substrate and an optical modulation layer disposed between these substrates, The first substrate includes a first signal wiring, a second signal wiring disposed substantially orthogonal to the first signal wiring, a pixel transistor disposed near an intersection point of the first signal wiring and the second signal wiring, the pixel transistor. A pixel electrode electrically connected to the pixel electrode and at least one end of one of the signal wirings of the first and second signal wirings, the one of the first and second voltages being connected to the signal wiring based on an external voltage and a timing signal. It includes a drive circuit including an output circuit for outputting the, And the output circuit is constituted by a plurality of circuit elements having an uneven driving ability to output the first voltage when the external voltage is input. The flat panel display of claim 9, wherein the output circuit is disposed at both ends of at least one of the first and second signal lines. The flat panel display of claim 10, wherein the driving circuit is provided on both sides of at least one of the signal wirings of the first and second signal wirings, and is integrally formed with a substrate. 10. The flat panel display of claim 9, wherein the output circuit includes a first circuit element and a second circuit element connected in series between two power supply terminals. The flat panel display according to claim 12, wherein the first circuit element of the output circuit is composed of a plurality of transistors connected in series, and the second circuit element is composed of a plurality of transistors connected in parallel. The flat panel display of claim 13, wherein the plurality of transistors have the same driving capability. The flat panel display according to claim 14, wherein the transistors constituting said first circuit element and said transistors constituting said second circuit element of said output circuit have different conductivity types. A signal wiring formed on the insulating substrate, and an output circuit for outputting one of the first voltage and the second voltage to the signal wiring based on an external voltage and a timing signal disposed at the end of the signal wiring; And the output circuit comprises a plurality of circuit elements having different resistance values to output the first voltage when the external voltage is input. The flat panel display of claim 16, wherein the output circuit is disposed at both ends of the signal line. A signal wiring formed on the insulating substrate, and an output circuit for setting a voltage to be output to the signal wiring based on an external voltage disposed at an end of the signal wiring and a timing signal, And said output circuit is composed of a plurality of circuit elements having uneven driving ability, and outputs the output of each circuit element to the signal wiring. 19. The circuit board of claim 18, wherein the output circuit is disposed at both ends of the signal wiring.