JP3755277B2 - Electro-optical device drive circuit, electro-optical device, and electronic apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a driving circuit for an electro-optical device such as an active matrix driving type liquid crystal panel driven by a thin film transistor (TFT), an electro-optical device provided with the driving circuit, and an electro-optical device provided with the driving circuit on a substrate Or belongs to a technical field of electronic equipment using the electro-optical device, and particularly belongs to a technical field of a drive circuit including a shift register circuit, an electro-optical device, and an electronic device.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, in an active matrix liquid crystal panel, a large number of scanning lines and data lines arranged vertically and horizontally, and a large number of pixel electrodes corresponding to respective intersections of the scanning lines and data lines are provided on the TFT array substrate. ing. In addition to these, various peripheral circuits including TFTs such as a scanning line driving circuit, a data line driving circuit, and a sampling circuit may be provided on such a TFT array substrate.
[0003]
Among these peripheral circuits, the scanning line driving circuit includes a shift register and a buffer circuit, and generates a pulsed scanning signal by the shift register and sequentially shifts the scanning signal in the arrangement direction of the scanning lines. The signal is amplified by the buffer circuit and supplied to the scanning line.
[0004]
Similarly to the scanning line driving circuit, the data line driving circuit includes a shift register and a buffer circuit, and a pulsed driving signal generated by the shift register is supplied to a sampling circuit connected to the data line driving circuit. At the same time, the drive signal is sequentially shifted in the arrangement direction of the sampling circuits. When the drive signal amplified by the buffer circuit is applied to each sampling circuit that samples the image signal for each data line or each of the plurality of data lines, the image signal is output for each data line or for each of the plurality of data lines. Is output and supplied to the data line.
[0005]
By providing the scanning line driving circuit, the data line driving circuit, and the sampling circuit configured as described above, voltage application to each of the pixel electrodes arranged in a matrix is controlled, and a desired image is displayed on the liquid crystal panel. Can be made.
[0006]
[Problems to be solved by the invention]
However, in the conventional liquid crystal panel, a circuit that requires power supply such as a clocked inverter circuit is used for the shift register that constitutes the scanning line driving circuit and the data line driving circuit. In this case, it is necessary to provide a connection region between the power supply wiring and the signal wiring, and it is difficult to reduce the area occupied by the shift register pattern.
[0007]
In general, each signal transfer unit and output signal generation unit constituting the shift register of the scanning line driving circuit is within a distance between adjacent scanning lines, that is, within a repeating pattern arrangement distance of scanning lines (hereinafter referred to as an arrangement pitch). Often formed. Also, for each signal transfer unit and output signal generation unit constituting the shift register of the data line driving circuit, sampling in which the output signal of one stage from the arrangement pitch of the data line or from the shift register is connected to the data line The arrangement pitch is often determined by how many stages of the circuit are selected simultaneously.
[0008]
The signal transfer unit and the output signal generation unit are not formed within the arrangement pitch of the scanning lines or data lines, but are divided into several blocks in a direction parallel to the scanning lines or data lines. In such a case, the arrangement pitch can be increased, but the signal waveform may be rounded or the signal may be delayed due to the pattern routing.
[0009]
Therefore, it is most preferable that each of the signal transfer unit and the output signal generation unit is formed within the arrangement pitch of the scanning lines or data lines.
[0010]
However, if a circuit that requires power supply wiring such as a clocked inverter circuit is used for at least one of the signal transfer units or signal generation units as described above, the signal transfer unit and the output corresponding to the power supply wiring are used. The area occupied by the signal generator becomes large, and it becomes difficult to integrate peripheral circuits.
[0011]
As a result, even if the distance between adjacent pixels, that is, the repetitive pattern arrangement distance (pixel pitch) of the pixels is further reduced, the arrangement pitch of the drive circuits including the signal transfer units and the output signal generation units is There is a problem that the pixel pitch is always larger than the pixel pitch, and the pixel pitch substantially depends on the occupied area of each signal transfer unit, each output signal generation unit, etc., and the pixel pitch cannot be miniaturized. there were.
[0012]
The present invention has been made in view of the above-described problems, and a liquid crystal panel driving device and a liquid crystal device capable of miniaturizing the pixel pitch even when the scanning line driving circuit or the data line driving circuit is constituted by a shift register. Another object is to provide an electronic device including a liquid crystal device.
[0013]
[Means for Solving the Problems]
In order to solve the above problems, the present invention provides a pixel region on a substrate.A plurality of data lines to which image signals are supplied, a plurality of scanning lines to which scanning signals are supplied, the plurality of data lines and the plurality of scanning lines.Provided for the intersection ofA plurality of switching means, and the switching meansCorrespondingly providedA drive circuit for an electro-optical device including a pixel electrode, the shift register supplying a control signal for supplying the image signal and the scanning signal to the data line and the scanning line, respectively.And provided on the substrateAt least one of a data line driving unit and a scanning line driving unit, and the shift register of at least one of the data line driving unit or the scanning line driving unit includes:RollSignal transmission directionIsA bidirectional shift register which is a direction, each stage of the bidirectional shift register isInput from the previous stage of each stageA transfer direction control unit that limits the transfer direction of the transfer signal to a predetermined direction based on the direction control signal;Based on the transfer signal input from the previous stage in synchronization with the clock signal,A transfer signal generator for generating a transfer signalThe transfer signal generation unit at each stage of the bidirectional shift register includes a first transmission gate that captures a transfer signal input from the previous stage by the transfer direction control unit, and a transfer that is captured by the first transmission gate. A first inverter to which a signal is input, a second inverter to which an output of the first inverter is input, and a second that performs feedback of the transfer signal of each stage output from the second inverter to the first inverter A transmission gate, and the distance from each stage of the bidirectional shift register to the pixel region is equal.It is characterized by that.
[0014]
According to the driving circuit of the electro-optical device described in the present invention, when at least one of the data line driving unit and the scanning line driving unit includes the bidirectional shift register, the direction control signal is bidirectional from the outside. When input to the directional shift register, the transfer direction control unit provided in each stage of the bidirectional shift register changes the transfer direction of the input signal in the forward direction (for example, the direction from left to right) or the reverse direction ( For example, it is limited to any one of the directions from right to left. In this state, when an input signal is supplied to the bidirectional shift register and a clock signal having a predetermined period is further supplied, the transfer signal generator synchronizes with the clock signal at the first stage of the bidirectional shift register. A transfer signal based on the input signal is generated, and the transfer signal is output to the next stage of the bidirectional shift register. Next, in the next stage of the bidirectional shift register, a transfer signal in the next stage is generated based on the transfer signal output from the first stage at a timing different from that in the first stage in synchronization with the clock signal. . Hereinafter, the transfer signals generated at each stage are sequentially transferred to the next stage.
[0015]
In the data line driving means, the image signal is sequentially supplied to the data lines or a plurality of data line groups based on the transfer signal transferred as described above. In the scanning line driving means, the above is performed. The scanning signal can be sequentially supplied to the scanning line based on the transfer signal transferred to the scanning line.
The drive circuit of the electro-optical device according to the invention includes a logic gate unit that obtains an output signal having the same polarity as the input signal regardless of the logic value of the input signal in the transfer direction control unit and the transfer signal generation unit. But you can.
[0016]
According to the drive circuit of this electro-optical device, the area occupied by each stage of the bidirectional shift register can be reduced. That is, at least one of the data line driving means and the scanning line driving means is means for driving each wiring by sequentially transferring a transfer signal from the first stage to the subsequent stage of the bidirectional shift register. The basic configuration is that a data line or a scanning line is connected to each stage of the directional shift register. Therefore, the occupied area and the array pitch of each stage of the bidirectional shift register affect the setting of the pixel pitch. However, at least one of the bidirectional shift registers of the data line driving means and the scanning line driving means has the same polarity as the input signal regardless of the logical value of the input signal in the transfer direction control section and the transfer signal generation section of each stage. Therefore, when the transfer direction control unit and the transfer signal generation unit are formed on the substrate, the gate unit includes an input signal line, an output signal line, and the clock signal line described above. It is sufficient to connect the direction control signal lines, and it is not necessary to connect the positive power supply line and the negative power supply line in addition to these signal lines. Therefore, the area occupied by the transfer direction control unit and the transfer signal generation unit can be reduced as compared with the conventional case where a positive power supply line and a negative power supply line are required. The arrangement pitch of each stage can be reduced. As a result, the arrangement pitch of data lines or scanning lines can be reduced, and the pixel pitch can be miniaturized.
[0020]
According to the driving circuit of the electro-optical device, the transmission gate includes an N-channel TFT that is turned on when the polarity of the signal input to the gate terminal is positive, and the polarity of the signal input to the gate terminal is negative. And a P-channel TFT that is sometimes conductive. The transfer direction control unit has a transmission gate in which a direction control signal is input to the gate terminal on the N channel side and an inverted signal of this signal is input to the gate terminal on the P channel side, and a gate terminal on the P channel side And a transmission gate to which an inverted signal of this signal is inputted to the gate terminal on the N channel side. Therefore, either one of the transmission gates becomes conductive according to the polarity of the direction control signal, and the transfer direction of the transfer signal is limited to any one direction. In the transfer signal generator, a clock signal is input to the gate terminal on the N channel side, a transmission gate in which an inverted signal of this signal is input to the gate terminal on the P channel side, and a gate terminal on the P channel side. A clock signal is input, and a transmission gate to which an inverted signal of this signal is input is connected to the gate terminal on the N channel side, and the arrangement order of the transmission gates is reversed in adjacent transfer signal generation units. Configured. Therefore, if the transmission signal is taken in at the rising edge of the clock signal in the preceding transfer signal generation unit and the transfer signal is taken in, the transmission gate is in the conducting state at the falling edge of the clock signal in the next transfer signal generation unit. Since the transfer signal is captured, the transfer signal generator at each stage captures the transfer signal of the previous stage at a timing shifted by a half cycle of the clock signal, and the transfer signal is transferred one after another. become.
[0021]
As described above, the transfer signal generation unit of each stage is provided with a plurality of transmission gates, and each transmission gate obtains an output signal having the same polarity as the input signal regardless of the logical value of the input signal. Since it has logic, it is not necessary to connect a positive power supply line and a negative power supply line in addition to the signal line for each TFT of each transmission gate. As a result, the area occupied by each stage of the bidirectional shift register can be reduced as compared with the prior art, and the liquid crystal panel can be driven satisfactorily by transferring appropriate transfer signals while realizing a finer pixel pitch. A driving device for a liquid crystal panel can be provided.
[0022]
  In addition, the present inventionCorresponding to the intersection of a plurality of data lines to which image signals are supplied to a pixel region on the substrate, a plurality of scanning lines to which scanning signals are supplied, and the plurality of data lines and the plurality of scanning lines. An electro-optical device drive circuit comprising a plurality of switching means provided and a pixel electrode provided corresponding to the switching means, wherein the image signal and the scanning signal are supplied to the data line and the scanning line, respectively. And a shift register for supplying a control signal, comprising at least one of a data line driving means and a scanning line driving means provided on the substrate, wherein at least one of the data line driving means or the scanning line driving means The shift register is a bidirectional shift register in which the transfer direction of a transfer signal is bidirectional, and each stage of the bidirectional shift register is input from a preceding stage of each stage. A transfer direction control unit that limits the transfer direction of a transmission signal to a predetermined direction based on a direction control signal, and generates a transfer signal for each stage based on a transfer signal input from the previous stage in synchronization with a clock signal A transfer signal generation unit configured to perform transfer, and the transfer signal generation unit at each stage of the bidirectional shift register is connected to the transfer direction control unit and takes in a transfer signal input from the previous stage, A first thin film transistor of one of the channel type, a first inverter to which a transfer signal taken in by the first thin film transistor is input, a second inverter to which an output of the first inverter is input, and the first The transfer signal of each stage output from the two inverters is fed back to the first inverter, and the N-channel type or P-channel type one of the conductivity type And a thin film transistor, a distance from each stage of the bidirectional shift register to the pixel region is equal to or equal to each other.
[0023]
According to the driving circuit of the electro-optical device, the transfer direction control unit includes a one-channel type composed of either one of a P-channel TFT and an N-channel TFT whose direction control signal is input to the gate terminal. A TFT and a single-channel TFT in which an inverted signal of the direction control signal is input to the gate terminal are provided. Accordingly, one of the single-channel TFTs is turned on according to the polarity of the direction control signal, and the transfer direction of the transfer signal is limited to one of the directions. In the transfer signal generation unit, a single-channel TFT whose clock signal is input to the gate terminal and a single-channel TFT whose clock signal is inverted are connected to the gate terminal, and adjacent transfer is performed. In the signal generation unit, the arrangement order of the single channel TFTs is reversed. Therefore, if the transfer signal is taken in at the rising edge of the clock signal in the preceding transfer signal generating section and the transfer signal is taken in, the transfer signal generating section in the next stage is switched to the one channel type at the falling edge of the clock signal. Since the TFT is turned on and the transfer signal is captured, the transfer signal generation unit at each stage captures the transfer signal of the previous stage at a timing shifted by a half cycle of the clock signal. Will be transferred.
[0024]
As described above, the transfer signal generation unit of each stage is provided with a plurality of single-channel TFTs. Each single-channel TFT has the same polarity as the input signal regardless of the logical value of the input signal. Since each of the single-channel TFTs has logic for obtaining an output signal, it is not necessary to connect a positive power supply line and a negative power supply line in addition to the signal line. As a result, the area occupied by each stage of the bidirectional shift register can be reduced as compared with the prior art, and the liquid crystal panel can be driven satisfactorily by transferring appropriate transfer signals while realizing a finer pixel pitch. A driving circuit for the electro-optical device can be provided.
[0025]
In the liquid crystal panel driving device of the present invention, each stage of the bidirectional shift register may correspond to each of the plurality of scanning lines, and the pattern length from each stage to the pixel region may be equal.
In the liquid crystal panel driving apparatus of the present invention, the scanning line driving means may be provided at both ends of the scanning line, and each scanning line driving means may be a bidirectional shift register.
According to another aspect of the invention, an electro-optical device includes a drive circuit for the electro-optical device.
[0026]
According to this electro-optical device, the driving device for the electro-optical device is provided, and the driving circuit has a bidirectional direction in which the transfer direction is limited to either the forward direction or the reverse direction according to the direction control signal. Since the data line driving means and the scanning line driving means having the directional shift register are provided, the scanning direction on the display screen is inverted at least up and down or left and right according to the direction control signal. In addition, at least one bidirectional shift register of the data line driving unit and the scanning line driving unit outputs an output signal having the same polarity as the input signal to the transfer direction control unit and the transfer signal generation unit regardless of the logical value of the input signal. Therefore, the area occupied by the drive circuit in the electro-optical device can be reduced, and a small-sized electro-optical device can be provided in combination with a liquid crystal panel having fine pixels.
[0027]
According to another aspect of the invention, an electronic apparatus includes the electro-optical device.
[0028]
According to this electronic apparatus, the electronic apparatus includes the above-described electro-optical device of the present invention, and various image displays can be performed by the electro-optical device that can easily reverse the scanning direction on the display screen at least vertically or horizontally. Is done. In addition, since the pixels of the electro-optical device can be miniaturized, high-definition image display is performed. Furthermore, since the electro-optical device can be reduced in size, the electronic device can be reduced in size.
[0029]
Such an operation and other advantages of the present invention will become apparent from the embodiments described below.
[0030]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0031]
(Configuration of liquid crystal device)
The configuration of the embodiment of the liquid crystal device will be described with reference to FIGS.
[0032]
First, an overall configuration of a liquid crystal device as an example of an electro-optical device will be described with reference to FIGS. 1 to 3. FIG. 1 is a block diagram showing a configuration of various wirings, peripheral circuits and the like provided on the TFT array substrate in the embodiment of the liquid crystal device, and FIG. 2 shows each configuration in which the TFT array substrate is formed thereon. It is the top view seen from the counter substrate side with the element, and FIG. 3 is HH 'sectional drawing of FIG. 2 shown including a counter substrate.
[0033]
In FIG. 1, a liquid crystal device 200 includes a TFT array substrate 1 made of, for example, a quartz substrate or hard glass. On the TFT array substrate 1, a plurality of pixel electrodes 11 provided in a matrix, a plurality of data lines 35 arranged in the X direction and extending in the Y direction, and a plurality of data electrodes 35 arranged in the Y direction are arranged. The scanning lines 31 extending along the X direction, the data lines 35 and the pixel electrodes 11 are respectively interposed between the scanning lines 31 and the conductive and non-conductive states are supplied via the scanning lines 31. A plurality of TFTs 30 are formed as an example of switching elements that are controlled in accordance with scanning signals. Although not shown in the figure, on the TFT array substrate 1, a capacitor line that is a wiring for a storage capacitor may be formed substantially in parallel along the scanning line 31.
[0034]
On the TFT array substrate 1, an inspection circuit 201 that supplies inspection signals to a plurality of data lines 35, a sampling circuit 301 that samples image signals and supplies them to the plurality of data lines 35, and data line driving A circuit 101 and a scanning line driving circuit 104 are formed.
[0035]
The scanning line driving circuit 104 is supplied from the external control circuit via the mounting terminal 102 as shown in FIGS. 1 and 2, the positive power supply VDDY and the negative power supply VSSY, the reference clock signal CLY, and its inverted signal CLY._INV In addition, based on the start signal SPY and the like, the scanning signal is applied to the scanning line 31 (gate electrode line) in a pulse-like manner in a line sequential manner at a predetermined timing.
[0036]
The data line driving circuit 101 is supplied from the external control circuit via the mounting terminal 102 as shown in FIGS. 1 and 2, the positive power supply VDDX and the negative power supply VSSX, the reference clock signal CLX, and its inverted signal CLX._INV Based on the start signal SPX and the image signal VID (for example, VID1 to VID6 when the image signal is 6 systems), for example, 6 systems of images are synchronized with the timing at which the scanning line driving circuit 104 applies the scanning signal. For each of the signals VID1 to VID6, a sampling circuit drive signal is supplied to the sampling circuit 301 via the sampling circuit drive signal line 306 for each data line 35.
[0037]
The sampling circuit 301 includes a TFT 302 for each data line 35, the image signals VID 1 to VID 6 are input to the source electrode of the TFT 302, and the sampling circuit drive signal line 306 is connected to the gate electrode of the TFT 302. Therefore, when a sampling circuit driving signal is input from the data line driving circuit 101 via the sampling circuit driving signal line 306, each of the six image signals VID1 to VID6 is sampled and sequentially applied to each data line 35. . That is, the data line driving circuit 101 and the sampling circuit 301, for example, develop serial image signals into six phases by an image signal processing IC or the like outside the liquid crystal device and use them as input signal lines for image signals on the TFT array 1. Supply. These six parallel image signals VID1 to VID6 are configured to be supplied to the data line 35 via the sampling circuit 301. Such a sampling circuit 301 is a circuit for sampling an image signal in order to stably supply a high-frequency image signal to each data line 35 at a predetermined timing in synchronization with the scanning signal. In accordance with the sampling capability of the sampling circuit 301, the number of phase expansions of the image signal input to the sampling circuit 301 is determined. That is, when the number of data lines 35 is fixed, the number of phase developments of the image signal can be reduced as the sampling capability increases. As a result, the burden on the image signal signal source such as the image signal processing circuit in order to perform high-resolution display is reduced by the sampling circuit 301.
[0038]
In the embodiment described above, the sampling circuit 301 sequentially samples the image signals expanded in six phases, but the number of phase expansions of the image signals is not limited to six. For example, if the sampling capability of the sampling circuit 301 is high, it may be configured with five-phase expansion or less, and if the frequency of the image signal is high, it may be seven-phase expansion or more. At this time, it is needless to say that image signal input signal lines are required at least as many as the number of phase developments of the image signal. When video display is performed using RGB parallel signals such as PAL signals and NTSC signals, it is most efficient to configure the number of phase expansions of the image signal as a multiple of 3.
[0039]
Instead of sequentially supplying the sampling circuit drive signal to the TFTs 302 of the sampling circuit 301 as in this embodiment, for example, the sampling circuit drive signals are simultaneously supplied to the six adjacent TFTs 302, and the image signal developed in six phases. The same display can be obtained by adjusting the phase timings of the two by the image signal processing or the like. By adopting such a configuration, the number of stages of the shift register circuit for supplying the sampling circuit drive signal can be reduced, and the drive frequency can be greatly reduced. As a result, the power consumption of the liquid crystal device can be reduced, and the circuit life of the peripheral circuit can be greatly extended, so that there is an advantage that the reliability is improved.
[0040]
The inspection circuit 201 is a circuit for inspecting the quality, defects, and the like of the liquid crystal device 200 during manufacturing or at the time of shipment. Since the inspection circuit 201 can inspect the TFT array substrate at the end of the process, for example, the defective product is not brought into the assembly process with the next counter substrate 2, and the manufacturing cost and the display inspection process for assembly can be reduced. realizable. In addition to or instead of the inspection circuit 201, a precharge circuit for writing a precharge signal (image auxiliary signal) of a predetermined potential level before writing an image signal to the data line 35 may be provided.
[0041]
In the present embodiment, the inspection circuit 201 and the sampling circuit 301 are provided on the TFT array substrate 1 at a position facing the light-shielding peripheral parting 53 formed on the counter substrate 2 as shown in FIGS. 2 and 3. The data line driving circuit 101 and the scanning line driving circuit 104 are provided on a narrow and long peripheral region of the TFT array substrate 1 that does not face the liquid crystal layer 50. A light-shielding peripheral parting 53 may be provided on the TFT array substrate 1. By adopting such a configuration, the bonding accuracy between the TFT array substrate 1 and the counter substrate 2 can be ignored, and thus there is an advantage that the light transmittance of the liquid crystal panel does not vary.
[0042]
2 and 3, on the TFT array substrate 1, a screen display area defined by a plurality of pixel electrodes 11 (that is, a liquid crystal panel area in which an image is actually displayed by a change in the alignment state of the liquid crystal layer 50). A sealing material 52 made of a photo-curable resin or the like as an example of a sealing member that surrounds the liquid crystal layer 50 by adhering both substrates around () is provided along the screen display area. A light-shielding peripheral parting 53 is provided between the screen display area on the counter substrate 2 and the sealing material 52.
[0043]
When the TFT array substrate 1 is placed in a light-shielding case that is provided with an opening corresponding to the screen display area later, the peripheral parting 53 is limited to the edge of the opening of the case due to a manufacturing error or the like. In other words, it is made of a band-shaped light-shielding material having a width of at least 500 μm around the screen display area so as to allow, for example, a deviation of about several hundred μm from the case of the TFT array substrate 1. It has been done. Such a light-blocking peripheral parting 53 is formed on the counter substrate 2 by sputtering, photolithography, etching, or the like using a metal material such as Cr (chrome) or Ni (nickel), for example. Or it forms from materials, such as resin black which disperse | distributed carbon and Ti (titanium) in the photoresist.
[0044]
A data line driving circuit 101 and mounting terminals 102 are provided along the lower side of the screen display area in the area outside the sealing material 52, and the scanning line driving circuit 104 is provided along the left and right sides of the screen display area. It is provided on both sides of the screen display area. Needless to say, if the delay of the scanning signal supplied to the scanning line 31 is not a problem, the scanning line driving circuit 104 may be provided on only one side. Further, the data line driving circuit 101 may be arranged on both sides along the side of the screen display area. For example, an odd-numbered data line supplies an image signal from a data line driving circuit disposed along one side of the screen display area, and an even-numbered data line extends along the opposite side of the screen display area. An image signal may be supplied from the arranged data line driving circuit. If the data lines 35 are driven in a comb-like shape in this way, the area occupied by the data line driving circuit can be expanded, and a complicated circuit can be configured. Further, on the upper side of the screen display area, a plurality of wirings 105 are provided for supplying signals between the scanning line driving circuits 104 provided on both sides. Further, at least one corner of the counter substrate 2 is provided with a silver point 106 made of a conductive material for establishing electrical continuity between the TFT array substrate 1 and the counter substrate 2. The counter substrate 2 having substantially the same outline as the sealing material 52 is fixed to the TFT array substrate 1 by the sealing material 52.
[0045]
(First Embodiment of Driving Circuit)
Next, a first embodiment of the drive circuit will be described with reference to FIGS. FIG. 4 is a diagram showing the scanning line driving circuit in the first embodiment. FIG. 5A is a block diagram showing a schematic configuration of the waveform control circuit and the buffer circuit in the scanning line driving circuit of this embodiment, and FIG. 5B is a timing chart of various signals in the scanning line driving circuit of this embodiment. is there. FIG. 6A is a block diagram showing a schematic configuration of another example of the waveform control circuit and the buffer circuit in the scanning line driving circuit of this embodiment, and FIG. 6B is the scanning line driving circuit in FIG. It is a timing chart of various signals.
[0046]
First, the scanning line driving circuit will be described.
[0047]
In FIG. 4, the scanning line driving circuit 104 includes a bidirectional shift register 111 and a plurality of waveform control circuits 112 a and buffer circuits 112 b provided corresponding to the outputs of the respective stages of the bidirectional shift register 111. It is prepared for.
[0048]
In the present embodiment, the scanning line driving circuit 104 as an example of the scanning line driving unit has each of the bidirectional shift registers 111 in the transfer direction corresponding to the U → D direction or the D → U direction shown in FIG. The transfer signal is sequentially output from the stage, the waveform control circuit 112a and the buffer circuit 112b select the waveform so that the on-state period of each transfer signal does not overlap, generate the scan signal, and apply the scan signal to each scan line 31. It is configured to supply sequentially. The bidirectional shift register 111 is configured to receive a start signal SPY (hereinafter simply referred to as SP) for starting transfer of the transfer signal as described above, and is directed in the U → D direction. A start signal SP (D) for starting transfer of the transfer signal is input, or a start signal SP (U) for starting transfer of the transfer signal in the direction D → U is input. Then, the scanning line driving circuit 104 has the start signals SP (D), SP (U), the clock signal CL, and the inverted signal CL at the timing shown in the timing chart of FIG._INVAre sequentially delayed by a half cycle of the clock signal CL, and scanning signals S1, S2, S3,..., Sn, each having a pulse width narrower than the pulse width of the clock signal CL, are supplied to the scanning line 31. It is configured as follows.
[0049]
Next, the bidirectional shift register 111 will be described in detail.
[0050]
As shown in FIG. 4, each stage of the bidirectional shift register 111 includes a binary transfer direction control signal D and an inverted signal D as an example of the direction control signal._INVA transfer direction control unit in which the transfer direction is fixed in accordance with the reference clock signal CL as an example of a clock signal having a predetermined period and its inverted signal CL._INVAnd a transfer signal generator for generating a transfer signal based on the above. In addition, the transfer signal generation unit includes a reference clock signal CL and its inverted signal CL._INVEach time the binary level changes, a signal capturing unit that captures an input signal, and a feedback unit that performs feedback of the captured signal to generate a transfer signal in each stage and transfer it to the next stage, It is configured to include.
[0051]
First, the transfer direction control unit includes transmission gates 114, 115, 116, and 117 that constitute an example of gate means.
[0052]
The transmission gates 114 and 116 are configured and connected so that transfer is possible when the signal D is at a high level and the transfer direction is limited to the U → D direction as an example of the forward direction.
[0053]
Transmission gates 115 and 117 receive signal D_INVIs configured and connected so that transfer is possible when the signal is at a high level, and the transfer direction is limited to the D → U direction as an example of the reverse direction.
[0054]
In each stage of the bidirectional shift register 111, transmission gates 114 and 115 or transmission gates 116 and 117 having different transfer directions are alternately provided.
[0055]
Next, the transfer signal generation unit is configured such that the signal capturing unit includes transmission gates 118 and 120 and the feedback unit includes transmission gates 119 and 121.
[0056]
The transmission gate 118 of the signal capturing unit provided in the odd-numbered stages of the bidirectional shift register 111 is connected via the transmission gate 114 when the transfer direction is restricted in the U → D direction by the transfer direction control unit. When the signal CL is at the high level, the transfer signal of the previous stage to be transferred, or the transfer signal of the previous stage to be transferred via the transmission gate 117 when the transfer direction is limited to the D → U direction, Configured and connected so as to be captured as a transfer signal.
[0057]
In addition, the transmission gate 119 of the feedback unit connected to the transmission gate 118 receives the inverted signal CL of the clock signal CL from the transfer signal taken in via the transmission gate 118._INVAre configured and connected to provide feedback during a high level period.
[0058]
Therefore, when a pulse signal that rises to a high level as shown in FIG. 5B is supplied to the first stage of the bidirectional shift register 111 as the start signals SP (D) and SP (U), the clock signal CL A transfer signal Q1 or Qn that maintains a high level for one period T is generated.
[0059]
On the other hand, the transmission gate 120 of the signal capturing unit in the even-numbered transfer signal generation unit of the bidirectional shift register 111 has a transmission gate 116 when the transfer direction is restricted in the U → D direction by the transfer direction control unit. The transfer signal of the previous stage transferred through the transmission gate 115, or the transfer signal of the previous stage transferred through the transmission gate 115 when the transfer direction is limited to the D → U direction, is an inverted signal of the clock signal CL. CL_INVIs configured and connected so as to be taken in as a transfer signal of its own stage when is at a high level.
[0060]
Further, the transmission gate 121 of the feedback unit connected to the transmission gate 120 is configured and connected so that the transfer signal taken in via the transmission gate 120 is fed back during a period when the clock signal CL is at a high level. .
[0061]
Therefore, as shown in FIG. 5B, the transfer signal Q1 generated in the first stage becomes a signal Q2 delayed by a half cycle of the clock signal CL in the second stage, and thereafter the clock signal CL is sequentially transferred to the subsequent stage. The transfer signal is transferred with a delay of half a cycle. Such a transfer operation is performed regardless of the transfer direction, and when the transfer direction is fixed in the D → U direction, transfer is delayed by half a cycle of the clock signal CL from Qn to Q1 of the transfer signal. Will be done.
[0062]
Next, the waveform control circuit 112a and the buffer circuit 112b will be described with reference to FIG.
[0063]
As shown in FIG. 5A, the waveform control circuit 112a is composed of a NAND circuit that negates the logical product of outputs at adjacent stages of the bidirectional shift register 111, and the buffer circuit 112b is an output by the NAND circuit. It consists of an inverter circuit that inverts the result.
[0064]
According to the waveform control circuit 112a and the buffer circuit 112b as described above, as shown in FIG. 5B, the high level only when the outputs at the adjacent stages of the bidirectional shift register 111 are both high level. Thus, the scanning signals S1 to Sn are supplied to the scanning line 31. As described above, the scanning signal supplied to the scanning line 31 is configured such that a period during which the scanning signal is at a high level, that is, a so-called selection period does not overlap between the scanning lines. Alternatively, the polarity of the start signal SP may be inverted and input to the bidirectional shift register, and the NOR circuit may be configured to operate when signals output from adjacent stages of the bidirectional shift register 111 are at a low level. good. In the case of a NOR circuit, at least two inverter circuits are required.
[0065]
The waveform control circuit 112a and the buffer circuit 112b may be configured as shown in FIG. In the example of FIG. 6A, the first enable signal ENB1 and the second enable signal ENB2 are supplied to the waveform control circuit 112a and the buffer circuit 112b, and the pulse of the transfer signal output from the odd-numbered stage of the bidirectional shift register 111. The width is limited to the pulse width of the first enable signal ENB1, and the pulse width of the transfer signal output from the even-numbered stage of the bidirectional shift register 111 is limited to the pulse width of the second enable signal ENB2. Has been. In this way, by controlling the waveform with the enable signal from the outside, it is possible to prevent overlapping of scanning signals and to prevent display quality deterioration such as ghost.
[0066]
Next, the data line driving circuit 101 will be described. The data line driving circuit 101 includes a bidirectional shift register, a waveform control circuit, and a buffer circuit having a configuration similar to that of the scanning line driving circuit 104. However, the data line driving circuit 101 is provided once for a plurality of adjacent TFTs 302 of the sampling circuit 301. Since the sampling circuit driving signal can be output to the scanning line driving circuit, the number of stages of the bidirectional shift register and the number of NAND circuits and inverter circuits constituting the waveform control circuit and buffer circuit corresponding to the number of stages are determined by the scanning line driving circuit. The number can be reduced as compared with 104 bidirectional shift registers. However, the present invention is not limited to such a configuration, and each stage of the bidirectional shift register corresponds to each of the TFTs 302 of the sampling circuit 301 as in the scanning line driving circuit 104 as shown in FIG. In this case, the present invention is particularly effective.
[0067]
As described above, in the data line driver circuit 101, the number of bidirectional shift registers can be configured to be smaller than the number of data lines, but in the scanning line driver circuit 104, the number of shift register series Unless a special circuit for waveform control is provided, the number of scanning lines must be equal to the number of scanning lines. As a result, the pixel pitch defined by the array pitch of the scan lines and the array pitch of the data lines is the occupied area of each stage of the bidirectional shift register, particularly the bidirectional shift register 111 in the scan line driver circuit 104. It depends on the size of the area occupied by the circuit at each stage.
[0068]
Therefore, various devices have been conventionally devised for the circuit arrangement of each stage of the bidirectional shift register 111. For example, as in Comparative Example 1 shown in FIG. 7, the odd-numbered and even-numbered stages of the bidirectional shift register of the scanning line driving circuit 104 are arranged in parallel in the direction parallel to the scanning line 31 and parallel to the data line 35. A method has been proposed in which odd-numbered and even-numbered stages of the bidirectional shift register of the data line driving circuit 101 are arranged in parallel in the direction. In this example, the configuration is such that the number of stages of the bidirectional shift register of the data line driving circuit 101 is equal to the number of the data lines 35.
[0069]
In FIG. 7, for example, the data line shift register 1 constituting the data line driving circuit 101 shows a one-stage latch circuit including a waveform control circuit, a buffer circuit, and the like, and the data line X1 is connected via the sampling circuit S / H1. Connected to. Next, the data line shift register 2 shows a one-stage latch circuit including a waveform control circuit, a buffer circuit, and the like, and is connected to the data line X2 via the sampling circuit S / H2. As shown in FIG. 7, these data line shift registers are constituted by blocks of odd-numbered data line shift registers and even-numbered data line shift registers. Alternatively, a multi-series shift register can be configured by forming the odd-numbered data line shift register and the even-numbered shift register as independent series. The scanning line shift register 1 constituting the scanning line driving circuit is a one-stage latch circuit including a waveform control circuit and a buffer circuit, and is connected to the scanning line Y1 and supplies a scanning signal. Next, the scanning line shift register 2 shows a one-stage latch circuit including a control circuit and a buffer circuit, and is connected to the scanning line Y2 to supply a scanning signal.
[0070]
According to this method, the width in the direction perpendicular to the scanning line 31 in the occupied area of each stage of the bidirectional shift register can be set to 2 LV with respect to the pixel pitch LV defined by the interval between the scanning lines 31. Similarly, with respect to the pixel pitch LH defined by the interval between the data lines 35, the width in the direction perpendicular to the data lines 35 in the occupied area of each stage of the bidirectional shift register can be set to 2LH. Therefore, even when it is difficult to reduce the width of the area occupied by each stage of the bidirectional shift register, the pixel pitches LV and LH can be relatively miniaturized. However, in this method, the width WV in the direction parallel to the scanning line 31 of the bidirectional shift register of the scanning line driving circuit 104 and the direction of the data line 35 in the bidirectional shift register of the data line driving circuit 101 are parallel. The total width of the odd-numbered and even-numbered stages is 2 WW and 2 WH, respectively, and the occupied area of the scanning line driving circuit 104 and the data line driving circuit 101 is increased, which makes it difficult to reduce the size of the liquid crystal panel. In addition, the odd-numbered stages of the bidirectional shift register have a longer wiring length to the pixel region than the even-numbered stages, causing the problem of delay of scanning signals due to the addition of wiring resistance and capacitance, and adjacent scanning lines. Alternatively, display unevenness may occur between pixels corresponding to the data lines.
[0071]
Next, in the comparative example 2 shown in FIG. 8, similarly to the present embodiment, a plurality of TFTs of the sampling circuit 301 are driven by each stage of the bidirectional shift register of the data line driving circuit 101. . For example, as shown in FIG. 8, when six sampling circuits S / H are simultaneously driven in each stage of the bidirectional shift register, the vertical line is perpendicular to the data line 35 in the occupied area of each stage. The direction width can be up to 6LH.
[0072]
Thus, by devising the number of phase expansions of the image signal and the like, the LH region can be freely expanded, so that the data line driving circuit can secure an occupied area relatively freely.
[0073]
On the other hand, the scanning line driving circuit 104 is provided with only the odd-numbered stages of the bidirectional shift register at the left end of the scanning line 31 in FIG. 8, and only the even-numbered stages at the right end in FIG. The odd-numbered stages and the even-numbered stages are alternately connected to the scanning line 31. In this way, by arranging the stages of the bidirectional shift register in a comb-like shape, the width WV of the occupied area of each stage in the direction parallel to the scanning line 31 is not increased, and it is perpendicular to the scanning line 31. The width of the occupied area of each stage in the direction can be up to 2 LV.
[0074]
However, according to this method, each stage of the bidirectional shift register is connected to only one side of the scanning line 31, and therefore, the end of the scanning line 31 on the side where each stage of the bidirectional shift register is not connected. There is a problem that a gate delay occurs in the part.
[0075]
Therefore, in this embodiment, as shown in FIG. 9, each stage of the bidirectional shift register and the scanning line 31 are made to correspond to each other, and the pattern length from each stage to the pixel region is made equal. With such a configuration, there is no difference in gate delay between scanning lines, and display unevenness can be suppressed. Although not shown in FIG. 9, if a bidirectional shift register is provided at both ends of the scanning line 31 so as to eliminate the gate delay at the end of the scanning line 31, the display unevenness is further reduced. Is effective. In FIG. 9, the bidirectional shift register of the data line driving circuit 101 is configured to drive each TFT of the sampling circuit 301 by each stage. With such a configuration, as with the scanning line driving circuit 104, it is not necessary to configure the bidirectional shift register in a block form or in a multi-series, and therefore image quality such as display unevenness is hardly deteriorated.
[0076]
However, in such a configuration, when the width of the occupied area of each stage of the bidirectional shift register is equal to the width LH and LV of the pixel, and the occupied area of each stage cannot be reduced, There is a problem that it is difficult to reduce the pixel pitch. In particular, in the prior art, as shown in FIG. 13, since the transfer signal generator is configured by clocked inverters 130, 131, 133, and 134, the area occupied by each stage of the bidirectional shift register 111 ′ is reduced. It was difficult.
[0077]
That is, the clocked inverters 130 and 133 represented by the symbols shown in FIG. 14A have the circuit configuration shown in FIG. 14B, and the clock signal CL and the inverted signal CL._INVIn addition, it is necessary to supply a positive power supply VDD and a negative power supply VSS. That is, as shown in FIG. 14B, the clocked inverters 130 and 133 include an N-channel TFT in which the clock signal CL is input to the gate, and a signal CL._INVP-channel TFTs, P-channel TFTs and N-channel TFTs connected in parallel so that transfer signals are input to the gates, power supply VSS (low potential power supply) and VDD (high potential power supply) Are connected as shown in the figure. Further, the signal CL is also applied to the clocked inverters 131 and 134._INVIs input to the gate of the N-channel TFT and the clock signal CL is input to the gate of the P-channel TFT, and has the same configuration as the clocked inverters 130 and 133, and requires the power supply VSS and VDD.
[0078]
Thus, since each clocked inverter requires the power supply VSS and VDD, it is necessary to route the power supply wiring to the entire bidirectional shift register 111 ′ shown in FIG. 13.
[0079]
Therefore, as shown in FIG. 15 which is a pattern diagram of the areas indicated by A-1 and A-2 in FIG. 13, the interval (arrangement pitch) H between adjacent stages of the bidirectional shift register is set to the positive power supply VDD and There is a problem that the power supply wiring of the negative power supply VSS is widened.
[0080]
However, in this embodiment, as an example of logic gate means for obtaining an output signal having the same polarity as the input signal regardless of the logical value of the input signal, not only in the transfer direction control unit but also in the transfer signal generation unit, FIG. Since the transmission gate represented by the symbol shown in FIG. 10A and having the circuit configuration of FIG. 10B is used, as shown in FIG. 11, the spacing between adjacent stages (arrangement pitch) of the bidirectional shift register H can be made narrower than before. 11, 12, and 15 are examples of patterns laid out using the same design rule, and are enlarged at the same enlargement ratio.
[0081]
In other words, the transmission gate has an N-channel TFT and a P-channel type depending on the potential difference between the direction control signal or clock signal applied to the gate electrode and the transfer signal applied to the input electrode or output electrode of the transfer signal. Since the TFTs are turned on at the same time, it is not necessary to supply the positive power supply VDD and the negative power supply VSS. Therefore, as shown in FIG. 11, it is not necessary to route these power supply patterns, and the interval (arrangement pitch) H between adjacent stages of the bidirectional shift register can be reduced, so that the liquid crystal panel can be downsized. It is advantageous.
[0082]
10A and 10B, the clock signal CL is applied to the N-channel TFT, and the inverted signal CL of the clock signal CL is applied to the P-channel TFT._INVOnly the transmission gates 118 and 121 in which both the N-channel TFT and the P-channel TFT are turned on when the clock signal CL is at the high level are shown. However, the clock signal is also applied to the transmission gates 119 and 120 shown in FIG. CL which is an inverted signal of CL_INVAre the same as the transmission gates 118 and 121 except that the N-channel TFT and the clock signal CL are input to the P-channel TFT. Further, the direction control signal D and the inversion signal D_INVThe transmission gates 114 to 117 to which are inputted have the same configuration as the transmission gate described above.
[0083]
Specifically, in a conventional driving device using a clocked inverter circuit, when the pixel pitch (LV and LH shown in FIG. 9) is 30 μm or less, the design rule is designed with, for example, a wiring and a wiring interval of about 2 μm each. Then, the pattern arrangement becomes difficult, and it is necessary to increase the length of the bidirectional shift register (WV and WH shown in FIG. 9). However, according to the driving device of this embodiment, the same design rule is used. The pixel pitch can be set to 20 μm or less, and the lengths WV and WH of the bidirectional shift register can be kept as they are. Accordingly, it is possible to miniaturize the pixels in which the peripheral circuits are built on the same substrate, and it is possible to reduce the size of the liquid crystal panel substrate.
[0084]
Note that the waveform control circuit 102a and the buffer circuit 102b require power supply wiring, but an input line for a control signal such as a clock signal or a transfer direction control signal is not necessary, so as shown in the pattern configuration example in FIG. It can be formed within the interval (arrangement pitch) H between adjacent stages of the bidirectional shift register defined by the transmission gate.
[0085]
(Second Embodiment of Driving Circuit)
Next, a second embodiment of the drive circuit of the present invention will be described with reference to FIGS. In addition, the same code | symbol is attached | subjected to a common location with 1st Embodiment of a drive circuit, and description is abbreviate | omitted.
[0086]
In the present embodiment, instead of the bidirectional shift register 111 described in the first embodiment, the transfer direction control unit and the transfer signal generation unit perform the conduction of the P-channel TFT and the N-channel TFT as shown in FIG. This is an example in which a bidirectional shift register 140 composed of single-channel TFTs 150 to 157 is used.
[0087]
In the bidirectional shift register 140, a single channel TFT is used as an example of a logic gate means for obtaining an output signal having the same polarity as the input signal regardless of the logic value of the input signal, instead of the transmission gate. FIG. 16 shows an example using N-channel TFTs 150 to 157. There is no problem even if only the P-channel TFT is formed, or the transfer direction control section is formed as a P-channel TFT and the transfer signal generation section is formed as an N-channel TFT.
[0088]
Even in such a configuration, as shown in FIG. 17, the power supply wiring of the positive power supply and the negative power supply is not required, and the interval (arrangement pitch) H between adjacent stages of the bidirectional shift register is set to the clocked inverter circuit. It can be made smaller than when it is used. Specifically, it can be made 15 μm or less by the above-mentioned design rule. Also, with this configuration, as shown in FIG. 17, the number of TFT elements can be reduced, and not only the arrangement pitch of peripheral circuits but also the length of the bidirectional shift register in the X direction shown in FIG. Therefore, the area occupied by the bidirectional shift register can be reduced. As a result, the liquid crystal panel substrate itself can be further reduced in size.
[0089]
When N-channel TFTs 150 to 157 are used, the spacing (arrangement pitch) H between adjacent stages of the bidirectional shift register is not changed by changing the arrangement of the TFT elements as shown in FIG. In addition, the length in the X direction can be further reduced, and there is an advantage that it can be applied to an ultra-small liquid crystal panel.
[0090]
Further, in the present embodiment, any N-channel or P-channel TFT can be used as long as it is a single-channel TFT. The pattern diagrams shown in FIGS. 17 and 18 are examples of patterns laid out using the same design rules as those in FIGS. 11, 12, and 15, and are enlarged at the same magnification.
[0091]
(Configuration of LCD panel)
Next, a specific configuration of a pixel portion and a peripheral circuit constituting a screen display area on the TFT array substrate 1 included in the liquid crystal device 200 will be described with reference to FIGS. 19 and 20. Here, FIG. 19A is a plan view of patterns of various electrodes formed on the TFT array substrate, and FIG. 19B is a cross-sectional view along AA ′ shown in FIG. The pixel switching TFT is shown. FIG. 20A is a plan view of a pattern of a single-channel TFT such as a P-channel TFT or an N-channel TFT, and FIG. 20B is along BB ′ shown in FIG. It is sectional drawing. In FIGS. 19 (a) and 20 (a), the scale is different for each layer and each member so that each layer and each member can be recognized on the drawing.
[0092]
Here, as shown in the plan view of FIG. 19A, the pixel electrodes 11 are arranged in a matrix on the TFT array substrate 1, TFTs 30 are provided adjacent to the pixel electrodes 11, and the pixels A data line 35 (source electrode) and a scanning line 31 (gate electrode) are provided along the vertical and horizontal boundaries of the electrode 11, respectively. In this embodiment, only one pixel switching TFT 30 for controlling the pixel electrode 11 is provided for each pixel electrode 11. However, between the source and drain of the TFT 30, that is, from the contact hole 37 to the contact hole 38. Two gate electrodes (scanning lines) 31 may be arranged in series between them to form a dual gate structure, or three or more may be arranged in series. As described above, by providing the TFT 30 with multiple stages of gates, there is an advantage that the resistance component increases and the leakage current when the TFT 30 is off can be reduced. Note that FIG. 19B is for simplifying the matrix arrangement of the pixel electrodes 11 and the like for convenience of explanation, and each actual electrode has a contact hole or the like between or above the interlayer insulating layers. As shown in FIG. 19B, it has a three-dimensionally more complicated configuration.
[0093]
19B, the liquid crystal panel 10 includes a TFT array substrate 1 and a first interlayer insulating layer 41, a semiconductor layer 32, and a gate insulating layer 33 stacked on the TFT array substrate 1 in the TFT 30 portion provided in each pixel. , A scanning line 31 (gate electrode), a second interlayer insulating layer 42, a data line 35 (source electrode), and a pixel electrode 11.
[0094]
The TFT array substrate 1 serving as a base of the TFT 30 is an insulating substrate formed of glass, quartz, or the like, and a semiconductor layer 32 in which a channel is formed by an electric field from the scanning line 31 is provided on the TFT array substrate 1. .
[0095]
The semiconductor layer 32 is formed, for example, by forming an a-Si (amorphous silicon) film on the TFT array substrate 1 as a base, and then subjecting it to an annealing process to solid-phase growth to a thickness of about 500 to 2000 mm. Thereafter, the gate insulating film 33 is formed by thermal oxidation or the like, and the gate electrode 31 is formed on the gate insulating film 33. When the N-channel TFT 30 is formed, a dopant of a group V element such as Sb (antimony), As (arsenic), P (phosphorus) or the like is selectively used in a portion to be a source / drain region of the semiconductor layer 32. A source region and a drain region are formed by doping by ion implantation or the like. When the P-channel TFT 30 is formed, III (such as Al (aluminum), B (boron), Ga (gallium), In (indium), etc.) is selectively formed in a portion to be a source / drain region of the semiconductor layer 32. A source region and a drain region are formed by doping by ion implantation using a dopant of a group element. Since these dopings are performed using the gate electrode 31 as a mask, a region where no doping is performed is formed as the channel region 32a. In particular, when the TFT 30 is an N-channel TFT having an LDD (Lightly Doped Drain) structure, the source region and the drain region are partially adjacent to the channel region 32a side by a dopant of a V group element such as P in a part of the source region and the drain region. The region 32b and the low concentration drain region 32c are formed, and the high concentration source region 32d and the high concentration drain region 32e are formed with a dopant of a group V element such as P. Further, in the case of the P-channel TFT 30, the low-concentration source region 32b and the high-concentration source region are formed on a part of the source / drain region adjacent to the channel region 32a by using a group III element dopant such as B. 32d, a low concentration drain region 32c and a high concentration drain region 32e are formed. Note that the N-channel TFT has an advantage of high operating speed, and is often used as the pixel switching TFT 30.
[0096]
In addition, when the LDD structure is used in this way, an advantage that the short channel effect can be reduced is obtained. The TFT 30 may be an TFT having an offset structure in which impurity ions are not implanted into the low-concentration source / drain regions 32b and 32c, or a high-concentration source in a self-aligned manner by implanting high-concentration impurity ions using the gate electrode 31 as a mask. A self-aligned TFT for forming the drain regions 32a and 32e may be used.
[0097]
The gate insulating layer 33 is obtained by thermally oxidizing the semiconductor layer 32 at a temperature of about 900 to 1300 ° C. to form a relatively thin thermal oxide film of about 300 to 1500 mm.
[0098]
The first interlayer insulating layer 41 and the second interlayer insulating layer 42 are each made of a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, a silicon oxide film, or the like having a thickness of about 5000 to 15000 mm. Note that a planarization film may be further applied on the second interlayer insulating layer 42 by spin coating or the like, or a CMP process may be performed. In this way, by flattening the surface on which the pixel electrode 11 is formed, it is possible to reduce as much as possible the region where liquid crystal disclination occurs due to poor alignment during rubbing.
[0099]
A contact hole 37 leading to the high concentration source region 32d is formed in the first interlayer insulating layer 41, and a contact hole 38 leading to the high concentration drain region 32e is formed in the first interlayer insulating layer 41 and the second interlayer insulating layer 42. Each is formed. The data line 35 (source electrode) is electrically connected to the high concentration source region 32d through the contact hole 37 to the high concentration source region 32d. Further, the pixel electrode 11 is electrically connected to the high concentration drain region 32e through a contact hole 38 to the high concentration drain region 32e. If each contact hole is formed by dry etching such as reactive etching or reactive ion beam etching, it can be opened with high dimensional accuracy.
[0100]
In general, a polysilicon film or the like forming the semiconductor layer 32 in which a channel is formed generates a photocurrent due to a photoelectric conversion effect of the polysilicon film when light is incident, and the transistor characteristics of the TFT 30 deteriorate. In the present embodiment, as shown in FIG. 3, since the light shielding layer 23 such as a black matrix made of a Cr film is formed on the counter substrate 2 at positions facing the respective TFTs 30, incident light is directly applied to the semiconductor layer 32. Incident light is prevented. Further, in addition to or instead of this, if the data line 35 (source electrode) is formed of an opaque metal thin film such as Al so as to cover the gate electrode from the upper side, it is possible to connect to the semiconductor layer 32 together with the light shielding layer 23 or alone. Irradiation of incident light (that is, light from the upper side in FIG. 19B) can be effectively prevented.
[0101]
The scanning line 31 (gate electrode) is formed by a photolithography process, an etching process, or the like after depositing a polysilicon film by a low pressure CVD method or the like. Alternatively, it may be formed of a refractory metal film such as W (tungsten) or Mo (molybdenum) or an alloy film such as a metal silicide film thereof.
[0102]
The data line 35 (source electrode) is formed from a low resistance metal such as Al or an alloy film such as metal silicide deposited to a thickness of about 1000 to 5000 mm by sputtering or the like.
[0103]
The pixel electrode 11 is made of a transparent conductive thin film such as an ITO film (Indium Tin Oxide film), and is provided on the upper surface of the second interlayer insulating layer 42 described above. The pixel electrode 11 is formed by depositing an ITO film or the like to a thickness of about 500 to 2000 mm by sputtering or the like, and then performing a photolithography process or an etching process. Note that when the liquid crystal panel 10 is used in a reflective liquid crystal device, the pixel electrode 11 may be formed from an opaque material having a high reflectance such as Al.
[0104]
On the other hand, the P-channel TFT and the N-channel TFT for controlling the peripheral circuits such as the data line driving circuit 101 and the scanning line driving circuit 104 described above basically have a planar structure as shown in FIG. The cross-sectional view along the line BB ′ has the structure shown in FIG. Thus, the difference between the TFT 60 and the pixel switching TFT 30 shown in FIG. 19A is that ITO is used for the pixel electrode 11 as the drain electrode of the TFT 30 and aluminum is used for the drain electrode of the TFT 60. However, it can be formed by a thin film forming process substantially the same as that for forming the TFT 30 in the pixel region.
[0105]
Specifically, first, a semiconductor layer 62 is formed on the TFT array substrate 1. The semiconductor layer 62 includes a channel region 62 a, a low concentration source region 62 b, a high concentration source region 62 d, a low concentration drain region 62 c, and a high concentration source region. A concentration drain region 62e is formed. A gate insulating layer 63 is formed on the semiconductor layer 62, and a gate electrode 61 is formed on the gate insulating layer 63. Then, the source electrode 64 and the drain electrode 65 are electrically connected to the high-concentration source region 62d and the high-concentration drain region 62e through the contact holes 66 formed in the first interlayer insulating layer 41, respectively. Further, the second interlayer insulating layer 42 is formed so as to cover the source electrode 64 and the drain electrode 65.
[0106]
The semiconductor layer 62 is in the semiconductor layer 32 of the TFT 30 in the pixel region, the channel region 62a is in the channel region 32a of the TFT 30, the low concentration source region 62b is in the low concentration source region 32b of the TFT 30, and the high concentration source region 62d is The high concentration source region 32d of the TFT 30, the low concentration drain region 62c corresponds to the low concentration drain region 32c of the TFT 30, and the high concentration drain region 62e corresponds to the high concentration drain region 32e of the TFT 30, respectively. The In the case where the pixel switching TFT 30 is formed of an N-channel TFT, a doping process is performed by ion implantation using a group III element dopant to form a P-channel TFT of the TFT 60 constituting the peripheral circuit. Can be added to form a complementary TFT.
[0107]
In this embodiment, the TFT 60 constituting the peripheral circuit is also formed with the LDD structure. However, the above-described offset structure TFT or a self-aligned TFT may be used. Note that if the TFT 60 is formed of a self-aligned TFT, high mobility can be obtained, so that a high-speed driving circuit can be realized.
[0108]
Further, the gate insulating layer 63 corresponds to the gate insulating layer 33 of the TFT 30 and the gate electrode 61 corresponds to the gate electrode 31 of the TFT 30 and is formed by the same process. The source electrode 66 and the drain electrode 65 correspond to the source electrode 35 of the TFT 30 and are formed by the same process.
[0109]
Therefore, the pixel pitch can be reduced as described above by configuring the data line driving circuit or the scanning line driving circuit with a single channel type TFT such as a transmission gate, a P channel type TFT, or an N channel type TFT. In addition, a transmission gate and a single-channel TFT can be formed in the same thin film forming process as the TFT in the pixel region, which is advantageous in manufacturing.
[0110]
Although not shown in FIG. 19, for example, a TN (twisted nematic) mode, STN (super) is provided on the side on which the projection light of the counter substrate 2 is incident and on the side of the TFT array substrate 1 on which the projection light is emitted. TN) mode, D-STN (double-STN) mode, and other modes, as well as normal white mode / normally black mode, polarizing films, retardation films, polarizing plates, etc. are arranged in a predetermined direction. The
[0111]
Since the liquid crystal panel 10 described above is applied to a color liquid crystal projector, the three liquid crystal panels 10 are respectively used as RGB light valves, and each panel is decomposed via a dichroic mirror for RGB color separation. Each color light is incident as incident light. Therefore, in each embodiment, the counter substrate 2 is not provided with a color filter. However, in the liquid crystal panel 10 as well, an RGB color filter may be formed on the counter substrate 2 together with its protective film in a predetermined region facing the pixel electrode 11 where the light shielding layer 23 is not formed. In this way, the liquid crystal panel of the present embodiment can be applied to a color liquid crystal device such as a direct-view type or a reflection type color liquid crystal television other than the liquid crystal projector.
[0112]
The switching element of the liquid crystal panel 10 has been described as being a normal staggered type or coplanar type polysilicon TFT, but the present invention is also applied to other types of TFTs such as an inverted staggered type TFT and an amorphous silicon TFT. The form of is effective.
[0113]
Furthermore, in the liquid crystal panel 10, the liquid crystal layer 50 is made of nematic liquid crystal as an example. However, if polymer dispersed liquid crystal in which liquid crystal is dispersed as fine particles in a polymer is used, an alignment film and the polarizing film described above are used. Further, there is no need for a polarizing plate or the like, and the advantages of high brightness and low power consumption of the liquid crystal panel can be obtained by increasing the light utilization efficiency. Further, when the liquid crystal panel 10 is applied to a reflective liquid crystal device by forming the pixel electrode 11 from a metal film having a high reflectance such as Al, SH in which liquid crystal molecules are substantially vertically aligned in the absence of voltage application. (Super homeotropic) type liquid crystal may be used. Furthermore, in the liquid crystal panel 10, the common electrode 21 is provided on the side of the counter substrate 2 so as to apply an electric field (vertical electric field) perpendicular to the liquid crystal layer 50, but an electric field (horizontal) parallel to the liquid crystal layer 50 is provided. The pixel electrode 11 is composed of a pair of electrodes for generating a horizontal electric field so that an electric field is applied (that is, the side of the TFT array substrate 1 is not provided with the electrode for generating a vertical electric field on the side of the counter substrate 2). It is also possible to provide a lateral electric field generating electrode. Using a horizontal electric field in this way is more advantageous in widening the viewing angle than using a vertical electric field. In addition, the present embodiment can be applied to various liquid crystal materials (liquid crystal phases), operation modes, liquid crystal alignments, driving methods, and the like.
[0114]
Further, when a voltage is applied to the pixel electrode 11, the alignment state of the liquid crystal in the portion sandwiched between the pixel electrode 11 and the common electrode 21 in the liquid crystal layer 50 changes. The incident light cannot pass through the liquid crystal part according to the applied voltage, and in the normally black mode, the incident light can pass through the liquid crystal part according to the applied voltage, and the liquid crystal panel 10 as a whole. Emits light having a contrast according to the image signal. At this time, particularly in this embodiment, since the image signal expanded in multiphase is sampled by the sampling circuit 301 and supplied to the data line as an image signal, the high-frequency image signal is stably supplied to each data line at a predetermined timing. Therefore, it can be supplied in synchronization with the scanning signal.
[0115]
Note that the data line driving circuit 101 and the scanning line driving circuit 104 are provided on the driving LSI mounted on the TAB (tape automated bonding substrate), for example, on the TFT array substrate 1 instead of being provided on the TFT array substrate 1. You may make it connect electrically and mechanically through the anisotropic conductive film provided in the peripheral part.
[0116]
Furthermore, in the above embodiment, as disclosed in JP-A-9-127497, JP-B-3-52611, JP-A-3-125123, JP-A-8-171101, and the like, A light shielding layer made of a refractory metal, for example, may also be provided at a position facing the TFT 30 on the TFT array substrate 1 (that is, below the TFT 30). If a light shielding layer is also provided below the TFT 30 as described above, it is possible to prevent the return light from the TFT array substrate 1 from entering the TFT 30 in advance.
[0117]
(Electronics)
Next, an embodiment of an electronic apparatus provided with the liquid crystal device 200 described in detail above will be described with reference to FIGS.
[0118]
First, FIG. 21 illustrates a schematic configuration of an electronic apparatus including the liquid crystal device 200 as described above.
[0119]
In FIG. 21, an electronic device includes a display information output source 1000, a display information processing circuit 1002, a display driving circuit 1004 including the above-described scanning line driving circuit 104 and data line driving circuit 101, a liquid crystal panel 10, a clock generation circuit 1008, and a power source. A circuit 1010 is provided. The display information output source 1000 includes a ROM (Read Only Memory), a RAM (Random Access Memory), a memory such as an optical disk device, a tuning circuit that tunes and outputs a television signal, and the like. Based on the clock signal, display information such as an image signal in a predetermined format is output to the display information processing circuit 1002. The display information processing circuit 1002 includes various known processing circuits such as an amplification / polarity inversion circuit, a phase expansion circuit, a rotation circuit, a gamma correction circuit, and a clamp circuit. The display information processing circuit 1002 receives the clock signal from the clock generation circuit 1008. A digital signal is sequentially generated from the input display information based on the received information and is output to the display driving circuit 1004 together with the clock signal CLK. The display driving circuit 1004 drives the liquid crystal panel 10 by the above-described driving method using the scanning line driving circuit 104 and the data line driving circuit 101. The power supply circuit 1010 supplies predetermined power to the above-described circuits. Note that a display drive circuit 1004 may be mounted on the TFT array substrate constituting the liquid crystal panel 10, and in addition to this, a display information processing circuit 1002 may be mounted.
[0120]
As an electronic apparatus having such a configuration, a liquid crystal projector shown in FIG. 22, a personal computer (PC) and engineering workstation (EWS) compatible with multimedia shown in FIG. 23, or a mobile phone, a word processor, a television, a viewfinder type, or Examples include a monitor direct-view video table recorder, an electronic notebook, an electronic desk calculator, a car navigation device, a POS terminal, and a device equipped with a touch panel.
[0121]
Next, specific examples of the electronic apparatus configured as described above are shown in FIGS.
[0122]
In FIG. 22, a liquid crystal projector 1100 as an example of an electronic device is a projection-type liquid crystal projector, and includes a light source 1110, dichroic mirrors 1113, 1114, reflection mirrors 1115, 1116, 1117, an incident lens 1118, a relay lens 1119, An exit lens 1120, liquid crystal light valves 1122, 1123, 1124, a cross dichroic prism 1125, and a projection lens 1126 are provided. The liquid crystal light valves 1122, 1123, and 1124 are prepared as three liquid crystal modules including the liquid crystal panel 10 in which the drive circuit 1004 described above is mounted on the TFT array substrate, and each is used as a liquid crystal light valve. The light source 1110 includes a lamp 1111 such as a metal halide and a reflector 1112 that reflects light from the lamp 1111.
[0123]
In the liquid crystal projector 1100 configured as described above, the dichroic mirror 1113 that reflects blue light and green light transmits red light of white light flux from the light source 1110 and reflects blue light and green light. . The transmitted red light is reflected by the reflection mirror 1117 and is incident on the liquid crystal light valve 1122 for red light. On the other hand, of the color light reflected by the dichroic mirror 1113, green light is reflected by the dichroic mirror 1114 that reflects green light and enters the liquid crystal light valve 1123 for green light. Blue light also passes through the second dichroic mirror 1114. For blue light, in order to prevent light loss due to a long optical path, light guiding means 1121 including a relay lens system including an incident lens 1118, a relay lens 1119, and an exit lens 1120 is provided, and blue light is transmitted through the blue light. The light enters the light liquid crystal light valve 1124. The three color lights modulated by the respective light valves enter the cross dichroic prism 1125. In this prism, four right-angle prisms are bonded together, and a dielectric multilayer film that reflects red light and a dielectric multilayer film that reflects blue light are formed in a cross shape on the inner surface. These dielectric multilayer films combine the three color lights to form light representing a color image. The synthesized light is projected onto the screen 1127 by the projection lens 1126 which is a projection optical system, and the image is enlarged and displayed.
[0124]
23, a laptop personal computer 1200, which is another example of an electronic device, includes a liquid crystal display 1206 in which the above-described liquid crystal panel 10 is provided in a top cover case, a CPU, a memory, a modem, and the like, and a keyboard. And a main body 1204 in which 1202 is incorporated.
[0125]
Further, as shown in FIG. 24, a liquid crystal device substrate 1304 in which liquid crystal is sealed between two transparent substrates 1304a and 1304b and the above-described drive circuit 1004 is mounted on a TFT array substrate is provided. A TCP (Tape Carrier Package) 1320 having an IC chip 1324 mounted on a polyimide table 1322 on which a metal conductive film is formed is connected to one of two transparent substrates 1304a and 1304b constituting the substrate 1304, for use in an electronic device. It can also be produced, sold, and used as a liquid crystal device that is a single component.
[0126]
As described above, in addition to the electronic devices described with reference to FIGS. 22 to 24, a liquid crystal television, a viewfinder type or a monitor direct-view type video tape recorder, a car navigation device, an electronic notebook, a calculator, a word processor, a workstation, a mobile phone A telephone, a videophone, a POS terminal, a device provided with a touch panel, and the like can be given as examples of the electronic device shown in FIG.
[0127]
In addition, this invention is not limited to the said Example, A various deformation | transformation implementation is possible within the range of the summary of this invention. For example, the present invention is not limited to those applied to driving the various liquid crystal panels described above, but can also be applied to electroluminescence and plasma display devices.
[0128]
As described above, according to the present embodiment, various electronic devices having high-definition pixels and including the small liquid crystal device 200 can be realized.
[0129]
【The invention's effect】
As described above, according to the electro-optical device of the present invention, in the bidirectional shift register of at least one of the scanning line driving unit and the data line driving unit, both the transfer direction control unit and the transfer signal generation unit Direction is possible. In addition, when a logic gate means for obtaining an output signal having the same polarity as the input signal regardless of the logic value of the input signal is provided, it is not necessary to route the power supply wiring when forming the pattern of the gate means. The area occupied by the direction control unit and the transfer signal generation unit can be reduced. Therefore, even when each stage of the bidirectional shift register is provided in one-to-one correspondence with the scanning line or the data line, the interval between the scanning line or the data line, that is, the pixel pitch can be reduced, and the high definition. A liquid crystal panel can be provided.
[Brief description of the drawings]
FIG. 1 is a block diagram of various wirings and peripheral circuits formed on a TFT array substrate in an embodiment of a liquid crystal device.
2 is a plan view showing an overall configuration of the liquid crystal device of FIG. 1. FIG.
3 is a cross-sectional view showing an overall configuration of the liquid crystal device of FIG. 1. FIG.
4 is a circuit diagram of a bidirectional shift register of a scanning line driving circuit in the liquid crystal device of FIG. 1. FIG.
5A is a circuit diagram illustrating an example of a waveform control circuit and a buffer circuit of a scanning line driving circuit in the liquid crystal device of FIG. 1, and FIG. 5B is a timing chart of the operation of the scanning line driving circuit.
6A is a circuit diagram illustrating another example of the waveform control circuit and the buffer circuit of the scanning line driving circuit in the liquid crystal device of FIG. 1, and FIG. 6B is a timing chart of the operation of the scanning line driving circuit. .
FIG. 7 is a block diagram showing an arrangement example of each stage of the bidirectional shift register of the data line driving circuit and the scanning line driving circuit of Comparative Example 1 compared with the present invention.
FIG. 8 is a block diagram showing an arrangement example of each stage of a bidirectional shift register of a data line driving circuit and a scanning line driving circuit of Comparative Example 2 compared with the present invention.
FIG. 9 is a block diagram illustrating an arrangement example of each stage of the bidirectional shift register of the data line driving circuit and the scanning line driving circuit in the embodiment of the present invention.
10A is a diagram showing a circuit symbol of a transmission gate constituting the bidirectional shift register according to the first embodiment of the present invention, and FIG. 10B is a circuit showing a circuit configuration of the transmission gate of FIG. 10A. FIG.
FIG. 11 is a diagram showing a pattern of a bidirectional shift register in the first embodiment of the present invention.
FIG. 12 is a diagram showing a pattern of a waveform control circuit and a buffer circuit in the first embodiment of the present invention.
FIG. 13 is a circuit diagram of a bidirectional shift register of a scanning line driving circuit of Comparative Example 1 compared with the present invention.
14A is a diagram showing circuit symbols of a clocked inverter constituting the bidirectional shift register of Comparative Example 1 compared with the present invention, and FIG. 14B is a circuit configuration of the clocked inverter of FIG. 14A. FIG.
FIG. 15 is a diagram showing a pattern of a bidirectional shift register of Comparative Example 1 compared with the present invention.
FIG. 16 is a circuit diagram of a bidirectional shift register of a scanning line driving circuit according to a second embodiment of the present invention.
FIG. 17 is a diagram showing an example of a bidirectional shift register pattern according to the second embodiment of the present invention.
FIG. 18 is a diagram showing another example of a bidirectional shift register pattern according to the second embodiment of the present invention.
19A is a plan view of pixels constituting a screen display region of a liquid crystal panel provided in the liquid crystal device, and FIG. 19B is a cross-sectional view taken along line A-A ′ of FIG.
20A is a plan view showing a configuration of a TFT constituting a scanning line driving circuit or a data line driving circuit provided in the liquid crystal device, and FIG. 20B is a cross-sectional view taken along line BB ′ in FIG. It is sectional drawing.
FIG. 21 is a block diagram showing a schematic configuration of an embodiment of an electronic apparatus according to the present invention.
FIG. 22 is a cross-sectional view showing a liquid crystal projector as an example of an electronic apparatus.
FIG. 23 is a front view showing a personal computer as another example of an electronic apparatus.
FIG. 24 is a perspective view showing a liquid crystal device using TCP as an example of an electronic apparatus.
[Explanation of symbols]
1 ... TFT array substrate
2 ... Counter substrate
10 ... LCD panel
11: Pixel electrode
21 ... Common electrode
23 ... Light shielding layer
30 ... TFT
31 ... Scanning line (gate electrode)
32 ... Semiconductor layer
32d ... High concentration source region
32e ... High concentration drain region
33 ... Gate insulating layer
35 ... Data line (source electrode)
37, 38 ... contact holes
41. First interlayer insulating layer
42. Second interlayer insulating layer
50 ... Liquid crystal layer
52 ... Sealing material
53.
60 ... TFT
61 ... Gate electrode
62 ... Semiconductor layer
62d ... High concentration source region
62e ... High concentration drain region
63 ... Gate insulating layer
64 ... Source electrode
65 ... Drain electrode
66 ... Contact hole
101: Data line driving circuit
102 ... Mounting terminal (external input / output terminal)
111 ... Bidirectional shift register
112a ... Waveform control circuit
112b ... Buffer circuit
114-121 ... Transmission gate
150 to 157 ... N-channel TFT
200 ... Liquid crystal device
201 ... inspection circuit
301: Sampling circuit
302 ... TFT

Claims (5)

A plurality of data lines to which image signals are supplied, a plurality of scanning lines to which scanning signals are supplied, and a plurality of data lines and a plurality of scanning lines are provided in a pixel region on the substrate in correspondence with the intersection of the plurality of data lines and the plurality of scanning lines. A drive circuit for an electro-optical device comprising a plurality of switching means and a pixel electrode provided corresponding to the switching means,
A shift register for supplying a control signal for supplying the image signal and the scanning signal to the data line and the scanning line, respectively, and at least one of the data line driving means and the scanning line driving means provided on the substrate; Prepared,
At least one of the shift register of the data line drive circuit or the scanning line drive means are bidirectional shift register transfer direction of rolling transmission signal is bidirectional,
Each stage of the bidirectional shift register is synchronized with a clock signal and a transfer direction control unit that limits the transfer direction of a transfer signal input from the preceding stage of each stage to a predetermined direction based on the direction control signal. A transfer signal generation unit that generates a transfer signal of each stage based on the transfer signal input from the preceding stage ,
The transfer signal generator at each stage of the bidirectional shift register is
A first transmission gate that captures a transfer signal input from the preceding stage by the transfer direction control unit;
A first inverter to which a transfer signal taken in by the first transmission gate is input and a second inverter to which an output of the first inverter is input;
A second transmission gate that performs feedback of the transfer signal of each stage output from the second inverter to the first inverter;
A driving circuit for an electro-optical device, wherein the distance from each stage of the bidirectional shift register to the pixel region is equal . A plurality of data lines to which image signals are supplied, a plurality of scanning lines to which scanning signals are supplied, and a plurality of data lines and the plurality of scanning lines are provided in a pixel region on the substrate in correspondence with the intersection of the plurality of data lines and the plurality of scanning lines. A drive circuit for an electro-optical device comprising a plurality of switching means and a pixel electrode provided corresponding to the switching means,
  Control signals for supplying the image signal and scanning signal to the data line and scanning line, respectively.
A shift register for supplying a signal, and includes at least one of a data line driving means and a scanning line driving means provided on the substrate,
  The shift level of at least one of the data line driving means and the scanning line driving means.
The register is a bidirectional shift register in which the transfer direction of the transfer signal is bidirectional.
  Each stage of the bidirectional shift register is synchronized with a clock signal and a transfer direction control unit that restricts a transfer direction of a transfer signal input from the previous stage of each stage to a predetermined direction based on the direction control signal. A transfer signal generation unit that generates a transfer signal of each stage based on the transfer signal input from the previous stage,
  The transfer signal generator at each stage of the bidirectional shift register is
  A first thin film transistor of one conductivity type of N-channel type and P-channel type, which is connected to the transfer direction control unit and takes in a transfer signal input from the previous stage;
  A first inverter to which a transfer signal taken in by the first thin film transistor is input, and a second inverter to which an output of the first inverter is input;
  A second thin film transistor of one conductivity type of N-channel type and P-channel type that performs feedback of the transfer signal of each stage output from the second inverter to the first inverter;
  A driving circuit for an electro-optical device, wherein distances from each stage of the bidirectional shift register to the pixel region are equal to each other. 3. The drive circuit for an electro-optical device according to claim 1, wherein the scanning line driving unit is provided at both ends of the scanning line, and each scanning line driving unit is a bidirectional shift register. Electro-optical apparatus comprising the driving circuit of the electro-optical device according to any one of claims 1 to 3. An electronic apparatus comprising the electro-optical device according to claim 4 .

Images