JP4352636B2 - Data line driving circuit, scanning line driving circuit, electro-optical panel, and electronic device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention , Data line drive circuit , The present invention relates to a scanning line driving circuit, an electro-optical panel, and an electronic apparatus.
[0002]
[Prior art]
An active matrix liquid crystal panel is mainly filled between an element substrate in which switching elements are provided on each of the pixel electrodes arranged in a matrix, a counter substrate on which a color filter or the like is formed, and the two substrates. Liquid crystal. In such a configuration, when a scanning signal is applied to the switching element via the scanning line, the switching element becomes conductive. In this conductive state, when an image signal is applied to the pixel electrode via the data line, a predetermined charge is accumulated in the liquid crystal layer between the pixel electrode and the counter electrode (common electrode).
[0003]
Even after the charge accumulation, even if the switching element is turned off, the resistance of the liquid crystal layer is sufficiently high, so that the charge accumulation in the liquid crystal layer is maintained. Therefore, the charge can be accumulated in the liquid crystal layer of each pixel in a part of the period. First, the scanning line driving circuit sequentially selects each scanning line, and second, the scanning line selection period. In the configuration, one or a plurality of data lines are sequentially selected by the data line driving circuit, and third, a plurality of scanning lines and data lines are provided by sampling and supplying the image signal to the selected data lines. A time-division multiplex drive common to the pixels is possible.
[0004]
In such a liquid crystal panel, it is necessary to reduce the pixel pitch in order to display a high-definition image. For this purpose, it is necessary to improve the degree of integration between the scanning line driving circuit and the data line driving circuit in accordance with the pixel pitch. Here, the scanning line driving circuit and the data line driving circuit are generally composed of a shift register circuit and a buffer circuit, respectively.
[0005]
For example, the buffer circuit in the data line driving circuit is configured by connecting inverters INV1 and INV2 in series as shown in the left part of FIG. In the inverter INV2, as shown in the center portion of FIG. 16, p-channel TFTs P2 to P5 connected in parallel and n-channel TFTs N2 to N5 connected in parallel are used. In general, since the output current of the inverter depends on the gate width of the TFT, the inverter INV2 can supply a large output current.
[0006]
The structure (pattern layout) of the buffer circuit is shown on the right side of FIG. In general, in designing an integrated circuit, the entire integrated circuit is divided into partial functions, a small-scale circuit structure for realizing each function is designed, and these are combined to determine one integrated circuit structure. A small circuit structure having a certain function is called a cell. The structure of the buffer circuit shown in FIG. 16 is a kind of cell used in the data line driver circuit.
A plurality of such buffer circuits are arranged in the output stage of the data line driving circuit. Therefore, the output stage of the data line driving circuit can be configured by simply arranging a plurality of buffer circuits shown in the drawing.
[0007]
Incidentally, in the buffer circuit shown in FIG. 16, the positive power supply line Ld and the negative power supply line Ls can be reversely arranged to adopt the structure shown in FIG. In other words, a certain circuit can be realized by a mirror-symmetric structure with the power supply line as the axis of symmetry. Since each buffer circuit constituting the output stage of the data line driver circuit only needs to have the same function, the structure shown in FIG. 16 or the structure shown in FIG. 17 may be used.
[0008]
Focusing on this point, when the power supply line is shared by adjacent buffer circuits, the output stage of the data line driving circuit has the structure shown in FIG. In this wiring structure, the buffer circuit shown in FIG. 16 and the buffer circuit shown in FIG. 17 are alternately arranged. Thereby, the positive power supply line and the negative power supply line can be shared, the degree of integration of the data line driving circuit can be improved, and the pixel pitch can be reduced.
[0009]
[Problems to be solved by the invention]
Incidentally, a latch circuit or the like is used for a shift register used in a data line driving circuit or a scanning line driving circuit. For this reason, there is a case where different circuits such as a buffer circuit and a latch circuit are desired to be arranged in parallel for the convenience of circuit arrangement.
[0010]
However, since the elements constituting the latch circuit are different from the elements constituting the buffer circuit, the elements constituting each cell are asymmetric even if the buffer circuit and the latch circuit are arranged in parallel. Therefore, unlike the buffer circuits described above, a mirror-symmetric structure with the power supply line as the axis of symmetry cannot be achieved.
[0011]
Thus, when sharing a power supply line between cells having different functions, there are the following problems. Each cell has a TFT connected to a power supply line, and these TFTs have a semiconductor island and a power supply line connected by a contact hole, but since each cell is designed independently, a semiconductor island and a contact hole are connected. Is different for each cell. Therefore, semiconductor islands and contact holes cannot be shared between cells having different functions.
[0012]
Furthermore, if a semiconductor island is formed freely in a cell and an adjacent cell, the semiconductor island is close to the lower part of the power supply line, and if the semiconductor island is placed beyond the processing accuracy, both of them are indefinitely shaped. May be connected in some parts. Originally, when semiconductor islands that should be formed independently are connected, there is a problem that even if there is no functional problem, it is considered that a defect has occurred in the process step in the substrate inspection.
[0013]
In addition, in the data line driving circuit and the scanning line driving circuit, it is desirable to improve the degree of integration and reduce the pixel pitch, but this has certain limitations.
The present invention has been made in view of the above-described circumstances, and provides a structure in which a semiconductor island and a contact hole are shared between cells having different functions, and is not regarded as defective in an integrated circuit inspection process. The purpose is to reduce the pixel pitch.
[0019]
[Means for Solving the Problems]
In the data line driving circuit of the present invention, a plurality of scanning lines, a plurality of data lines, pixel electrodes and switching elements arranged in a matrix corresponding to the intersections of the scanning lines and the data lines, Formed in an electro-optic panel A data line driving circuit for driving the data line, the first cell having a plurality of first semiconductor elements, and a circuit configuration different from the first cell, adjacent to the first cell, A second cell having a second semiconductor element; and a power supply line that is formed at a boundary between the first cell and the second cell and supplies a power supply voltage, and includes at least one of the plurality of first semiconductor elements. One semiconductor element and one semiconductor element of the plurality of second semiconductor elements are provided on a common semiconductor island, the common semiconductor island has an asymmetric shape with the boundary as an axis, and The common semiconductor island is provided with a common contact hole connected to the power supply line, and a power supply voltage is connected to the first cell and the first cell through the common contact hole. 2 Having an integrated circuit structure, each of which is powered to the Le It is characterized by that. In addition, it is preferable that an interval from a boundary between a certain first cell and a second cell to a boundary between the next first cell and the second cell matches the interval between the data lines. According to the present invention, the interval between the data lines can be narrowed by sharing the cells as described above.
[0020]
In the scanning line driving circuit of the present invention, a plurality of scanning lines, a plurality of data lines, pixel electrodes and switching elements arranged in a matrix corresponding to the intersections of the scanning lines and the data lines, Formed in an electro-optic panel A scanning line driving circuit for driving the scanning line, the first cell having a plurality of first semiconductor elements, and a circuit configuration different from the first cell, adjacent to the first cell, A second cell having a second semiconductor element; and a power supply line that is formed at a boundary between the first cell and the second cell and supplies a power supply voltage, and includes at least one of the plurality of first semiconductor elements. One semiconductor element and one semiconductor element of the plurality of second semiconductor elements are provided on a common semiconductor island, the common semiconductor island has an asymmetric shape with the boundary as an axis, and The common semiconductor island is provided with a common contact hole connected to the power supply line, and a power supply voltage is connected to the first cell and the first cell through the common contact hole. 2 cells Having an integrated circuit structure, each of which is powered to It is characterized by that. In this case, it is preferable that the interval from the boundary between a certain first cell and the second cell to the boundary between the next first cell and the second cell matches the interval between the scanning lines. According to the present invention, it is possible to reduce the interval between the scanning lines by sharing the cells as described above.
[0021]
In the electro-optical panel of the present invention, , At least one of the above-described data line driving circuit and the above-described scanning line driving circuit is provided. According to the present invention, the pixel pitch can be narrowed.
[0022]
Furthermore, an electronic apparatus according to the present invention includes the above-described electro-optical panel, and includes, for example, a projector, a mobile personal computer, a PDA, a mobile phone, and the like.
[0023]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
<1. Overall configuration of electro-optical device>
First, the electro-optical device according to the embodiment will be described taking a liquid crystal display device as an example. FIG. 1 is a block diagram showing an electrical configuration of the liquid crystal display device. As shown in this figure, the liquid crystal display device includes a liquid crystal panel 100, a timing generator 200, and an image signal processing circuit 300. Among these, the timing generator 200 outputs a timing signal used in each unit.
[0024]
The image signal processing circuit 300 generates the image signal VID and supplies it to the liquid crystal panel 100. At this time, the image signal processing circuit 300 inverts the image signal VID as necessary. As for whether to invert or not, in general, whether the data signal application method is (1) polarity inversion in units of scanning lines, (2) polarity inversion in units of data lines, or (3) polarity in units of pixels It is determined depending on whether it is inversion or (4) polarity inversion in pixel units, and the inversion period is set to one horizontal scanning period or dot clock period, or one vertical scanning period. Note that polarity reversal in the present embodiment refers to reversing the voltage level alternately between positive polarity and negative polarity with reference to the amplitude center potential of the image signal.
[0025]
<2. Electrical configuration of LCD panel>
Next, the electrical configuration of the liquid crystal panel 100 will be described. As will be described later, the liquid crystal panel 100 has a configuration in which an element substrate and a counter substrate are pasted with their electrode formation surfaces facing each other. Among them, in the element substrate, a plurality of scanning lines 112 are formed in parallel along the X direction in FIG. 1, and a plurality of data are paralleled along the Y direction orthogonal thereto. A line 114 is formed. The gate electrode of the TFT 116 is connected to the scanning line 112 at each intersection of the scanning line 112 and the data line 114. Further, the source electrode of the TFT 116 is connected to the data line 114, and the drain electrode of the TFT 116 is connected to the pixel electrode 118.
[0026]
Each pixel includes a pixel electrode 118, a common electrode formed on a counter substrate described later, and a liquid crystal sandwiched between these electrodes. Therefore, each pixel is arranged in a matrix corresponding to each intersection of the scanning line 112 and the data line 114. That is, one pixel is formed in a region surrounded by the scanning line 112 and the data line 114. The interval between adjacent scanning lines 112 coincides with the length of the pixel in the Y direction, and this is referred to as a Y direction pixel pitch PY. On the other hand, the interval between adjacent data lines 114 coincides with the length of the pixel in the X direction, and this is referred to as the X direction pixel pitch PX.
In addition, for each pixel, a storage capacitor (not shown) may be formed in parallel with the liquid crystal sandwiched between the pixel electrode 118 and the common electrode when viewed electrically.
[0027]
As will be described later, the data line driving circuit 130, the sampling circuit 140, and the scanning line driving circuit 150 are formed on the opposing surface of the element substrate and in the periphery of the display area. The active elements of these circuits are all formed by a combination of a p-channel TFT and an n-channel TFT. Therefore, it can be formed by a manufacturing process common to the TFT 116 used for the pixel (for example, a process temperature of about 1000 ° C.), which is advantageous in terms of integration, manufacturing cost, element uniformity, and the like.
[0028]
Here, among the driving circuits, the data line driving circuit 130 includes a shift register, shifts the X start pulse SPX based on the clock signal CLX from the timing generator 200 and its inverted clock signal CLXINV, and performs the sampling signal S1. ~ Sn is generated.
[0029]
The sampling circuit 140 samples and supplies the image signal VID to each data line 114 according to the sampling signals S1 to Sn. Specifically, in the sampling circuit 140, a switch 141 made of TFT is provided at one end of each data line 114, and a source electrode of each switch 141 is connected to a signal line to which an image signal VID is supplied. The drain electrode of each switch 141 is connected to one data line 114. Further, the gate electrode of each switch 141 is connected to one of signal lines to which the sampling signals S1 to Sn are supplied.
[0030]
The scanning line driving circuit 150 includes a shift register, shifts the Y start pulse SPY based on the clock signal CLY from the timing generator 200 and its inverted clock signal CLYINV, and sends the scanning signals Y1 to Ym to each scanning line 112. On the other hand, it outputs sequentially.
[0031]
<3. Mechanical configuration of LCD panel>
Next, the mechanical configuration of the liquid crystal panel 100 according to the above-described electrical configuration will be described with reference to FIGS. Here, FIG. 2 is a perspective view showing a configuration of the liquid crystal panel 100, and FIG. 3 is a sectional view taken along the line ZZ ′ in FIG.
[0032]
As shown in these drawings, the liquid crystal panel 100 is configured so that the element substrate 101 and the counter substrate 102 are opposed to each other with a predetermined gap between the element substrate 101 and the counter substrate 102 with a sealant 104 mixed with the spacer 103. It is what was pasted together. The element substrate 101 is made of a transparent insulating substrate such as glass. A silicon thin film is formed on the substrate, and a TFT and a pixel electrode 118 are formed on the thin film. On the other hand, the counter substrate 102 is formed of a transparent flat plate such as glass.
[0033]
The liquid crystal panel 100 has a structure in which a liquid crystal 105 as an electro-optical material is sealed in a gap between the element substrate 101 and the counter substrate 102. Note that the sealant 104 is formed along the periphery of the counter substrate 102, but a part thereof is opened to enclose the liquid crystal 105. For this reason, after the liquid crystal 105 is sealed, the opening is sealed with the sealing material 106.
[0034]
Here, the sampling circuit 140 and the data line driving circuit 130 described above are formed on the opposite surface of the element substrate 101 and on the outer side of the sealing material 104. Further, a plurality of connection electrodes 107 are formed on this side, and various signals from the timing generator 200 and the image signal processing circuit 300 are supplied thereto. Two scanning line driving circuits 150 are formed on two sides adjacent to the one side. Note that if the delay of the scanning signal supplied to the scanning line 112 does not cause a problem, a configuration in which the scanning line driving circuit 150 is formed on only one side may be employed.
[0035]
On the other hand, the common electrode 108 of the counter substrate 102 is electrically connected to the element substrate 101 by a conductive material provided in at least one of the four corners of the bonding portion with the element substrate 101. In addition, the counter substrate 102 is provided with color filters arranged in a stripe shape, a mosaic shape, a triangle shape, or the like according to the use of the liquid crystal panel 100, and secondly, for example, chromium. A black matrix such as resin black in which carbon, titanium, or the like is dispersed in a photoresist is provided, and third, a backlight for irradiating the liquid crystal panel 100 with light is provided. Particularly in the case of color light modulation, a black matrix is provided on the counter substrate 102 without forming a color filter.
[0036]
In addition, the opposing surfaces of the element substrate 101 and the counter substrate 102 are each provided with an alignment film or the like that is rubbed in a predetermined direction, and a polarizing plate (not shown) corresponding to the alignment direction on each back side. Are provided respectively. However, if a polymer dispersion type liquid crystal dispersed as fine particles in a polymer is used as the liquid crystal 105, the above-described alignment film, polarizing plate, and the like are not required. As a result, the light utilization efficiency is increased. This is advantageous in terms of reducing power consumption.
[0037]
Instead of forming part or all of the peripheral circuits such as a drive circuit on the element substrate 101, for example, a driving IC chip mounted on a film using a TAB (Tape Automated Bonding) technique is used. The driving IC chip itself may be connected to the element substrate 101 by using a COG (Chip On Grass) technique, through an anisotropic conductive film provided at a predetermined position. It is good also as a structure electrically and mechanically connected to a predetermined position via an anisotropic conductive film.
[0038]
<4. Structure of Scan Line Driver Circuit and Data Line Driver Circuit>
As described above, the data line driving circuit 130 and the scanning line driving circuit 150 include a shift register and a buffer circuit. The shift register includes a latch circuit. Further, the data line driving circuit 130 and the scanning line driving circuit 150 are configured by combining various cells that are logic blocks including a plurality of elements.
[0039]
Here, as an example of the cell, the first cell C1 constituting the buffer circuit and the second cell C2 constituting the latch circuit are taken up. FIG. 4 shows a circuit diagram of the buffer circuit, a plan view showing the structure of the first cell C1, and an explanatory diagram showing the positional relationship of the contact holes. As shown in this figure, on the element substrate 101, semiconductor islands 401 to 405 are formed between a positive power supply line Ld and a negative power supply line Ls for supplying a positive power supply voltage Vdd and a negative power supply voltage Vss. These semiconductor islands 401 to 405 extend to the lower part of the positive power supply line Ld and the positive power supply line Ls. The semiconductor islands 401 to 405 are connected to the positive power supply line Ld through the contact holes 411 to 420, and are connected to the positive power supply line Ls through the contact holes 421 to 430. Further, the semiconductor islands 401 to 405 form a TFT source region, drain region, and channel region.
[0040]
The semiconductor island 401 and the gate electrode 406 constitute a p-channel TFT P1 and an n-channel TFT N1. The wiring 408 connects the drain of the p-channel TFT P1 and the source of the n-channel TFT N1 to the gate electrode 409.
[0041]
Further, the semiconductor islands 402 to 405 and the gate electrode 409 constitute p-channel TFTs P2 to P5 and n-channel TFTs N2 to N5. The gate electrode 409 is common to the p-channel TFTs P2 to P5 and the n-channel TFTs N2 to N5. Therefore, the p-channel TFTs P2 to P5 are connected in parallel, and the n-channel TFTs N2 to N5 are also connected in parallel. Then, the input signal inA is supplied through the wiring 407, while the output signal outA is output through the wiring 410.
[0042]
Here, the contact holes 411 to 420 and 421 to 430 are arranged at positions that are a natural number multiple, assuming that their minimum distance is A. For example, the distance between the contact hole 421 and the contact hole 422 is “A”, and the distance between the contact hole 422 and the contact hole 423 is “3A”. In other words, the contact holes 411 to 430 formed on the positive power supply line Ld and the positive power supply line Ls are arranged on parallel virtual lines L1 to L21 having an interval A as shown in the figure. Is done.
[0043]
Next, the latch circuit will be described. FIG. 5 is a block diagram of the latch circuit. As shown in the figure, the latch circuit includes a transfer gate G, a clocked inverter INVC, and an inverter INVD, and is supplied with a latch signal LAT and an inverted latch signal LATB obtained by inverting the latch signal LAT.
[0044]
First, the transfer gate G is configured by connecting a p-channel TFT P6 and an n-channel TFT N6 in parallel as shown in FIG. The transfer gate G is turned on when the latch signal LAT is at the H level, supplies the input signal inB to the inverter INVD, and turns off when the latch signal LAT is at the L level.
[0045]
Next, the clocked inverter INVC is configured by connecting p-channel TFTs P7 and P8 and n-channel TFTs N7 and N8 in series between the positive power supply line Ld and the positive power supply line Ls as shown in FIG. . Therefore, the clocked inverter INVD functions as an inverter when the latch signal LAT is at L level, and sets the output terminal to a high impedance state when the latch signal LAT is at H level.
[0046]
Therefore, when the latch signal LAT is at the H level, the input signal inB is supplied to the inverter INVD via the transfer gate G, and the output signal outB obtained by inverting the input signal inB is output. On the other hand, when the latch signal LAT is at L level, the transfer gate G is turned off, so that the input signal inB is not supplied to the inverter INVD. In this case, since the clocked inverter INVC becomes active, the logic level of the output signal outB is held by the clocked inverter INVC and the inverter INVD.
[0047]
FIG. 7 shows a circuit diagram of the latch circuit, a plan view showing the structure of the second cell C2, and an explanatory diagram showing the positional relationship of the contact holes. As shown in the figure, the second cell C <b> 2 includes semiconductor islands 501 to 505. Among these, the semiconductor islands 501 to 503 extend to the lower part of the positive power supply line Ld and the negative power supply line Ls. Semiconductor islands 501 and 502 are connected to negative power supply line Ls through contact holes 514 to 516. Semiconductor islands 502 and 503 are connected to positive power supply line Ld through contact holes 517 to 519.
[0048]
The semiconductor island 504 and the gate electrode 506 form a p-channel TFT P 6, the semiconductor island 505 and the gate electrode 507 form an n-channel TFT N 6, the semiconductor island 501 and the gate electrodes 506 and 510 form an n-channel TFT N 7 and N 8, and the semiconductor island 502 and the gate electrode 512. Thus, n-channel TFT N9 and p-channel TFT P9 are formed, and P-channel TFTs P7 and P8 are formed by semiconductor island 503 and gate electrodes 507 and 510, respectively.
[0049]
Here, the contact holes 514 to 519 are arranged at a position that is a natural number times the minimum interval A in the first cell C1. For example, the distance between the contact hole 518 and the contact hole 519 is “A”, and the distance between the contact hole 518 and the contact hole 517 is “4A”. In other words, the contact holes 514 to 519 formed on the positive power supply line Ld and the negative power supply line Ls are arranged on parallel virtual lines L1 to L21 having an interval A as shown in the figure. Is done.
[0050]
In the present embodiment, the first cell C1 and the second cell C2 are alternately arranged to constitute a part of the data line driving circuit 130 and the scanning line driving circuit 150. Various sharings are made between the first cell C1 and the second cell C2. 8 is a plan view showing a structure in which the first cell C1 and the second cell C2 are arranged, and FIG. 9 is a cross-sectional view taken along the line WW ′ in FIG.
[0051]
First, the sharing is examined by focusing on the first cell C1 at the left end and the second cell C2 at the center. First, the semiconductor island 403 and the semiconductor island 501 are integrally formed as a common semiconductor island A1, and the semiconductor island 405 and the semiconductor island 502 are integrally formed as a common semiconductor island A2. Second, the negative power supply line Ls is shared between these cells. Third, the contact hole CH1 is a common use of the contact hole 425 of the first cell C1 and the contact hole 514 of the second cell C2, and the contact holes CH2 and CH3 are the contact hole 429 of the first cell C1 and 430 and the contact holes 515 and 516 of the second cell C2 are shared.
[0052]
That is, the negative power supply line Ls is supplied with the negative power supply voltage Vss to the contact holes 421 to 424, 427 and 428 for supplying the negative power supply voltage Vss only to the first cell C1, and the first cell C1 and the second cell C2. Contact holes CH1 to CH3 and 426 are formed. That is, since the contact holes CH1 to CH3 and 426 are shared by the first cell C1 and the second cell C2, they function as a common contact hole. The contact hole 426 is originally used to supply the negative power supply voltage Vss only to the first cell C1, but as a result of the shared use of the contact hole CH1, the negative power supply voltage Vss is also supplied to the second cell C2. Is.
[0053]
Now, the relationship between the contact hole CH1 and the common semiconductor island A1 will be described with reference to FIG. As shown in this figure, a common semiconductor island A1 made of a polysilicon film is formed on the element substrate. The high-concentration impurity region 20 of the common semiconductor island A1 is formed by doping a group III element dopant such as Al (aluminum) or B (boron) from above the polysilicon film by ion implantation or the like. On the other hand, the high-concentration impurity region 30 of the common semiconductor island A1 is formed by doping a dopant of a group V element such as Sb (antimony), As (arsenic), or P (phosphorus) by ion implantation or the like from above the polysilicon film. It is formed.
[0054]
A first interlayer insulating film 40, gate electrodes 409 and 506, and a second interlayer insulating film 50 are stacked on the common semiconductor island A1. In addition, contact holes ch1 to ch4 are provided in the first interlayer insulating film 40, and electrodes 51 to 53 are formed thereon. The reason why the contact holes ch1 to ch4 are formed without forming the contact holes directly reaching the semiconductor layer A1 from the positive and negative power supply lines Ld and Ls and the wiring 410 constituting the third layer as described above is as follows. That is, since the film thickness of the first interlayer insulating film 40 is extremely thin compared to the film thickness of the second interlayer insulating film 50 and the semiconductor island A1, an attempt is made to form a contact hole that directly extends from the third layer to the semiconductor layer A1. This is because it is difficult to precisely adjust the depth of the contact hole, and the contact hole may penetrate the semiconductor island A1. On the other hand, when a contact hole is formed in the first interlayer insulating film 40 and the second interlayer insulating film 50 as in this embodiment, it is possible to reliably connect without such inconvenience.
[0055]
In the p-channel TFT P3, the source region 21 in the high concentration impurity region 20 is connected to the source electrode 51 through the contact hole ch1, and the source electrode 51 is further connected to the positive power supply line Ld through the contact hole 415. ing. The drain region 23 of the p-channel TFT P3 and the source region 31 of the n-channel TFT N3 are connected to the common electrode 52 through contact holes ch2 and ch3, and the common electrode 52 is connected to the wiring 410 through the contact hole 431. Yes. The gate of the p-channel TFT P3 is formed by the gate region 22 and the gate electrode 409, while the gate of the n-channel TFT N3 is formed by the gate region 32 and the gate electrode 409.
[0056]
Next, the source region 33 in the high concentration impurity region 30 functions as a common source for the n-channel TFTs N3 and N8. The source region 33 is connected to the source electrode 53 via the contact hole ch4, and further connected to the negative power supply line Ls via the contact hole CH1. That is, the contact hole CH1 is used to supply the negative power supply voltage Vss to the n-channel TFT N3 of the first cell C1 and the n-channel TFT N8 of the second cell C2.
[0057]
Next, returning to FIG. 8, focusing on the second cell C2 at the center and the first cell C1 at the right end, sharing is considered. First, the semiconductor island 503 and the semiconductor island 404 are integrally formed as a common semiconductor island A3, and the semiconductor island 405 and the semiconductor island 502 are integrally formed as a common semiconductor island A2. Second, the positive power supply line Ld is shared between these cells. Third, the contact hole CH4 is a common use of the contact hole 517 of the second cell C2 and the contact hole 417 of the first cell C1, and the contact holes CH5 and CH6 are the contact hole 518 of the second cell C2 and 519 and the contact holes 419 and 420 of the first cell C1 are shared.
[0058]
That is, the contact holes 411 to 416 for supplying the positive power supply voltage Vdd only to the first cell C1 and the contact holes CH4 to CH4 for supplying the positive power supply voltage Vdd to the first cell C1 and the second cell C2 are connected to the positive power supply line Ld. CH6 and 418 are formed. Note that the contact hole 418 is originally used to supply the positive power supply voltage Vss only to the first cell C1, but as a result of sharing the contact hole CH4, the positive power supply voltage Vdd is also supplied to the second cell C2. Is.
[0059]
As described above, in this embodiment, the arrangement of the contact holes 411 to 420 and 517 to 519 formed in the positive power supply line Ld in various cells is set to be a natural number multiple of the minimum interval A, and the negative power supply line Since the arrangement of the contact holes 421 to 430 and 514 to 516 formed in Ls is set to be a natural number multiple of the minimum interval A, between the adjacent first cell C1 and second cell C2, the semiconductor island, Power line and contact hole can be shared.
[0060]
As a result, the degree of integration of the data line driving circuit 130 and the scanning line driving circuit 150 can be improved. As the degree of integration increases, the X-direction pixel pitch PX and the Y-direction pixel pitch PY can be reduced. Here, an example in which the structure of the first cell C1 and the second cell C2 described above is applied to the data line driving circuit 130 will be described.
[0061]
FIG. 10 is a conceptual diagram for explaining the relationship between the first cell C1 and the second cell C2 and the X-direction pitch PX. As shown in this figure, the data line driving circuit 130 includes a plurality of unit circuits U. Each unit circuit U includes a first cell C1 and a second cell C2. When viewed as the entire data line driving circuit 130, the first cells C1 and the second cells C2 are arranged alternately.
[0062]
An output terminal of the data line driving circuit 130 is connected to each data line 114 via each switch 141 constituting the sampling circuit 140. Accordingly, the distance from the left end of the first cell C1 to the right end of the second cell C2 matches the X-direction pixel pitch PX that is the interval between the adjacent data lines 114. As described above, since the positive power supply line Ld and the negative power supply line Ls are shared between the first cell C1 and the second cell C2, the pixel pitch PX in the X direction can be reduced. On the other hand, the Y-direction pixel pitch PY can be reduced by sharing the scanning line driving circuit 150 as described above. As a result, the liquid crystal panel 100 can display a high-definition image by narrowing the pixel pitch in the X direction and the Y direction.
[0063]
<5. Modification>
The present invention is not limited to the above-described embodiment, and for example, the following modifications are possible.
(1) In the above-described embodiment, a plurality of semiconductor islands are formed below the positive and negative power supply lines Ld and Ls. However, if the minimum distance A between contact holes is set narrow, the semiconductor islands are close to each other. Will do. Since there is a certain limit to the accuracy of the process of forming semiconductor islands, adjacent semiconductor islands may be partially connected. In the inspection of the element substrate, if a semiconductor island that should be formed independently is connected, it is considered that a defect has occurred in the process step.
[0064]
However, since the positive power supply voltage Vdd or the negative power supply voltage Vss is supplied to the semiconductor island below the positive and negative power supply lines Ld and Ls, there is no problem even if the semiconductor island is connected. Therefore, a semiconductor island in which semiconductor islands formed under the positive and negative power supply lines Ld and Ls are connected in advance may be formed under the power supply lines Ld and Ls.
By the way, depending on the circuit configuration, it may be desired to form a P-channel semiconductor island and an N-channel semiconductor island under a certain power supply line. In such a case, it is not possible to integrally form semiconductor islands of different types of semiconductors. Therefore, a plurality of semiconductor islands divided into the entire lower portion of the power supply line may be formed, and the semiconductor types may be different in adjacent semiconductor islands.
[0065]
(2) In the above-described embodiment, the data line driving circuit 130 and the scanning line driving circuit 150 may be arranged below the seal portion. FIG. 11 is a cross-sectional view of the liquid crystal panel 100 in which the data line driving circuit 130 is disposed below the seal portion. In the figure, a seal portion Q is a portion around the counter substrate 102 where a seal material 104 mixed with a spacer 104 is provided. Since the seal portion Q is not provided with pixels, this portion does not contribute to image display. Therefore, if the data line driving circuit 130 and the like are formed on the element substrate 101 and below the seal portion Q, the area of the element substrate 101 can be reduced and the entire liquid crystal panel 100 can be reduced in size. Become.
[0066]
Incidentally, the liquid crystal panel 100 has a configuration in which a liquid crystal 105 is sandwiched between an element substrate 101 and a counter substrate 102. On the other hand, when a contact hole is formed on the power supply line, a convex portion is formed in the vicinity of the portion. If a contact hole is formed at an arbitrary position on the power supply line and the arrangement of the contact holes is biased when viewed as the entire liquid crystal panel 100, the distance between the element substrate 101 and the counter substrate 102 is corresponding to the bias. It changes slightly. In other words, the element substrate 101 and the counter substrate 102 are close to each other in some places, and the element substrate 101 and the counter substrate 102 are separated in other places. Since the liquid crystal panel 100 performs light modulation with the liquid crystal 105 to display gradation, if the distance between the element substrate 101 and the counter substrate 102 is not uniform, display unevenness occurs and the quality of the display image deteriorates. .
[0067]
Therefore, in addition to the contact holes of the above-described embodiment, dummy contact holes CHd may be formed at the minimum interval A in the positive and negative power supply lines Ld and the negative power supply lines Ls. FIG. 12 is a plan view showing the arrangement of dummy contact holes CHd in the cell structure shown in FIG. As shown in this figure, by forming the dummy contact holes CHd, the contact holes on the positive power supply line Ld and the negative power supply line Ls are arranged at equal intervals A. As a result, the contact holes can be uniformly arranged in the seal portion Q located in the peripheral portion of the counter substrate 102, and unevenness in the peripheral portion can be eliminated and the quality of the display image can be improved.
[0068]
(3) In the above-described embodiment, the contact holes ch1 to ch4 are formed in the first interlayer insulating film 40, but the present invention is not limited to this. For example, the contact holes 415, 431, and CH1 The positive and negative power supply lines Ld and Ls and the wiring 410 may be provided directly to the semiconductor island A1. In this case, the contact holes ch1 to ch4 and the electrodes 51 to 53 can be omitted.
[0069]
(4) In addition, the element substrate 101 is constituted by a semiconductor substrate, and the switching element of the pixel and the element of the drive circuit are constituted by an insulated gate field effect transistor in which a source, a drain, and a channel are formed on the surface of the semiconductor substrate. You may do it. When the element substrate 101 is formed of a semiconductor substrate as described above, it cannot be used as a transmissive display panel. Therefore, the pixel electrode 118 is formed of aluminum or the like and used as a reflective type. Alternatively, the element substrate 101 may be a transparent substrate and the pixel electrode 118 may be a reflection type.
[0070]
Furthermore, in the above-described embodiment, the switching element of the pixel has been described as a three-terminal element typified by a TFT, but may be configured by a two-terminal element such as a diode. However, when a two-terminal element is used as a pixel switching element, the scanning line 112 is formed on one substrate, the data line 114 is formed on the other substrate, and the two-terminal element is connected to the scanning line 112 or the data line. It is necessary to form between any one of 114 and a pixel electrode. In this case, the pixel includes a two-terminal element connected in series between the scanning line 112 and the data line 114 and a liquid crystal.
[0071]
In the above-described embodiments, the active matrix type liquid crystal display device has been described as an example. However, the present invention is not limited to this, and the present invention can also be applied to a passive type using STN (Super Twisted Nematic) liquid crystal. Furthermore, as an electro-optical material, in addition to liquid crystal, an electroluminescence element or the like can be used for a display device that performs display by the electro-optical effect. That is, the present invention is applicable to all electro-optical devices having a configuration similar to that of the liquid crystal display device described above.
[0072]
<6. Electronic equipment>
Next, the case where the liquid crystal device according to the above-described embodiment and modification is applied to various electronic devices will be described.
<6-1: Projector>
First, a projector using this liquid crystal device as a light valve will be described. FIG. 13 is a plan view showing a configuration example of the projector.
[0073]
As shown in this figure, a lamp unit 1102 including a white light source such as a halogen lamp is provided inside the projector 1100. The projection light emitted from the lamp unit 1102 is separated into three primary colors of RGB by four mirrors 1106 and two dichroic mirrors 1108 arranged in the light guide 1104, and serves as a light valve corresponding to each primary color. The light enters the liquid crystal panels 1110R, 1110B, and 1110G.
[0074]
The configuration of the liquid crystal panels 1110R, 1110B, and 1110G is the same as that of the liquid crystal panel 100 described above, and is driven by R, G, and B primary color signals supplied from an image signal processing circuit (not shown). The light modulated by these liquid crystal panels enters the dichroic prism 1112 from three directions. In this dichroic prism 1112, R and B light is refracted at 90 degrees, while G light travels straight. Accordingly, as a result of the synthesis of the images of the respective colors, a color image is projected onto the screen or the like via the projection lens 1114.
[0075]
Here, paying attention to the display images by the liquid crystal panels 1110R, 1110B, and 1110G, the display image by the liquid crystal panel 1110G needs to be horizontally reversed with respect to the display images by the liquid crystal panels 1110R, 1110B.
[0076]
Note that since light corresponding to the primary colors R, G, and B is incident on the liquid crystal panels 1110R, 1110B, and 1110G by the dichroic mirror 1108, it is not necessary to provide a color filter.
[0077]
<6-2: Mobile computer>
Next, an example in which the liquid crystal panel is applied to a mobile personal computer will be described. FIG. 14 is a perspective view showing the configuration of this personal computer. In the figure, a computer 1200 includes a main body 1204 having a keyboard 1202 and a liquid crystal display unit 1206. The liquid crystal display unit 1206 is configured by adding a backlight to the back surface of the liquid crystal panel 100 described above.
[0078]
<6-3: Mobile phone>
Further, an example in which the liquid crystal panel 100 is applied to a mobile phone will be described. FIG. 15 is a perspective view showing the configuration of the mobile phone. In the figure, a cellular phone 1300 includes a plurality of operation buttons 1302 and a transmissive liquid crystal panel 1005. In the transmissive liquid crystal panel 1005, a front light is provided on the front surface as necessary.
[0079]
In addition to the electronic devices described with reference to FIGS. 13 to 15, a liquid crystal television, a viewfinder type, a monitor direct view type video tape recorder, a car navigation device, a pager, an electronic notebook, a calculator, a word processor, a work Stations, videophones, POS terminals, devices with touch panels, etc. Needless to say, the present invention can be applied to these various electronic devices.
[0080]
【The invention's effect】
As described above, according to the present invention, it is possible to share power supply lines, contact holes, etc. between cells having different functions, thereby reducing the area occupied by the integrated circuit structure. Furthermore, by applying this integrated circuit structure to a data line driver circuit or a scanning line driver circuit, it becomes possible to display a high-definition image by narrowing the pixel pitch.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an electrical configuration of a liquid crystal display device according to an embodiment of the present invention.
FIG. 2 is a perspective view showing a configuration of a liquid crystal panel 100 in the same embodiment.
FIG. 3 is a cross-sectional view taken along the line ZZ ′ in FIG.
FIG. 4 is a diagram in which a circuit diagram of a buffer circuit, a plan view showing a structure of a first cell C1, and an explanatory diagram showing a positional relationship of contact holes are shown.
FIG. 5 is a block diagram of a latch circuit.
FIG. 6 is a circuit diagram of a transfer gate G and a clocked inverter INVC used in the latch circuit.
FIG. 7 is a circuit diagram of a latch circuit, a plan view showing the structure of a second cell C2, and an explanatory diagram showing the positional relationship of contact holes.
FIG. 8 is a plan view showing a structure in which a first cell C1 and a second cell C2 are arranged.
9 is a cross-sectional view taken along line WW ′ in FIG.
FIG. 10 is a conceptual diagram for explaining the relationship between the first cell C1 and the second cell C2 and the X-direction pitch PX.
FIG. 11 is a cross-sectional view of the liquid crystal panel 100 in which the data line driving circuit 130 is disposed below the seal portion.
12 is a plan view showing the arrangement of dummy contact holes CHd in the cell structure shown in FIG.
FIG. 13 is a cross-sectional view of a video projector as an example of an electronic apparatus to which a liquid crystal device is applied.
FIG. 14 is a perspective view illustrating a configuration of a personal computer as an example of an electronic apparatus to which a liquid crystal device is applied.
FIG. 15 is a perspective view illustrating a configuration of a mobile phone as an example of an electronic apparatus to which a liquid crystal device is applied.
FIG. 16 is a diagram showing a configuration of a conventional buffer circuit.
FIG. 17 is a diagram illustrating another structure example of the buffer circuit.
FIG. 18 is a diagram illustrating a structure example of an output stage of a data line driving circuit.
[Explanation of symbols]
C1 …… First cell
C2 …… Second cell
Ld, Ls: Positive power line, negative power line
A1-A3 ... Common semiconductor island
CH1-CH6 …… Common contact hole
112 ... Scanning line
114 …… Data line
116 …… TFT (switching element)
100 …… Liquid crystal panel (electro-optical panel)
130... Data line driving circuit
150... Scanning line driving circuit.

Claims (12)

The data line is formed in an electro-optical panel having a plurality of scanning lines, a plurality of data lines, and pixel electrodes and switching elements arranged in a matrix corresponding to intersections of the scanning lines and the data lines. A data line driving circuit for driving
A first cell having a plurality of first semiconductor elements;
A second cell having a different circuit configuration from the first cell and adjacent to the first cell and having a plurality of second semiconductor elements;
A power line formed at a boundary between the first cell and the second cell and supplying a power voltage;
Have
At least one semiconductor element of the plurality of first semiconductor elements and one semiconductor element of the plurality of second semiconductor elements are provided on a common semiconductor island,
The common semiconductor island has an asymmetric shape with the boundary as an axis, and is provided so as to intersect the power supply line.
The common semiconductor island is provided with a common contact hole connected to the power line,
A power supply voltage is supplied to the first cell and the second cell through the common contact hole.
A data line driving circuit having an integrated circuit structure . From the boundary between a certain first cell and the second cell, distance to the boundary with the next first cell and the second cell, according to claim 1, characterized in that coincides with the spacing of the respective data lines Data line driving circuit. Either the first cell or the second cell has an individual semiconductor island having a region overlapping with the power supply line,
The data line driving circuit according to claim 1, further comprising an individual contact hole that connects the individual semiconductor island and the power supply line . The data line driving circuit according to claim 3 , wherein the interval between the common contact hole and the individual contact hole is a natural number multiple of a predetermined reference distance . The data line driving circuit according to claim 4 , wherein dummy contact holes are arranged at intervals of the reference distance in addition to the common contact holes or the individual contact holes . The scanning line is formed in an electro-optical panel having a plurality of scanning lines, a plurality of data lines, and pixel electrodes and switching elements arranged in a matrix corresponding to intersections of the scanning lines and the data lines. A scanning line driving circuit for driving
A first cell having a plurality of first semiconductor elements;
A second cell having a different circuit configuration from the first cell and adjacent to the first cell and having a plurality of second semiconductor elements;
A power line formed at a boundary between the first cell and the second cell and supplying a power voltage;
Have
At least one semiconductor element of the plurality of first semiconductor elements and one semiconductor element of the plurality of second semiconductor elements are provided on a common semiconductor island,
The common semiconductor island has an asymmetric shape with the boundary as an axis, and is provided so as to intersect the power supply line.
The common semiconductor island is provided with a common contact hole connected to the power line,
A power supply voltage is supplied to the first cell and the second cell through the common contact hole.
A scanning line driving circuit having an integrated circuit structure . From the boundary between a certain first cell and the second cell, according to claim 6 in which spacing to the boundary between the next first cell and the second cell, characterized in that to match the spacing of the respective scan lines Scanning line driving circuit. Either the first cell or the second cell has an individual semiconductor island having a region overlapping with the power supply line,
The scanning line driving circuit according to claim 6 , further comprising an individual contact hole for connecting the individual semiconductor island and the power supply line . The scanning line driving circuit according to claim 8 , wherein the interval between the common contact hole and the individual contact hole is a natural number multiple of a predetermined reference distance . The scanning line driving circuit according to claim 9 , wherein dummy contact holes are arranged at intervals of the reference distance in addition to the common contact holes or the individual contact holes . An electro-optical panel comprising at least one of the data line driving circuit according to claim 2 or the scanning line driving circuit according to claim 7 . An electronic apparatus comprising the electro-optical panel according to claim 11 .

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