JP3649205B2 - Electro-optical device and electronic apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention belongs to a technical field of an electro-optical device such as an active matrix driving type liquid crystal device driven by a thin film transistor (hereinafter referred to as a TFT) and an electronic apparatus using the same, and particularly, data provided on a TFT array substrate. The present invention belongs to a technical field of an electro-optical device of a type in which a data line is driven at a high frequency based on a control signal such as a clock signal by a line driving circuit and an electronic device using the same.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, in an active matrix driving type liquid crystal device using TFT driving, a large number of pixel electrodes are provided on a TFT array substrate corresponding to a large number of scanning lines and data lines arranged in the vertical and horizontal directions and their intersections. Yes. In addition to these, a data signal supplying means for supplying a data signal to the data line including a data line driving circuit, a sampling circuit, and the like, and a scanning signal supplying means for supplying a scanning signal to the scanning line including a scanning line driving circuit, May be provided on such a TFT array substrate.
[0003]
In this case, the data signal supply means corresponds to the control signal such as the data line side reference clock for operating the data line driving circuit which is the reference of the data signal supply timing, and the content of the image to be displayed. An image signal as a signal base, a positive or negative constant potential power source, and the like are supplied via an external input terminal and a wiring provided on the TFT array substrate, respectively. On the other hand, the scanning signal supply means is also provided with a scanning line side reference clock for operating the scanning line driving circuit which is a reference for the scanning signal supply timing, a positive or negative constant potential power source, etc. on the TFT array substrate. It is supplied via an external input terminal and wiring. In the scanning signal supply means, for example, a scanning signal is supplied to the scanning lines line-sequentially at a timing based on the scanning line side reference clock by a scanning line driving circuit. In response to this, in the data signal supply means, for example, the data line driving circuit sequentially drives the sampling circuit that samples the input image signal at the timing based on the data line side reference clock, and the data signal is output from the sampling circuit. Supplied to the data line. As a result, each TFT gate-connected to the scanning line is turned on in response to the supply of the scanning signal, and the data signal is supplied to the pixel electrode through the TFT to display an image in each pixel.
[0004]
In recent years, in particular, in a liquid crystal device for a liquid crystal projector or the like, a serial image signal with a very high frequency has been input as the resolution of a display image is increased. For example, the dot frequency of the image signal is about 65 MHz and about 135 MHz in the XGA display mode and the SXGA display mode used on a recent high-resolution personal computer screen, respectively. Much higher than 30MHz). In order to cope with this, in particular, the frequency of the data line side reference clock supplied to the data signal supply means has become very high.
[0005]
[Problems to be solved by the invention]
However, under the recent demand for high-quality display images, the generation of high-frequency clock noise due to such a high reference clock frequency cannot be ignored. That is, for example, in a configuration in which the sampling circuit is driven by supplying a data line side reference clock having a relatively low frequency to the data line driving circuit, if the frequency of the clock signal is increased as it is, an image input to the sampling circuit High-frequency clock noise occurs in the signal or in the data signal output from the sampling circuit, and the data signal to be supplied to the data line is deteriorated. When such a deteriorated data signal is supplied, the image displayed by each pixel electrode also deteriorates. For example, when an intermediate level gradation display is performed in each pixel, even if a very small noise of about 10 mV jumps into the image signal, it appears as a visible noise in the display image. This is because the transmission of the liquid crystal with respect to the change in the liquid crystal driving voltage at the intermediate level is compared with the case where the white or black level display corresponding to the highest or lowest liquid crystal driving voltage (for example, a voltage between 0 to 5 V) is performed. This is because the rate change is steep. Thus, in order to realize high-precision multi-gradation display, the problem of high-frequency clock noise is serious.
[0006]
On the other hand, the frequency of the image signal supplied to the sampling circuit can be lowered by increasing the number of phase expansion, but the number of external input terminals for image signal input that must be provided on the substrate of the liquid crystal panel is the number of phase expansion. It must be increased in response to the increase. That is, for example, in the case of 6-phase development, 6 external input terminals for inputting image signals are required, and in the case of 12-phase development, 12 external input terminals are required. Further, the number of wirings routed from the external input terminal for inputting these image signals to the sampling circuit is also required by the number of phase developments. As a result, the proportion of the image signal wiring on the substrate surface of the liquid crystal panel is increased, and a region for forming the data signal supply means including the sampling circuit, the data line driving circuit, etc. is secured on the substrate. It becomes difficult. Here, as in the conventional case, a wiring for a control signal such as a clock signal is routed to one side of the data line driving circuit as viewed from the edge of the substrate on which the external input terminal is provided, and the other side of the data line driving circuit is connected. If a large number of wirings for image signals are routed to the side, the number of wirings routed to each side is remarkably different, so that the wiring arrangement balance around the data line driving circuit becomes very poor (that is, wiring) Is biased to one side). In this case, it is possible to secure the area for forming the wiring area and the data line driving circuit by enlarging the substrate of the liquid crystal panel. However, this increases the size of the screen with a limited substrate size. Contrary to basic requirements in the technical field.
[0007]
The present invention has been made in view of the above-described problems, and even if the number of wirings and the number of external input terminals increase with an increase in the number of phase expansions of image signals, these can be wired and arranged in a well-balanced manner. In addition, it is possible to provide a liquid crystal device capable of reducing adverse effects such as high-frequency clock noise exerted by a control signal such as a high-frequency clock signal on an image signal, and capable of displaying a high-quality image, and an electronic apparatus including the liquid crystal device. Let it be an issue.
[0008]
[Means for Solving the Problems]
The electro-optical device according to the aspect of the invention includes a display area including a plurality of pixels on a substrate, a data line driving circuit that is provided on one side of the substrate and supplies an image signal to the pixels, and the data lines A scanning line driving circuit provided on a side not facing the driving circuit, a clock signal line of a data line driving circuit for supplying a clock signal to the data line driving circuit, and a scanning for supplying a clock signal to the scanning line driving circuit A clock signal line of the line drive circuit, a clock signal line external terminal of the data line drive circuit connected to the clock signal line of the data line drive circuit, and a scan line connected to the clock signal line of the scan line drive circuit An external terminal for a clock signal line of a driving circuit, an image signal line group composed of a plurality of image signal lines for supplying an image signal to the pixel, and an external terminal for an image signal line connected to the image signal line And each external terminal is provided on one side of the substrate, and is fixed between an image signal line external terminal of the image signal line group and a clock signal line external terminal of the data line driving circuit. A constant potential wiring external terminal connected to the potential wiring is provided, and the constant potential wiring connected to the constant potential wiring between the image signal line external terminal and the clock signal line external terminal of the scanning line driving circuit. An external terminal is provided.
[0012]
In the electro-optical device according to the aspect of the invention, the data line driving circuit includes a plurality of constituent circuits, and a constant potential wiring is provided between the constituent circuits.
[0013]
In the electro-optical device according to the aspect of the invention, the constant potential wiring may be disposed between the display area and the scanning line driving circuit.
[0014]
In the electro-optical device according to the aspect of the invention, the constant potential wiring may be disposed along a peripheral parting that defines the display area.
[0015]
According to another aspect of the invention, an electronic apparatus includes the electro-optical device.
[0016]
Such an operation and other advantages of the present invention will become apparent from the embodiments described below.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0018]
(Configuration of liquid crystal device)
As an example of an electro-optical device, a configuration of an embodiment of a liquid crystal device will be described with reference to FIGS. FIG. 1 is a plan view showing configurations of various wirings, peripheral circuits, and the like including conductive lines (hereinafter referred to as shield lines) provided on the TFT array substrate in the embodiment of the liquid crystal device. FIGS. 3A and 3B are plan views showing a more detailed two-dimensional layout of the shield line in FIG. 1, and FIGS. 3A and 3B are views showing wiring such as a shield line, an image signal line, and a clock signal line, respectively. FIG. 5 is an enlarged plan view of the pixel portion of FIG. 1, and FIG. 6 is a diagram showing each component on which the TFT array substrate is formed. 7 is a plan view seen from the counter substrate side, and FIG. 7 is a cross-sectional view taken along line HH ′ of FIG. 6 including the counter substrate. FIG. 8 is a schematic plan view (FIG. 8A) showing an example of the two-dimensional layout of the image signal lines in FIG. 1 and a schematic plan view (FIG. 8B) showing another example.
[0019]
In FIG. 1, a liquid crystal device 200 includes a TFT array substrate 1 made of, for example, a quartz substrate or hard glass. On the TFT array substrate 1, a plurality of pixel electrodes 11 provided in a matrix, a plurality of data lines 35 arranged in the X direction and extending in the Y direction, and a plurality of data electrodes 35 arranged in the Y direction are arranged. The scanning lines 31 extending along the X direction, the data lines 35 and the pixel electrodes 11 are respectively interposed between the scanning lines 31 and the conductive and non-conductive states are supplied via the scanning lines 31. A plurality of TFTs 30 are formed as an example of switching elements that are controlled in accordance with scanning signals. On the TFT array substrate 1, a capacitor line 31 ′ that is a wiring for a storage capacitor (see FIG. 9) described later is formed substantially in parallel along the scanning line 31.
[0020]
On the TFT array substrate 1, a sampling circuit 301 and a data line driving circuit 101 that constitute an example of the data signal supply means, and a scanning line driving circuit 104 that constitutes an example of the scanning signal supply means are formed. Further, scanning provided on both sides of the screen display area is provided on the upper side of the screen display area defined by the plurality of pixel electrodes 11 (that is, the area of the liquid crystal panel in which an image is actually displayed by a change in the alignment state of the liquid crystal). A plurality of wirings 105 for connecting the line drive circuits 104 are provided, and silver made of a conductive material for establishing electrical conduction between the TFT array substrate 1 and the counter substrate is provided at the four corners of the screen display area. Point 106 is provided. However, at least one vertical conduction point is sufficient. In the following description of FIGS. 1 to 8, the names of signals input through the external input terminals 102 provided along the lower side of the TFT array substrate 1 and the signal wiring thereof are shown for ease of explanation. The same alphabet symbol is added after the signal and the wiring for reference (for example, the signal wiring is called “wiring CLX” for the signal name “clock signal CLX”).
[0021]
The scanning line driving circuit 104 uses the negative power supply VSSY and the positive power supply VDDY for the scanning line driving circuit 104 supplied from the external control circuit via the external input terminal 102 and the wirings VSSY and VDDY as power supplies. To start the built-in shift register circuit. The scanning line is supplied at a predetermined timing based on the reference clock signal CLY for the built-in shift register circuit of the scanning line driving circuit 104 and its inverted clock signal CLY ′, which is supplied via the external input terminal 102 and the wirings CLY and CLY ′. A scanning signal is applied to 31 in a line sequential manner in a pulse manner.
[0022]
The data line driving circuit 101 uses a negative power source VSSX and a positive power source VDDX for the data line driving circuit, which are supplied from the external control circuit via the external input terminal 102 and the signal wirings VSSX and VDDX, as a power source. To start the built-in shift register circuit. Based on the reference clock signal CLX for the built-in shift register circuit of the data line driving circuit 101 and its inverted clock signal CLX ′ supplied via the external input terminal 102 and the wirings CLX and CLX ′, the scanning line driving circuit 104. In accordance with the timing at which the scanning signal is applied, the sampling circuit drive signal is supplied for each data line 35 for each of the 12-phase developed image signals VID1 to VID12 supplied via the external input terminal 102 and the wirings VID1 to VID12. The signal is supplied to the sampling circuit 301 through the sampling circuit drive signal line 306 at a predetermined timing.
[0023]
The sampling circuit 301 includes a TFT 302 for each data line 35, wirings VID 1 to VID 12 are connected to the source electrode of the TFT 302, and a sampling circuit driving signal line 306 is connected to the gate electrode of the TFT 302. When the image signals VID1 to VID12 are input, these image signals are sampled. When a sampling circuit driving signal is input from the data line driving circuit 101 via the sampling circuit driving signal line 306, the image signals sampled for each of the image signals VID1 to VID12 are converted into twelve adjacent data lines 35. Sequentially applied to each group consisting of
[0024]
As described above, the data line driving circuit 101 and the sampling circuit 301 are configured to supply the image signals VID <b> 1 to VID <b> 12 expanded in 12 phases as data signals to the data line 35. In the present embodiment, the sampling circuit 301 connected to the 12 adjacent data lines 35 is selected at the same time, and the transfer is sequentially performed for each group of 12 data lines 35. May be selected every 6 or every 24. Alternatively, two or more arbitrary numbers may be selected at the same time. Further, if the capability of the TFT 302 of the sampling circuit 301 is high, the data may be sequentially selected for each data line. In this case, it goes without saying that the image signal external input terminals 102 and image signal lines are required at least as many as the number of phase expansions of the image signal. Particularly in the present embodiment, since the wirings VID1 to VID12 are routed from both sides of the data line driving circuit 101 as described below, the number (phase development number) is balanced on the TFT array substrate 1 at most. Wiring can be done well. Note that the number of phase expansions of the image signal and the number of sampling circuits 301 selected at the same time may be equal to each other, or the former may be configured to be greater than the latter.
[0025]
As shown in FIG. 2, when the start signal DX is input, the data line driving circuit 101 starts the sequential generation of the transfer signal based on the reference clock signal CLX and its inverted clock signal CLK ′; A waveform control circuit 101b and a buffer circuit 101c are provided which, after waveform shaping and buffering the transfer signal from the shift register circuit 101a, supply the sampling signal to the sampling circuit 301 via the sampling circuit drive signal line 306. The sampling circuit 301 has 12 TFTs 302 connected in parallel to each sampling circuit drive signal line 306 corresponding to the image signals VID1 to VID12 expanded in 12 phases.
[0026]
That is, the switches S1 to S12 configured by the TFT 302 are connected to the first sampling circuit drive signal line 306 from the left, and the switches S13 to S24 are connected to the second sampling circuit drive signal line 306 from the left. , Switches Sn-11 to Sn are connected to the rightmost sampling circuit drive signal line 306. The enable signals ENB1 and ENB2 omitted in FIG. 1 and shown in FIG. 2 are input to an enable circuit provided in the waveform control circuit 101b. In this enable circuit, the selection period of the sampling circuit 301 is controlled by limiting the width of the pulses sequentially output from the shift register circuit 101a to the pulse widths of the enable signals ENB1 and ENB2. This prevents ghosts from occurring between the data lines 35 that receive image signals from the same wiring (VID 1 to 12) separated by 12 data lines. Therefore, the enable signals ENB1 and ENB2 belong to a high frequency control signal having a cycle shorter than the horizontal scanning period, like the clock signals CLX and CLX ′. On the other hand, the start signal DX input to the shift register circuit 101a has a period not shorter than the horizontal scanning period, like the clock signals CLY and CLY ′ and the start signal DY input to the shift register on the scanning line driving circuit side. It belongs to the low frequency control signal.
[0027]
Here, a specific circuit configuration and operation of the shift register circuit 101a will be described with reference to FIG. 3A is a circuit diagram showing a shift register circuit including an enable circuit, and FIG. 3B is a timing chart of various signals in the shift register circuit.
[0028]
First, in FIG. 3A, an enable circuit 112 is provided corresponding to the output of each stage of the shift register circuit 101a. Each stage of the shift register circuit 101a outputs a reference clock signal CLX having a predetermined cycle and its inverted signal CLX so that a transfer signal is sequentially output from each stage in a transfer direction corresponding to the right direction (the direction from left to right). Each time the binary level of 'changes, it includes two clocked inverters that feed back the transfer signal and transfer it to the next stage. The enable circuit 112 limits the pulse width of the transfer signal output from the odd-numbered stage of the shift register circuit 101a to the pulse width of the first enable signal ENB1, and reduces the pulse width of the transfer signal output from the even-numbered stage. In order to limit to the pulse width of the second enable signal ENB2, the NAND circuit takes an exclusive logical product of the transfer signal and the enable signal ENB1 or ENB2, and an inverter circuit that inverts the result. A signal DX for starting transfer of a transfer signal is input to the shift register circuit 101a from the left side in the figure.
[0029]
When the signal DX, the clock signal CLX and its inverted signal CLX ′, and the first and second enable signals ENB1 and ENB2 are input at the timing shown in the timing chart of FIG. 3B, the configuration is as described above. Transfer signals that are sequentially delayed by a half cycle of the clock signal CLX are sequentially output from the shift register circuit 101a. Then, the enable circuit 112 limits the pulse width of the transfer signal to the pulse widths of the signals ENB1 and ENB2, and the sampling circuit drive signals Q1, Q2, and Q3 each having a pulse width narrower than the pulse width of the clock signal CLX. ,..., Qn (where n is an odd number) are sequentially supplied to the sampling circuit 301 via the waveform control circuit 101b and the buffer circuit 101c shown in FIG.
[0030]
Particularly in the present embodiment, as shown in FIGS. 1 and 2, the TFT array substrate 1 also serves as a constant potential shield line 80 that also serves as the wiring VSSY for the negative power supply VSSY and the wiring VSSX for the negative power supply VSSX. The constant potential shield line 80 ', the constant potential shield line 82 that also serves as the wiring VDDX for the positive power supply VDDX, and the constant potential shield line 86 that also serves as the wiring VDDY for the positive power supply VDDY are wired. By these shield lines 80, 80 ′, 82 and 86, the wirings VID1 to VID12 which are image signal lines are electrically shielded from the wirings CLX and CLX ′ and the wirings ENB1 and ENB2. Accordingly, even when the frequency of the clock signal CLX is high, jumps of high-frequency clock noise or the like from the wirings CLX and CLX ′, which are high-frequency control signal lines, and the wirings ENB1 and ENB2 to the wirings VID1 to VID12 can be reduced.
[0031]
Moreover, as shown in FIGS. 1 and 2, odd-numbered image signal lines VID1, 3, 5, 7, 9, and 11 constituting an example of the first image signal line group are arranged on the TFT array substrate 1 as X The even-numbered image signal lines VID2, 4, 6, 8, 10, and 12 constituting an example of the second image signal line group are arranged in the TFT array. It is routed to the left side of the data line driving circuit 101 on the substrate 1. Therefore, for example, by performing a relatively multi-phase expansion number such as 12-phase expansion, the frequency of the image signals VID1 to 12 supplied to the sampling circuit 301 is lowered, and a large number of wirings VID1 to 12 are data They can be arranged on both sides of the line drive circuit 101 with good balance. As a result, a region for forming the data signal supply means including the sampling circuit 301 and the data line driving circuit 101 can be easily secured on the TFT array substrate 1. Therefore, the screen can be enlarged on a limited substrate size.
[0032]
Particularly in this embodiment, as shown in FIG. 2, the lines VID1 to VID12 as image signal lines are connected to the clock signals CLX and CLX ′ and the enable signal belonging to the above-described high-frequency control signal by the shield line 80 ′ having a constant potential. The wires CLX and CLX ′, which are high-frequency control signal lines that supply ENB1 and ENB2, are electrically shielded from the wires ENB1 and ENB2. Therefore, even when the frequency of the clock signal is high, jumping of high frequency clock noise or the like from these high frequency control signal lines to the wirings VID1 to VID12 can be reduced. On the other hand, for the start signals DX and DY and the clock signals CLY and CLY ′ belonging to the low-frequency control signal, the image signals on the wirings VID1 to 12 and the data signals on the data line 35 supplied based on the image signals are supplied. It does not cause high frequency noise inside. For this reason, the wirings DX, DY, CLY, and CLY ′, which are low-frequency control signal lines, may or may not be shielded by constant potential shield lines. In the present embodiment, as shown in FIG. 2, on the right side, the wirings VID1, 3,..., 11 are shielded from the wirings DY, CLY, and CLY ′ by the shield line 86 made of the constant potential wiring VDDY. On the left side, the wirings VID2, 4,..., 12 are shielded from the wiring DY by a shield line 80 made of a constant potential wiring VSSY. Further, from the wiring DX, the wirings VID1 to VID12 are shielded by the shield line 80 ′.
[0033]
Further, in the present embodiment, in particular, in the right (odd number) image signal line group, the wiring VID11 located on the side close to the wirings CLX and CLX ′ which are high frequency control signal lines is two wirings VSSX and VDDX, respectively. The shield lines 80 'and 82 are separated from the wirings CLX and CLX' and are electrically shielded. In addition, the wiring VID12 located on the side close to the wirings CLX and CLX ′ which are high-frequency control signal lines in the left (even-numbered) image signal line group includes one shield line 80 ′ composed of the wiring VSSX and low-frequency control. Due to the presence of the wiring DX as a signal line, the wiring DXX is separated from the wirings CLX and CLX ′ and is electrically shielded. That is, the wiring DX belonging to the low frequency control signal line that does not cause high frequency noise in the image signal or the data signal is connected to the wiring CLX and CLX ′ serving as the high frequency control signal line and the wiring VID12 together with the shield line 80 ′. By disposing, the adverse effects such as clock noise on the VID 12 of the wirings CLX and CLX ′ can be further reduced. In general, electromagnetic waves decrease according to the distance and the presence of obstacles. Therefore, the shield lines (wirings 80, 80 ', 82, 86, etc.) are defined between the wirings CLX and CLX', the wirings ENB1 and ENB2, and the wirings VID1 to 12. The potential wiring) and the low frequency control signal lines (wirings to which low frequency control signals such as wirings DX, DY, CLY, CLY ′, etc.) are wired as much as possible reduce electromagnetic waves that generate clock noise. , Clock noise and the like are reduced. As described above, it is advantageous from the viewpoint of effective use of the space on the TFT substrate 1 and noise reduction to interpose the low frequency control signal line in addition to the shield line between the high frequency control signal line and the image signal line.
[0034]
Further, as shown in FIG. 2, in the present embodiment, on the peripheral portion of the TFT array substrate 1, the external input terminals 102 respectively connected to the wirings VID1 to VID12 are arranged on both sides, and the wiring ENB1, The external input terminals 102 connected to ENB2, CLX ′ and CLX are centrally arranged. The external input terminal 102 connected to the shield line 80 ′ (wiring VSSX) is arranged between the external input terminal 102 connected to the wiring VID12 and the external input terminal 102 connected to the wiring ENB1. Further, the external input terminal 102 connected to the shield line 80 ′ (wiring VSSX) is arranged between the external input terminal 102 connected to the wiring VID11 and the external input terminal 102 connected to the wiring CLX. Accordingly, it is possible to easily obtain a configuration in which the shield line 80 ′ is wired between the wirings VID1 to VID12 and the wirings ENB1, ENB2, CLX ′, and CLX. In particular, before being input to the liquid crystal device 200, for example, in the wiring from the external circuit such as the display information processing circuit to the liquid crystal device 200, the clock signal CLX or the like generates clock noise or the like with respect to the image signals VID1 to 12. It is possible to effectively prevent the situation that occurs. Thus, according to the present embodiment, before and after being input to the liquid crystal device 200, it is possible to reduce high-frequency clock noise jumping from the clock signal wiring to the image signal wiring. More preferably, in the region where the external input terminal 102 can be formed in the peripheral portion of the TFT array substrate 1, the external input terminals 102 for the wirings VID 1 to 12 are arranged as close to both sides (right side and left side) as possible. At the same time, the external input terminal 102 for the shield line 80 ′, etc. is arranged at this interval with a space as far as possible from the external input terminal 102 for the wiring CLX ′ etc. concentrated in the center.
[0035]
In the present embodiment, the wirings VSSY, VSSX, VDDX, and VSSY are respectively extended to form shield lines 80, 80 ′, 82, and 86, so that external input terminals and wirings can be shared, and the device configuration Simplification and space saving. Further, the potentials of the shield lines 80, 80 ′, 82, and 86 are easily set to a constant potential by sharing the constant potential line. However, the power supply wiring and the shield line may be separately wired.
[0036]
In the present embodiment, as shown in FIG. 2, two external input terminals 102 to which a negative power supply VSSX is input are provided. The wirings VID1 to VID12 are surrounded on the TFT array substrate 1 by a shield line 80 ′ that is set to the potential (negative potential) of the negative power supply VSSX. In particular, a shield line 80 ′ formed of the same metal layer as Al as the data line 35 extends between the shift register circuit 101 a and the waveform control circuit 101 b. The extended shield wire 80 ′ has a tip part, for example, from the same conductive layer such as polysilicon as the scanning line 31 below the metal layer such as Al via the first interlayer insulating layer as will be described later. It is connected to the shield line 80 ′ through the formed shield line connection portion 81 so as to surround the waveform control circuit 101b and the buffer circuit 101c.
[0037]
On the other hand, as shown in FIG. 2, the wirings CLX and CLX ′ are arranged on the TFT array substrate 1 in the portion adjacent to the data line driving circuit 101 by the shield line 82 set to the potential (positive potential) of the positive power supply VDDX. Surrounded by In particular, a shield line 82 formed of the same metal layer such as Al as the data line 35 extends between the waveform control circuit 101b and the buffer circuit 101c, and the tip of the shield line 82 is connected to the scanning line 31, for example. It is connected to the shield line 82 so as to surround the waveform control circuit 101b and the shift register circuit 101a via a shield line connection portion 83 formed of the same conductive layer such as polysilicon.
[0038]
Accordingly, the wirings VID1 to VID12 have a configuration in which the wirings CLX and CLX ′ and the wirings ENB1 and ENB2 are double-shielded on the TFT array substrate 1, and the shift register circuit 101a, the waveform control circuit 101b, and the buffer circuit are used. The shield for 101c is also highly reliable. However, at least one shield line 80, 80 ′, 82 and 86 is interposed between the wirings CLX, CLX ′, ENB1 and ENB2 and the wirings VID1 to VID12 without adopting such a surrounding configuration. If so, the effect of shielding can be obtained somewhat.
[0039]
In this embodiment, as shown in FIGS. 1 and 2, the screen display region and the plurality of data lines 35 are surrounded on the TFT array substrate 1 by the shield lines 80. For this reason, the screen display area and the plurality of data lines 35 are also shielded from the wirings CLX, CLX ′, ENB1, and ENB2. Therefore, it is possible to reduce the occurrence of high-frequency clock noise in the sampling circuit driving signal output from the data line driving circuit 101, the data signal reaching the TFT 30 or the pixel electrode 11, and the like. However, even if the configuration surrounding the screen display area is not adopted, if the wirings VID1 to VID6 leading to the sampling circuit 301 are shielded by the shield lines 80, 80 ′, 82 or 86, the shield The effect can be obtained somewhat. In this case, as can be seen from FIG. 1, the shield line 80 extends from the wiring VSSY, and extends so as to redundantly supply the power supply signal VSSY to the scanning line driving circuits 104 provided on both sides of the screen display area. It is installed. For this reason, even if a disconnection occurs in the shield line 80 or the wiring VSSY, it is difficult to cause a device defect, which is advantageous.
[0040]
As shown in the cross-sectional views of FIGS. 4A and 4B, various wirings DY, VSSY,..., VDDX connected to the external input terminal 102 are connected to the data line 35 such as Al (aluminum), for example. It is formed from the same low resistance metal material. Therefore, even if the routing area of the shield lines 80 (wiring VSSY), 80 ′ (wiring VSSX), 82 (wiring VDDX) and 86 (wiring VDDY) is long, the shield lines 80, 80 ′, 82 and 86 The resistance is kept low enough for practical use. That is, as shown in FIG. 2, it is possible to sew shield wires 82 and 80 'in a zigzag pattern by sewing gaps between various other wirings, shift register circuit 101a, waveform control circuit 101b, and buffer circuit 101c, and further, screen display area The shield wire 80 can be wired long in a wide area including the above. Thus, the effect of the shield can be enhanced as a whole with a relatively simple configuration. As shown in FIGS. 4A and 4B, the various wirings DY, VSSY,..., VDDX are formed on the first interlayer insulating layer 42 formed on the TFT array substrate 1, that is, on the same layer. ing. Therefore, the shielding effect is more efficiently exhibited. Further, with this configuration, in the manufacturing process of the liquid crystal device 200, various wirings DY, VSSY,..., VDDX can be formed in one step from the same low-resistance metal layer such as an Al layer in the same process. This is advantageous in manufacturing.
[0041]
The signal LCCOM input from the external input terminal 102 shown in FIGS. 1 to 4 is a power supply signal for the common electrode, and is provided on the counter substrate described later via the wiring LCCOM and the silver point 106 described above. It is supplied to the common electrode (see FIG. 9).
[0042]
Here, as shown in the plan view of FIG. 5, the capacitor line 31 ′ is formed on the TFT array substrate 1 in parallel with the scanning line 31 (gate electrode), for example, from the conductive polysilicon layer or the like, similar to the scanning line 31. It is connected to the shield line 80 via the contact hole 80a. With this configuration, wiring for setting the capacitor line 31 ′ at a constant potential can also be used as the shield line 80, and an external input terminal necessary for setting the capacitor line 31 ′ at a constant potential can also be used for the shield line 80. The external input terminal 102 can also be used.
[0043]
Particularly in the present embodiment, the sampling circuit 301 is located at a position facing the light-blocking peripheral parting 53 formed on the counter substrate 2 as shown by the hatched area in FIG. 1 and as shown in FIGS. 6 and 7. The data line driving circuit 101 and the scanning line driving circuit 104 are provided on the TFT array substrate 1, and are provided on the narrow and long peripheral portion of the TFT array substrate 1 that does not face the liquid crystal layer 50. On the TFT array substrate 1, a sealing material 52 made of a photocurable resin as an example of a sealing member that surrounds the liquid crystal layer 50 by adhering both substrates around the screen display region is provided along the screen display region. Is provided. A light-shielding peripheral parting 53 is provided between the screen display area on the counter substrate 2 and the sealing material 52.
[0044]
When the TFT array substrate 1 is placed in a light-shielding case that is provided with an opening corresponding to the screen display area later, the peripheral parting 53 is limited to the edge of the opening of the case due to a manufacturing error or the like. In other words, it is made of a band-shaped light-shielding material having a width of at least 500 μm around the screen display area so as to allow, for example, a deviation of about several hundred μm from the case of the TFT array substrate 1. It has been done. Such a light-shielding peripheral parting 53 is formed on the counter substrate 2 by sputtering using a metal material such as Cr (chromium), Ni (nickel), Al (aluminum), a photolithography process, an etching process, or the like. The Or it forms from materials, such as resin black which disperse | distributed carbon and Ti (titanium) in the photoresist. Further, a light-blocking peripheral parting 53 may be provided on the TFT array substrate 1. If the peripheral parting 53 is built in the TFT array substrate 1, the aperture area of the pixel is not affected by variations in accuracy in the bonding process between the TFT array substrate 1 and the counter substrate 2. The rate can be maintained with high accuracy.
[0045]
A data line driving circuit 101 and an external input terminal (mounting terminal) 102 are provided along the lower side of the screen display area in the area outside the sealing material 52, and scanning is performed along the left and right sides of the screen display area. Line drive circuits 104 are provided on both sides of the screen display area. The counter substrate 2 having substantially the same outline as the sealing material 52 is fixed to the TFT array substrate 1 by the sealing material 52.
[0046]
As described above, since the shield line 80 and the sampling circuit 301 are provided under the peripheral parting 53 on the TFT array substrate 1, space saving on the TFT array substrate 1 can be achieved, for example, a scanning line driving circuit. 104 and the data line driving circuit 101 can be formed with a margin in the peripheral portion of the TFT array substrate 1, and the effective display area in the liquid crystal device 200 is hardly or not reduced by the formation of the shield line 80.
[0047]
FIG. 8A shows an enlarged drawing method of the wirings VID1 to VID12 between the scanning line driving circuit 101 and the sampling circuit 301 shown in FIGS. In the figure, wirings VID1,..., 11 as odd-numbered image signal lines and wirings VID2,..., 12 as even-numbered image signal lines are alternately routed in a comb-teeth shape from both sides for each wiring. . Therefore, around the data line driving circuit 101, the wirings VID1 to VID12 and the sampling circuit driving signal line 306 are wired with very regularity and good balance.
[0048]
By the way, in this embodiment, various methods for inverting the liquid crystal driving voltage, for example, field or frame inversion driving, scanning line inversion, in order to prevent the liquid crystal from being deteriorated by DC driving or to prevent flicker on the display screen, etc. Driving (so-called 1H inversion driving), data line inversion driving (so-called 1S inversion driving), dot inversion driving, and the like can be employed. Here, in particular, when the liquid crystal driving is performed by inverting the voltage polarity between adjacent data lines such as 1S inversion and dot inversion, as shown in FIG. Rather than comb-teeth, as shown in FIG. 8 (b), two wires VID1, 2, 5, 6 and so on corresponding to two adjacent data lines 35 are paired every two wires. In addition to being routed from one side (for example, the right side), the other two lines VID3 and 4, 7, and 8 corresponding to the two adjacent data lines 35 are paired and the other side (for example, the other side) It is more preferable that the two wirings are paired between the data line driving circuit 101 and the sampling circuit 301 and are comb-shaped from both sides. If wired in this way, the image signals supplied from each pair of wirings 1 and 2, 3 and 4,... Adjacent to each other on the TFT array substrate 1 are reversed in polarity and supplied to the data line 35. The noise components caused by the same noise source existing in these signals have the effect of canceling each other out of each pair, which helps to reduce the noise.
[0049]
(Configuration of the LCD panel)
Next, a specific configuration of the liquid crystal panel portion included in the liquid crystal device 200 will be described with reference to FIGS. FIG. 9 is a cross-sectional view of the TFT 30 portion of the liquid crystal panel, and FIG. 10 is a cross-sectional view taken along the shield line 80 of the liquid crystal panel under the peripheral parting. In FIGS. 9 and 10, the scale of each layer and each member is different in order to make each layer and each member recognizable on the drawings.
[0050]
In the cross-sectional view of FIG. 9, the liquid crystal panel 10 includes a TFT array substrate 1, a semiconductor layer 32, a gate insulating layer 33, a scanning line 31 (gate electrode), a first electrode, A first interlayer insulating layer 42, a data line 35 (source electrode), a second interlayer insulating layer 43, a pixel electrode 11, and an alignment film 12 are provided. The liquid crystal panel 10 also includes a counter substrate 2 made of, for example, a glass substrate, and a common electrode 21, an alignment film 22, and a light shielding layer 23 stacked thereon. The liquid crystal panel 10 further includes a liquid crystal layer 50 sandwiched between these two substrates.
[0051]
Here, first, the structure of each layer of these layers excluding the TFT 30 will be described in order.
[0052]
The first and second interlayer insulating layers 42 and 43 are each formed of a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, a silicon oxide film, or the like having a thickness of about 5000 to 15000 mm. Note that an interlayer insulating layer serving as a base of the TFT 30 may be formed on the TFT array substrate 1 from a silicate glass film, a silicon nitride film, a silicon oxide film, or the like.
[0053]
The pixel electrode 11 is made of a transparent conductive thin film such as an ITO film (Indium Tin Oxide film). Such a pixel electrode 11 is formed by depositing an ITO film or the like to a thickness of about 500 to 2000 mm by sputtering or the like, and then performing a photolithography process or an etching process. When the liquid crystal panel 10 is used in a reflective liquid crystal device, the pixel electrode 11 may be formed from an opaque material having a high reflectance such as Al.
[0054]
The alignment film 12 is made of, for example, an organic thin film such as a polyimide thin film. Such an alignment film 12 is formed, for example, by applying a polyimide coating solution and then rubbing it in a predetermined direction so as to have a predetermined pretilt angle.
[0055]
The common electrode 21 is formed over the entire surface of the counter substrate 2. Such a common electrode 21 is formed, for example, by depositing an ITO film or the like to a thickness of about 500 to 2000 mm by sputtering or the like.
[0056]
The alignment film 22 is made of, for example, an organic thin film such as a polyimide thin film. Such an alignment film 22 is formed, for example, by applying a polyimide coating solution and then rubbing it in a predetermined direction so as to have a predetermined pretilt angle.
[0057]
The light shielding layer 23 is provided in a predetermined region facing the TFT 30. Such a light shielding layer 23 is formed by a process such as sputtering, photolithography and etching using a metal material such as Cr or Ni, or a resin in which carbon or Ti is dispersed in a photoresist, like the peripheral parting 53 described above. It is formed from a material such as black. The light shielding layer 23 has functions such as improving contrast and preventing color mixture of colors in addition to shielding the semiconductor layer (polysilicon film) 32 of the TFT 30.
[0058]
The liquid crystal layer 50 is a space surrounded by a sealing material 52 (see FIGS. 6 and 7) between the TFT array substrate 1 and the counter substrate 2 arranged so that the pixel electrode 11 and the common electrode 21 face each other. The liquid crystal is sealed by vacuum suction or the like. The liquid crystal layer 50 takes a predetermined alignment state by the alignment films 12 and 22 in a state where an electric field from the pixel electrode 11 is not applied. The liquid crystal layer 50 is made of, for example, a liquid crystal in which one kind or several kinds of nematic liquid crystals are mixed. The sealing material 52 is an adhesive made of, for example, a photo-curing resin or a thermosetting resin for bonding the two substrates 1 and 2 around them, and a distance between the two substrates is set to a predetermined value. Spacers are mixed.
[0059]
Next, the configuration of each layer related to the TFT 30 will be described in order.
[0060]
The TFT 30 is formed on the scanning line 31 (gate electrode), the semiconductor layer 32 in which a channel is formed by an electric field from the scanning line 31, a gate insulating layer 33 that insulates the scanning line 31 from the semiconductor layer 32, and the semiconductor layer 32. A source region 34, a data line 35 (source electrode), and a drain region 36 formed in the semiconductor layer 32 are provided. A corresponding one of the plurality of pixel electrodes 11 is connected to the drain region 36.
[0061]
As will be described later, the source region 34 and the drain region 36 are doped by doping the semiconductor layer 32 with a predetermined concentration of N-type or P-type dopant depending on whether an n-type or p-type channel is formed. Is formed. N-channel TFTs have the advantage of high operating speed, and are often used as TFTs 30 that are pixel switching elements.
[0062]
The semiconductor layer 32 constituting the TFT 30 is formed, for example, by forming an a-Si (amorphous silicon) film on the TFT array substrate 1 and then subjecting it to an annealing process to solid-phase growth to a thickness of about 500 to 2000 mm. . At this time, in the case of the N-channel TFT 30, doping may be performed by ion implantation using a dopant of a group V element such as Sb (antimony), As (arsenic), or P (phosphorus). In the case of the p-channel TFT 30, doping is performed by ion implantation using a group III element dopant such as B (boron), Ga (gallium), and In (indium). In particular, in the case where the TFT 30 is an N-channel TFT having an LDD (Lightly Doped Drain) structure, the source region 34 and the drain region 36 are partially adjacent to the channel side of the source region 34 and the drain region 36, respectively. A lightly doped region is formed with a dopant of a group V element, and a heavily doped region is formed with a dopant of a group V element such as P. In the case of a P-channel TFT 30, a source region 34 and a drain region 36 are formed in an N-type semiconductor layer 32 using a group III element dopant such as B. When the LDD structure is used as described above, there is an advantage that the short channel effect can be reduced. The TFT 30 may be an offset structure TFT in which ions are implanted into a lightly doped region in the LDD structure, or a high concentration source and drain in a self-aligned manner by doping high concentration impurity ions using a gate electrode as a mask. A self-aligned TFT for forming a region may be used.
[0063]
In the present embodiment, in FIG. 9, two gate electrodes 31 to which the same scanning signal is supplied are provided between the source and drain of the TFT 30 via the gate insulating film 2, and a dual gate (double gate) is provided. A TFT having a structure may be used. Thereby, the leakage current of the TFT 30 can be reduced. Further, if the dual gate TFT has the above-mentioned LDD structure or offset structure, the leakage current of the TFT 30 can be further reduced and a high contrast ratio can be realized. Further, the dual gate structure can provide redundancy, greatly reduce pixel defects, and can realize high contrast ratio image quality because of low leakage current even at high temperature operation. Needless to say, three or more gate electrodes 31 may be provided between the source and drain of the TFT 30.
[0064]
The gate insulating layer 33 is obtained by thermally oxidizing the semiconductor layer 32 at a temperature of about 900 to 1300 ° C. to form a relatively thin thermal oxide film of about 300 to 1500 mm.
[0065]
The scanning line 31 (gate electrode) is formed by a photolithography process, an etching process, or the like after depositing a polysilicon film by a low pressure CVD method or the like. Alternatively, it may be formed of a refractory metal film such as W (tungsten) or Mo (molybdenum) or a metal silicide film. In this case, if the scanning line 31 (gate electrode) is disposed as a light-shielding film corresponding to a part or all of the region covered by the light-shielding layer 23, the light-shielding property of the metal film or the metal silicide film causes the one of the light-shielding layers 23. It is also possible to omit some or all of the parts. In this case, in particular, there is an advantage that it is possible to prevent the pixel aperture ratio from being lowered due to the bonding deviation between the counter substrate 2 and the TFT array substrate 1.
[0066]
The data line 35 (source electrode) may be formed of a transparent conductive thin film such as an ITO film in the same manner as the pixel electrode 11. Alternatively, it may be formed of a low resistance metal such as Al or a metal silicide deposited to a thickness of about 1000 to 5000 by sputtering or the like.
[0067]
In the first interlayer insulating layer 42, a contact hole 37 that leads to the source region 34 and a contact hole 38 that leads to the drain region 36 are formed.
[0068]
The data line 35 (source electrode) is electrically connected to the source region 34 through the contact hole 37 to the source region 34. Further, a contact hole 38 to the drain region 36 is formed in the second interlayer insulating layer 43. The pixel electrode 11 is electrically connected to the drain region 36 through the contact hole 38 to the drain region 36. The pixel electrode 11 described above is provided on the upper surface of the second interlayer insulating layer 43 thus configured. Each contact hole is formed by dry etching such as reactive etching or reactive ion beam etching.
[0069]
In general, when light is incident on the semiconductor layer 32 in which a channel is formed, a photocurrent is generated due to a photoelectric conversion effect, and the transistor characteristics of the TFT 30 are deteriorated. Since the light shielding layers 23 are formed at positions facing the TFTs 30 respectively, incident light is prevented from entering the semiconductor layer 32. Further, in addition to or instead of this, if the data line 35 (source electrode) is formed of an opaque metal thin film such as Al so as to cover the gate electrode from the upper side, it is possible to connect to the semiconductor layer 32 together with the light shielding layer 23 or alone. Incident light (that is, light from the upper side in FIG. 9) can be effectively prevented from entering.
[0070]
In FIG. 9, a storage capacitor 70 is provided for each pixel electrode 11. More specifically, the storage capacitor 70 includes a first storage capacitor electrode layer 32 ′ formed by the same process as the semiconductor layer 32, an insulating layer 33 ′ formed by the same process as the gate insulating layer 33, and the scanning line 31. The capacitor line 31 ′ (second storage capacitor electrode), the first and second interlayer insulating layers 42 and 43, and the first and second interlayer insulating layers 42 and 43 formed through the same process as It is comprised from a part of pixel electrode 11 which opposes. Since the storage capacitor 70 is provided in this way, high-definition display is possible even when the duty ratio is small.
[0071]
As shown in the cross-sectional view of FIG. 10, the shield line 80 passes over the first interlayer insulating layer 42 at a position facing the peripheral parting line 53 and above the plurality of scanning lines 31. The shield line 80 is a low-resistance wire made of a metal thin film such as Al formed in the same process as the data line (source electrode) 35 described above.
[0072]
Thus, in the manufacturing process of the liquid crystal device 200, the shield line 80 and the data line 35 can be formed in a lump, which is advantageous in manufacturing.
[0073]
Particularly in this embodiment, since the TFT 30 is a polysilicon type TFT, the sampling circuit 301, the data line driving circuit 101, the scanning line driving circuit 104, etc. are similarly polysilicon TFT type in the same thin film forming process when the TFT 30 is formed. A peripheral circuit composed of the TFT 302 and the like can be formed, which is advantageous in manufacturing.
[0074]
For example, these peripheral circuits are formed in a peripheral portion on the TFT array substrate 1 from a plurality of TFTs having a complementary structure composed of an N channel type polysilicon TFT and a P channel type polysilicon TFT.
[0075]
Although not shown in FIGS. 9 and 10, in the liquid crystal panel 10, for example, TN on the side on which the projection light of the counter substrate 2 enters and on the side on which the projection light of the TFT array substrate 1 exits, for example, (Twisted nematic) mode, STN (super TN) mode, D-STN (double-STN) mode, etc., depending on the normal white mode / normally black mode, polarizing film, retardation film, polarizing A plate or the like is arranged in a predetermined direction.
[0076]
Further, since the liquid crystal panel 10 described above is applied to a color liquid crystal projector, the three liquid crystal panels 10 are used as RGB light valves, and each panel is connected to a dichroic mirror for RGB color separation. The decomposed light of each color is incident as incident light. Therefore, in each embodiment, the counter substrate 2 is not provided with a color filter. However, in the liquid crystal panel 10 as well, an RGB color filter may be formed on the counter substrate 2 together with its protective film in a predetermined region facing the pixel electrode 11 where the light shielding layer 23 is not formed.
[0077]
In this way, the liquid crystal panel of the present embodiment can be applied to a color liquid crystal device such as a direct-view type or a reflective type color liquid crystal television other than the liquid crystal projector. Furthermore, a micro lens may be formed on the counter substrate 2 so as to correspond to one pixel. In this way, a bright liquid crystal panel can be realized by improving the collection efficiency of incident light. Furthermore, a dichroic filter that produces RGB colors by using interference of light may be formed by depositing several layers of interference layers having different refractive indexes on the counter substrate 2. According to this counter substrate with a dichroic filter, a brighter color liquid crystal panel can be realized.
[0078]
In the liquid crystal panel 10, a planarizing film may be further applied on the second interlayer insulating layer 43 by spin coating or the like in order to suppress alignment failure of liquid crystal molecules on the TFT array substrate 1 side, or CMP treatment may be performed. You may give it. Alternatively, the second interlayer insulating layer 43 may be formed of a planarizing film.
[0079]
Although the switching element of the liquid crystal panel 10 has been described as being a normal stagger type or coplanar type polysilicon TFT, this embodiment is also applied to other types of TFTs such as an inverted stagger type TFT and an amorphous silicon TFT. Is valid.
[0080]
In the liquid crystal panel 10, the liquid crystal layer 50 is composed of nematic liquid crystal as an example. However, if polymer dispersed liquid crystal in which liquid crystal is dispersed as fine particles in a polymer is used, the alignment films 12 and 22, and the above-described polarization Films, polarizing plates and the like are not necessary, and the advantages of high brightness and low power consumption of the liquid crystal panel due to increased light utilization efficiency can be obtained. Further, when the liquid crystal panel 10 is applied to a reflective liquid crystal device by forming the pixel electrode 11 from a metal film having a high reflectance such as Al, SH in which liquid crystal molecules are substantially vertically aligned in the absence of voltage application. (Super homeotropic) type liquid crystal may be used. Furthermore, in the liquid crystal panel 10, the common electrode 21 is provided on the side of the counter substrate 2 so as to apply an electric field (vertical electric field) perpendicular to the liquid crystal layer 50, but an electric field (horizontal) parallel to the liquid crystal layer 50 is provided. The pixel electrode 11 is composed of a pair of electrodes for generating a horizontal electric field so that an electric field is applied (that is, the side of the TFT array substrate 1 is not provided with the electrode for generating a vertical electric field on the side of the counter substrate 2). It is also possible to provide a lateral electric field generating electrode. Using a horizontal electric field in this way is more advantageous in widening the viewing angle than using a vertical electric field. In addition, the present embodiment can be applied to various liquid crystal materials (liquid crystal layers), operation modes, liquid crystal alignments, driving methods, and the like.
[0081]
In the embodiment described above, a known peripheral circuit such as a precharge circuit or an inspection circuit may be provided below the peripheral parting 53 or in the peripheral part of the TFT array substrate 1. The precharge circuit is a timing preceding the data signal supplied from the data line driving circuit to the data line for the purpose of improving the contrast ratio, stabilizing the potential level of the data line, and reducing line unevenness on the display screen. In this circuit, the precharge signal is supplied to reduce the load when the data signal is written to the data line. For example, Japanese Patent Laid-Open No. 7-295520 discloses an example of such a precharge circuit. On the other hand, the inspection circuit is a circuit for inspecting the quality, defects, and the like of the liquid crystal device in the middle of manufacture and at the periphery of the peripheral parting 53 and the peripheral portion of the TFT array substrate.
[0082]
In the above embodiment, as disclosed in JP-A-9-127497, JP-B-3-52611, JP-A-3-125123, JP-A-8-171101, etc. A light shielding layer made of a refractory metal such as W (tungsten) or Mo (molybdenum) or a metal silicide may be provided on the array substrate 1 at a position facing the TFT 30 (that is, below the TFT 30). If a light shielding layer is also provided below the TFT 30 as described above, it is possible to prevent the return light from the TFT array substrate 1 from entering the TFT 30 in advance. Therefore, the liquid crystal device 200 can be suitably used as a light valve for a liquid crystal projector.
[0083]
Furthermore, in the above embodiment, the switching element may be composed of a two-terminal nonlinear element such as MIM (Metal Insulator Metal) instead of the TFT 30. In this case, one of the data line and the scanning line is arranged on the counter substrate to function as a counter electrode, and a switching element is arranged between the other line provided on the TFT array substrate and the pixel electrode. LCD drive. Even in such a configuration, the pixel signal line and the data line are shielded from the clock signal line, so that the effect of preventing the high-frequency clock noise from jumping into the image signal and the data signal is exhibited.
[0084]
(Operation of liquid crystal device)
Next, the operation of the liquid crystal device 200 configured as described above will be described with reference to FIG.
[0085]
First, the scanning line driving circuit 104 applies scanning signals to the scanning lines 31 in a pulse-sequential manner at predetermined timing.
[0086]
In parallel with this, if parallel image signals are received from the 12 wires VID1 to VID12,
The ring circuit 301 samples these image signals. The data line driving circuit 101 supplies a sampling circuit driving signal for each data line for each of the twelve wirings VID1 to VID12 in accordance with the timing at which the scanning line driving circuit 104 applies the gate voltage. The TFT 302 is turned on. Thereby, the sampled data signal is sequentially applied to the 12 adjacent data lines 35 to the sampling circuit 301. That is, the 12-phase expanded parallel image signals VID 1 to VID 12 input from the wirings VID 1 to VID 12 by the data line driving circuit 101 and the sampling circuit 301 are supplied to the data line 35.
[0087]
As described above, in the TFT 30 to which both the scanning signal (gate voltage) and the data signal (source voltage) are applied, the pixel electrode 11 is connected to the pixel region 11 via the source region 34 and the channel and drain region 36 formed in the semiconductor layer 32. A voltage is applied. The voltage of the pixel electrode 11 is held by the storage capacitor (see FIG. 9) for a time that is, for example, three orders of magnitude longer than the time when the source voltage is applied. In particular, since the wirings VID1 to VID12 are shielded from the wirings CLX and CLX ′ and the wirings ENB1 and ENB2 by the shield lines 80, 80 ′, 82 and 86, even when the frequency of the clock signal CLX is high. Jumps such as high-frequency clock noise from CLX and CLX ′ and the wirings ENB1 and ENB2 to the wirings VID1 to VID12 can be reduced.
[0088]
As described above, when a voltage is applied to the pixel electrode 11, the alignment state of the liquid crystal in the portion of the liquid crystal layer 50 sandwiched between the pixel electrode 11 and the common electrode 21 changes. In accordance with the applied voltage, incident light cannot pass through the liquid crystal part. In the normally black mode, incident light can pass through the liquid crystal part according to the applied voltage. The liquid crystal panel 10 emits light having a contrast corresponding to the image signal.
[0089]
As a result, even when high-resolution serial image signals VID1 to VID12 are input, an image to be displayed has high resolution, while using a clock signal CLX having a high frequency correspondingly. The image quality is hardly or completely deteriorated by the occurrence, and high-quality image display is possible. In addition, as a result of phase expansion into a relatively large number of phases, ie, 12-phase expansion, sampling can be performed by a normal performance sampling circuit by reducing the frequency of the image signal.
[0090]
(Electronics)
Next, an embodiment of an electronic apparatus provided with the liquid crystal device 200 described in detail above will be described with reference to FIGS.
[0091]
First, FIG. 11 shows a schematic configuration of an electronic apparatus including the liquid crystal device 200 as described above.
[0092]
In FIG. 11, the electronic device includes a display information output source 1000, a display information processing circuit 1002, a drive circuit 1004, a liquid crystal panel 10, a clock generation circuit 1008, and a power supply circuit 1010. The display information output source 1000 includes a ROM (Read Only Memory), a RAM (Random Access Memory), a memory such as an optical disk device, a tuning circuit that tunes and outputs a television signal, and the like. Based on this, display information such as an image signal in a predetermined format is output to the display information processing circuit 1002. The display information processing circuit 1002 includes various known processing circuits such as an amplification / polarity inversion circuit, a phase expansion circuit, a rotation circuit, a gamma correction circuit, and a clamp circuit, and a display input based on a clock signal. A digital signal is sequentially generated from the information and output to the drive circuit 1004 together with the clock signal CLK. The drive circuit 1004 drives the liquid crystal panel 10. The power supply circuit 1010 supplies predetermined power to the above-described circuits. Note that the drive circuit 1004 may be mounted on the TFT array substrate constituting the liquid crystal panel 10, and in addition to this, the display information processing circuit 1002 may be mounted.
[0093]
Next, FIGS. 12 to 15 show specific examples of the electronic apparatus configured as described above.
[0094]
In FIG. 12, a liquid crystal projector 1100 as an example of an electronic device prepares three liquid crystal modules including the liquid crystal panel 10 in which the driving circuit 1004 described above is mounted on a TFT array substrate, and RGB light valves 100R and 100G, respectively. And as a projector used as 100B. In the liquid crystal projector 1100, when projection light is emitted from a lamp unit 1102 of a white light source such as a metal halide lamp, light components R, G, and R corresponding to the three primary colors of RGB are obtained by three mirrors 1106 and two dichroic mirrors 1108. B is divided into the light valves 100R, 100G and 100B corresponding to the respective colors. At this time, in particular, the B light is guided through a relay lens system 1121 including an incident lens 1122, a relay lens 1123, and an exit lens 1124 in order to prevent light loss due to a long optical path. The light components corresponding to the three primary colors modulated by the light valves 100R, 100G, and 100B are synthesized again by the dichroic prism 1112 and then projected as a color image on the screen 1120 via the projection lens 1114.
[0095]
In the present embodiment, in particular, if a light shielding layer is also provided on the lower side of the TFT as described above, the reflected light and incident light from the projection optical system in the liquid crystal projector based on the incident light from the liquid crystal panel 10 are not generated. Reflected light from the surface of the TFT array substrate when passing, part of incident light (part of R light and G light) that penetrates the dichroic prism 1112 after being emitted from another liquid crystal panel, etc. as return light Even if the light is incident from the TFT array substrate side, it is possible to sufficiently shield light from a channel such as a pixel electrode switching TFT. In this case, even if a prism suitable for miniaturization is used in the projection optical system, an AR film for preventing return light is attached between the TFT array substrate of each liquid crystal panel and the prism, or an AR film treatment is applied to the polarizing plate. It is very advantageous to make the configuration small and simple.
[0096]
In FIG. 13, a laptop personal computer (PC) 1200 compatible with multimedia, which is another example of an electronic device, includes the above-described liquid crystal panel 10 in a top cover case, and further includes a CPU, a memory, a modem, and the like. And a main body 1204 in which a keyboard 1202 is incorporated.
[0097]
In FIG. 14, a pager 1300 as another example of an electronic device includes a light guide including a backlight 1306a, in which a liquid crystal panel 10 in which the driving circuit 1004 is mounted on a TFT array substrate in a metal frame 1302 to form a liquid crystal module. 1306, a circuit board 1308, first and second shield plates 1310 and 1312, two elastic conductors 1314 and 1316, and a film carrier tape 1318. In the case of this example, the display information processing circuit 1002 (see FIG. 11) described above may be mounted on the circuit board 1308 or on the TFT array substrate of the liquid crystal panel 10. Further, the above-described drive circuit 1004 can be mounted on the circuit board 1308.
[0098]
14 is a pager, a circuit board 1308 and the like are provided. However, in the case of the liquid crystal panel 10 in which the driving circuit 1004 and the display information processing circuit 1002 are mounted to form a liquid crystal module, a liquid crystal device in which the liquid crystal panel 10 is fixed in a metal frame 1302 is used as or in addition to the liquid crystal device. As a backlight type liquid crystal device incorporating the light guide 1306, it is possible to produce, sell, use, and the like.
[0099]
As shown in FIG. 15, in the case of the liquid crystal panel 10 in which the driving circuit 1004 and the display information processing circuit 1002 are not mounted, an IC 1324 including the driving circuit 1004 and the display information processing circuit 1002 is mounted on a polyimide tape 1322. (Tape Carrier Package) 1320 can be physically and electrically connected to the periphery of the TFT array substrate 1 through an anisotropic conductive film to produce, sell, use, etc. as a liquid crystal device Is possible.
[0100]
In addition to the electronic devices described above with reference to FIGS. 12 to 15, a liquid crystal television, a viewfinder type or a monitor direct-view type video tape recorder, a car navigation device, an electronic notebook, a calculator, a word processor, an engineering workstation ( EWS), a mobile phone, a video phone, a POS terminal, a device equipped with a touch panel, and the like are examples of the electronic device shown in FIG.
[0101]
As described above, according to the present embodiment, the generation of high-frequency clock noise is reduced, high-quality image display is possible, and the screen display area is larger than the substrate size. Various electronic devices equipped with can be realized.
[0102]
[Appendix]
Appendix 1. The electro-optical device includes a plurality of data lines on a substrate, a plurality of scanning lines intersecting the plurality of data lines, a plurality of switching elements connected to the plurality of data lines and the scanning lines, and the plurality of the plurality of data lines. A plurality of pixel electrodes connected to the switching element; a plurality of image signal lines to which an image signal is supplied; a plurality of control signal lines to which a control signal including a clock signal is supplied; the image signal line and the control signal Data signal supply means for inputting the image signal and the control signal through each line, and supplying a data signal corresponding to the image signal to the plurality of data lines based on the control signal, Of the plurality of image signal lines, the first image signal line group is routed to one side of the data signal supply means on the substrate, and the second image signal line group of the plurality of image signal lines is the Base And at least one conductive line that is routed to the other side of the data signal supply means and electrically shields the first and second image signal line groups from the plurality of control signal lines, respectively. It is further provided on the substrate.
[0103]
According to this electro-optical device, the image signal is supplied to the data signal supply means via the image signal line. In parallel with this, a control signal including a clock signal, an enable signal and the like is supplied to the data signal supply means via the control signal line. Then, a data signal corresponding to an image signal is supplied to a plurality of data lines based on the control signal by a data signal supply unit configured to include, for example, a data line driving circuit and a sampling circuit. Here, in particular, the image signal lines are electrically shielded from control signal lines such as a clock signal line and an enable signal line by conductive lines wired on the substrate. Therefore, even when the frequency of the clock signal is high, it is possible to reduce the jumping of high-frequency clock noise or the like from the control signal line such as the clock signal line to the image signal line.
[0104]
On the other hand, a scanning signal is supplied to the switching element via the scanning line by scanning signal supply means including a scanning line driving circuit or the like formed on the substrate or connected to the substrate. In parallel with this, the data signal corresponding to the image signal with reduced high-frequency clock noise and the like as described above is supplied to the switching element via the data line, and further supplied via the switching element. As a result, the voltage applied to the pixel electrode changes, and the liquid crystal facing the pixel electrode is driven.
[0105]
As a result, the resolution of the image to be displayed is high. For example, even when an image signal that has been developed in multiple phases is input, the image quality is hardly or completely deteriorated due to the occurrence of high-frequency clock noise or the like. Image display is possible. Moreover, the first image signal line group is routed to one side of the data signal supply means on the substrate, and the second image signal line group is routed to the other side of the data signal supply means on the substrate. ing. Therefore, for example, a large number of image signal lines corresponding to multi-phase expansion while lowering the frequency of the image signal supplied to the data signal supply means by increasing the number of phase expansions such as 12-phase expansion, 24-phase expansion,. Can be arranged with good balance on both sides of the data signal supply means. As a result, it is possible to easily secure an area for forming the data signal supply means including the sampling circuit or the sampling circuit, the data line driving circuit, and the like on the substrate. Therefore, it is possible to increase the size of the screen with a limited substrate size.
[0106]
Appendix 2. In the electro-optical device according to appendix 1, the conductive line includes a high-frequency control signal line that supplies a high-frequency control signal having a period shorter than at least a horizontal scanning period of the image signal among the plurality of control signal lines. The first and second image signal line groups are shielded.
[0107]
According to this electro-optical device, the image signal line is electrically shielded from the high-frequency control signal line that supplies a high-frequency control signal (for example, a clock signal, an enable signal, etc.) among the plurality of control signal lines by the conductive line. ing. Therefore, even when the frequency of the clock signal is high, jumping of high-frequency clock noise or the like from the high-frequency control signal line to the image signal line can be reduced. Note that a low-frequency control signal (for example, a start signal for a shift register in a data line driving circuit) does not cause high-frequency noise in an image signal or a data signal. The wire may or may not be shielded with a conductive wire.
[0108]
Appendix 3. In the electro-optical device according to attachment 2, between the first and second image signal line groups and the high-frequency control signal line, at least the horizontal of the image signal among the plurality of control signal lines together with the conductive line. A low frequency control signal line for supplying a low frequency control signal having a period not shorter than the scanning period is provided.
[0109]
According to this electro-optical device, the image signal lines located on the side closer to the high-frequency control signal line in the first and second image signal line groups are at least a total of two low-frequency control signal lines and conductive lines. Due to the presence of the wiring, it is separated from the high-frequency control signal line and is electrically shielded. That is, a low frequency control signal line that supplies a low frequency control signal (for example, a start signal for a shift register in a data line driving circuit) that does not cause high frequency noise in an image signal or a data signal is connected to the high frequency control signal. By arranging it together with the conductive line between the line and the image signal line, it is possible to further reduce adverse effects such as clock noise on the image signal line of the high frequency control signal line. In particular, since electromagnetic waves generally decrease according to the distance and the presence of obstacles, a configuration in which as many conductive lines and low-frequency control signal lines as possible are arranged between the control signal line and the image signal line, from the high-frequency control signal line. Electromagnetic waves applied to the image signal lines are reduced. As described above, it is advantageous from the viewpoint of effective use of the space on the substrate and noise reduction to interpose the low frequency control signal line in addition to the conductive line between the high frequency control signal line and the image signal line.
[0110]
Appendix 4. The electro-optical device according to attachment 1, wherein a plurality of first external input terminals that are connected to the first image signal line group and to which the image signals are input from an external image signal source, and the second image signal lines. A plurality of second external input terminals that are connected to a group and to which the image signal is input from the external image signal source, respectively, and the control signal that is connected to the control signal line and that is input from the external control signal source. A plurality of third external input terminals and a plurality of fourth external input terminals respectively connected to the conductive wires on the periphery of the substrate, and between the first and second external input terminals. The third external input terminal is disposed, and the fourth external input terminal is disposed between the first and third external input terminals and between the third and second external input terminals. It is characterized by being.
[0111]
According to this electro-optical device, the plurality of first and second external input terminals connected to the first and second image signal line groups are connected to the control signal line on the peripheral portion of the substrate. A plurality of third external input terminals are arranged. That is, a plurality of third external input terminals connected to the control signal line are centrally arranged on the periphery of the substrate on which the first to fourth external input terminals are provided, and the first and A plurality of first and second external input terminals respectively connected to the second image signal line group are arranged. And between these, the 4th external input terminal connected to the conductive wire is arranged. Accordingly, it is possible to easily obtain a configuration in which a distance is placed on the substrate between the first and second image signal line groups and the control signal line, and a conductive line is wired between them. In particular, it is possible to effectively prevent a control signal such as a clock signal from generating clock noise or the like with respect to an image signal before being input to the electro-optical device. If a plurality of external input terminals connected to the image signal line and a plurality of external input terminals connected to the control signal line are mixed or adjacent to each other, before being input to the electro-optical device. At this stage, the wiring portion where the image signal line and the control signal line are adjacent or close to each other becomes inevitable, and clock noise or the like jumps into the image signal. As described above, according to the present invention, it is possible to reduce high-frequency clock noise jumping from the clock signal line to the image signal line before and after being input to the electro-optical device. More preferably, in the region where the external input terminal can be formed in the peripheral portion of the substrate, the first and second external input terminals are arranged as close to both sides as possible, and the third arranged between them. A fourth external input terminal connected to the conductive line is arranged at a distance from the external input terminal as much as possible.
[0112]
Appendix 5. In the electro-optical device according to appendix 4, the conductive line includes a high-frequency control signal line that supplies a high-frequency control signal having a cycle shorter than a horizontal scanning period of the image signal among the plurality of control signal lines. The first and second image signal line groups are shielded, and the terminal adjacent to the fourth external input terminal among the third external input terminals is at least from the horizontal scanning period of the image signal among the plurality of control signal lines. It is also characterized in that it is connected to a low frequency control signal line that supplies a low frequency control signal having a cycle that is not short.
[0113]
According to this electro-optical device, the image signal line is electrically shielded from the high-frequency control signal line by the conductive line. Here, in particular, the terminal adjacent to the fourth external input terminal connected to the conductive line among the third external input terminals connected to the control signal line is connected to the low frequency control signal line. Is separated from the high-frequency control signal line and is electrically shielded by the presence of at least two wirings of the low-frequency control signal line and the conductive line.
[0114]
Appendix 6. The electro-optical device according to appendix 1, wherein the conductive line includes a portion composed of a data line driving constant potential line that supplies a constant potential data line driving power source to the data signal supply means. To do.
[0115]
According to this electro-optical device, the conductive line includes a portion composed of a data line driving constant potential line for supplying a constant potential data line driving power source to the data signal supply means. By sharing the device itself, in other words, by extending the constant potential line to be a conductive wire, the configuration can be simplified and the space can be saved. In particular, it is extremely easy to set the conductive wire to a constant potential. It becomes.
[0116]
Appendix 7. The electro-optical device according to appendix 6, wherein the data line driving constant potential line includes first and second constant potential lines for supplying power of different constant potentials to the data signal supply means. The conductive line portion formed of a potential line surrounds the first and second image signal line groups on the substrate, and the conductive line portion formed of the second constant potential line is formed on the substrate. The control signal line is surrounded on one substrate.
[0117]
According to this electro-optical device, the first and second image signal line groups are surrounded on the substrate by the conductive line portion formed of, for example, the first constant potential line for supplying a negative power supply having a ground potential. Yes. The control signal line is surrounded on the substrate by a conductive line portion made up of a second constant potential line for supplying positive power, for example. Therefore, the image signal line is double-shielded from the control signal line on the first substrate.
[0118]
Appendix 8. The electro-optical device according to any one of appendices 1 to 7, wherein the conductive line extends so as to surround a screen display region defined by the plurality of pixel electrodes and the plurality of data lines on the substrate. It is characterized by that.
[0119]
According to this electro-optical device, since the screen display area and the plurality of data lines are surrounded on the substrate by the conductive lines, the screen display area and the plurality of data lines are also control signal lines such as clock signal lines. Will be shielded from. Therefore, it is possible to reduce the occurrence of high-frequency clock noise or the like in the data signal output from the data signal supply means, the data signal reaching the switching element or the pixel electrode, and the like.
[0120]
Appendix 9. The electro-optical device according to appendix 8, wherein a counter substrate is provided to face the substrate, and the light-shielding periphery is formed on at least one of the substrate and the counter substrate along the outline of the screen display region The conductive line further includes a part provided on the substrate along the peripheral parting at a position facing the peripheral parting.
[0121]
According to this electro-optical device, since the conductive lines are provided under the periphery of the substrate, space saving on the TFT array substrate can be achieved. For example, the scanning line driving circuit and the data line driving circuit are arranged on the substrate. The peripheral portion can be formed with a margin, and there is little or no reduction in the effective display area in the liquid crystal device due to the formation of the conductive lines.
[0122]
Appendix 10. The liquid crystal device according to any one of appendices 1 to 9, wherein the conductive line and the data line are formed of the same low-resistance metal material.
[0123]
According to this electro-optical device, since the conductive line is made of the same low-resistance metal material as the data line, such as Al (aluminum), the conductive line is long even if the lead-out area of the conductive line is long. The resistance is sufficiently low for practical use. That is, without lowering the shielding effect due to the increase in resistance, for example, the gap between other wirings and circuits can be sewn and the conductive lines can be extended in a zigzag pattern, or the conductive lines can be extended over a wide area including the screen display area. Since wiring becomes possible, the effect of the shield as a whole can be further enhanced with a relatively simple configuration. Furthermore, in the manufacturing process of the electro-optical device, the conductive line and the data line can be formed from the same low-resistance metal material in the same process. That is, an increase in the manufacturing process due to the formation of the conductive line can be minimized.
[0124]
Appendix 11. The electro-optical device according to any one of appendices 1 to 10, further comprising a capacitor line that applies a predetermined amount of capacitance to the pixel electrode, wherein the capacitor line is connected to the conductive line. And
[0125]
According to this electro-optical device, since a predetermined amount of capacitance is applied to the pixel electrode by the capacitance line, high-definition display is possible even when the duty ratio is small. The capacitor line is connected to the conductive line. Therefore, adverse effects on the switching element and the pixel electrode due to the potential fluctuation of the capacitor line are prevented. Moreover, the wiring for setting the capacitance line to a constant potential can be used also as the conductive line, and the external input terminal necessary for setting the capacitance line to the constant potential is, for example, dedicated to the third external input terminal or the conductive line described above. Can also be used as an external input terminal.
[0126]
Appendix 12. 12. The electro-optical device according to any one of appendices 1 to 11, further comprising a scanning signal supply unit on the substrate for sequentially supplying a scanning signal to the plurality of scanning lines, wherein the conductive line is the scanning line. It includes a portion constituted by a scanning line driving constant potential line for supplying a scanning line driving power source of constant potential to the signal supply means.
[0127]
According to this electro-optical device, the image signal line is electrically shielded from the control signal line by the conductive line portion constituted by the scanning line driving constant potential line. Therefore, even when the frequency of the clock signal is high, jumping of high-frequency clock noise or the like from the control signal line to the image signal line can be reduced.
[0128]
Appendix 13. The electro-optical device according to appendix 12, wherein the scanning signal supply unit is provided on both sides of a screen display region defined by the plurality of pixel electrodes, and is configured of the scanning line driving constant potential line. The conductive line portion extends so as to surround the screen display region and the plurality of data lines on the substrate and to supply the scanning line driving power supply redundantly to the scanning line supply means.
[0129]
According to this electro-optical device, the screen display area and the plurality of data lines are surrounded on the substrate by the conductive line portion formed of the scanning line driving constant potential line. The data line is also shielded from a control signal line such as a clock signal line. Therefore, it is possible to reduce the occurrence of high-frequency clock noise or the like in the data signal output from the data signal supply means, the data signal reaching the switching element or the pixel electrode, and the like. Further, the conductive line portion constituted by the scanning line driving constant potential line is extended so as to supply the scanning line driving power supply redundantly to the scanning line supply means provided on both sides of the screen display area. Therefore, even if a disconnection occurs in the scanning line driving constant potential line in the conductive line portion constituted by the scanning line driving constant potential line or in other portions, it is advantageous because it is difficult to cause a device defect.
[0130]
Appendix 14. 14. The electro-optical device according to claim 1, wherein the data signal supply unit includes a sampling circuit that samples the image signal, and a data line driving circuit that drives the sampling circuit based on the control signal. The image signal lines included in the first image signal line group and the image signal lines included in the second image signal line group are between the data line driving circuit and the sampling circuit, It is characterized in that at least one image signal line is alternately drawn in a comb shape from both sides of the data line driving circuit.
[0131]
According to this electro-optical device, the image signal lines included in the first image signal line group (for example, the image signal lines VID1, 3, 5, 7,... Corresponding to the odd-numbered data lines) and the second image signal lines. The image signal lines included in the group (for example, the image signal lines VID2, 4, 6, 8,... Corresponding to the even-numbered data lines) are at least one image signal line from both sides of the data line driving circuit. It is drawn around alternately in a comb shape. Accordingly, the image signal lines and the data lines can be regularly and well-balanced around the data line driving circuit.
[0132]
Appendix 15. 15. The electro-optical device according to appendix 14, wherein the data signal supply unit inverts the voltage polarity of the data signal for each data line, and the image signal line and the second image included in the first image signal line group. The image signal lines included in the signal line group are alternately routed in a comb shape from both sides of the data line driving circuit with two image signal lines corresponding to two adjacent data lines as a pair. It is characterized by.
[0133]
According to this electro-optical device, the data signal supply means inverts the voltage polarity of the data signal for each data line, so-called inversion driving such as 1S inversion and dot inversion is performed, and flicker on the display screen is reduced. Here, the image signal lines included in the first image signal line group (for example, every two image signal lines VID1, 2, 5, 6... Corresponding to two adjacent data lines) and the second image signal. The image signal lines included in the line group (for example, every two image signal lines VID3, 4, 7, 8,... Corresponding to the two adjacent data lines) are the two adjacent data lines. Two corresponding image signal lines are alternately routed in a comb shape from both sides of the data line driving circuit. Accordingly, image signals having opposite polarities are supplied to adjacent image signal lines, and noise components caused by the same noise source have an effect of canceling each other, thereby reducing noise. This is advantageous.
[0134]
Appendix 16. An electronic apparatus includes the electro-optical device according to any one of appendices 1 to 15.
[0135]
According to this electronic apparatus, the electronic apparatus includes the above-described liquid crystal device of the present invention, which reduces high-frequency clock noise and the like, and enables high-quality image display.
[0136]
【The invention's effect】
According to the electro-optical device of the present invention, since the image signal line is shielded from the control signal line such as the clock signal line by the constant potential conductive line wired on the substrate, the clock signal line to the image signal line. Therefore, it is possible to reduce the jumping in of high-frequency clock noise and the like, and to display a high-quality image in accordance with a high-frequency image signal for displaying a high-resolution image.
[0137]
In addition, according to the electronic device of the present invention, various types of liquid crystal projectors, personal computers, pagers, etc. that can reduce high-frequency clock noise and display a high-quality image with a large screen display area compared to the substrate size. Electronic devices can be realized.
[Brief description of the drawings]
FIG. 1 is a schematic plan view of various wirings including a shield line formed on a TFT array substrate and peripheral circuits in an embodiment of a liquid crystal device.
FIG. 2 is a schematic plan view showing a two-dimensional layout of the shield line in FIG. 1 in more detail.
3 is a circuit diagram (a) and a timing chart (b) in the shift register circuit shown in FIG. 2. FIG.
4 is an AA ′ sectional view (a) and a BB ′ sectional view (b) of a shield line, an image signal line, and a clock signal line formed on the TFT array substrate of FIG. 1. FIG.
5 is an enlarged plan view of an end portion of a screen display area for pixel electrodes, scanning lines, data, etc. formed on the TFT array substrate of FIG. 1; FIG.
6 is a plan view showing an overall configuration of the liquid crystal device of FIG. 1. FIG.
7 is a cross-sectional view showing an overall configuration of the liquid crystal device of FIG. 1. FIG.
8 is a schematic plan view (a) showing an example of a two-dimensional layout of the image signal lines (wirings VID1 to 12) of FIG. 1, and a schematic plan view (b) showing another example.
9 is a cross-sectional view of a TFT portion provided in a screen display region of the liquid crystal device of FIG.
10 is a cross-sectional view of a shield line portion provided in a peripheral parting region of the liquid crystal device of FIG.
FIG. 11 is a block diagram showing a schematic configuration of an embodiment of an electronic device according to the present invention.
FIG. 12 is a cross-sectional view illustrating a liquid crystal projector as an example of an electronic apparatus.
FIG. 13 is a front view showing a personal computer as another example of an electronic apparatus.
FIG. 14 is an exploded perspective view showing a pager as an example of an electronic apparatus.
FIG. 15 is a perspective view showing a liquid crystal device using TCP as an example of an electronic apparatus.
[Explanation of symbols]
1 ... TFT array substrate
2 ... Counter substrate
10 ... LCD panel
11: Pixel electrode
12 ... Alignment film
21 ... Common electrode
22 ... Alignment film
23 ... Light shielding layer
30 ... TFT
31 ... Scanning line (gate electrode)
32 ... Semiconductor layer
33 ... Gate insulating layer
34 ... Source area
35 ... Data line (source electrode)
36 ... Drain region
37, 38 ... contact holes
42. First interlayer insulating layer
43 ... Second interlayer insulating layer
50 ... Liquid crystal layer
52 ... Sealing material
53.
70 ... Storage capacity
80, 80 ', 82, 86 ... shielded wire (constant potential wire)
101: Data line driving circuit
102 ... External input terminal (mounting terminal)
104: Scanning line driving circuit
112 ... Enable circuit
200 ... Liquid crystal device
301: Sampling circuit
302 ... TFT

Claims (6)

A display region including a plurality of pixels on a substrate; a data line driving circuit provided on one side of the substrate for supplying an image signal to the pixel; and a side not facing the data line driving circuit A scanning line driving circuit provided; a clock signal line of a data line driving circuit for supplying a clock signal to the data line driving circuit; a clock signal line of a scanning line driving circuit for supplying a clock signal to the scanning line driving circuit; A clock signal line external terminal of the data line driving circuit connected to the clock signal line of the data line driving circuit, and a clock signal line external of the scanning line driving circuit connected to the clock signal line of the scanning line driving circuit. A terminal, an image signal line group including a plurality of image signal lines for supplying an image signal to the pixel, and an image signal line external terminal connected to the image signal line,
Each external terminal is provided on the one side of the substrate,
A constant potential wiring external terminal connected to a constant potential wiring is provided between the image signal line external terminal of the image signal line group and the clock signal line external terminal of the data line driving circuit, and the image signal line An electro-optical device, wherein a constant potential wiring external terminal connected to a constant potential wiring is provided between an external terminal for clock and a clock signal line external terminal of the scanning line driving circuit.   The electro-optical device according to claim 1, wherein the data line driving circuit includes a plurality of constituent circuits, and a constant potential wiring is disposed between the constituent circuits.   The electro-optical device according to claim 1, wherein the constant potential wiring is disposed between the display region and the scanning line driving circuit.   The electro-optical device according to claim 3, wherein the constant potential wiring is disposed along a peripheral parting that defines the display area.   The electro-optical device according to claim 1, wherein the number of the plurality of image signal lines is the number of layer developments.   An electronic apparatus comprising the electro-optical device according to claim 1.

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