JPH11204795A - Thin film transistor circuit and liquid crystal panel with drive circuit using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce dimensions of a thin film transistor circuit and to reduce the dimensions of a liquid crystal panel having a drive circuit which uses the thin film transistor circuit. SOLUTION: In a NAND gate, first and second n-MOS transistors are arranged so as to position a grounding electrode 6 and an output electrode 4 substantially on one line and also a gate electrode 7 and a gate electrode 8 substantially on one line. The first and, the second n-MOS transistors are connected by a silicon layer 11 which connects the grounding electrode 6 with the output electrode 4. Thus, the dimension in the vertical direction is having in comparison with the conventional one.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a thin film transistor circuit formed on a quartz substrate or a glass substrate and a liquid crystal panel having a driving circuit using the same.

[0002]

2. Description of the Related Art In recent years, liquid crystal panels have been used as flat panel displays in notebook computers, navigation, video cameras, and the like, and as light valves in projectors, and have been commercialized. In notebook computers, high-speed processing and large-capacity CPUs have progressed, and the amount of information has dramatically increased. At the same time, the liquid crystal panel as a man-machine interface has a large screen, high resolution,
High definition display is required. Usually, an active matrix type liquid crystal panel is mainly used for such a liquid crystal panel.

In the active matrix type liquid crystal panel, each pixel is provided with a TFT as a switching element, and each pixel is displayed by selectively turning on and off the TFT by a source signal line and a gate signal line. These signal lines and switching elements are formed by repeating thin film formation, selective etching, and the like on a glass substrate. Conventionally, this TFT has been formed of an amorphous silicon transistor (hereinafter referred to as a-Si). a-Si has sufficient performance to drive a pixel, but has insufficient performance to form a drive circuit for driving a source or gate signal line. Driving line. On the other hand, a polysilicon transistor (hereinafter referred to as p-Si
In this case, since the performance as a semiconductor is high, a part of the signal line driver circuit can be formed over the same substrate by the same process and incorporated. In particular, in recent years, p-Si formation technology using a low-temperature process has been developed, and p-Si
Since Si can be formed, great expectations are placed on cost reduction and power consumption reduction.

[0004]

However, even if p-Si is used, its performance as a semiconductor is still lower than that of single crystal silicon used in ordinary ICs and LSIs, and it is large as a pattern rule. However, the circuit area is considerably large even if the above configuration is adopted.

In particular, liquid crystal panels used in projectors in recent years have become increasingly smaller in panel area, higher in resolution, and extremely small in pixel pitch. When a driving circuit is formed of p-Si in such a liquid crystal panel, if the circuit area is large, the area of the entire panel is not reduced because the driving circuit portion is large, despite the small pixel portion. If the liquid crystal panel is large, the entire projector system becomes large, and portability is lost.

[0006] This is not limited to p-Si, and it goes without saying that the circuit area becomes large if a large-scale circuit is formed of single-crystal silicon. Therefore, the same can be said for a light valve such as a reflective liquid crystal panel using single crystal silicon or a DMD (digital micromirror device) for electrically modulating the tilt of a mirror.

[0007] In addition to the projector, not only the display area but also the so-called frame area of the direct-view type liquid crystal panel can be reduced by forming the drive circuit inside the substrate with p-Si, so that the system size can be reduced. However, when the area of the drive circuit is increased, the frame area is increased.

[0008]

In order to achieve this object, a thin film transistor circuit according to the present invention comprises a first P-MOS transistor and a second P-MOS transistor connected in parallel with each other.
In a CMOS-NAND type thin film transistor circuit in which a MOS transistor, a first N-MOS transistor and a second N-MOS transistor are connected in series, respective gates of the first and second N-MOS transistors The electrode, the output electrode, and the ground electrode are each formed substantially on a straight line, and each has a structure in which they are connected by a silicon semiconductor layer.

Similarly, a first N-MOS transistor and a second N-MOS transistor connected in parallel with each other, and a first P-MOS transistor and a second
CMO with P-MOS transistors connected in series
Also in the S-NOR type thin film transistor circuit, the respective gate electrodes, the output electrode, and the power supply electrode of the first and second P-MOS transistors are formed substantially in a straight line, and each is formed of a silicon semiconductor layer. Take a connected structure.

Similarly, a first P-MOS transistor, a second P-MOS transistor, and a first N-M
An OS transistor and a second N-MOS transistor are connected in series, and a clock pulse signal is supplied to the gate electrodes of the first P-MOS transistor and the second N-MOS transistor. In the clocked CMOS inverter type thin film transistor circuit for inputting an input signal to the gate electrode of the first N-MOS transistor, respectively,
A gate electrode of each of the MOS transistor and the first and second N-MOS transistors, an output electrode and a ground electrode, an output electrode and a power electrode are formed substantially in a straight line, respectively, each of which is a silicon semiconductor layer; Take the structure connected by.

The NAND or NOR having the above-described structure is used.
Using a gate or clocked CMOS inverter,
An RS flip-flop type thin film transistor circuit or a clocked CMOS latch type thin film transistor circuit is formed.

A liquid crystal panel according to the present invention is a drive circuit for driving a source signal line and a gate signal line of an active matrix type liquid crystal panel comprising source signal lines, gate signal lines, and TFTs arranged in a matrix. The thin film transistor circuit described above is used.

In particular, by using a thin film transistor circuit having such a structure for a shift register or a buffer,
By making the width of the unit drive circuit for driving one signal line smaller than the pixel pitch, a liquid crystal panel with a narrow frame can be obtained.

[0014]

Embodiments of the present invention will be described with reference to the drawings.

(First Embodiment) FIG. 1 shows a planar structure of a (first embodiment) of a thin film transistor circuit according to the present invention. FIG. 1 shows a NAND gate, and its logic circuit will be briefly described with reference to the circuit diagram of FIG. N
An AND gate is a basic gate of a logic circuit, and is a read-only memory (ROM) or a programmable logic array (P).
LA), and is commonly used in general.

FIG. 2A shows a logical symbol of a NAND, and an output f is determined by two input signals of inputs A and B. The operation function is shown in FIG. 2 (b). The NAND gate shown here is composed of two PMOS transistors and two nMOS transistors in a CMOS circuit, and has a configuration shown in FIG. 2 (c). The operation of the NAND gate will be described with reference to FIG.

If inputs A and B are both at 0 level, n
1, n2 is turned off, p1 and p2 are turned on, and the output f is 1
Level.

When the input A is at the 1 level and the input B is at the 0 level, n1 and p2 are turned on, n2 and p1 are turned off, and the output f becomes 1 level.

When the input A is at the 0 level and the input B is at the 1 level, n1 and p2 are turned off, n2 and p1 are turned on, and the output f is at 1 level.

When both inputs A and B are at one level, n
1, n2 is turned on, p1 and p2 are turned off, and the output f becomes 0
Level.

FIG. 1 shows a layout when such a NAND gate is formed as an actual device on a silicon substrate or a glass substrate. n-MOS
And p-MOS transistors are basically sources,
A silicon semiconductor layer is formed in a region sandwiched between a source and a drain electrode, and is connected to a gate via an insulating layer. Layer is n + or p
+ Is ion-doped to have a relatively low resistance.

In FIG. 1, reference numerals 1 and 2 denote power supply electrodes, 3, 4, and 5 output electrodes, 6 a ground electrode, 7 and 8 gate electrodes, and 9, 10, and 11 silicon layers. In order to supplement the explanation further, A- in FIG.
A cross-sectional view at A ′ is shown in FIG. FIG. 3 shows an example in which polysilicon is formed as a semiconductor layer on a glass substrate. The electrodes 1 to 6 are made of Al, Cr, Mo, T
It is made of a metal having a relatively low resistance such as i or a thin film of an alloy thereof, and a contact hole indicated by a dotted line is formed in the center of these electrodes so that the electrode can be directly connected to the underlying silicon layer 9. Reference numeral 6 denotes a silicon layer that forms a p-channel, and 7 denotes a silicon layer that forms an n-channel, on which gate electrodes 4 and 5 are formed via an insulating layer 21.

The NAND gate of the present invention shown in FIG. 1 is a first p-MOS transistor comprising a power supply electrode 1, an output electrode 3 and a gate electrode 7, a power supply electrode 2 and an output electrode 5, Second p-M composed of gate electrode 8
An OS transistor, a first n-MOS transistor including an output electrode 4, a silicon layer 11, and a gate electrode 7, a second n-MOS transistor including a ground electrode 6, a silicon layer 11, and a gate electrode 8 Consists of
When an input signal is input to the gate electrodes 7 and 8 and +10 V is applied to the power supply electrodes 1 and 2 and -10 V is applied to the ground electrode 6, an output corresponding to the input signal is obtained at the output electrodes 3, 4, and 5. .

The configuration of a conventional NAND gate is shown in FIG.
Shown in In particular, in the n-MOS transistor, the ground electrode 221 and the output electrode 224 are connected to the first and second n-MOS transistors.
The structure is common to S transistors, and has a structure in which two gate electrodes 222 and 223 are arranged between them, so that the size becomes extremely large in the vertical direction. For example, when a pattern as shown in FIG. 22 is formed by a process rule of a line width of 5 μm, the vertical size is 86 μm.

On the other hand, in the NAND gate of the present invention,
In the first and second n-MOS transistors, as shown in FIG. 1, the ground electrode 6 and the output electrode 4 are substantially on a straight line, and the gate electrode 7 and the gate electrode 8 are also substantially in a straight line. In this case, the vertical size is reduced to 43 μm at the largest portion, which is １ ／ of the conventional size. The first and second n-MOS transistors are connected by a silicon layer 11 connecting the ground electrode 6 and the output electrode 4. At this time, the silicon layer 1
Among them, the resistance value of the shaded portion connecting two n-MOS transistors becomes a problem. If the resistance of this part is too large, the two n-MOS transistors will not operate normally, and this limit is calculated to be about 50 kΩ. If the resistance value is lower than this, the device can be operated without any problem, but the space becomes a problem this time.

In FIG. 1, the grounding electrode 6 and the output electrode 4 and the gate electrodes 7 and 8 are shown to be arranged on one straight line. Does not depart from the gist of the present application.

(Second Embodiment) A thin film transistor circuit according to a (second embodiment) of the present invention is shown in FIG.

In the thin-film transistor circuit shown in FIG. 4, the first n-MOS transistor comprises an output electrode 6, a silicon layer 11 and a gate electrode 7, and a second n-MOS transistor.
The MOS transistor has a ground electrode 6 and a silicon layer 11
And a gate electrode 8.

If space permits, the resistance can be reduced by covering or replacing the low-resistance metal on the hatched portion of the silicon layer 11 as shown in FIG.

As shown in FIG. 4, the first and second n
A region several μm from the overlap between the gate electrode 7 or 8 of the MOS transistor and the silicon layer 11
The reliability may be improved by using a DD (Lightly Doped Drain).

In FIG. 4, the grounding electrode 6 and the output electrode 4 and the gate electrodes 7 and 8 are shown to be arranged on one straight line, but each is shifted from the one straight line. Does not depart from the gist of the present application.

(Third Embodiment) A thin film transistor circuit according to a (third embodiment) of the present invention is shown in FIG.

In the thin-film transistor circuit shown in FIG. 5, the first n-MOS transistor comprises an output electrode 6, a silicon layer 11 and a gate electrode 7, and a second n-MOS transistor.
The MOS transistor has a ground electrode 6 and a silicon layer 11
And a gate electrode 8.

The NAND of the present invention having the configuration shown in FIG.
As shown in FIG. 5, the gate may be configured such that the gate electrode 8 of the second n-MOS transistor and the gate electrode 8 of the second p-MOS transistor are connected across the entire device. .

According to this configuration, the thin film transistor circuit can be made smaller than the conventional example.

In FIG. 5, the ground electrode 6 and the output electrode 4 and the gate electrodes 7 and 8 are shown to be arranged on one straight line, but each is shifted from the one straight line. Does not depart from the gist of the present application.

(Fourth Embodiment) Next, a fourth thin film transistor circuit according to the present invention will be described. FIG. 6 shows a planar structure of a thin film transistor circuit (fourth embodiment) of the present invention. (FIG. 6) is a NOR gate, and its logic circuit will be briefly described with reference to the circuit diagram of FIG.
The NOR gate is also a basic gate of the logic circuit, and is a NAND gate.
Like a gate, it is a basic circuit such as a read-only memory (ROM) or a programmable logic array (PLA), and is commonly used.

FIG. 7A shows a NOR logical symbol, and the output f is determined by two input signals of inputs A and B. FIG. 7B shows the operation function. The NOR gate shown here is 2 in a CMOS circuit.
It comprises two P-MOS transistors and two n-MOS transistors, and has a configuration shown in FIG. 7C. The operation of the NOR gate will be described based on FIG.

If both inputs A and B are at 0 level, n
1, n2 is turned off, p1 and p2 are turned on, and the output f is 1
Level.

When the input A is at level 1 and the input B is at level 0, n1 and p2 are turned on, n2 and p1 are turned off, and the output f is at level 0.

When the input A is at the 0 level and the input B is at the 1 level, n1 and p2 are turned off, n2 and p1 are turned on, and the output f becomes 0 level.

If both inputs A and B are at one level, n
1, n2 is turned on, p1 and p2 are turned off, and the output f becomes 0
Level.

FIG. 6 shows a layout when such a NOR gate is formed as an actual device on a silicon substrate or a glass substrate. Each of the n-MOS and p-MOS transistors basically includes three electrodes of a source, a drain, and a gate. A silicon semiconductor layer is formed in a region sandwiched between the source and the drain electrodes. It is a connected configuration.

In FIG. 6, reference numerals 61 and 62 denote power supply electrodes, 63, 64, and 65 output electrodes, 66 a ground electrode, 67 and 68 gate electrodes, and 69, 70, and 71 silicon layers. The electrodes 61 to 66 are made of Al, Cr, M
It is made of a relatively low-resistance metal such as o or Ti or a thin film of an alloy thereof. A contact hole indicated by a dotted line is formed at the center of these electrodes so that a direct connection with the lower silicon layer 69 can be obtained. . Reference numeral 66 denotes a silicon layer for forming a p-channel, and 67 denotes a silicon layer for forming an n-channel.
4, 65 are formed.

The NOR gate of the present invention shown in FIG. 6 is a first n-MOS transistor comprising a ground electrode 66, an output electrode 64 and a gate electrode 67, and a ground electrode 6
2, a second n-MOS transistor including an output electrode 65 and a gate electrode 68, and a first p-M transistor including an output electrode 63, a silicon layer 70, and a gate electrode 67.
The transistor includes an OS transistor, a second p-MOS transistor including a power supply electrode 61, a silicon layer 70, and a gate electrode 68. When an input signal is input to the gate electrodes 67 and 68 and +10 V is applied to the power supply electrode 61 and -10 V is applied to the ground electrodes 62 and 66, an output corresponding to the input signal is obtained at the output electrodes 63, 64, and 65. .

FIG. 23 shows the structure of a conventional NOR gate. In particular, in the p-MOS transistor, the power supply electrode 231 and the output electrode 234 are first and second p-MOS transistors.
Common to transistors, between which gate electrodes 232 and 2
In the structure in which two 33 are arranged, it becomes very large in the vertical direction. For example, when a pattern as shown in FIG. 23 is formed with a process rule of a line width of 5 μm, the vertical size is 86 μm.

On the other hand, in the NOR gate of the present invention, in the first and second p-MOS transistors, (FIG. 6)
As shown in (2), if the power supply electrode 61 and the output electrode 63 are arranged substantially on a straight line, and the gate electrode 67 and the gate electrode 68 are arranged substantially in a straight line,
The size in the vertical direction is 43 μm where it is the largest, which is reduced to １ ／ of the conventional size. The first and second p-MOS transistors are connected by a silicon layer 70 connecting the power supply electrode 61 and the output electrode 63. At this time, even in the silicon layer 70, the resistance value of the shaded portion connecting the two p-MOS transistors becomes a problem. If the resistance of this part is too large, the two p-MOS transistors will not operate normally, and this limit is calculated to be about 50 kΩ. If the resistance value is lower than this, the device can be operated without any problem, but the space becomes a problem this time. If space permits, it is possible to lower the resistance value by covering or replacing the low-resistance metal on the hatched portion of the partial silicon layer 70.

The power supply electrode 61 and the output electrode 63,
The gate electrodes 67 and 68 need not necessarily be on the same straight line.

The gate electrodes 67 or 68 of the first and second n-MOS transistors and the silicon layer 71 or 6
The area of several μm from the overlapping portion with each of 9 may be made into LDD to improve the reliability.

(Fifth Embodiment) A thin film transistor circuit according to a (fifth embodiment) of the present invention is shown in FIG.

In the thin-film transistor circuit shown in FIG. 8, the first p-MOS transistor is
And a silicon layer 70 and a gate electrode 67,
The p-MOS transistor includes an output electrode 61, a silicon layer 70, and a gate electrode 68.

The NOR gate of the present invention having the structure shown in FIG. 6 has a gate electrode 67 of the first p-MOS transistor and a gate electrode 67 of the first n-MOS transistor as shown in FIG. May be connected across the entire element.

In FIG. 8, the power supply electrode 63 and the output electrode 61 and the gate electrodes 67 and 68 are shown to be arranged on one straight line, but each is shifted from the one straight line. Does not depart from the gist of the present application.

(Sixth Embodiment) Next, the sixth embodiment of the present invention will be described.
Embodiment) will be described. FIG. 9 shows a planar structure of a thin film transistor circuit (sixth embodiment) of the present invention. FIG. 9 shows a clocked CMOS inverter whose logic circuit is shown in FIG.
This will be briefly described with reference to the circuit diagram of FIG. Clocked CM
The OS inverter is opened and closed by a clock pulse.
This is a MOS inverter, a circuit conceived to increase the degree of integration, and is used for clocked CMOS gates, clocked CMOS latches, clocked CMOS flip-flops, and the like.

FIG. 10A shows a logic symbol of the clocked CMOS inverter. The input signal A is inverted to the output f in synchronization with the clock pulse φ and can be taken out. The operation function is shown in FIG. 10 (b). The clocked CMOS inverter shown here is a circuit in which switch elements p2 and n2 that are opened and closed by clock pulses φ and φ * are provided between a power supply VDD, GND and a CMOS inverter in a general CMOS inverter (FIG. 10C). It has a configuration shown in FIG. Clocked CMOS based on (FIG. 10)
The operation of the inverter will be described.

When 1 level is supplied to the clock φ, n
2 and p2 are turned on at the same time, and a CMOS comprising n1 and p1
The inverter inverts the signal input A as an ordinary inverter and transmits it to the output f.

On the other hand, when the 0 level is supplied to the clock φ, n2 and p2 are simultaneously turned off, and the CM composed of n1 and p1 is turned off.
The OS inverter is disconnected from the power supplies VDD and GND, and the output f becomes high impedance.

FIG. 9 shows a layout when such a clocked CMOS inverter is formed as an actual device on a silicon substrate or a glass substrate. Each of the n-MOS and p-MOS transistors basically includes three electrodes of a source, a drain, and a gate. A silicon semiconductor layer is formed in a region sandwiched between the source and the drain electrodes. It is a connected configuration.

In FIG. 9, reference numeral 91 denotes a power supply electrode;
Is an output electrode, 92 is a ground electrode, 94, 95, and 96 are gate electrodes, and 97 and 98 are silicon layers. 91
The electrodes 96 to 96 are made of a relatively low-resistance metal such as Al, Cr, Mo, or Ti, or a thin film of an alloy thereof. A contact hole indicated by a dotted line is formed in the center of these electrodes, and a lower silicon layer 98, 97 can be directly connected. 98 is a silicon layer forming a p-channel, 97 is a silicon layer forming an n-channel,
Gate electrodes 95 and 94 and 94 and 96 are formed on this upper layer via an insulating layer.

The clocked CMO of the present invention shown in FIG.
The S inverter includes a first n-MOS transistor including an output electrode 93, a gate electrode 94, and a silicon layer 97, and a first p-MOS transistor including an output electrode 93, a gate electrode 94, and a silicon layer 98. An inverter is composed of a MOS transistor, a power supply electrode 91 and a silicon layer 9.
8 and a second p-MOS transistor comprising a gate electrode 95, and a grounding electrode 92, a second n-MOS transistor comprising a silicon layer 97 and a gate electrode 96. The input signal is input to the gate electrode 94, and the clock pulse is input to the gate electrodes 95 and 96. When +10 V is applied to the power supply electrode 91 and -10 V is applied to the ground electrode 92, an output obtained by inverting the input signal is obtained at the output electrode 93.

The configuration of a conventional clocked CMOS inverter is shown in FIG. In the p-MOS transistor, the power supply electrode 241 and the output electrode 244 are the first and second electrodes.
And two gate electrodes 242 and 243 are arranged between the p-MOS transistors.
The same applies to the transistor, and the circuit becomes very large in the vertical direction. For example, when a pattern as shown in FIG. 24 is formed by a process rule of 5 μm between line widths, the size in the vertical direction is 99 μm.

On the other hand, in the clocked CMOS inverter of the present invention, in the first and second p-MOS transistors, the power supply electrode 91 and the output electrode 93 are substantially on a straight line as shown in FIG. And the gate electrode 95 and the gate electrode 94 are also substantially aligned, and also in the first and second n-MOS transistors, the ground electrode 92 and the output electrode 93 are positioned substantially on a straight line, If the gate electrode 96 and the gate electrode 94 are also arranged so as to be substantially aligned, the size in the vertical direction is 33 μm at the largest portion, which is reduced to 1/3 of the conventional size.

The first and second p-MOS transistors are formed of a silicon layer 9 connecting the power supply electrode 91 and the output electrode 93.
8 are connected. At this time, the resistance value of the portion of the silicon layer 98 that couples the two p-MOS transistors becomes a problem. If the resistance of this part is too large, the two p-MOS transistors will not operate normally, and this limit is calculated to be about 2 kΩ. If the resistance value is lower than this, the device can be operated without any problem, but the space becomes a problem this time. If space permits, it is possible to lower the resistance value by covering or replacing the partial silicon layer 98 with a metal having a low resistance value. Similarly, the first and second n-MOS transistors are also connected by a silicon layer 97 connecting the ground electrode 92 and the output electrode 93. At this time, even in the silicon layer 97,
The resistance value at the portion connecting the two n-MOS transistors becomes a problem. If the resistance of this part is too large, the two n-MOS transistors will not operate normally,
This limit is calculated to be about 50 kΩ.

The power supply electrode 91, the output electrode 93,
The ground electrode 92, the gate electrodes 94 and 96, and the gate electrodes 94 and 95 need not necessarily be on the same straight line.

(Seventh Embodiment) A thin film transistor circuit according to a (seventh embodiment) of the present invention is shown in FIG.

In the thin-film transistor circuit shown in FIG. 11, the first p-MOS transistor is
1, a silicon layer 98, and a gate electrode 95. The second p-MOS transistor includes an output electrode 93, a silicon layer 98, and a gate electrode 94.

As shown in FIG. 11, the first and second n-
A few μm from the overlapping portion between the gate electrode 96 or 94 of the MOS transistor and the silicon layer 97, respectively.
May be made LDD to improve reliability.

In FIG. 11, the power supply electrode 91 is used.
And the output electrode 93 and the gate electrodes 95 and 94
Although shown as being arranged on a straight line,
The deviation from the straight line does not depart from the gist of the present application.

(Eighth Embodiment) Next, the eighth embodiment of the present invention will be described.
Embodiment) will be described. FIG. 12 shows a planar structure of the thin film transistor circuit of the present invention (eighth embodiment).

FIG. 12 shows an RS flip-flop circuit using two NAND gates. The NAND gate is a thin film transistor circuit of the first embodiment (FIG. 1)
The logic circuit is briefly described with reference to the circuit diagram of FIG. The RS flip-flop circuit crosses a pair of NAND gates to store input data. The stable on / off state is convenient for storing 1-bit information, and is widely used for static memories, counters, and the like.

FIG. 13A shows a logical symbol of the RS flip-flop, in which the input signal A = 1 level and the input signal B
= 0 level or input signal A = 0 level, input signal B
= 1 level, and keeps this stable state unless an external signal is given. FIG. 13B shows the operation function. Two NAND
The configuration shown in FIG. 13 (c) is such that the input of one gate is connected to the output of the other gate, and the input of the other gate is connected to the output of one gate. The operation of the RS flip-flop will be described based on FIG.

When a 1 level is input to the input A and a 0 level is input to the input B, the output Q * becomes 1 level and the output Q becomes 0 level.

Conversely, when a 0 level is input to the input A and a 1 level is input to the input B, the output Q becomes 1 level and the output Q * becomes 0 level.

When the inputs A and B both become 0 level in such a state, the outputs Q and Q * hold data without changing.

However, if both inputs A and B become 0 after both inputs A and B become 1 level, outputs Q and Q * cannot maintain 0 level and both outputs Q and Q * become unknown.

FIG. 12 shows a layout when such an RS flip-flop is formed on a silicon substrate or a glass substrate as an actual device. n
Both the -MOS and p-MOS transistors basically include three electrodes of a source, a drain, and a gate. A silicon semiconductor layer is formed in a region interposed between the source and the drain electrodes, and is connected to the gate via an insulating layer. Configuration.

In FIG. 12, 121, 127, 13
1, 137 are power supply electrodes, 122, 125, 128, 1
33, 135, 136 are output electrodes, 124 and 13
4 is a ground electrode, 123, 126, 132, 138 are gate electrodes, 129 and 130 are electrodes for connecting the gate and the source, and 139 and 140 are silicon layers. The electrodes 121 to 138 are made of a metal having a relatively low resistance such as Al, Cr, Mo, or Ti or an alloy thin film thereof, and a contact hole indicated by a dotted line is formed in the center of these electrodes to form a lower silicon layer or A direct connection with the gate electrode can be obtained. 139 and 140 are n
A silicon layer for forming a channel, on which a gate electrode 123, 126 and 132, 13
8 are formed.

The RS flip-flop of the present invention shown in FIG. 12 has output electrodes 122, 125, 128, gate electrodes 123, 126, a ground electrode 124, and a power supply electrode 1.
21 and 127 and a silicon layer 139, a first NAND gate, and output electrodes 133, 135 and 136.
, Gate electrodes 132 and 138, a ground electrode 134, power supply electrodes 131 and 137, and a second NAND gate composed of a silicon layer 140. Input signal A
Is input to the gate electrode 123, and the input signal B is input to the gate electrode 138. Power supply electrodes 121, 127, 13
1 and 137 are all connected. When +10 V is applied thereto and -10 V is applied to the grounding electrodes 124 and 134,
The output Q is applied to the output electrodes 122, 125, 128,
* Is obtained on the output electrodes 133, 135, and 136.

The input of the first NAND gate and the second NA
The output of the ND gate connects the gate electrode 126 and the output electrode 133 by the gate / source connection electrode 129. The input of the second NAND gate and the output of the first NAND gate connect the gate electrode 132 and the output electrode 128 by the gate / source connection electrode 130.

On the other hand, in the RS flip-flop of the present invention, in the first and second n-MOS transistors, the ground electrode 124 and the output electrode 125 are substantially on a straight line as shown in FIG. And the gate electrode 123 and the gate electrode 126 are also substantially aligned, and also in the third and fourth n-MOS transistors, the ground electrode 134 and the output electrode 135 are positioned substantially on a straight line, and If the gate electrode 132 and the gate electrode 138 are also arranged so as to be substantially aligned, the size in the vertical direction is reduced to 41 μm at the largest portion as compared with the related art.

The output electrode 125 and the ground electrode 12
4. Output electrode 135 and ground electrode 134, and gate electrodes 123 and 126, and gate electrodes 132 and 1.
38 do not necessarily have to be on the same straight line.

Further, the reliability may be improved by making the regions of several μm from the overlapping portions of the gate electrodes of the first to fourth n-MOS transistors and the silicon layer, respectively, LDD.

(Ninth Embodiment) Next, the ninth embodiment of the present invention will be described.
Embodiment) will be described. FIG. 14 shows a planar structure of a ninth embodiment of the thin film transistor circuit of the present invention.

(FIG. 14) shows an R using two NOR gates.
This is an S flip-flop circuit. The NOR gate is (second
Embodiment 2), and its logic circuit will be briefly described with reference to the circuit diagram of FIG. 15. The RS flip-flop circuit crosses a pair of two NOR gates to store input data. The stable on / off state is convenient for storing 1-bit information, and is widely used for static memories, counters, and the like.

FIG. 15A shows a logical symbol of the RS flip-flop, in which the input signal A = 1 level and the input signal B
= 0 level or input signal A = 0 level, input signal B
= 1 level, and keeps this stable state unless an external signal is given. FIG. 15B shows the operation function. From the inputs of one of the two NOR gates to the output of the other,
The configuration shown in FIG. 15C is such that the input of the other gate is connected back to the output of one gate.
The operation of the RS flip-flop will be described based on FIG.

When a 1 level is input to the input A and a 0 level is input to the input B, the output Q * becomes the 0 level and the output Q becomes the 1 level.

On the contrary, when the input A has a 0 level and the input B has a 1 level, the output Q has the 0 level and the output Q * has the 1 level.

When the inputs A and B both become 0 level in such a state, the outputs Q and Q * hold data without changing.

However, if both the inputs A and B become 1 after both the inputs A and B become 1 level, the outputs Q and Q * cannot maintain the 0 level and both outputs Q and Q * become unknown.

FIG. 14 shows a layout when such an RS flip-flop is formed as an actual device on a silicon substrate or a glass substrate. n
Both the -MOS and p-MOS transistors basically include three electrodes of a source, a drain, and a gate. A silicon semiconductor layer is formed in a region interposed between the source and the drain electrodes, and is connected to the gate via an insulating layer. Configuration.

In FIG. 14, 141, 147, 15
1, 157 are grounding electrodes, 142, 145, 148, 1
53, 155 and 156 are output electrodes, 144 and 15
4 is a power supply electrode, 143, 146, 152, and 158 are gate electrodes, 149 and 150 are electrodes for connecting a gate and a source, and 159 and 160 are silicon layers. The electrodes 141 to 158 are made of a metal having a relatively low resistance such as Al, Cr, Mo, or Ti, or a thin film of an alloy thereof. A contact hole indicated by a dotted line is formed in the center of these electrodes, and a lower silicon layer or A direct connection with the gate electrode can be obtained. 159 and 160 are p
A silicon layer for forming a channel, on which a gate electrode 143, 146 and 152, 15
8 are formed.

The RS flip-flop of the present invention shown in FIG. 14 is composed of output electrodes 142, 145, 148, gate electrodes 143, 146, ground electrodes 141, 147, a power electrode 144, and a silicon layer 159. A first NOR gate, output electrodes 153, 155, 156, gate electrodes 152, 158, and ground electrodes 151, 157.
And a second NOR gate composed of the power supply electrode 154 and the silicon layer 160. An input signal A is input to the gate electrode 143, and an input signal B is input to the gate electrode 15
Enter 8 Grounding electrodes 141, 147, 151, 1
57 are all connected. When -10 V is applied thereto and +10 V is applied to the power supply electrodes 144 and 154, the output Q
Are obtained at the output electrodes 142, 145, and 148, and the output Q * is obtained at the output electrodes 153, 155, and 156.

The input of the first NOR gate and the second NOR gate
The output of the gate is provided by the gate / source connection electrode 149.
The gate electrode 146 and the output electrode 153 are connected. The input of the second NOR gate and the output of the first NOR gate connect the gate electrode 152 and the output electrode 148 by the gate / source connection electrode 150.

On the other hand, in the RS flip-flop of the present invention, in the first and second p-MOS transistors, the power supply electrode 144 and the output electrode 145 are substantially in a straight line as shown in FIG. And the gate electrode 143 and the gate electrode 146 are also substantially aligned, and also in the third and fourth p-MOS transistors, the power supply electrode 154 and the output electrode 155 are positioned substantially on a straight line, and If the gate electrode 152 and the gate electrode 158 are also arranged so as to be substantially aligned, the size in the vertical direction is reduced to 41 μm at the maximum, compared to the conventional case.

The output electrode 145 and the power supply electrode 14
4. Output electrode 155 and power supply electrode 154, and gate electrodes 143 and 146 and gate electrodes 152 and 1
58 do not necessarily have to be on the same straight line.

Using the RS flip-flops of the fourth and fifth thin film transistors of the present invention, it is possible to configure a latch circuit as described below.

FIG. 16 is a circuit diagram of a latch circuit using an RS flip-flop circuit according to (eighth embodiment) of the present invention. This is a configuration in which two NAND gates and one inverter are added to the RS flip-flop, and when a clock pulse is input, information is written and held in the circuit.

The operation will be described.
When the clock CLK becomes 1 level, the point A becomes 1
Level, point B is 0 level, output Q * is 1 level,
The output Q becomes 0 level. Here, when the clock CLK goes to the 0 level, both the points A and B go to the 1 level, and the flip-flop is held regardless of the input data.

Next, when the input data D is set to 1 level and the clock CLK is set to 1 level, the point A becomes 0 level and the point B becomes
Becomes 1 level, the output Q becomes 1 level, and the output Q * becomes 0 level. When the clock CLK goes to the 0 level, both the points A and B go to the 1 level regardless of the input data, and the flip-flop enters the holding state.

The same operation can be realized by the latch circuit shown in FIG. Also in this case, the RS flip-flop shown in the eighth embodiment and the N flip-flop shown in the first embodiment are used.
It is obtained by connecting two AND gates as shown in FIG.

(Tenth Embodiment) Further, a thin film transistor circuit according to a (tenth embodiment) of the present invention will be described. (10th embodiment)
(Embodiment 2) is shown in FIG.

FIG. 18 shows a latch circuit using two clocked CMOS inverters and one inverter. The clocked CMOS inverter is the one shown in the thin film transistor circuit of the third embodiment (FIG. 5), and its logic circuit will be briefly described with reference to the circuit diagram of FIG. The latch circuit is a circuit that captures input data with a clock pulse as a synchronization signal and temporarily stores the input data. The latch circuit has a function of outputting asynchronous input data in synchronization with the edge of the clock pulse. This is an indispensable circuit for the register.

FIG. 19A shows the logic symbol of the clocked CMOS latch circuit, and FIG. 19B shows its operation function, and FIG. 19C shows the logical symbol of the clocked CMOS latch circuit. Has become. This operation will be described with reference to FIG.

When input data D is at level 0, clock φ
Becomes 1 level, the first clocked inverter is turned on, the second clocked inverter is turned off, the point A becomes 0 level, and the output Q becomes 0 level.

Here, when the clock φ becomes 0 level, the first
Is turned off, the second clocked inverter is turned on, and the 0 level at point A is maintained.

When the input data D becomes 1 level and the clock φ becomes 1 level, the first clocked inverter is turned on, the second clocked inverter is turned off, the point A becomes 1 level, and the output Q1 level and Become.

Here, when clock φ goes to 0 level, the first
Is turned off, the second clocked inverter is turned on, and one level at the point A is maintained.

FIG. 18 shows a layout when such a clocked CMOS latch circuit is formed on a silicon substrate or a glass substrate as an actual device. Each of the n-MOS and p-MOS transistors basically includes three electrodes of a source, a drain, and a gate. A silicon semiconductor layer is formed in a region sandwiched between the source and the drain electrodes. It is a connected configuration.

In FIG. 18, 181 191 19
4 is a power supply electrode, 184, 190, 197 are output electrodes, 184, 189, 198 are ground electrodes, 182, 1
83, 185, 188, 193, 196, and 199 are gate electrodes, and 187, 192, and 195 are electrodes for connecting the gate and the source. These electrodes are Al, Cr,
It is made of a relatively low-resistance metal such as Mo or Ti or a thin film of an alloy thereof, and a contact hole indicated by a dotted line is formed in the center of these electrodes.

The clocked CM of the present invention shown in FIG.
The OS latch circuit includes an output electrode 184 and a gate electrode 18.
2, 183, 185, grounding electrode 186, and power supply electrode 1
81, a first clocked inverter comprising:
Output electrode 197 and gate electrodes 193, 196, 199
, A second clocked inverter composed of a ground electrode 198 and a power electrode 194, an output power source 190, a gate electrode 188, a ground electrode 189, and a power electrode 191.
And an inverter composed of Input signal D is input to gate electrode 183, clock φ is applied to gate electrodes 182 and 193, and clock φ * is applied to gate electrode 1
85 and 199. Grounding electrodes 186, 18
9, 198 to -10 V, power supply electrodes 181, 191, 1
When +10 V is applied to the output 94, the output Q becomes the gate electrode 19
6 is obtained.

The output of the first clocked inverter and the input of the inverter are connected by the gate / source connection electrode 187.
The gate electrode 188 and the output electrode 184 are connected. The input of the second clocked inverter and the output of the inverter connect the gate electrode 196 and the output electrode 190 by the gate / source connection electrode 192.

On the other hand, in the clocked CMOS latch circuit of the present invention, in the first and second clocked CMOS inverters, the first and second p-MOS transistors as shown in FIG. The electrode 181 and the output electrode 184 are positioned substantially on a straight line, and the gate electrode 182 and the gate electrode 183 are also substantially aligned. Also in the first and second n-MOS transistors,
The grounding electrode 186 and the output electrode 184 are located substantially on a straight line, and the gate electrode 185 and the gate electrode 18
3 are also arranged substantially in a straight line, and in the third and fourth p-MOS transistors, the power supply electrode 19
4 and the output electrode 197 are positioned substantially on a straight line, and the gate electrode 193 and the gate electrode 196 are also substantially aligned, so that the third and fourth n-MOS transistors also have If the electrode 197 and the gate electrode 196 are arranged substantially in a straight line and the gate electrode 196 and the gate electrode 199 are arranged substantially in a straight line,
The size in the vertical direction is 33 μm at the largest point, which is reduced to 1/3 of the conventional size.

The reliability may be improved by forming LDD in a region of several μm from the overlapping portion between the gate electrode of each of the first to fifth n-MOS transistors and the silicon layer.

(Eleventh Embodiment) The liquid crystal panel of the present invention will be described. FIG. 20 shows a plan view of a liquid crystal panel of the present invention. The liquid crystal panel is of an active matrix type, and includes a gate signal line 203 and a source signal line 204.
Intersect in a matrix, and a TFT 205 and a pixel electrode 206 are formed at the intersection. The TFT 205 is a thin film transistor using polysilicon which is crystallized at a low temperature by laser annealing as a semiconductor.

Gate signal line 203 and source signal line 2
X driver 20 which is a driving circuit for driving the
1 and the Y driver 202 are also formed of a thin film transistor circuit using polysilicon as a semiconductor on the same glass substrate. The X driver 201 sequentially inputs a pulse to the gate signal line 203, and the Y driver 202 inputs a video signal to each source signal line 204. As a result, a predetermined voltage is applied to the pixel electrode 206 selected by the gate signal line 203 and the source signal line 204 using the TFT 205 as a switching element.

X driver 201 and Y driver 202
Are largely divided into a shift register section and a buffer section as drive circuits. Further, since one shift register and one buffer are required for one signal line, this is called a unit drive circuit.

FIG. 21 is a plan view showing the layout of the unit driver circuits of the X driver at the transistor level.

The shift register is provided with the clocked CMOS latch circuit described in the tenth embodiment of the present invention.
The buffer unit uses the NAND gate described in the first embodiment of the present invention. As a result, the unit driver circuit of the X driver has a width of 33 μm, and a small liquid crystal panel can be obtained without increasing the driver area even in a small high-definition XGA panel with a pixel pitch of 40 μm and a diagonal of 2 inches.

Also, in a liquid crystal projection device using the same, the panel size is small, so that the set can be downsized, and a projection device with excellent portability can be realized.

The present embodiment is not limited to low-temperature polysilicon, but may be high-temperature polysilicon or single-crystal silicon used for a reflection-type liquid crystal panel.
It can also be used for a mirror device such as an MD.

[0121]

In the NAND gate, conventionally, the first and second n-MOS transistors are arranged in such a manner that two gate electrodes are arranged in parallel between the same ground electrode and output electrode. There is a problem in that the vertical length from the ground electrode to the output electrode is long.

In the present invention, the first and second n-MOS transistors are arranged in parallel, the ground electrode and the output electrode are arranged so as to be substantially linear, and the respective gate electrodes are also substantially linear. By arranging the first and second n-MOS transistors so as to be connected by a silicon layer connecting the ground electrode and the output electrode, the size in the vertical direction is smaller than that in the related art. Can be reduced by half.

Similarly, in the present invention, the size in the vertical direction can be reduced to half of the conventional size by arranging the first and second p-MOS transistors in parallel in the NOR gate.

Similarly, according to the present invention, the size of the clocked inverter can be reduced. The present invention can also reduce the size of various circuits configured by combining NAND and NOR elements. One example is a circuit such as a flip-flop or a latch.

Further, it is possible to reduce the size of a semiconductor such as an IC or an LSI or a liquid crystal panel in which such elements and circuits are integrated.

[Brief description of the drawings]

FIG. 1 is a plan view of a thin film transistor circuit according to a first embodiment of the present invention;

FIG. 2 is a circuit diagram and operation explanatory diagram of a NAND gate.

FIG. 3 is a cross-sectional view of a thin film transistor circuit according to a first embodiment of the present invention;

FIG. 4 is a plan view of a thin film transistor circuit according to a second embodiment of the present invention;

FIG. 5 is a plan view of a thin film transistor circuit according to a third embodiment of the present invention;

FIG. 6 is a plan view of a thin film transistor circuit according to a fourth embodiment of the present invention;

FIG. 7 is a circuit diagram and operation explanatory diagram of a NOR gate.

FIG. 8 is a plan view of a thin film transistor circuit according to a fifth embodiment of the present invention.

FIG. 9 is a plan view of a thin film transistor circuit according to a sixth embodiment of the present invention.

FIG. 10 is a circuit diagram and operation explanatory diagram of a clocked CMOS inverter.

FIG. 11 is a plan view of a thin film transistor circuit according to a seventh embodiment of the present invention.

FIG. 12 is a plan view of a thin film transistor circuit according to an eighth embodiment of the present invention;

FIG. 13 is a circuit diagram and operation explanatory diagram of an RS flip-flop.

FIG. 14 is a sectional view of a thin film transistor circuit according to a ninth embodiment of the present invention;

FIG. 15 is a circuit diagram and operation explanatory diagram of an RS flip-flop;

FIG. 16 is a circuit diagram of a latch circuit using a flip-flop.

FIG. 17 is a circuit diagram of a latch circuit using a flip-flop.

FIG. 18 is a sectional view of a thin film transistor circuit according to a tenth embodiment of the present invention.

FIG. 19 is a circuit diagram and operation explanatory diagram of a latch circuit using a clocked inverter.

FIG. 20 is a plan view of a liquid crystal panel of the present invention.

FIG. 21 is a plan view of a unit driver circuit of an X driver laid out at a transistor level.

FIG. 22 is a plan view of a conventional NAND circuit.

FIG. 23 is a plan view of a conventional NOR circuit.

FIG. 24 is a plan view of a conventional clocked CMOS inverter circuit.

[Explanation of symbols]

 1, 2 power supply electrode 3, 4, 5 output electrode 6 ground electrode 7, 8 gate electrode 9, 10, 11 silicon layer 12, 13 LDD region

Claims (11)

[Claims] 1. A first P- connected in parallel with each other.
A MOS transistor and a second P-MOS transistor; a first N-MOS transistor and a second N-MOS transistor;
-CMOS in which MOS transistors are connected in series-
In the NAND type thin film transistor circuit, respective gate electrodes of the first and second N-MOS transistors are formed substantially in a straight line, and respective output electrodes of the first and second N-MOS transistors are connected to ground. A thin film transistor circuit having a structure in which the electrodes are formed on a substantially straight line, and each of the electrodes is connected by a silicon semiconductor layer. 2. A first N-parallel connected to each other in parallel with each other.
A MOS transistor and a second N-MOS transistor; a first P-MOS transistor and a second P-MOS transistor;
-CMOS in which MOS transistors are connected in series-
In a NOR type thin film transistor circuit, respective gate electrodes of the first and second P-MOS transistors are formed substantially in a straight line, and respective output electrodes of the first and second P-MOS transistors and a power supply A thin film transistor circuit having a structure in which the electrodes are formed on a substantially straight line, and each of the electrodes is connected by a silicon semiconductor layer. 3. A first P-MOS transistor and a second P-MOS transistor.
P-MOS transistor, a first N-MOS transistor, and a second N-MOS transistor are connected in series, and a clock is applied to the gate electrodes of the first P-MOS transistor and the second N-MOS transistor. The pulse signal is supplied to the second P-MOS transistor and the first N-MOS transistor.
A clocked CMOS inverter thin-film transistor circuit for inputting an input signal to a gate electrode of a MOS transistor, wherein respective gate electrodes of the first and second P-MOS transistors are formed substantially in a straight line; Each gate electrode of the second N-MOS transistor is formed substantially on a straight line, the output electrode and the ground electrode are formed substantially on a straight line, and the output electrode and the power supply electrode are substantially aligned on a straight line. Wherein each of said electrodes is connected by a silicon semiconductor layer. 4. A silicon semiconductor between respective gate electrodes of a first P-MOS transistor and a second P-MOS transistor or respective gate electrodes of a first N-MOS transistor and a second N-MOS transistor. 4. The thin film transistor circuit according to claim 1, wherein a resistance value of a silicon semiconductor between the thin film transistors is 50 kΩ or less. 5. A silicon semiconductor between respective gate electrodes of a first P-MOS transistor and a second P-MOS transistor or a respective gate electrode of a first N-MOS transistor and a second N-MOS transistor. 4. The thin film transistor circuit according to claim 1, wherein a metal thin film for an electrode is connected to a part of the silicon semiconductor therebetween. 6. An input terminal of the first NAND gate is connected to a second NAND gate.
2. An RS flip-flop thin film transistor circuit in which an input terminal of a second NAND gate is connected to an output terminal of the second NAND gate and an output terminal of the second NAND gate. A thin film transistor circuit characterized by using: 7. The input terminal of the first NOR gate is connected to the second NOR gate.
And the input terminal of the second NOR gate is connected to the output terminal of the second NOR gate.
An S flip-flop thin film transistor circuit, wherein the thin film transistor circuit having the structure according to claim 2 is used. 8. An output terminal of the first clocked CMOS inverter and an output terminal of the second clocked CMOS inverter, an input terminal of the second clocked CMOS inverter and an output terminal of the inverter, and a second clocked CMOS inverter. CMO
A clocked CMOS latch thin film transistor circuit in which an output terminal of an S inverter is connected to an input terminal of the inverter, wherein at least one thin film transistor circuit having the structure according to claim 3 is used. 9. Signal lines and TFs arranged in a matrix
9. An active matrix liquid crystal panel comprising T and pixel electrodes, wherein a driving circuit for driving the signal line formed on the same substrate as the liquid crystal panel is provided.
A liquid crystal panel, wherein the thin film transistor circuit according to the above item is used. 10. The liquid crystal panel according to claim 9, wherein a width of a unit drive circuit for driving one signal line is smaller than a pixel pitch. 11. The liquid crystal panel according to claim 9, wherein the semiconductor of the thin film transistor circuit is polysilicon crystallized at a low temperature.