JP2009053660A - Electro-optical device and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce an adverse influence of a light leak and light reflection in a peripheral area of an electro-optical device, such as a liquid crystal device, without making transistor characteristics degradation. <P>SOLUTION: The electro-optical device includes, on a substrate (10), a plurality of pixel electrodes (9a), a transistor (71) provided in a peripheral area surrounding a pixel area (10a) where the plurality of pixel electrodes are arrayed, and a light-shielding film (510) which is disposed below the transistor, overlaps with at least a part of the transistor in plane view on the substrate, and includes a longitudinal opening (510s) formed in a channel length direction of the transistor. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a technical field of an electro-optical device such as a liquid crystal device, and an electronic apparatus such as a liquid crystal projector including the electro-optical device.

  In this type of electro-optical device, a large number of scanning lines and data lines arranged vertically and horizontally in a display area composed of a plurality of pixels, and a large number of pixel electrodes corresponding to the respective intersections thereof are provided on the TFT substrate. It is done. Such an electro-optical device employs, for example, an active matrix driving method by TFT (Thin Film Transistor) driving, and a pixel switching TFT is provided for each pixel. The image signal supplied to the data line is supplied to the pixel electrode in accordance with the switching operation of the pixel switching TFT formed in each pixel, and an image is displayed in the display area. In addition, various peripheral circuits for controlling a plurality of pixels are formed in the peripheral region located around the display region on the TFT array substrate on which the TFT is formed. Such a peripheral circuit includes a transistor such as a TFT.

  For example, Patent Document 1 discloses a technique for reducing deterioration and variation in transistor characteristics by adjusting a coupling capacitance between a light shielding film and a gate electrode or a drain electrode of a transistor.

JP-A-10-70277

  When this type of electro-optical device is used as a light valve of a projector, a part of the transmitted light that has passed through the peripheral circuit in the peripheral region travels obliquely with respect to the display region, so that it is near the edge of the display region. There is a risk of light leakage from the surrounding area. Furthermore, the return light that has entered the peripheral area may be reflected again in the peripheral circuit and eventually be mixed into the light emitted from the display area. As a result, a light / dark pattern corresponding to reflection or transmission in the peripheral circuit (for example, a light / dark pattern corresponding to the arrangement pattern of a plurality of transistors constituting the peripheral circuit) may be displayed near the edge of the display image.

  For this reason, a light-shielding film may be provided on the lower layer side (or the emission side from which light is emitted) of the transistors constituting the peripheral circuit provided near the edge of the display area in the peripheral area on the substrate. Thereby, the adverse effect on the display image due to the light leakage from the peripheral region and the reflection of light in the peripheral circuit can be reduced.

  However, there is a technical problem that the characteristics of the transistor may deteriorate due to the light shielding film disposed on the lower layer side of the transistor constituting the peripheral circuit.

  The present invention has been made in view of the above-described problems, for example, and prevents adverse effects on a display image caused by light leakage or light reflection in the peripheral region without deteriorating the characteristics of the transistors constituting the peripheral circuit, for example. An electro-optical device capable of displaying a high-quality image and an electronic apparatus including such an electro-optical device are provided.

  In order to solve the above problems, a first electro-optical device according to the present invention is provided on a substrate in a peripheral region positioned around a pixel region in which the plurality of pixel electrodes are arranged. A transistor and a lower layer side than the transistor, and when viewed in plan on the substrate, overlap with at least a part of the transistor and form a longitudinal opening along the channel length direction of the transistor A light-shielding film.

  According to the first electro-optical device of the present invention, each of the plurality of pixel electrodes is made of a transparent material such as ITO (Indium Tin Oxide), for example, and the pixel region or the pixel array region (or “image display” on the substrate). The region is also referred to as a region, for example, arranged in a matrix corresponding to the intersection of a plurality of data lines and a plurality of scanning lines. The transistor is provided in a peripheral region located around the pixel region and constitutes at least a part of a peripheral circuit such as a sampling circuit or a data line driver circuit. A plurality of transistors are typically provided along one side of the pixel region. During operation of the electro-optical device, for example, the potential of the pixel electrode is controlled based on an image signal or the like, and image display is performed in a pixel region in which a plurality of pixel electrodes are arranged. The electro-optical device emits display light, for example, through the pixel region in accordance with incident light incident from a light source, for example. The electro-optical device is mounted as a light valve in a projection display device, for example.

  In the present invention, in particular, the light-shielding film is disposed on the lower layer side than the transistor and overlaps at least a part of the transistor when viewed in plan on the substrate. Further, the light shielding film has a longitudinal or slit-shaped opening along the channel length direction of the transistor.

  Typically, the light-shielding film is provided on a lower layer side than the transistor so as to overlap with a semiconductor layer included in the transistor. For example, one light shielding film is provided for each of a plurality of transistors provided along one side of the pixel region, so that a plurality of light shielding films are provided along the one side. The opening is formed in the light shielding film so as to extend along the channel length direction of the transistor (in other words, the carrier flow direction in the transistor) with a width of, for example, 1 μm or less. Further, a plurality of openings are formed at predetermined intervals along the channel width direction of the transistor (that is, the direction intersecting the channel length direction).

  Therefore, light leakage from the peripheral region and re-reflection of return light by the transistor can be reduced or prevented by the light shielding film. Here, “return light” refers to display light emitted from the electro-optical device, such as back-surface reflection on a substrate or light that is emitted from another electro-optical device by a multi-plate projector or the like and penetrates the composite optical system. The light which goes to the side into which incident light injects from the side is meant. Therefore, for example, it is possible to reduce or prevent the bright / dark pattern according to the reflection or transmission of light in the peripheral region, such as the bright / dark pattern according to the arrangement pattern of the plurality of transistors, being displayed near the edge of the display image. That is, it is possible to reduce or prevent adverse effects on the display image due to light leakage or light reflection in the peripheral region.

  Furthermore, since the light shielding film has a longitudinal opening along the channel length direction of the transistor, if the light shielding film is formed in a solid shape without an opening, or in the channel width direction of the transistor, When it is formed so as to have only a longitudinal opening along it, there is little or no deterioration of the transistor characteristics that may be caused by the light shielding film. Such deterioration of the characteristics of the transistor may be caused by, for example, capacitive coupling (that is, capacitive coupling) between the light-shielding film and the transistor, contamination of the semiconductor layer due to the light-shielding film, or stress change on the semiconductor layer. This is considered to be caused by the above.

  As a result, according to the first electro-optical device of the present invention, for example, a display image caused by light leakage or light reflection in the peripheral region with little or no deterioration of the characteristics of the transistors constituting the peripheral circuit. Can be prevented, and a high-quality image can be displayed.

  In one aspect of the first electro-optical device according to the present invention, a plurality of the openings are formed at a predetermined interval in the channel width direction of the transistor.

  According to this aspect, for example, a plurality of openings are formed at a predetermined interval of, for example, 1 μm from a portion of the light shielding film that overlaps one end of the transistor in the channel width direction to a portion that overlaps the other end of the transistor in the channel width direction. Is done. Accordingly, it is possible to more reliably reduce or prevent the deterioration of transistor characteristics that may be caused by the light shielding film.

  In another aspect of the first electro-optical device according to the invention, the opening portion at least partially overlaps the channel region of the transistor when viewed in plan on the substrate.

  According to this aspect, the light shielding film does not at least partially overlap the channel region of the transistor. Thus, adverse effects that the light shielding film may have on the channel region of the transistor can be reduced or prevented. Accordingly, it is possible to more reliably reduce or prevent the deterioration of transistor characteristics that may be caused by the light shielding film.

  In another aspect of the first electro-optical device according to the invention, the width of the opening is 1 μm or less.

  According to this aspect, the light can be almost completely or practically blocked by the light shielding film. Therefore, light leakage from the peripheral region and re-reflection of return light by the transistor can be more reliably reduced or prevented.

  In another aspect of the first electro-optical device according to the present invention, the light-shielding film includes a first light-shielding portion having the opening, and the pixel more than the first light-shielding portion along a channel width direction of the transistor. And a second light-shielding portion formed adjacent to the first light-shielding portion on the side far from the region and having a different plane pattern from the first light-shielding portion.

  According to this aspect, it is possible to reduce light leakage and light reflection in the peripheral region that is relatively close to the pixel region by the first light shielding portion having the opening. Furthermore, for example, by forming the second light-shielding portion so that the portion overlapping the transistor has a smaller planar pattern than the first light-shielding portion, it is possible to more reliably reduce deterioration in transistor characteristics that may be caused by the light-shielding film. Can be prevented. In other words, in the peripheral region, the portion where the light shielding film and the transistor overlap is small in a region far from the pixel region to such an extent that the display image caused by light leakage or light reflection has little or no practical effect. Further, by forming the second light shielding portion, it is possible to more reliably reduce or prevent the deterioration of the transistor characteristics.

  In the aspect in which the light-shielding film includes the first and second light-shielding portions, the second light-shielding portion may be formed so as not to at least partially overlap the transistor when viewed in plan on the substrate. .

  In this case, it is possible to more reliably reduce or prevent deterioration of transistor characteristics that may be caused by the light shielding film.

  In another aspect of the first electro-optical device according to the invention, the transistor has a channel width of 5 μm or more.

  According to this aspect, it is possible to more effectively reduce or prevent deterioration of transistor characteristics that may be caused by the light shielding film.

  In another aspect of the first electro-optical device according to the invention, the channel width of the transistor is longer than the channel length of the transistor.

  According to this aspect, it is possible to more effectively reduce or prevent deterioration of transistor characteristics that may be caused by the light shielding film.

  In another aspect of the first electro-optical device according to the invention, a plurality of scanning lines and a plurality of data lines wired in the pixel region, and an image signal line provided in the peripheral region and supplying an image signal, A plurality of sampling transistors that supply image signals supplied to the image signal lines to the plurality of data lines according to a sampling signal and are arranged corresponding to the plurality of data lines. Formed as.

  According to this aspect, the transistors are arranged as a plurality of sampling transistors constituting the sampling circuit, for example, in the vicinity of the pixel region along the arrangement direction of the plurality of data lines (that is, the direction in which the plurality of scanning lines extend). A plurality are formed. Therefore, a plurality of light-shielding films having long openings are formed, for example, in the vicinity of the pixel region so as to be arranged along the arrangement direction of the plurality of data lines. Therefore, it is possible to more effectively reduce or prevent the adverse effect on the display image due to light leakage or light reflection in the peripheral region.

  In order to solve the above problems, a second electro-optical device according to the present invention is provided on a substrate in a peripheral region positioned around a pixel region in which the plurality of pixel electrodes are arranged. The complementary transistor and the complementary transistor and the substrate, and when viewed in plan on the substrate, overlaps at least one of the complementary transistors, and the channel length of the transistor And a light shielding film in which a longitudinal opening along the direction is formed.

  According to the second electro-optical device according to the present invention, it is possible to receive the same benefits as those received by the first electro-optical device according to the present invention described above.

  Note that the second electro-optical device according to the present invention can also adopt various aspects similar to the various aspects of the first electro-optical device according to the present invention described above.

  In order to solve the above problems, an electronic apparatus according to the present invention includes the above-described electro-optical device according to the present invention (including various aspects thereof).

  According to the electronic apparatus of the present invention, since the electro-optical device of the present invention described above is provided, a projection display device, a television, a mobile phone, an electronic notebook, and a word processor capable of performing high-quality image display. Various electronic devices such as a viewfinder type or a monitor direct view type video tape recorder, a workstation, a videophone, a POS terminal, and a touch panel can be realized. In addition, as an electronic apparatus of the present invention, for example, an electrophoretic device such as electronic paper, an electron emission device (Field Emission Display and Conduction Electron-Emitter Display), and a display device using these electrophoretic device and electron emission device are realized. Is also possible.

  The operation and other advantages of the present invention will become apparent from the best mode for carrying out the invention described below.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, a driving circuit built-in type TFT active matrix driving type liquid crystal device, which is an example of the electro-optical device of the present invention, is taken as an example.
<First Embodiment>
The liquid crystal device according to the first embodiment will be described with reference to FIGS.

  First, the overall configuration of the liquid crystal device according to the present embodiment will be described with reference to FIGS. 1 and 2. FIG. 1 is a plan view showing the overall configuration of the liquid crystal device according to this embodiment, and FIG. 2 is a cross-sectional view taken along the line II-II ′ of FIG.

  1 and 2, in the liquid crystal device according to the present embodiment, a TFT array substrate 10 and a counter substrate 20 are arranged to face each other. A liquid crystal layer 50 is sealed between the TFT array substrate 10 and the counter substrate 20, and the TFT array substrate 10 and the counter substrate 20 are surrounded by an image display region 10a as an example of the “pixel region” according to the present invention. They are bonded to each other by a sealing material 52 provided in a sealing region located in the area.

  In FIG. 1, a light-shielding frame light-shielding film 53 that defines the frame area of the image display region 10a is provided on the counter substrate 20 side in parallel with the inside of the seal region where the sealing material 52 is disposed. In the present embodiment, the peripheral region is defined as a region farther than the frame region defined by the frame light shielding film 53 when viewed from the center of the TFT array substrate 10, and is a region including the frame region. That is, the peripheral area is an area on the TFT array substrate 10 excluding the image display area 10a, and is set as an area that does not emit light.

  A data line driving circuit 101 and an external circuit connection terminal 102 are provided along one side of the TFT array substrate 10 in a region located outside the sealing region in which the sealing material 52 is disposed in the peripheral region. The sampling circuit 7 is provided so as to be covered with the frame light shielding film 53 on the inner side of the seal region along the one side. The scanning line driving circuit 104 is provided so as to be covered with the frame light-shielding film 53 inside the seal region along two sides adjacent to the one side. On the TFT array substrate 10, vertical conduction terminals 106 for connecting the two substrates with the vertical conduction material 107 are arranged in regions facing the four corner portions of the counter substrate 20. Thus, electrical conduction can be established between the TFT array substrate 10 and the counter substrate 20.

  On the TFT array substrate 10, a lead wiring 90 is formed for electrically connecting the external circuit connection terminal 102 to the data line driving circuit 101, the scanning line driving circuit 104, the vertical conduction terminal 106, and the like. .

  In FIG. 2, on the TFT array substrate 10, a laminated structure in which wirings such as pixel switching TFTs, scanning lines, and data lines are formed. In the image display area 10a, pixel electrodes 9a made of a transparent material such as ITO are provided in a matrix on the upper layers of pixel switching TFTs, scanning lines, data lines and the like. An alignment film is formed on the pixel electrode 9a. On the other hand, a light shielding film 23 is formed on the surface of the counter substrate 20 facing the TFT array substrate 10. The light shielding film 23 is formed of, for example, a light shielding metal film or the like, and is patterned, for example, in a lattice shape in the image display region 10a on the counter substrate 20. On the light shielding film 23, the counter electrode 21 made of a transparent material such as ITO is formed in a solid shape so as to face the plurality of pixel electrodes 9a. An alignment film is formed on the counter electrode 21. The liquid crystal layer 50 is made of, for example, a liquid crystal in which one or several types of nematic liquid crystals are mixed, and takes a predetermined alignment state between the pair of alignment films.

  In the present embodiment, it is assumed that incident light incident on the liquid crystal layer 50 in the image display region 10a from the counter substrate 20 side is emitted as display light from the TFT array substrate 10 side.

  Although not shown here, in addition to the data line driving circuit 101 and the scanning line driving circuit 104, the TFT array substrate 10 is used for inspecting the quality, defects, and the like of the liquid crystal device during manufacturing or at the time of shipment. An inspection circuit, an inspection pattern, or the like may be formed.

  Next, the electrical configuration of the liquid crystal device according to the present embodiment will be described with reference to FIG. FIG. 3 is a block diagram showing the electrical configuration of the liquid crystal device according to this embodiment.

  As shown in FIG. 3, the liquid crystal device according to this embodiment includes a peripheral circuit including a scanning line driving circuit 104, a data line driving circuit 101, and a sampling circuit 7 in the peripheral region on the TFT array substrate 10, and an image signal. Line 6 is provided.

  The scanning line driving circuit 104 is supplied with a Y clock signal CLY, an inverted Y clock signal CLYinv, and a Y start pulse DY. When the Y start pulse DY is input, the scanning line driving circuit 104 sequentially receives the scanning signal Gi (where i = 1,..., M) at a timing based on the Y clock signal CLY and the inverted Y clock signal CLYinv. Generate and output.

  The data line driving circuit 101 is supplied with an X clock signal CLX, an inverted X clock signal CLXinv, and an X start pulse DX. When the X start pulse DX is input, the data line driving circuit 101 receives the sampling signal Si (where i = 1, 2,..., N) at a timing based on the X clock signal CLX and the inverted X clock signal XCLXinv. Are generated and output sequentially.

  The sampling circuit 7 includes a plurality of sampling TFTs 71 provided for each data line 6a. The sampling TFT 71 is an example of the “transistor” according to the present invention, and is composed of, for example, a P-channel or N-channel single-channel TFT. The sampling TFT 71 may be composed of a complementary TFT.

  The source wiring 71S of the sampling TFT 71 is electrically connected to the image signal line 6, the gate wiring 71G of the sampling TFT 71 is electrically connected to the sampling signal line 97, and the drain wiring of the sampling TFT 71. 71D is electrically connected to the data line 6a. Each sampling TFT 71 receives an image signal VID via the image signal line 6 and also receives a sampling signal Si from the data line driving circuit 101 via the sampling signal line 97 (where i = 1, 2,... When n) is input, the image signal VID is sampled and applied to each data line 6a as a data signal Di (where i = 1, 2,..., n).

  As shown in FIG. 3, each of a plurality of pixels formed in a matrix that forms the image display region 10a of the TFT array substrate 10 includes a pixel electrode 9a and pixel switching for switching control of the pixel electrode 9a. The TFT 30 is formed, and the data line 6 a to which the data signal Di is supplied is electrically connected to the source of the pixel switching TFT 30. The data signal Di written to the data line 6a may be supplied line-sequentially in this order, or may be supplied for each group of a plurality of adjacent data lines 6a. Further, the scanning line 11 a is electrically connected to the gate of the pixel switching TFT 30. The scanning signals G1, G2,..., Gm are applied to the scanning line 11a in this order from the scanning line driving circuit 104 at a predetermined timing. In the present embodiment, for the sake of simplicity of explanation, the scanning signals G1, G2,..., Gm are configured to be applied to the scanning lines 11a in this order, but the scanning signals Gi (however, , I = 1, 2,..., M) may be applied to the scanning line 11a in any order. The pixel electrode 9a is electrically connected to the drain of the pixel switching TFT 30, and the pixel switching TFT 30 serving as a switching element is closed for a certain period so that the data signal Di supplied from the data line 6a is received. Write at a predetermined timing.

  A predetermined level of data signal Di (where i = 1, 2,..., N) written to the liquid crystal via the pixel electrode 9a is applied to the counter electrode 21 (see FIG. 2). (See FIG. 2). The liquid crystal modulates light and enables gradation display by changing the orientation and order of the molecular assembly depending on the applied voltage level. In the normally white mode, the transmittance for incident light is reduced according to the voltage applied in units of each pixel, and in the normally black mode, the light is incident according to the voltage applied in units of each pixel. The light transmittance is increased, and light having a contrast corresponding to an image signal is emitted from the liquid crystal device as a whole.

  In order to prevent the image signal held here from leaking, a storage capacitor 70 is added in parallel with the liquid crystal capacitor formed between the pixel electrode 9 a and the counter electrode 21. One electrode of the storage capacitor 70 is electrically connected to the drain of the pixel switching TFT 30 in parallel with the pixel electrode 9a, and the other electrode is electrically connected to the fixed potential capacitor line 400 so as to have a constant potential. It is connected to the.

  Next, a specific configuration of the sampling TFT according to this embodiment will be described with reference to FIGS. 4 to 6 together with a configuration of a light shielding film provided corresponding to the sampling TFT. FIG. 4 is a plan view showing the configuration of the sampling TFT. FIG. 5 is a cross-sectional view taken along the line V-V ′ of FIG. 4. FIG. 6 is a plan view showing the configuration of the light shielding film provided corresponding to the sampling TFT. In FIG. 5, the scale of each layer / member is different for each layer / member to have a size that can be recognized on the drawing.

  4 and 5, each sampling TFT 71 is formed on a base insulating film 12 provided on the TFT array substrate 10. The sampling TFT 71 includes a semiconductor layer 74, a source wiring 71S, a drain wiring 71D, a gate wiring 71G, and a gate insulating film 75.

  The semiconductor layer 74 has a channel region 74C in which a channel is formed by an electric field from the gate wiring 71G, a source region 74S, and a drain region 74D. The region adjacent to the channel region 74C may be an LDD (Lightly Doped Drain) region.

  In the present embodiment, the sampling TFT 71 has a channel length L (ie, a distance between the source region 74S and the drain region 74D or a length along the X direction of the channel region 74C) L in the range of 3 to 5 μm, for example. And the channel width (length along the Y direction of the channel region) W is, for example, a predetermined length within a range of 50 μm to 600 μm. Therefore, the channel width W of the sampling TFT 71 is longer than the channel length L of the sampling TFT 71.

  The source wiring 71S is formed of a metal film such as aluminum on the upper layer side of the semiconductor layer 74 via the interlayer insulating films 41 and 42. The source wiring 71S is electrically connected to the source region 74S through a contact hole 8S opened through the interlayer insulating films 41 and 42. The source wiring 71S is formed so as to extend along the direction in which the data line 6a extends (that is, the Y direction). The source wiring 71S is electrically connected to the image signal line 6 through a contact hole and a relay wiring (not shown) (see FIG. 3).

  The drain wiring 71D is formed of the same film as the source wiring 71S. That is, the drain wiring 71D is formed of a metal film such as aluminum on the upper side of the semiconductor layer 74 via the interlayer insulating films 41 and 42. Here, the same film means that a thin film made of the same conductive material is simultaneously patterned. The drain wiring 71D is electrically connected to the drain region 74D through a contact hole 8D opened through the interlayer insulating films 41 and 42. The drain wiring 71D is formed so as to extend along the direction in which the data line 6a extends (that is, the Y direction). The drain wiring 71D is electrically connected to the data line 6a through a contact hole and a relay wiring (not shown) (see FIG. 3).

  The gate wiring 71G is formed of, for example, a conductive polysilicon film or the like on the upper layer side of the semiconductor layer 74 via the gate insulating film 75. The gate wiring 71G includes a gate electrode that overlaps the channel region 74 of the semiconductor layer 74 via the gate insulating film 75, and is formed so as to extend along the direction in which the data line 6a extends (that is, the Y direction). The gate wiring 71G is electrically connected to the sampling signal line 97 through a contact hole and a relay wiring (not shown) (see FIG. 3).

  Interlayer insulating films 43 and 44 are sequentially stacked on the upper layer side of the source wiring 71S and the drain wiring 71D.

  4 and 5, in the present embodiment, a light shielding film 510 provided for each sampling TFT 71 is provided. The light shielding film 510 is disposed on the lower layer side with respect to the sampling TFT 71 through the base insulating film 12 and is formed so as to overlap the sampling TFT 71 when viewed in plan on the TFT array substrate 10. One light shielding film 510 is provided for each of the plurality of sampling TFTs 71, so that a plurality of light shielding films 510 are provided in the vicinity of the image display region 10 a along the X direction. The light shielding film 510 is, for example, a simple metal, an alloy, or a metal silicide containing at least one of refractory metals such as titanium (Ti), chromium (Cr), tungsten (W), tantalum (Ta), and molybdenum (Mo). , Polysilicide or a light-shielding conductive material such as a laminate thereof.

  As shown in FIG. 6, the light shielding film 510 is formed so as to overlap the region 71 a where the sampling TFT 71 is formed, and the light shielding film 510 has a plurality of slits 510 s. The slit 510 s is an example of the “opening” according to the present invention, and is opened in the light shielding film 510 so as to extend along the channel length direction (that is, the X direction) of the sampling TFT 71.

  Each of the plurality of slits 510s is formed in the light shielding film 510 so as to extend along the channel length direction (that is, the X direction) of the sampling TFT 71 with a predetermined width d1 of, for example, 1 μm or less. Further, the plurality of slits 510s are formed so as to be arranged at a predetermined interval d2 of, for example, 1 μm along the channel width direction (that is, the Y direction) of the sampling TFT 71. In FIG. 6, the scale of the slit 510 s is different from that of the light-shielding film 510 so that the slit 510 s can be recognized on the drawing.

  Therefore, light leakage from the peripheral region located around the image display region 10 a and re-reflection of the return light by the sampling TFT 71 can be reduced by the light shielding film 510. That is, the plurality of light shielding films 510 can reduce the occurrence of light leakage from the peripheral area near the edge on the side where the sampling TFT 71 is formed in the image display area 10a, Returning light (light traveling from the lower side to the upper side in FIG. 5) emitted from another liquid crystal device by a multi-plate projector or the like and penetrating the combining optical system is reflected by the sampling TFT 71. Can be reduced. Accordingly, it is possible to reduce the appearance of a light / dark pattern according to the reflection or transmission of light in the peripheral region, such as a light / dark pattern according to the arrangement pattern of the plurality of sampling TFTs 71, near the edge of the image display region 10a. That is, it is possible to reduce adverse effects on the display image due to light leakage or light reflection in the peripheral region.

  In FIG. 6, in the present embodiment, the width d1 of the slit 510s is 1 μm or less. Therefore, the light shielding film 510 can block light almost completely or in practice. Therefore, light leakage from the peripheral region and re-reflection of return light by the transistor can be more reliably reduced or prevented.

  Furthermore, since the light shielding film 510 has slits 510s along the channel length direction (that is, the X direction) of the sampling TFT 71, if the light shielding film 510 is formed in a solid shape without any slits, There is little or no deterioration in the characteristics of the sampling TFT 71 that can occur when the sampling TFT 71 is formed to have only slits along the channel width direction (ie, the Y direction). There is little or no deterioration in the characteristics of the sampling TFT 71 that may be caused by capacitive coupling between the TFT and the sampling TFT 71, or contamination of the semiconductor layer 74 by forming the light shielding film 510.

  In addition, in the present embodiment, in particular, the slit 510s is formed so as to overlap the channel region 74C of the sampling TFT 71. Therefore, the light shielding film 510 does not overlap the channel region 74C of the sampling TFT 71 in the region where the slit 510s is formed. Therefore, the adverse effect that the light shielding film 510 may have on the channel region 74C of the sampling TFT 71 can be reduced. Therefore, the deterioration of the characteristics of the sampling TFT 71 that can be caused by the light shielding film 510 can be more reliably reduced.

  In addition, in the present embodiment, in particular, the plurality of slits 510 s are provided from the portion of the light shielding film 510 that overlaps one end of the sampling TFT 71 in the channel width direction (that is, the Y direction) to the other end of the sampling TFT 71 in the channel width direction. The overlapping portions are formed so as to be arranged at a predetermined interval d2. Therefore, the deterioration of the characteristics of the sampling TFT 71 that can be caused by the light shielding film 510 can be more reliably reduced.

  In FIG. 4, the channel width W of the sampling TFT 71 is, for example, a predetermined length in the range of 50 μm to 600 μm, for example, a predetermined length in the range of 3 to 5 μm. Since it is longer than the channel length L, the deterioration of the characteristics of the sampling TFT 71 that may be caused by the light shielding film 510 can be reduced more effectively.

As a result of the above, according to the liquid crystal device according to the present embodiment, the characteristics of the sampling TFT 71 constituting the sampling circuit 7 are hardly deteriorated, or the display image due to light leakage or light reflection in the peripheral region is reduced. Adverse effects can be prevented and high-quality images can be displayed.
Second Embodiment
A liquid crystal device according to a second embodiment will be described with reference to FIG. FIG. 7 is a plan view having the same concept as FIG. 6 in the second embodiment. In FIG. 7, the same reference numerals are given to the same components as those according to the first embodiment shown in FIGS. 1 to 6, and description thereof will be omitted as appropriate.

  In FIG. 7, the liquid crystal device according to the second embodiment differs from the liquid crystal device according to the first embodiment described above in that it includes a light shielding film 520 instead of the light shielding film 510 in the first embodiment described above. About the point, it is comprised substantially the same as that of the liquid crystal device which concerns on 1st Embodiment mentioned above.

  As shown in FIG. 7, in this embodiment, in particular, the light shielding film 520 includes the first light shielding portion 521 having a plurality of slits 520 s and the first light shielding along the channel width direction (that is, the Y direction) of the sampling TFT 71. A second light-shielding portion 522 formed adjacent to the first light-shielding portion 521 is provided on the side farther from the image display area 10a than the portion 521.

  Each of the plurality of slits 520s formed in the first light shielding portion 521 is opened in the light shielding film 520, similarly to the slit 510s in the first embodiment described above. Each of the plurality of slits 520s is formed in the light shielding film 520 so as to extend along the channel length direction of the sampling TFT 71 with a predetermined width d1 of, for example, 1 μm or less. Further, a plurality of slits 520 s are formed along the channel width direction of the sampling TFT 71 with a predetermined interval d 2 of 1 μm, for example.

  The second light shielding portion 522 has a different plane pattern from the first light shielding portion 521, more specifically, overlaps the source region 74S and drain region 74D of the sampling TFT 71, and does not overlap the channel region 74C of the sampling TFT 71. It has a planar pattern. In other words, the second light shielding portion 522 is formed in a planar pattern such that the portion overlapping the sampling TFT 71 is smaller than the first light shielding portion 521.

  Therefore, the deterioration of the characteristics of the sampling TFT 71 that can be caused by the light shielding film 520 can be more reliably reduced.

  That is, in the present embodiment, in particular, in the region 71a where the sampling TFT 71 is formed, the region close to the image display region 10a to the extent that there is a possibility that the display image may be adversely affected due to light leakage or light reflection. Since the first light-shielding portion 521 having 520 s is formed, the adverse effect on the display image near the edge of the image display region 10 a due to light leakage or light reflection in the peripheral region can be reduced, and the characteristics of the sampling TFT 71 can be reduced. Of the region 71a where the sampling TFT 71 can be formed, the degradation can be reduced, and the region 71a far from the image display region 10a to such an extent that there is little or no adverse effect on the display image due to light leakage or light reflection. The portion overlapping the sampling TFT 71 is the first light shielding portion 521 and the sampling TFT 71 are Since the second light-shielding portion 522 having a smaller becomes such a planar pattern than the part made is formed, it can be more reliably reduce the deterioration of the characteristics of the sampling TFT 71.

  FIG. 8 is a plan view having the same concept as in FIG. 6 in a modification of the second embodiment.

  As shown as a modified example in FIG. 8, the light shielding film 520 includes only the first light shielding portion 521 described above, and does not need to include the second light shielding portion 522 described above. In other words, the light shielding film 520 overlaps with the sampling TFT 71 in an area far from the image display area 10a to such an extent that the display image caused by light leakage or light reflection has little or no adverse effect on the display image. You may form so that it may not become.

In this case, the deterioration of the characteristics of the sampling TFT 71 due to the light shielding film 520 can be more reliably reduced.
<Third Embodiment>
A liquid crystal device according to a third embodiment will be described with reference to FIGS.

  The liquid crystal device according to the third embodiment is provided with the light shielding film 530 (see FIG. 11 and FIG. 12) in the region where the scanning line driving circuit 104 is formed on the TFT array substrate 10. Unlike the liquid crystal device according to the embodiment, the other points are substantially the same as those of the liquid crystal device according to the first embodiment described above.

  First, the electrical configuration of the scanning line driving circuit of the liquid crystal device according to the present embodiment will be described in detail with reference to FIGS.

  FIG. 9 is a circuit diagram showing an electrical configuration of the scanning line driving circuit. FIG. 10 is a circuit diagram showing a specific configuration of the output buffer. In FIGS. 9 and 10 and FIGS. 11 and 12 to be described later, the same reference numerals are given to the same components as the components according to the first embodiment shown in FIGS. Are omitted as appropriate.

  In FIG. 9, the scanning line driving circuit 104 includes a shift register 240 and an output buffer 230.

  The shift register 240 includes a plurality of inverters 241 and a NAND circuit 242, and transfers the image signal at a timing at which an image signal should be supplied to the pixel electrode 9a of each pixel based on the Y clock signal CLY and the inverted Y clock signal CLYinv. Signals are sequentially output and transferred to the output buffer 230.

  In the output buffer 230, inverters 231, 232 and 233 are electrically connected in series. An input terminal of the output buffer 230 is electrically connected to an output terminal of the shift register 240, and a transfer signal from the shift register 240 is input to the input terminal of the output buffer 230. The output buffer 230 gives drive capability to the transfer signal transferred from the shift register 240. The transfer signal that has obtained the driving capability (in other words, the current supply capability) is finally supplied from the scanning line driving circuit 104 to the pixel switching TFT 30 via the scanning line 11a as a scanning signal.

  As described above, the output buffer 230 includes a plurality of inverters 231, 232, and 233, and has a function of outputting the transfer signal as a scanning signal after increasing the driving capability, shaping the waveform, and adjusting the timing.

  As shown in detail in FIG. 10, the inverter 231 is configured as a complementary transistor, and includes an TFT 231a that is an N-channel TFT and a TFT 231b that is a P-channel TFT. Similarly, the inverter 232 includes an N-channel TFT 232a and a P-channel TFT 232b, and the inverter 233 includes an N-channel TFT 233a and a P-channel TFT 233b. Has been. The input terminal of the output buffer 230 is electrically connected to the gates of the TFT 231a and the TFT 231b. The output terminal of the output buffer 230 is electrically connected to the drains of the TFTs 233a and 233b.

  The inverters 231, 232 and 233 are driven by the scan drive circuit high potential power supply VDDY and the low potential power supply VSSY. Therefore, the voltage of the transfer signal transits between the potential of the scanning drive circuit high potential power supply VDDY and the potential of the scan drive circuit low potential power supply VSSY, and the driving capability is gradually increased, and the scanning signals G1,. Output as Gm.

  Next, a specific configuration of the inverter located in the final stage on the output side to the scanning line among the plurality of inverters constituting the output buffer described above will be described with reference to FIGS.

  FIG. 11 is a plan view showing a specific configuration of the inverter located in the final stage on the output side to the scanning line among the plural stages of inverters constituting the output buffer. FIG. 12 is a plan view showing the configuration of the light shielding film provided corresponding to the inverter located at the final stage on the output side to the scanning line among the plural stages of inverters constituting the output buffer.

  In FIG. 11, the inverter 233 is configured as a complementary transistor composed of a TFT 233a which is an N-channel TFT and a TFT 233b which is a P-channel TFT.

  The TFT 233a includes a semiconductor layer 310. The semiconductor layer 310 is formed on the base insulating film 12 in the same manner as the semiconductor layer 74 described above with reference to FIGS. The semiconductor layer 310 includes a channel region in which a channel is formed by an electric field from the gate wiring 350 provided in common to the TFTs 233 a and 233 b, and a source region electrically connected to the source wiring 311 through the contact hole 81. And a drain region electrically connected through a contact hole 84 to a drain wiring 330 provided in common to the TFTs 233a and 233b.

  The TFT 233b includes a semiconductor layer 320. The semiconductor layer 320 is formed on the base insulating film 12 similarly to the semiconductor layer 74 described above with reference to FIGS. 4 and 5. The semiconductor layer 320 includes a channel region in which a channel is formed by an electric field from the gate wiring 350, a source region electrically connected to the source wiring 321 through the contact hole 82, and a contact hole 83 in the drain wiring 330. And a drain region electrically connected to each other.

  The gate wiring 350 is formed of the same film as the gate wiring 71G described above with reference to FIGS. 4 and 5. That is, for example, the conductive wiring 350 is formed on the upper layer side of the semiconductor layers 310 and 320 via the gate insulating film. It is formed from a silicon film or the like. Note that the gate wiring 350 is electrically connected to the output terminal of the inverter 232.

  The source wiring 311 of the TFT 233b is formed of the same film as the source wiring 71S described above with reference to FIGS. 4 and 5, that is, on the upper layer side from the semiconductor layer 310 via the interlayer insulating films 41 and 42, for example, It is formed from a metal film such as aluminum. Note that the source wiring 311 is electrically connected to a scanning line driving circuit low potential power supply wiring that supplies the scanning line driving circuit low potential power supply VSSY.

  The source wiring 321 of the TFT 233a is formed of the same film as the source wiring 311. That is, the source wiring 321 is formed of a metal film such as aluminum on the upper side of the semiconductor layer 320 via the interlayer insulating films 41 and 42. Note that the source wiring 321 is electrically connected to the scanning line driving circuit high potential power wiring for supplying the scanning line driving circuit high potential power VDDY.

  The drain wiring 330 is formed of the same film as the source wirings 321 and 322, that is, is formed of a metal film such as aluminum on the upper side of the semiconductor layers 310 and 320 via the interlayer insulating films 41 and 42. Yes. The drain wiring 330 is electrically connected to the scanning line 11a through a contact hole and a relay wiring (not shown).

  In FIG. 11 and FIG. 12, in this embodiment, a light shielding film 530 provided for each inverter 233 is provided. The light shielding film 530 is disposed below the TFTs 233a and 233b constituting the inverter 233 via the base insulating film 12, and is formed so as to overlap the TFTs 233a and 233b when viewed in plan on the TFT array substrate 10. Yes. One light shielding film 530 is provided for each of the plurality of inverters 233, so that a plurality of light shielding films 530 are provided in the vicinity of the image display region 10a along the Y direction. The light shielding film 530 is formed of, for example, titanium (Ti), chromium (Cr), tungsten (W), tantalum (Ta), molybdenum (Mo), or the like, similar to the light shielding film 510 described above with reference to FIGS. It is made of a light-shielding conductive material such as a single metal containing at least one of refractory metals, an alloy, metal silicide, polysilicide, or a laminate thereof.

  As shown in FIG. 12, the light shielding film 530 is formed so as to overlap with a region 233S where the inverter 233 is formed, and the light shielding film 530 has a plurality of slits 530s. The slit 530 s is an example of the “opening” according to the present invention, and is opened in the light shielding film 530 so as to extend along the channel length direction (that is, the Y direction) of the TFTs 233 a and 233 b constituting the inverter 233. .

  Each of the plurality of slits 530s is formed in the light shielding film 530 so as to extend along the channel length direction (that is, the X direction) of the TFTs 233a and 233b with a predetermined width of, for example, 1 μm or less. Further, the plurality of slits 530s are formed so as to be arranged at a predetermined interval of, for example, 1 μm along the channel width direction (that is, the X direction) of the TFTs 233a and 233b. In FIG. 12, the scale of the slit 530s is different from that of the light shielding film 530 in order to make the slit 530s recognizable on the drawing.

Therefore, the light shielding film 530 can reduce the light leakage from the peripheral region located around the image display region 10a and the re-reflection of the return light by the TFTs 233a and 233b constituting the inverter 233. That is, the plurality of light shielding films 530 can reduce the occurrence of light leakage from the peripheral region near the edge of the image display region 10a on the side where the scanning line driving circuit 104 is formed, and the back surface of the TFT array substrate 10. It is possible to reduce reflection and return light such as light emitted from another liquid crystal device by a multi-plate projector or the like and penetrating the composite optical system is reflected by the TFTs 233a and 233b. Accordingly, a light / dark pattern according to the reflection or transmission of light in the peripheral area, such as a light / dark pattern according to the arrangement pattern of the plurality of inverters 233 (in other words, TFTs 233a and 233b), is displayed near the edge of the image display area 10a. Can be reduced.
<Fourth embodiment>
A liquid crystal device according to a fourth embodiment will be described with reference to FIGS.

  FIG. 13 is a block diagram schematically showing the configuration of the liquid crystal device according to the fourth embodiment. In FIG. 13, the same components as those in the first embodiment shown in FIGS. 1 to 6 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  In FIG. 13, the liquid crystal device according to the fourth embodiment includes a phase difference correction circuit 600 in a peripheral region located around the image display region 10 a on the TFT array substrate 10, and a plurality of components constituting the phase difference correction circuit 600 are included. Unlike the liquid crystal device according to the first embodiment described above, other points are provided in that a light-shielding film as an example of the “light-shielding film” according to the present invention is provided corresponding to at least one of the transistors. Is configured in substantially the same manner as the liquid crystal device according to the first embodiment described above.

  The phase difference correction circuit 600 is provided in the vicinity of the image display region 10a (for example, a region whose distance from the edge of the image display region 10a is several hundred um (for example, about 400 to 800 um)). More specifically, the phase difference correction circuit 600 is a position facing the sampling circuit 7 or the data line driving circuit 101 across the image display area 10a in the peripheral area located around the image display area 10a. The image display area 10a is arranged on a center line that bisects the width in the X direction. The phase difference correction circuit 600 is supplied with a Y clock signal CLY and an inverted Y clock signal CLYinv.

  Note that the Y clock signal CLY is transmitted from the Y clock signal terminal among the plurality of external circuit connection terminals 102 (see FIG. 1) via a Y clock signal line that is wired so that the peripheral region extends along the outer periphery of the TFT array substrate 10. And supplied to the phase difference correction circuit 600. The inverted Y clock signal CLYinv is corrected for phase difference from the inverted Y clock signal terminal among the plurality of external circuit connection terminals 102 via an inverted Y clock signal line wired in the peripheral region along the outer periphery of the TFT array substrate 10. This is supplied to the circuit 600.

  The phase difference correction circuit 600 corrects the phases of the Y clock signal CLY and the inverted Y clock signal CLYinv supplied from the outside via the Y clock signal line and the inverted Y clock signal line wired in the peripheral region, and then To the scanning line driving circuit 104 (that is, each of the two scanning line driving circuit portions 104L and 104R arranged to face each other across the image display region 10a). Accordingly, the scanning line driving circuit 104 can be driven normally or with high accuracy without causing a malfunction.

  FIG. 14 is a circuit diagram showing an electrical configuration of the phase difference correction circuit of the liquid crystal device according to the present embodiment.

  In FIG. 14, the phase difference correction circuit 600 includes a first buffer circuit 601, a bistable circuit 602, and a second buffer circuit 603. The first buffer circuit 601 includes inverters 601a and 601b configured as complementary transistors, respectively. The second buffer circuit 602 includes inverters 602a and 602b configured as complementary transistors, respectively. The third buffer circuit 603 includes inverters 603a and 603b each configured as a complementary transistor.

  In the phase difference correction circuit 600, the buffer circuit 601 composed of the inverters 601a and 601b supplements the drive capability of the circuit that supplies the Y clock signal CLY and the inverted Y clock signal CLYinv, and one inverter 602a of the bistable circuit 602. Is supplied to the input of the other inverter 602b, and the output of the other inverter 602b is supplied to the input of one inverter 602a, so that the input signals of the respective inverters 602a and 602b are positively fed back to obtain a phase difference. It has a configuration to be eliminated. Further, in the phase difference correction circuit 600, a second buffer circuit 603 is provided after the bistable circuit 602, and the function of the second buffer circuit 603 prevents the driving ability of the bistable circuit 602 from being lowered. Yes.

  In FIG. 13 again, the phase difference correction circuit 600 passes through the Y clock signal line 691R and the inverted Y clock signal line 692R to the scanning line driving circuit portion 104R disposed on the right side in FIG. On the other hand, through the Y clock signal line 691L and the inverted Y clock signal line 692L, the scanning line driving circuit 104 is electrically connected to the scanning line driving circuit portion 104L disposed on the left side in FIG. It is connected to the.

  With this configuration, the Y clock signal CLY and the inverted Y clock signal CLYinv whose phase differences are corrected by the above-described operation of the phase difference correction circuit 600 are converted into the scanning line driving circuit 104 (that is, the scanning line). To the drive circuit portions 104R and 104L). Further, with this configuration, the wiring distance from the phase difference correction circuit 600 to the scanning line driving circuit portion 104R is equal to the wiring distance from the phase difference correction circuit 600 to the scanning line driving circuit portion 104L. The wiring time constants are equal. Therefore, for example, even when a signal delay occurs between the phase difference correction circuit 600 and the scanning line driving circuit portions 104R and 104L to a level that cannot be ignored, the respective signal delay amounts to the left and right scanning line driving circuit portions. Therefore, it is possible to prevent problems such as a shift in driving timing between the left and right scanning line driving circuit portions due to signal delay.

  In this embodiment, in particular, a light shielding film is provided for each of a plurality of inverters constituting the phase difference correction circuit 600 (that is, one for each of the inverters 601a, 601b, 602a, 602b, 603a, and 603b). ing. The light shielding film is disposed between the inverter constituting the phase difference correction circuit 600 and the TFT array substrate 10 (that is, below the complementary TFT constituting the inverter on the TFT array substrate 10). When viewed in plan on the TFT array substrate 10, a plurality of longitudinal slits are formed along the channel length direction of the TFT while overlapping with the TFT constituting the inverter. The light shielding film has substantially the same planar shape as the light shielding film 510 in the first embodiment described above with reference to FIG.

Therefore, light leakage from the peripheral area located around the image display area 10a and re-reflection of the return light by the TFT constituting the inverter of the phase difference correction circuit 600 is shielded for each inverter of the phase difference correction circuit 600. Can be reduced by the membrane. That is, such a light shielding film can reduce the occurrence of light leakage from the peripheral region near the edge of the image display region 10a on the side where the phase difference correction circuit 600 is formed, and the back surface of the TFT array substrate 10. It is possible to reduce reflection and return light such as light emitted from another liquid crystal device by a multi-plate projector or the like and penetrating the composite optical system from being reflected by the TFT constituting the inverter of the phase difference correction circuit 600. Therefore, it is possible to reduce the brightness / darkness pattern according to the reflection / transmission of light in the peripheral area, such as the brightness / darkness pattern according to the arrangement pattern of the plurality of inverters of the phase difference correction circuit 600, being displayed near the edge of the image display area 10a. it can.
<Electronic equipment>
Next, the case where the above-described liquid crystal device which is an electro-optical device is applied to various electronic devices will be described with reference to FIGS. Hereinafter, a projector using the liquid crystal device as a light valve will be described. FIG. 15 is a plan view showing a configuration example of the projector.

  As shown in FIG. 15, a projector 1100 includes a lamp unit 1102 made up of a white light source such as a halogen lamp. The projection light emitted from the lamp unit 1102 is separated into three primary colors of RGB by four mirrors 1106 and two dichroic mirrors 1108 arranged in the light guide 1104, and serves as a light valve corresponding to each primary color. The light enters the liquid crystal panels 1110R, 1110B, and 1110G.

  The configurations of the liquid crystal panels 1110R, 1110B, and 1110G are the same as those of the liquid crystal device described above, and are driven by R, G, and B primary color signals supplied from the image signal processing circuit. The light modulated by these liquid crystal panels enters the dichroic prism 1112 from three directions. In the dichroic prism 1112, R and B light is refracted at 90 degrees, while G light travels straight. Therefore, as a result of the synthesis of the images of the respective colors, a color image is projected onto the screen or the like via the projection lens 1114.

  Here, paying attention to the display images by the liquid crystal panels 1110R, 1110B, and 1110G, the display image by the liquid crystal panel 1110G needs to be horizontally reversed with respect to the display images by the liquid crystal panels 1110R and 1110B.

  In addition, since light corresponding to each primary color of R, G, and B is incident on the liquid crystal panels 1110R, 1110B, and 1110G by the dichroic mirror 1108, it is not necessary to provide a color filter.

  In addition to the electronic device described with reference to FIG. 15, a mobile personal computer, a mobile phone, a liquid crystal television, a viewfinder type, a monitor direct view type video tape recorder, a car navigation device, a pager, and an electronic notebook , Calculators, word processors, workstations, videophones, POS terminals, devices with touch panels, and the like. Needless to say, the present invention can be applied to these various electronic devices.

  The present invention is not limited to the above-described embodiments, and can be appropriately changed without departing from the spirit or idea of the invention that can be read from the claims and the entire specification, and an electro-optical device with such a change. In addition, an electronic apparatus including the electro-optical device is also included in the technical scope of the present invention.

It is a top view which shows the whole structure of the liquid crystal device which concerns on 1st Embodiment. It is the II-II 'sectional view taken on the line of FIG. 1 is a block diagram illustrating an electrical configuration of a liquid crystal device according to a first embodiment. It is a top view which shows the structure of TFT for sampling. FIG. 5 is a cross-sectional view taken along line V-V ′ in FIG. 4. It is a top view which shows the structure of the light shielding film provided corresponding to the TFT for sampling. It is a top view of the same meaning as FIG. 6 in 2nd Embodiment. It is a top view of the same meaning as FIG. 6 in the modification of 2nd Embodiment. It is a circuit diagram which shows the electrical structure of a scanning line drive circuit. It is a circuit diagram which shows the specific structure of an output buffer. It is a top view which shows the specific structure of the inverter located in the last stage of the output side to a scanning line among the several stages of inverters which comprise an output buffer. It is a top view which shows the structure of the light shielding film provided corresponding to the inverter located in the last stage of the output side to a scanning line among the multiple stages of inverters which comprise an output buffer. It is a block diagram which shows roughly the structure of the liquid crystal device which concerns on 4th Embodiment. It is a circuit diagram which shows the electrical structure of a phase difference correction circuit. It is a top view which shows the structure of the projector which is an example of the electronic device to which the electro-optical apparatus is applied.

Explanation of symbols

  6a ... data line, 7 ... sampling circuit, 9a ... pixel electrode, 10 ... TFT array substrate, 10a ... image display area, 11a ... scanning line, 20 ... counter substrate, 21 ... counter electrode, 50 ... liquid crystal layer, 71 ... sampling TFT for use 101, data line drive circuit, 102, external circuit connection terminal, 104, scanning line drive circuit, 510, light shielding film, 510s, slit

Claims (11)

On the board
A plurality of pixel electrodes;
A transistor provided in a peripheral region located around a pixel region in which the plurality of pixel electrodes are arranged;
A light-shielding film that is disposed on a lower layer side than the transistor, and overlaps at least a part of the transistor when viewed in plan on the substrate and has a longitudinal opening along the channel length direction of the transistor And an electro-optical device.   2. The electro-optical device according to claim 1, wherein a plurality of the openings are formed at a predetermined interval in the channel width direction of the transistor.   3. The electro-optical device according to claim 1, wherein the opening portion at least partially overlaps a channel region of the transistor when viewed in plan on the substrate.   The electro-optical device according to claim 1, wherein the width of the opening is 1 μm or less. The light shielding film is
A first light-shielding portion having the opening;
A second pattern formed adjacent to the first light shielding portion on the side farther from the pixel region than the first light shielding portion along the channel width direction of the transistor and having a different plane pattern from the first light shielding portion. The electro-optical device according to claim 1, further comprising: a light shielding portion.   6. The electro-optical device according to claim 5, wherein the second light-shielding portion is formed so as not to overlap at least partially with the transistor when viewed in plan on the substrate.   The electro-optical device according to claim 1, wherein a channel width of the transistor is 5 μm or more.   The electro-optical device according to claim 1, wherein a channel width of the transistor is longer than a channel length of the transistor. A plurality of scanning lines and a plurality of data lines wired in the pixel region;
An image signal line provided in the peripheral region and supplying an image signal;
The transistors are formed as a plurality of sampling transistors that supply an image signal supplied to the image signal line to the plurality of data lines in response to a sampling signal and are arranged corresponding to the plurality of data lines. The electro-optical device according to claim 1, wherein On the board
A plurality of pixel electrodes;
A complementary transistor provided in a peripheral region located around a pixel region in which the plurality of pixel electrodes are arranged;
The complementary transistor is disposed between the complementary transistor and the substrate. When viewed in plan on the substrate, the transistor overlaps at least one of the complementary transistors and has a longitudinal shape along the channel length direction of the transistor. An electro-optical device comprising: a light-shielding film having an opening formed therein.   An electronic apparatus comprising the electro-optical device according to claim 1.

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