JP3688548B2 - Image display device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to an image display device such as a liquid crystal display device, and more particularly to an image display device capable of obtaining high drive capability and high reliability in a drive circuit for driving the image display device. is there.
[0002]
[Prior art]
  An active matrix liquid crystal display device is known as one of conventional image display devices. This liquid crystal display device is generally composed of a pixel array composed of a plurality of pixels, a drive circuit for driving each pixel, and the like.
[0003]
  By the way, in recent years, in order to reduce the size and resolution of a liquid crystal display device and reduce the mounting cost, attention has been paid to a technique for forming the pixel array for controlling display and the driving circuit on the same substrate. Yes. In such a liquid crystal display device integrated with a drive circuit, for example, a transmissive liquid crystal display device widely used at present, a quartz substrate or a glass substrate used for a pixel array is used as the same substrate. Therefore, a polycrystalline silicon thin film transistor that can be formed on such a substrate is used as an active element constituting the drive circuit.
[0004]
  As shown in FIG. 18, this polycrystalline silicon thin film transistor includes a contamination-preventing silicon oxide film 101 formed on a glass substrate 100, a channel region 102a, a source region 102b, and a silicon oxide film 101 formed on the silicon oxide film 101. It comprises a polycrystalline silicon thin film 102 composed of a drain region 102c, a gate insulating film 103, a gate electrode 104 and an interlayer insulating film 105, and metal wirings 106 and 106, which are sequentially deposited on the polycrystalline silicon thin film 102. . Such a polycrystalline silicon thin film transistor is manufactured, for example, by the following process.
[0005]
  First, after a silicon oxide film (not shown) is formed on the glass substrate 100 shown in FIG. 19A, an amorphous silicon thin film a-Si is deposited thereon (FIG. 19B). Next, the amorphous silicon thin film a-Si is irradiated with an excimer laser to form a polycrystalline silicon thin film 102 (FIG. 19C). The polycrystalline silicon thin film 102 is patterned into a desired shape (FIG. 19D), and a gate insulating film 103 made of silicon dioxide is formed thereon (FIG. 19E).
[0006]
  Further, the gate electrode 104 is formed of aluminum or the like (FIG. 19F). Thereafter, impurities (phosphorus in the n-type region and boron in the p-type region) are implanted into portions to be the source region 102b and the drain region 102c in the polycrystalline silicon thin film 102 (FIGS. 19G and 19H). When the impurity is implanted into the n-type region, the p-type region is masked with the resist 108 (FIG. 19G), and when the impurity is implanted into the p-type region, the n-type region is masked with the resist 108. (FIG. 19 (h)).
[0007]
  Then, an interlayer insulating film 105 made of silicon dioxide, silicon nitride or the like is deposited (FIG. 19 (i)), and contact holes 105a ... are formed in the interlayer insulating film 105 (FIG. 19 (j)). Finally, metal wirings 106 such as aluminum are formed in the contact holes 105a (FIG. 19 (k)).
[0008]
  In the production of a liquid crystal display device, a transparent electrode (in the case of a transmissive liquid crystal display device) or a reflective electrode (reflective type) is formed on the thin film transistor fabricated as described above via another interlayer insulating film. In the case of a liquid crystal display device).
[0009]
[Problems to be solved by the invention]
  By the way, the transistors constituting the drive circuit of the image display device described above have a simple drain structure as shown in FIGS. 20A and 20B, but in addition to this, FIG. In some cases, an LDD (Lightly Doped Drain) structure shown in FIG. This is because the LDD structure can improve the breakdown voltage of the transistor by providing impurity regions (high resistance regions) 115 and 116 having impurity concentrations lower than those of the source region 112 and the drain region 113 on both sides of the channel region 114. This is because it is extremely effective in increasing the reliability of the circuit.
[0010]
  20 (a) and 21 (a) show the structure of an n-channel transistor and a symbol representing it. FIGS. 20 (b) and 21 (b) show the structure of a p-channel transistor and it. The symbol showing is shown. In these drawings, reference numeral 111 denotes a gate electrode.
[0011]
  However, the LDD structure has the merit that the reliability of the circuit can be improved, but the driving force of the transistor is reduced due to the impurity regions 115 and 116 becoming a high resistance region, so that the performance of the circuit is limited. Also have.
[0012]
  For this reason, even if all the transistors constituting the drive circuit of the image display device have an LDD structure, there is a problem that it is impossible to obtain both high reliability and a wide operation margin in the circuit. Such a problem similarly occurs even when a transistor having a GOLD (gate overlapped lightly doped drain) structure in which the gate electrode overlaps the impurity region on the source region side and the impurity region on the drain region side is used.
[0013]
  The present invention has been made in order to solve the above-described problems. The object of the present invention is to change the structure of a transistor constituting a driving circuit of an image display device according to the application, thereby achieving high reliability and wide operation. An object of the present invention is to provide an image display device capable of obtaining both margins.
[0014]
[Means for Solving the Problems]
  In order to solve the above problems, an image display device according to the present invention is provided in a matrix and supplies a plurality of pixels for displaying an image and a signal for driving and displaying the pixels to the pixels. In the image display device including the drive circuit, the drive circuit includes:A transistor having an asymmetric structure between the source region side and the drain region side where current flows only in one direction, and a transistor having a symmetrical structure between the source region side and the drain region side in which the direction of current flow changes. This transistor has an impurity region whose impurity concentration is lower than that of the source region and the drain region only on the drain region side outside the region directly under the gate electrode, and the transistor having the symmetric structure is located outside the region directly under the gate electrode. The impurity region is provided on both the source region side and the drain region side.
[0015]
  The drive circuit includes, for example, a drive circuit for supplying video data to each pixel provided in a matrix and a drive circuit for controlling writing of the video data to the pixels. By controlling the writing of video data to each pixel by these drive circuits, an image corresponding to the video data is displayed at each pixel.
[0016]
  By the way, although these drive circuits are configured to include a plurality of transistors, the operation conditions are not necessarily the same in each transistor. For example, in the above drive circuit, there are a transistor in which the direction of current flow changes and a transistor in which the current flows in one direction.
[0017]
  In the former transistor, the electric field concentration side is switched between the source region side and the drain region side depending on the direction of the current. Therefore, in order to ensure circuit reliability, the lateral electric field should be relaxed. As in the LDD structure or the GOLD structure, it is necessary to provide impurity regions having a lower impurity concentration than the source region side and the drain region as high resistance regions on both the source region side and the drain region side.
[0018]
  However, in the latter transistor, the current concentration side is always only one side on the drain region side, so that the lateral electric field is alleviated only by providing the high resistance region only on one side on the drain region side. Circuit reliability can be ensured. In addition, in this case, since there is no high resistance region on the source region side, the on-resistance of the entire transistor including the parasitic resistance is reduced, and a large driving force can be secured.
[0019]
  In other words, even if all of the transistors do not have a symmetric structure, the reliability of the circuit is ensured by adopting an asymmetrical transistor in which a high resistance region is provided only on the drain side according to the operating conditions of the transistor. As a result, a decrease in driving capability can be minimized. Therefore, according to the above configuration, it is possible to reliably obtain both high reliability and a wide operation margin in the circuit as compared with the case where all of the transistors constituting the driving circuit are configured with the LDD structure or the GOLD structure.
[0020]
  An image display apparatus according to the present inventionAccording toThe drive circuit includes a transistor in which current flows only in one direction, and at least a part of the transistor has the asymmetric structure.
[0021]
  In a transistor in which current flows only in one direction, the current concentration side is always only one side on the drain region side, so that the circuit reliability can be improved by providing the high resistance region only on one side on the drain region side. It can be secured. In addition, in this case, since there is no high resistance region on the source region side, the on-resistance of the entire transistor including the parasitic resistance is reduced, and a large driving force can be secured.
[0022]
  Accordingly, in a transistor in which current flows only in one direction, an asymmetric structure in which a high resistance region is provided only on the drain region side can provide both high reliability and large driving capability in the circuit.
[0023]
  Further, in a transistor in which current flows only in one direction, depending on the applied voltage, the magnitude of the current, a flowing period, and the like, circuit reliability may be ensured without adopting the above asymmetric structure. For example, since a p-channel transistor has a higher element breakdown voltage than an n-channel transistor, circuit reliability can be ensured without adopting the asymmetric structure. In such a case, it is desirable from the viewpoint of driving capability to use a symmetrical structure (simple drain structure) in which the high resistance region is not provided on either the source region side or the drain region side.
[0024]
  That is, by providing at least a part of the transistor in which current flows only in one direction with the above asymmetric structure, both high reliability and a wide operation margin in the circuit can be obtained.
[0025]
  Image display device according to the present inventionAccording toThe drive circuit includes a transistor having a symmetrical structure on the source region side and the drain region side, in which the direction of current flow changes, and the transistor having the asymmetric structure is provided only on the drain region side outside the region immediately below the gate electrode. The transistor having the impurity region and having the symmetric structure has the impurity region on both the source region side and the drain region side outside the region directly below the gate electrode.
[0026]
  In a transistor in which current flows only in one direction, a high electric field is applied only to the drain region side, whereas in a transistor in which the direction of current flow changes, a high electric field is applied to both the source region side and the drain region side. Is done. Therefore, for example, in a transistor in which a current flows only in one direction, a high resistance region having a low impurity concentration is provided only on the drain region side outside the region directly below the gate electrode to form an asymmetric structure (one-side LDD structure). In the transistor in which the flowing direction changes, the high resistance region is provided on both the source region side and the drain region side outside the region immediately below the gate electrode to form a symmetric structure (double-sided LDD structure). As a result, the electric field is relaxed, and high reliability can be obtained in the circuit.
[0027]
  Further, in a transistor in which current flows only in one direction, since there is no high resistance region on the source region side, a reduction in driving capability can be suppressed and a large operation margin can be secured.
[0028]
  In order to solve the above problems, an image display device according to the present invention includes:A transistor having an asymmetric structure between the source region side and the drain region side where current flows only in one direction, and a transistor having a symmetric structure between the source region side and the drain region side, in which the direction of current flow changes,The transistor with the asymmetric structure has the impurity region only on the drain region side in the region immediately below the gate electrode. The transistor with the symmetric structure has both the source region side and the drain region side in the region immediately below the gate electrode. In addition, the semiconductor device has the impurity region.
[0029]
  In a transistor in which current flows only in one direction, a high electric field is applied only to the drain region side, whereas in a transistor in which the direction of current flow changes, a high electric field is applied to both the source region side and the drain region side. Is done. Therefore, for example, in a transistor in which current flows only in one direction, a high resistance region having a low impurity concentration is provided only on the drain region side in a region immediately below the gate electrode to form an asymmetric structure (one-sided GOLD structure), while the direction of current flow In a transistor with a variable resistance, the high resistance region is provided on both the source region side and the drain region side in the region immediately below the gate electrode to form a symmetrical structure (both sides GOLD structure), so that the electric field is relaxed by the high resistance region. Thus, high reliability can be obtained in the circuit.
[0030]
  Further, in a transistor in which current flows only in one direction, since there is no high resistance region on the source region side, a reduction in driving capability can be suppressed and a large operation margin can be secured.
[0031]
  In order to solve the above problems, an image display device according to the present invention includes:A transistor having an asymmetric structure between the source region side and the drain region side where current flows only in one direction, and a transistor having a symmetric structure between the source region side and the drain region side, in which the direction of current flow changes,The transistor with the asymmetric structure has the impurity region only on the drain region side so as to partially overlap the gate electrode, and the transistor with the symmetrical structure has a portion overlapping with the gate electrode. Further, the impurity region is provided on both the source region side and the drain region side.
[0032]
  In a transistor in which current flows only in one direction, a high electric field is applied only to the drain region side, whereas in a transistor in which the direction of current flow changes, a high electric field is applied to both the source region side and the drain region side. Is done. Therefore, for example, in a transistor in which current flows only in one direction, a high resistance region having a low impurity concentration is provided only on the drain region side so as to partially overlap the gate electrode, thereby forming an asymmetric structure (one-side GOLD structure). In a transistor in which the direction of current flow changes, the high-resistance region is provided on both the source region side and the drain region side so as to partially overlap the gate electrode to have a symmetrical structure (both sides GOLD structure). As a result, the electric field is relaxed by the high resistance region, and high reliability can be obtained in the circuit.
[0033]
  Further, in a transistor in which current flows only in one direction, since there is no high resistance region on the source region side, a reduction in driving capability can be suppressed and a large operation margin can be secured.
[0034]
  In order to solve the above problems, in the image display device according to the present invention, only the n-channel transistor among the transistors included in the driver circuit has the impurity region, and the p-channel transistor includes the impurity The transistor is characterized in that it does not include a region and has a symmetrical structure on the source region side and the drain region side.
[0035]
  Since the p-channel transistor has a higher element breakdown voltage than the n-channel transistor, the p-channel transistor does not have a configuration in which the impurity region (high resistance region) is provided on the drain region side. In some cases, the reliability of the circuit can be ensured. Therefore, by providing the high resistance region only in the n-channel transistor and making the p-channel transistor have a simple drain structure, there is an advantage that the driving capability of the p-channel transistor can be increased.
[0036]
  In addition, as long as the n-channel transistor has the above-described high resistance region, it is possible to adopt an asymmetric structure such as a one-side LDD or a one-side GOLD structure or a symmetric structure such as a both-side LDD or a both-side GOLD structure. . Which structure is adopted can be set according to the operating conditions, voltage conditions, and the like of the transistor.
[0037]
  In order to solve the above problems, an image display device according to the present invention includes a logic circuit including a plurality of transistors, and a current flows only in one direction, and at least a part of the transistors is on the drain region side. It is characterized in that it has an asymmetric structure having the impurity region only.
[0038]
  An example of the logic circuit is a CMOS (complementary metal oxide semiconductor) logic circuit. If the current flows only in one direction, in the transistor constituting the logic circuit, for example, if the impurity region is only on the side where the electric field is concentrated (drain region side), the impurity region is a high resistance region. As a result, the electric field is relaxed, and at least the reliability of the circuit can be secured. Further, depending on the applied voltage, the magnitude of the current, the flow period, etc., the reliability of the circuit can be achieved without providing the high resistance region on the drain region side and adopting an asymmetric structure, that is, without providing the high resistance region. In some cases, sex can be secured.
[0039]
  Therefore, by providing at least a part of the transistors constituting the logic circuit with an asymmetric structure, both high reliability and high driving capability can be obtained in the logic circuit and thus the driving circuit.
[0040]
  In order to solve the above problems, an image display device according to the present invention includes:It is configured to include a plurality of transistors, and includes an asymmetric transistor having an impurity region whose impurity concentration is lower than that of the source region and the drain region only on the drain region side,A symmetric structure including a plurality of transistors, including a transfer gate that changes the direction of current flow according to the level of an input signal, and the transfer gate includes the impurity regions on both the source region side and the drain region side It is characterized by being composed of transistors.
[0041]
  In the transfer gate, the direction of current flow changes according to the level of the input signal. Therefore, in the transistor constituting the transfer gate, a high electric field can be applied to either the source region side or the drain region side. Therefore, by forming the transfer gate with a transistor having a symmetric structure having the impurity region on both the source region side and the drain region side, the concentration of the electric field on both sides of the source region side and the drain region side is reduced and the transfer is performed. A reduction in the reliability of the gate and the drive circuit can be avoided.
[0042]
  In order to solve the above problems, an image display device according to the present invention includes:It is configured to include multiple transistors and is more impure than the source and drain regions A transistor having an asymmetric structure having an impurity region with a low concentration of substance only on the drain region side,A sampling circuit for sampling an analog video signal to be supplied to each pixel is provided, and the sampling circuit is configured by a transistor having a symmetric structure having the impurity regions on both the source region side and the drain region side. .
[0043]
  In the sampling circuit, the direction of current flow changes according to the level of the input analog video signal. Therefore, in the transistor constituting the sampling circuit, a high electric field is present on either the source region side or the drain region side. Can be applied. Therefore, by forming a sampling circuit with a transistor having a symmetric structure having the impurity region on both the source region side and the drain region side, the concentration of the electric field on both sides of the source region side and the drain region side is reduced and sampling is performed. A decrease in the reliability of the circuit and the drive circuit can be avoided.
[0044]
  In order to solve the above problems, the image display device according to the present invention is configured such that the drive circuit includes a plurality of circuits driven by a plurality of power supply voltages, and the width of the impurity region of the transistor in each circuit is The transistor is set according to the power supply voltage corresponding to the transistor.
[0045]
  When the power supply voltage corresponding to an arbitrary circuit is high, the electric field applied to the drain region in the transistor of the circuit is also high. In this case, in order to reduce the electric field, it is necessary to increase the width of the impurity region (high resistance region) provided on the drain region side of the transistor.
[0046]
  Therefore, by setting the width (length) of the high resistance region of the transistor in accordance with the power supply voltage corresponding to the transistor of each circuit, the electric field that is concentrated can be generated regardless of what power supply voltage is applied to the circuit. Therefore, the reliability of the circuit can be reliably improved.
[0047]
  In order to solve the above problems, an image display device according to the present invention controls a plurality of data signal lines for supplying video data to be written to the pixels, and writing of the video data to the pixels. A plurality of scanning signal lines, and the driving circuit includes a data signal line driving circuit for driving the data signal line and a scanning signal line driving circuit for driving the scanning signal line. It is characterized by being.
[0048]
  The scanning signal line driving circuit controls the writing of the video data supplied to each pixel by the data signal line driving circuit through the plurality of data signal lines through the plurality of scanning signal lines. It is possible to display an image corresponding to video data in the pixel.
[0049]
  In the image display device according to the present invention, in order to solve the above problems, at least one of the data signal line driving circuit and the scanning signal line driving circuit is formed on a substrate on which the pixels are formed. It is characterized by.
[0050]
  According to the above configuration, at least one of the data signal line driving circuit and the scanning signal line driving circuit can be formed on the same substrate as the pixel by the same process, and the manufacturing cost and the mounting cost can be reduced. The rate can be expected to increase.
[0051]
  In order to solve the above problems, the image display device according to the present invention is characterized in that an active element constituting at least one of the data signal line driving circuit and the scanning signal line driving circuit is a polycrystalline silicon thin film transistor. It is said.
[0052]
  When a transistor is formed using a polycrystalline silicon thin film in this manner, the characteristics described above can be obtained because it has extremely high driving power compared to an amorphous silicon thin film transistor used in a conventional active matrix liquid crystal display device. In addition, there is an advantage that at least one of the signal line driver circuit and the scanning signal line driver circuit and the pixel can be easily formed on the same substrate.
[0053]
  In addition, since the polycrystalline silicon thin film transistor is inferior in crystallinity as compared with the single crystal silicon transistor, the breakdown voltage is low even in an element of the same size, and the driving capability is also small. Therefore, it is generally difficult to construct a high-performance circuit using a polycrystalline silicon thin film transistor.
[0054]
  However, according to the present invention, high reliability and high drive capability can be obtained at the same time in the circuit. Therefore, when a polycrystalline silicon thin film transistor is applied to the image display device of the present invention, high reliability and good performance are obtained. Image display can be realized.
[0055]
  In order to solve the above problems, the image display device according to the present invention is characterized in that the active element is formed at a temperature of 600 ° C. or lower.
[0056]
  As described above, when a polycrystalline silicon thin film transistor is formed at a process temperature of 600 ° C. or lower, glass having a low strain point temperature but low in cost and easy to enlarge can be used as the substrate. In addition to the effect, a large image display device can be manufactured at low cost.
[0057]
DETAILED DESCRIPTION OF THE INVENTION
  [Embodiment 1]
  An embodiment of the present invention will be described below with reference to the drawings.
[0058]
  The image display device according to the present embodiment is an active matrix drive type liquid crystal display device. As shown in FIG. 2, the pixel array 1, the scanning signal line drive circuit 2, the data signal line drive circuit 3, and the precharge circuit 4 are used. And the control circuit 5 and the like.
[0059]
  The pixel array 1 includes a plurality of data signal lines SL (SL_i, SL_{i + 1},...; I is a natural number) and a plurality of scanning signal lines GL (GL) arranged in the row direction._j, GL_{j + 1},...; J is a natural number). That is, the data signal line SL and the scanning signal line GL intersect each other vertically. A pixel (in the drawing, PIX) 1a is provided in a portion surrounded by two adjacent data signal lines SL and two adjacent scanning signal lines GL. Therefore, the pixels 1a are provided in a matrix.
[0060]
  As shown in FIG. 3, the pixel 1a includes a pixel transistor SW as a switching element and a liquid crystal capacitor C._L Including pixel capacitance C_P (Auxiliary capacity C if necessary_SIs added). In the pixel 1a, the data signal line SL and the pixel capacitance C are connected via the drain and source of the pixel transistor SW._POf the pixel transistor SW, the gate of the pixel transistor SW is connected to the scanning signal line GL, and the pixel capacitance C_P The other electrode is connected to a common electrode line (not shown) common to all pixels. As a result, the liquid crystal capacitance C in the pixel capacitance CP is obtained._L When a voltage is applied to the liquid crystal, the transmittance or reflectance of the liquid crystal is modulated, and an image corresponding to the video signal DAT is displayed on the pixel array 1.
[0061]
  The data signal line driving circuit 3 samples the input video signal (data) DAT in synchronization with a control signal such as the clock signal CKS, amplifies it as necessary, and outputs it to each data signal line SL.
[0062]
  The scanning signal line driving circuit 2 sequentially selects the scanning signal line GL in synchronization with a control signal such as the clock signal CKG, and controls the opening / closing of the pixel transistor SW in the pixel 1a, whereby each data signal line SL is supplied to each data signal line SL. The output video signal DAT is written in each pixel 1a and held in each pixel 1a.
[0063]
  The precharge circuit 4 is a circuit provided as necessary to assist the output of the video signal to the data signal line SL, and before the video signal is output from the data signal line driving circuit 3 to the data signal line SL. In addition, the data signal line is precharged.
[0064]
  The control circuit 5 is a circuit that generates various control signals for controlling operations of the scanning signal line driving circuit 2, the data signal line driving circuit 3, and the precharge circuit 4. As control signals, a clock signal GCK / SCK, a start signal GST / SST, an enable signal GEN, a video signal DAT, a precharge control signal PCT, a charge level signal PSG, and the like are prepared.
[0065]
  By the way, as a driving method of the data signal line, a dot sequential driving method and a line sequential driving method are known from the difference in the input video signal DAT. In general, in a polycrystalline silicon TFT panel in which a drive circuit and a pixel are integrated, a dot sequential drive type drive circuit is often used because of the simplicity of the circuit configuration. Therefore, details of the data signal line driving circuit 3 and the scanning signal line driving circuit 2 of the dot sequential driving method will be described below.
[0066]
  The data signal line driving circuit 3 includes a shift register circuit 11, a buffer circuit 12, and a sampling circuit 13, for example, as shown in FIG. The shift register circuit 11 includes a plurality of flip-flop circuits 11a and a NAND gate 11b, and sequentially transfers the start signal SST at the timing of the clock signal SCK and the inverted clock signal / SCK (inverted signal of SCK). . The buffer circuit 12 takes in the pulse signal output from the shift register circuit 11, holds and amplifies it, and generates an inverted signal as necessary. The sampling circuit 13 is turned on by a control signal to take in and sample the input analog video signal DAT and to sample the data signal line SL._n (N = 1, 2, 3,...)
[0067]
  That is, in the dot sequential driving method, the input video signal DAT is output pulse SN of each stage (each flip-flop circuit 11a) of the shift register circuit 11._n By opening and closing the sampling circuit 13 in synchronization with (n = 1, 2, 3,...), The data signal line SL_n(N = 1, 2, 3, 4,...) Here, in the configuration of FIG. 4, the sampling signal S is obtained from the overlapping pulse of the output signals from the two adjacent flip-flop circuits 11a._n, / S_n (S_n Inverted signal) is generated. Therefore, the sampling signal S_n Falling edge and sampling signal / S_nThe video signal DAT at the rise timing of the data signal line SL_n Is output.
[0068]
  As shown in FIG. 5, the scanning signal line driving circuit 2 includes a shift register 11 that sequentially transfers the start signal GST at the timing of the clock signal GCK and the inverted clock signal / GCK (inverted signal of GCK). In the scanning signal line driving circuit 2, the output signals GN of two adjacent flip-flop circuits 11a and 11a in the shift register 11 are used._n The logical operation (n = 1, 2, 3,...) Is performed by the NAND gate 11b. Then, a logical operation of the output pulse of the NAND gate 11b and the inverted signal / GEN of the enable signal GEN supplied from the control circuit 5 is performed in the NOR gate 14, and the result is scanned as a scanning signal through the buffer circuit 15. Signal line GL_n(N = 1, 2, 3,...)
[0069]
  The scanning signal line drive circuit 2 outputs an output pulse signal GN that is sequentially transferred in synchronization with the clock signal GCK._n And the product (AND) signal of the signal GPS defining the pulse width with the scanning signal line GL_nIt can also be set as the structure output to.
[0070]
  Writing and holding of the video signal DAT to each pixel is controlled by the scanning signal described above.
[0071]
  Next, the structure of the transistors constituting the data signal line driving circuit 3 and the scanning signal line driving circuit 2 will be described.
[0072]
  FIG. 1A to FIG. 1D show the structures of transistors constituting the data signal line driving circuit 3 and the scanning signal line driving circuit 2 provided in the image display device according to the present invention, and symbols representing them. Yes. Note that the transistors in FIGS. 1A and 1B are n-channel transistors, and the transistors in FIGS. 1C and 1D are p-channel transistors.
[0073]
  In the transistors of FIGS. 1A and 1C, a source region 22c and a drain region 22d are provided between a source region 22c and a drain region 22d (each high-concentration impurity region) and a channel region 22e (a region immediately below the gate electrode). Lower impurity concentration regions 22a and 22b are formed. And the impurity region on the source side22aAnd drain side impurity regions22bA part of each overlaps with the gate electrode 25.
[0074]
  On the other hand, in the transistors of FIGS. 1B and 1D, the impurity region 22b having a lower concentration than the drain region 22d is formed only between the channel region 22e and the drain region 22d. An impurity region having a lower concentration than the source region 22c is not formed between the source region 22c and the source region 22c. A part of the drain-side impurity region 22 b overlaps with the gate electrode 25.
[0075]
  Accordingly, the transistors in FIGS. 1A and 1C have a symmetric structure on the source side and the drain side, and the transistors in FIGS. 1B and 1D have an asymmetric structure on the source side and the drain side. It has become.
[0076]
  1A and 1C, the impurity regions 22a and 22b both overlap the gate electrode 25. Therefore, such a structure is called a double-sided GOLD structure in this embodiment. On the other hand, in the transistors shown in FIGS. 1B and 1D, only the impurity region 22b on one side overlaps the gate electrode 25. Therefore, such a structure is called a one-sided GOLD structure in this embodiment.
[0077]
  Here, the transistors in FIGS. 1A to 1D are applied to, for example, the flip-flop circuit (latch circuit) 11a of the shift register circuit 11 in the scanning signal line driving circuit 2 and the data signal line driving circuit 3. Is as follows.
[0078]
  As shown in FIG. 6, the flip-flop circuit 11 a includes three inverters 31, 32, and 33 and two transfer gates 34 and 35. Each of the inverters 31, 32, and 33 is formed by connecting an n-channel transistor 41 shown in FIG. 1B and a p-channel transistor 42 shown in FIG. On the other hand, each of the transfer gates 34 and 35 is formed by connecting an n-channel transistor 43 shown in FIG. 1A and a p-channel transistor 44 shown in FIG. 1C in parallel.
[0079]
  Here, in the transistors constituting the inverters 31, 32, and 33, the current flows only in one direction (from the power source to the ground), whereas in the transistors constituting the transfer gates 34 and 35, the direction of the current is Since it varies depending on the signal level, current can flow in both directions (source and drain directions).
[0080]
  Therefore, in the present embodiment, the transistors constituting the inverters 31, 32, and 33 are asymmetrical transistors, while the transistors constituting the transfer gates 34 and 35 are symmetrically structured transistors.
[0081]
  On the other hand, if the transistors in FIGS. 1A to 1D are applied to, for example, a circuit subsequent to the flip-flop circuit 11a in the data signal line driving circuit 3, the following results.
[0082]
  As shown in FIG. 7, the NAND circuit 11b of the data signal line driving circuit 3 includes two n-channel transistors 41 shown in FIG. 1B and two p-channel transistors shown in FIG. 42. The buffer circuit 12 is composed of three inverters 36, 37, and 38. Each of the inverters 36, 37, and 38 is formed by connecting an n-channel transistor 41 and a p-channel transistor 42 in series between a power source and a ground. The sampling circuit 13 is formed by connecting an n-channel transistor 43 shown in FIG. 1A and a p-channel transistor 44 shown in FIG. 1C in parallel. Each of the n-channel transistor 43 and the p-channel transistor 44 constitutes an analog switch.
[0083]
  Here, the NAND circuit 11b and the inverters 36, 37, and 38 are logic circuits. In the transistors that form these, current flows only in one direction (from the power source to the ground), while the sampling circuit 13 In the constituent transistors, the direction of the current varies depending on the signal level, so that the current can flow in both directions.
[0084]
  Therefore, in the present embodiment, the transistors constituting the NAND circuit 11b and the inverters 36, 37, and 38 are asymmetrical transistors, while the transistors constituting the sampling circuit 13 are symmetrical transistors.
[0085]
  In this way, at least a part of the transistors constituting the data signal line driving circuit 3 and the scanning signal line driving circuit 2 by selectively using a transistor having a symmetric structure and an asymmetric structure in accordance with the operation state of the transistor (how the current flows). The reason for adopting an asymmetric structure is as follows.
[0086]
  In general, in a transistor in which the direction in which current flows changes, the side where the electric field is concentrated is switched between the source side and the drain side depending on the direction of the current. Therefore, in order to secure the reliability of the circuit, it is possible to provide impurity regions 22a and 22b as in the LDD structure or the GOLD structure in order to reduce the electric field in the lateral direction.
[0087]
  However, in a transistor in which current flows only in one direction, the current concentration side is always only one side on the drain side, so there is no need to provide the impurity region 22a on the source side, and the impurity region 22b on the drain side. If it is provided, it becomes possible to relax the electric field in the lateral direction and ensure the reliability of the circuit. In addition, in this case, since there is no high resistance region on the source side, the on-resistance of the entire transistor including the parasitic resistance is reduced, and a large driving force can be secured.
[0088]
  In other words, even if not all of the transistors constituting each driving circuit have a symmetric structure, the reliability of the circuit is ensured by adopting an asymmetrical transistor having only the impurity region 22b according to the operating conditions of the transistor. However, a decrease in driving capability can be minimized.
[0089]
  Therefore, a transistor in which current flows only in one direction (in the above example, the transistors constituting the inverters 31, 32, and 33, the NAND circuit 11b, and the inverters 36, 37, and 38) has an asymmetric structure (one-sided GOLD structure) having only the impurity region 22b. ), And a transistor in which the direction of current flow (transistor constituting the transfer gates 34 and 35 and the sampling circuit 13 in the above example) has a symmetric structure (both sides) having both impurity regions 22a and 22b. By configuring with a transistor having a GOLD structure, both high reliability and a wide operation margin can be reliably obtained in the circuit as compared with a case where all transistors are configured with a GOLD structure on both sides.
[0090]
  By the way, the transistors constituting the data signal line driving circuit 3 and the scanning signal line driving circuit 2 are not limited to those shown in FIGS. 1 (a) to 1 (d).
[0091]
  For example, FIGS. 8A to 8D show another structure of the transistor and a symbol representing it. Note that the transistors in FIGS. 8A and 8B are n-channel transistors, and the transistors in FIGS. 8C and 8D are p-channel transistors.
[0092]
  In the transistors of FIGS. 8A and 8C, impurity regions 22a and 22b are formed between the source region 22c and drain region 22d (each high-concentration impurity region) and the channel region 22e, respectively. These impurity regions 22a and 22b are provided so as to overlap the gate electrode 25 only in the region immediately below the gate electrode.
[0093]
  On the other hand, in the transistors of FIGS. 8B and 8D, the impurity region 22b is formed only between the channel region 22e and the drain region 22d, and the source region 22c is formed between the channel region 22e and the source region 22c. A lower concentration impurity region is not formed. The impurity region 22b on the drain side is provided so as to overlap with the gate electrode 25 only in a region immediately below the gate electrode.
[0094]
  Accordingly, the transistors in FIGS. 8A and 8C have a symmetric structure on the source side and the drain side, and the transistors in FIGS. 8B and 8D have an asymmetric structure on the source side and the drain side. It has become.
[0095]
  8A and 8C has a structure in which both impurity regions 22a and 22b overlap with the gate electrode 25, and has a double-sided GOLD structure. On the other hand, the transistors in FIGS. 8B and 8D have a one-sided GOLD structure in which only the impurity region 22b on one side overlaps the gate electrode 25.
[0096]
  The transistors shown in FIGS. 8A to 8D are basically the same as those shown in FIGS. 1A to 1D except that the impurity regions 22a and 22b and the gate electrode 25 are overlapped. The structure is the same as that of the transistor. Therefore, the effect of this embodiment can be obtained even when the transistors of FIGS. 8A to 8D are used instead of the transistors of FIGS. 1A to 1D.
[0097]
  For example, FIGS. 9A to 9D show still another structure of the transistor and symbols representing it. Note that the transistors in FIGS. 9A and 9B are n-channel transistors, and the transistors in FIGS. 9C and 9D are p-channel transistors.
[0098]
  9A and 9C, impurity regions 22a and 22b are formed between a source region 22c and a drain region 22d (each high-concentration impurity region) and a channel region 22e, respectively. The channel region 22 e is formed immediately below the gate electrode, and the impurity regions 22 a and 22 b do not overlap with the gate electrode 25. That is, in the transistor, the impurity regions 22a and 22b are formed outside the region immediately below the gate electrode.
[0099]
  On the other hand, in the transistors of FIGS. 9B and 9D, the impurity region 22b is formed only between the channel region 22e and the drain region 22d, and the source region is formed between the channel region 22e and the source region 22c. Impurity regions having a concentration lower than that of 22c are not formed. The channel region 22 e is formed immediately below the gate electrode, and the drain-side impurity region 22 b does not overlap the gate electrode 25. That is, in the transistor, the impurity region 22b is formed on the drain side outside the region immediately below the gate electrode.
[0100]
  Accordingly, the transistors in FIGS. 9A and 9C have a symmetric structure on the source side and the drain side, and the transistors in FIGS. 9B and 9D have an asymmetric structure on the source side and the drain side. It has become.
[0101]
  9A and 9C has a double-sided LDD structure in which the impurity regions 22a and 22b do not overlap the gate electrode 25. On the other hand, the transistors of FIGS. 9B and 9D have a configuration in which only one impurity region 22b is provided in the LDD structure, and this structure is referred to as a one-side LDD structure in this embodiment.
[0102]
  The transistors in FIGS. 9A to 9D are basically the same as those in FIGS. 1A to 1D except that the impurity regions 22a and 22b and the gate electrode 25 are different from each other. It has the same structure as the transistor d). Therefore, the effect of this embodiment can be obtained even when the transistors of FIGS. 9A to 9D are used instead of the transistors of FIGS. 1A to 1D.
[0103]
  FIG. 10 shows a configuration in which a level shift circuit (indicated by LS in the figure) 16 is provided between the two inverters 15a and 15b that constitute the buffer circuit 15 of the scanning line driving circuit 2. In this configuration, drive power supplies corresponding to the scanning circuit portion before the level shift circuit 16 and the output circuit portion after the level shift circuit 16 are provided. In this case, the output circuit portion is driven with a voltage (VDD2) higher than the drive voltage (VDD1) of the scanning circuit portion.
[0104]
  When the scanning line driving circuit is configured by a circuit driven by a plurality of power supply voltages as described above, the width (length) of the low-concentration impurity regions 22a and 22b in each transistor is set according to the corresponding power supply voltage. In this way, an optimum combination of reliability and driving capability can be realized in each circuit portion.
[0105]
  [Embodiment 2]
  The following will describe another embodiment of the present invention with reference to the drawings. For convenience of explanation, the same components as those in the first embodiment are denoted by the same member numbers, and the description thereof is omitted.
[0106]
  As shown in FIG. 11, the image display apparatus according to the present embodiment is similar to the image display apparatus according to the first embodiment. The pixel array 1, the scanning signal line drive circuit 2, the data signal line drive circuit 3, and the pre- A charge circuit 4 and a control circuit 5 are provided, and a power supply circuit 6 is further provided. In the present embodiment, the pixel array 1, the scanning line driving circuit 2, and the data signal line driving circuit 3 are formed on the same substrate. The scanning signal line drive circuit 2 and the data signal line drive circuit 3 are driven by a control circuit 5 and a power supply circuit 6.
[0107]
  The power supply circuit 6 is a high-potential-side power supply voltage applied to the scanning signal line drive circuit 2V _GH And low-side power supply voltageV _GL , And the power supply voltage V on the high potential side applied to the data signal line drive circuit 3 and the precharge circuit 4_SHAnd low-potential side power supply voltage V_SLIs output. The power supply circuit 6 outputs a common potential COM applied to the common electrode on the counter substrate.
[0108]
  In such a configuration, since the data signal line driving circuit 3 is widely dispersed and arranged in an area having almost the same length as the screen (display area), the wiring length of the signal line or the like is extremely long. . As a result, the rounding of the signal is increased and the operation margin is reduced, so that the effect of the present invention is increased.
[0109]
  Further, by forming the scanning signal line driving circuit 2 and the data signal line driving circuit 3 on the same substrate as the pixel array 1 (in a monolithic manner), the manufacturing cost of the driving circuit can be reduced compared to the case where they are separately configured and mounted. In addition, the mounting cost can be reduced and the reliability can be improved. Even if only one of the above circuits is formed on the same substrate as the pixel array 1, the above effect can be obtained.
[0110]
  In the case of forming a transmissive liquid crystal display device, it is necessary to form a display portion (pixel portion) using a transparent substrate such as quartz or glass. As an active element, an amorphous silicon thin film transistor or a polycrystalline silicon thin film transistor is used. Etc. can be used.
[0111]
  On the other hand, in order to form a drive circuit, a transistor with high drive capability is required. Therefore, it is desirable that the scanning signal line driving circuit 2 and the data signal line driving circuit 3 are configured using a polycrystalline silicon thin film transistor having a high driving capability.
[0112]
  Here, since the polycrystalline silicon thin film transistor can be formed using a transparent substrate such as quartz or glass, the polycrystalline silicon thin film transistor can be formed on the same transparent substrate as the pixel array 1 in the same manufacturing process. The scanning signal line driving circuit 2 and the data signal line driving circuit 3 having a practical driving capability can be configured. Therefore, the configuration of the present embodiment in which each drive circuit and the pixel array 1 are integrally formed using a polycrystalline silicon thin film transistor is more effective than the first embodiment.
[0113]
  By the way, the polycrystalline silicon thin film transistor has a driving capability with the same size of 1 to 2 orders of magnitude smaller than that of a single crystal silicon transistor (MOS transistor), and it is difficult to ensure an operation margin. Therefore, in the present embodiment, as in the first embodiment, a region having a low impurity concentration is provided on one side (drain region side) or both sides (source region side and drain region side) of the channel region as necessary. An operation margin is secured. Specifically, the transistors shown in FIGS. 12A to 12C are used.
[0114]
  FIGS. 12A to 12C show the structures of the transistors constituting the data signal line driving circuit 3 and the scanning signal line driving circuit 2 provided in the image display device according to the present embodiment, and the symbols representing them. ing. Note that the transistors in FIGS. 12A and 12B are n-channel transistors, and the transistor in FIG. 12C is a p-channel transistor.
[0115]
  That is, the transistor in FIGS. 12A and 12B has the same structure as the transistor in FIGS. 1A and 1B, and the transistor in FIG. 12C has a lower concentration than the transistor in FIG. It has a simple drain structure having no impurity region. Accordingly, the transistors in FIGS. 12A and 12C have a symmetric structure (both sides GOLD structure only in FIG. 12A), and only the transistor in FIG. 12B has an asymmetric structure (one-side GOLD structure).
[0116]
  That is, of the transistors constituting the data signal line driving circuit 3 and the scanning signal line driving circuit 2, only the n-channel transistors have the impurity regions 22a and 22b, and the p-channel transistors are the impurity regions 22a and 22b. Is a transistor having a symmetrical structure on the source side and the drain side.
[0117]
  In general, a p-channel transistor has higher device breakdown voltage than an n-channel transistor, and thus reliability may be ensured without adopting a structure having a low-concentration impurity region. In such a case, the current driving force becomes larger when the simple drain structure is adopted, and the operation margin can be expanded. For this reason, in this embodiment, only a simple drain structure is adopted in the p-channel transistor. Therefore, for example, the p-channel transistors 42 and 44 in FIGS. 6 and 7 are both replaced with transistors having the structure of FIG. 12C in this embodiment.
[0118]
  In this case, only a part of the transistors constituting the logic circuit (inverters 31, 32, and 33 in FIG. 6) and the buffer circuit 12 (inverters 36, 37, and 38 in FIG. 7) in which current flows only in one direction has an asymmetric structure. A transistor (n-channel transistor 41 in the figure) is formed. In other words, according to the present invention, in a transistor in which current flows only in one direction, at least a part of the transistor may be an asymmetric structure.
[0119]
  Next, a method for manufacturing the transistor shown in FIGS. 13A to 13K are cross-sectional views in the manufacturing process of the transistor.
[0120]
  First, an amorphous silicon thin film a-Si is deposited on the glass substrate 21 (FIG. 13A). Next, the amorphous silicon thin film a-Si is irradiated with an excimer laser to form a polycrystalline silicon thin film 22 (FIG. 13B). The polycrystalline silicon thin film 22 is patterned into a desired shape (FIG. 13 (c)), and a resist (23) is used to form phosphorus (P^-By locally implanting ions), a low concentration impurity region (n^- Regions) 22a and 22b are formed (FIG. 13D). Note that, in the polycrystalline silicon thin film 22, a region 22e immediately under the gate electrode into which low-concentration impurities are not implanted is a channel region. Thereafter, a gate insulating film 24 made of silicon dioxide is formed (FIG. 13E).
[0121]
  Further, after the gate electrode 25 is formed of aluminum or the like so as to overlap with the impurity regions 22a and 22b (FIG. 13F), the source region (n⁺ Region) 22c and drain region (n⁺ Impurities are implanted into the portion to be the region 22d (FIGS. 13G and 13H). At this time, phosphorus (P⁺Ions) and boron (B) in the p-type region.⁺ Ions)).
[0122]
  Note that when the impurity is implanted into the n-type region, the resist 26 is masked to cover the gate electrode 25 (FIG. 13G). Thereby, the impurity regions 22a and 22b are formed outside the region directly under the gate electrode. On the other hand, when the impurity is implanted into the p-type region, the n-type region is masked with the resist 26 (FIG. 13H).
[0123]
  Then, an interlayer insulating film 27 made of silicon dioxide, silicon nitride or the like is deposited (FIG. 13 (i)), and contact holes 27a ... are formed in the interlayer insulating film 27 (FIG. 13 (j)). Finally, metal wirings 28 such as aluminum are formed in the contact holes 27a (FIG. 13 (k)).
[0124]
  In the liquid crystal display device, thereafter, a transparent electrode (in the case of a transmission type liquid crystal display device) and a reflection electrode (in the case of a reflection type liquid crystal display device) are formed via another interlayer insulating film.
[0125]
  In the manufacture of the transistor having the structure of FIG. 12B, the mask pattern of the resist 23 is appropriately set when impurities are implanted in the step of FIG. 13D, so that the concentration is lower than that of the source region 22c. The impurity region 22a may be prevented from being formed.
[0126]
  The polycrystalline silicon thin film transistor as an active element manufactured in the above process is formed at a process temperature of 600 ° C. or lower. In the case of forming the transistor, an inexpensive glass substrate having a large area can be used, so that it is possible to easily realize a reduction in price and an increase in area of the image display device.
[0127]
  Incidentally, in addition to the transistors having the structures shown in FIGS. 12A to 12C, for example, transistors having the structures shown in FIGS. 14A to 14C may be used.
[0128]
  14A to 14C show other structures of the transistors constituting the data signal line driving circuit 3 and the scanning signal line driving circuit 2 provided in the image display device according to the present embodiment, and symbols representing the same. Is shown. Note that the transistors in FIGS. 14A and 14B are n-channel transistors, and the transistor in FIG. 14C is a p-channel transistor.
[0129]
  That is, the transistor in FIGS. 14A and 14B has the same structure as the transistor in FIGS. 8A and 8B, and the transistor in FIG. 14C is the same as the transistor in FIG. It is a simple drain structure. Accordingly, the transistors in FIGS. 14A and 14C have a symmetrical structure (both sides GOLD structure only in FIG. 14A), and only the transistor in FIG. 14B has an asymmetric structure (one-sided GOLD structure). In the p-channel transistor, by adopting a simple drain structure as described above, a large current driving capability can be obtained and an operation margin can be expanded.
[0130]
  Next, a method for manufacturing the transistor shown in FIGS. FIG. 15A to FIG. 15K are cross-sectional views in the manufacturing process of the transistor.
[0131]
  First, an amorphous silicon thin film a-Si is deposited on the glass substrate 21 (FIG. 15A). Next, the amorphous silicon thin film a-Si is irradiated with an excimer laser to form a polycrystalline silicon thin film 22 (FIG. 15B). This polycrystalline silicon thin film 22 is patterned into a desired shape (FIG. 15C), and a resist 23 is used to form phosphorus (P^-By locally implanting ions), a low concentration impurity region (n^- Regions) 22a and 22b are formed (FIG. 15D). In the polycrystalline silicon thin film 22, the region 22e into which the low concentration impurity is not implanted is a region that becomes a channel region. Thereafter, a gate insulating film 24 made of silicon dioxide is formed (FIG. 15E).
[0132]
  Further, after the gate electrode 25 is formed of aluminum or the like so as to overlap the impurity regions 22a and 22b (FIG. 15F), the source region (n⁺ Region) 22c and drain region (n⁺ Impurities are implanted into the portion to be the region 22d (FIGS. 15G and 15H). At this time, phosphorus (P⁺Ions) and boron (B⁺ Ions).
[0133]
  When implanting impurities into the n-type region, unlike FIG. 13G, only the p-type region is masked with the resist 26 (FIG. 15G), and the impurity is implanted into the p-type region. In this case, the n-type region is masked with the resist 26 (FIG. 15H). Even if the n-type region is not masked with the resist 26, the gate electrode 25 serves as a mask during the impurity implantation, and as a result, the low-concentration impurity regions 22a and 22b remain just under the gate electrode.
[0134]
  Then, an interlayer insulating film 27 made of silicon dioxide, silicon nitride or the like is deposited (FIG. 15 (i)), and contact holes 27a ... are formed in the interlayer insulating film 27 (FIG. 15 (j)). Finally, metal wirings 28 such as aluminum are formed in the contact holes 27a (FIG. 15 (k)).
[0135]
  In the liquid crystal display device, thereafter, a transparent electrode (in the case of a transmission type liquid crystal display device) and a reflection electrode (in the case of a reflection type liquid crystal display device) are formed via another interlayer insulating film.
[0136]
  In the manufacture of the transistor having the structure shown in FIG. 14B, the mask region of the resist 23 is set appropriately when impurities are implanted in the step shown in FIG. The impurity region 22a may be prevented from being formed.
[0137]
  In addition to the transistors having the structures shown in FIGS. 12A to 12C, for example, transistors having the structures shown in FIGS. 16A to 16C may be used.
[0138]
  FIGS. 16A to 16C show still another structure of the transistors constituting the data signal line driving circuit 3 and the scanning signal line driving circuit 2 included in the image display device according to the present embodiment, and the structure thereof. The symbol is shown. Note that the transistors in FIGS. 16A and 16B are n-channel transistors, and the transistor in FIG. 16C is a p-channel transistor.
[0139]
  That is, the transistor in FIGS. 16A and 16B has the same structure as the transistor in FIGS. 9A and 9B, and the transistor in FIG. 16C is the same as the transistor in FIG. It is a simple drain structure. Therefore, the transistors in FIGS. 16A and 16C have a symmetrical structure (both sides LDD structure in FIG. 16A only), and only the transistor in FIG. 16B has an asymmetric structure (one-side LDD structure). In the p-channel transistor, by adopting a simple drain structure as described above, a large current driving capability can be obtained and an operation margin can be expanded.
[0140]
  Next, a method for manufacturing the transistor shown in FIGS. FIG. 17A to FIG. 17K are cross-sectional views in the manufacturing process of the transistor.
[0141]
  First, an amorphous silicon thin film a-Si is deposited on the glass substrate 21 (FIG. 17A). Next, the amorphous silicon thin film a-Si is irradiated with an excimer laser to form a polycrystalline silicon thin film 22 (FIG. 17B), and the polycrystalline silicon thin film 22 is patterned into a desired shape (FIG. 17B). FIG. 17 (c)). Next, a gate insulating film 24 made of silicon dioxide is formed (FIG. 17D), and a gate electrode 25 is formed thereon with aluminum or the like (FIG. 17E).
[0142]
  Then, the p-type region is masked with the resist 23, and the n-type region is masked with the resist 23 so as to cover the gate electrode 25, and phosphorus (P⁺ Ions) are implanted locally (FIG. 17F). As a result, in the n-type region, the source region (n⁺Region) 22c. Drain region (n⁺ Region) 22d is formed.
[0143]
  Next, the p-type region is masked with a resist 26 and the n-type region is phosphorus (P^- Ions) are implanted (FIG. 17G). At this time, since the gate electrode 25 serves as a mask in the n-type region, an impurity region (concentration lower than that of the source region 22c and the drain region 22d) is formed between the region immediately below the gate electrode and the source region 22c and the drain region 22d. n @-regions) 22a and 22b are formed. Further, the n-type region is masked with a resist 26 and boron (B⁺ Ions) are implanted (FIG. 17H).
[0144]
  Then, an interlayer insulating film 27 made of silicon dioxide, silicon nitride or the like is deposited (FIG. 17I), and contact holes 27a... Are formed in the interlayer insulating film 27 (FIG. 17J). Finally, metal wirings 28 such as aluminum are formed in the contact holes 27a (FIG. 17 (k)).
[0145]
  In the liquid crystal display device, thereafter, a transparent electrode (in the case of a transmission type liquid crystal display device) and a reflection electrode (in the case of a reflection type liquid crystal display device) are formed via another interlayer insulating film.
[0146]
  Further, in the manufacture of the transistor having the structure of FIG. 16B, the mask region of the resist 23 is appropriately set when the impurity is implanted in the step of FIG. 17F, so that the concentration is lower than that of the source region 22c. The impurity region 22a may be prevented from being formed.
[0147]
  By the way, when a polycrystalline silicon thin film transistor is used as an active element constituting the data signal line driving circuit 3 and the scanning signal line driving circuit 2, there are the following merits.
[0148]
  For example, a normal IC (integratedcircuit), The number of masks increases by one (the number of processes increases) as compared with the double-sided LDD structure. That is, in an IC, generally, an impurity is implanted using a side wall of a gate electrode as a mask to form a symmetric structure for forming an LDD structure. Since it is necessary to remove only the side wall, the process (photo process + etching process) for that purpose increases.
[0149]
  On the other hand, in the manufacturing process of a polycrystalline silicon thin film transistor (TFT), it is necessary to increase the length of the LDD due to characteristic restrictions, and therefore cannot be realized in the side wall process. A process is required. Therefore, an asymmetric structure can be realized simply by changing the shape of the mask. That is, in the TFT process, the number of masks does not change between the one-side LDD (GOLD) structure and the two-sided LDD (GOLD) structure in the manufacturing process, and only by changing the mask pattern, the same number of masks (in the same process) ) A one-sided LDD structure and a two-sided LDD structure can be obtained. In the TFT process, no additional process is required as in the case of IC.
[0150]
  Further, in the polycrystalline silicon thin film transistor, the width (length) of the impurity regions 22a and 22b can be freely changed by a mask, so that an optimum design can be performed according to the purpose and application.
[0151]
  Further, the following effects can be obtained by using a transistor that handles analog signals, that is, a transistor constituting the sampling circuit 13 as a polycrystalline silicon thin film transistor having a symmetric structure including the impurity regions 22a and 22b.
[0152]
  That is, in a transistor that handles an analog signal, a minute potential difference / charge amount is important. Therefore, if there is a leak in a transistor that constitutes the transistor, malfunction is likely to occur. Note that a malfunction in the sampling circuit 13 is expected to be a defective writing to the data line (resulting in a display defect such as the appearance of stripes).
[0153]
  Therefore, since the transistor constituting the sampling circuit 13 has a double-sided GOLD (LDD) structure, the leakage current can be reduced regardless of whether the current flows in the source side or the drain side. Can be avoided.
[0154]
  Needless to say, the transistor described in each embodiment can be applied to any of the other embodiments.
[0155]
  In the above description, the active matrix type liquid crystal display device has been described as an example of the image display device that is the subject technology of the present invention. However, the present invention is not limited to this, and other image display devices can also be used. It is effective.
[0156]
【The invention's effect】
  In the image display device according to the present invention, as described above, the drive circuit isA transistor having an asymmetric structure between the source region side and the drain region side where current flows only in one direction, and a transistor having a symmetrical structure between the source region side and the drain region side in which the direction of current flow changes. This transistor has an impurity region whose impurity concentration is lower than that of the source region and the drain region only on the drain region side outside the region directly under the gate electrode, and the transistor having the symmetric structure is located outside the region directly under the gate electrode. The impurity region is provided on both the source region side and the drain region side.It is a configuration.
[0157]
  Therefore, for example, in a transistor in which current flows only in one direction, the impurity region (high resistance region) is provided only on the drain region side outside the region directly below the gate electrode to have an asymmetric structure (one-side LDD structure), In a transistor in which the direction of current flow changes, the high resistance region is provided on both the source region side and the drain region side outside the region directly below the gate electrode to form a symmetrical structure (double-sided LDD structure). The electric field is relieved by the resistance region, and there is an effect that high reliability can be obtained in the circuit.
[0158]
  Further, in this case, in a transistor in which current flows only in one direction, since there is no high resistance region on the source region side, a reduction in driving capability can be suppressed and a large operating margin can be secured. Play.
[0159]
  Further, as compared with the case where all the transistors constituting the driving circuit are configured with the LDD structure or the GOLD structure, there is an effect that it is possible to surely obtain both high reliability and a wide operation margin in the circuit.
[0160]
  In the image display device according to the present invention, as described above, the drive circuit isA transistor having an asymmetric structure between the source region side and the drain region side where current flows only in one direction, and a transistor having a symmetric structure between the source region side and the drain region side, in which the direction of current flow changes,The transistor with the asymmetric structure has the impurity region only on the drain region side in the region immediately below the gate electrode. The transistor with the symmetric structure has both the source region side and the drain region side in the region immediately below the gate electrode. Further, the structure has the impurity region.
[0161]
  Therefore, for example, in a transistor in which current flows only in one direction, a high resistance region having a low impurity concentration is provided only on the drain region side in a region immediately below the gate electrode to have an asymmetric structure (one-side GOLD structure), while current flows. In a transistor whose direction changes, the high resistance region is provided on both the source region side and the drain region side in the region immediately below the gate electrode to form a symmetrical structure (both sides GOLD structure), whereby an electric field is generated by the high resistance region. It is mitigated, and there is an effect that high reliability can be obtained in the circuit.
[0162]
  Further, in this case, in a transistor in which current flows only in one direction, since there is no high resistance region on the source region side, a reduction in driving capability can be suppressed and a large operating margin can be secured. Play.
[0163]
  In the image display device according to the present invention, as described above, the drive circuit isA transistor having an asymmetric structure between the source region side and the drain region side where current flows only in one direction, and a transistor having a symmetric structure between the source region side and the drain region side, in which the direction of current flow changes,The transistor with the asymmetric structure has the impurity region only on the drain region side so as to partially overlap the gate electrode, and the transistor with the symmetrical structure has a portion overlapping with the gate electrode. Further, the impurity region is provided on both the source region side and the drain region side.
[0164]
  Therefore, for example, in a transistor in which current flows only in one direction, a high resistance region having a low impurity concentration is provided only on the drain region side so as to partially overlap the gate electrode, thereby forming an asymmetric structure (one-sided GOLD structure). On the other hand, in a transistor in which the direction of current flow changes, the high resistance region is provided on both the source region side and the drain region side so as to partially overlap the gate electrode, and a symmetrical structure (both sides GOLD structure) By doing so, the electric field is relaxed by the high resistance region, and it is possible to obtain high reliability in the circuit.
[0165]
  Further, in this case, in a transistor in which current flows only in one direction, since there is no high resistance region on the source region side, a reduction in driving capability can be suppressed and a large operating margin can be secured. Play.
[0166]
  As described above, in the image display device according to the present invention, only the n-channel transistor among the transistors included in the driver circuit has the impurity region, and the p-channel transistor does not include the impurity region. The transistor has a symmetrical structure on the source region side and the drain region side.
[0167]
  Therefore, since the p-channel transistor has a higher element breakdown voltage than the n-channel transistor, the reliability of the circuit is ensured without adopting a configuration in which the high-resistance region having a low impurity concentration is provided on the drain region side. May be possible. Therefore, by providing the high resistance region only in the n-channel transistor and making the p-channel transistor have a simple drain structure, the driving ability of the p-channel transistor can be increased.
[0168]
  As described above, the image display device according to the present invention includes a plurality of transistors, and includes a logic circuit in which a current flows only in one direction. At least a part of the transistors includes the impurity only on the drain region side. This is an asymmetric structure having a region.
[0169]
  Therefore, in a transistor constituting a logic circuit, for example, if the region having a low impurity concentration is only on the side where the electric field is concentrated (drain region side), the electric field is relaxed because the region is a high resistance region. At least the reliability of the circuit can be ensured. Further, depending on the applied voltage, the magnitude of the current, the flow period, etc., the reliability of the circuit can be achieved without providing the high resistance region on the drain region side and adopting an asymmetric structure, that is, without providing the high resistance region. In some cases, sex can be secured.
[0170]
  Therefore, by providing at least a part of the transistors constituting the logic circuit with an asymmetric structure, there is an effect that both high reliability and high driving capability can be obtained in the logic circuit, and in the drive circuit.
[0171]
  In the image display device according to the present invention, as described above, the drive circuit isIt is configured to include a plurality of transistors, and includes an asymmetric transistor having an impurity region whose impurity concentration is lower than that of the source region and the drain region only on the drain region side,A symmetric structure including a plurality of transistors, including a transfer gate that changes the direction of current flow according to the level of an input signal, and the transfer gate includes the impurity regions on both the source region side and the drain region side It is the structure comprised by this transistor.
[0172]
  Therefore, in the transistor constituting the transfer gate, a high electric field can be applied to either the source region side or the drain region side. Therefore, by forming the transfer gate with a transistor having a symmetric structure having the impurity region on both the source region side and the drain region side, the concentration of the electric field on both sides of the source region side and the drain region side is alleviated to transfer There is an effect that it is possible to avoid a reduction in the reliability of the gate and the drive circuit.
[0173]
  In the image display device according to the present invention, as described above, the drive circuit isIt is configured to include a plurality of transistors, and includes an asymmetric transistor having an impurity region whose impurity concentration is lower than that of the source region and the drain region only on the drain region side,A sampling circuit for sampling an analog video signal supplied to each pixel is provided, and the sampling circuit is configured by a transistor having a symmetric structure having the impurity regions on both the source region side and the drain region side.
[0174]
  Therefore, in the transistor constituting the sampling circuit, a high electric field can be applied to either the source region side or the drain region side. Therefore, the concentration of the electric field on both sides of the source region side and the drain region side can be reduced by configuring the sampling circuit with a transistor having a symmetric structure having the low impurity concentration region on both the source region side and the drain region side. As a result, it is possible to avoid a decrease in the reliability of the sampling circuit and thus the drive circuit.
[0175]
  In the image display device according to the present invention, as described above, the drive circuit is composed of a plurality of circuits driven by a plurality of power supply voltages, and the width of the impurity region of the transistor in each circuit corresponds to the transistor. It is the structure set according to the power supply voltage to perform.
[0176]
  Therefore, by setting the width (length) of the high-resistance region of the transistor in accordance with the power supply voltage corresponding to the transistor of each circuit, the electric field that is concentrated even when any power supply voltage is applied to the circuit. Can be reliably mitigated, and the reliability of the circuit can be improved with certainty.
[0177]
  As described above, the image display device according to the present invention includes a plurality of data signal lines for supplying video data to be written to the pixels and a plurality of scanning signals for controlling writing of the video data to the pixels. And the driving circuit includes a data signal line driving circuit for driving the data signal line and a scanning signal line driving circuit for driving the scanning signal line. .
[0178]
  Therefore, the scanning signal line driving circuit controls the writing of the video data supplied to each pixel by the data signal line driving circuit through the plurality of data signal lines to the pixel through the plurality of scanning signal lines. Thus, it is possible to display an image corresponding to the video data in each pixel.
[0179]
  As described above, the image display device according to the present invention has a configuration in which at least one of the data signal line driving circuit and the scanning signal line driving circuit is formed on a substrate on which the pixels are formed.
[0180]
  Therefore, it is possible to form at least one of the data signal line driving circuit and the scanning signal line driving circuit on the same substrate as the pixel in the same process, thereby reducing the manufacturing cost and the mounting cost and increasing the mounting non-defective rate. There is an effect that you can expect.
[0181]
  As described above, the image display device according to the present invention has a configuration in which the active element constituting at least one of the data signal line driving circuit and the scanning signal line driving circuit is a polycrystalline silicon thin film transistor.
[0182]
  Therefore, it is possible to easily form at least one of the signal line driver circuit and the scanning signal line driver circuit and the pixel for image display on the same substrate.
[0183]
  In addition, since the polycrystalline silicon thin film transistor is inferior in crystallinity as compared with the single crystal silicon transistor, the breakdown voltage is low even in an element of the same size, and the driving capability is also small. Therefore, it is generally difficult to construct a high-performance circuit using a polycrystalline silicon thin film transistor. However, according to the present invention, high reliability and high drive capability can be obtained simultaneously in the circuit. When the polycrystalline silicon thin film transistor is applied to the image display device of the present invention, it is possible to combine the effects that high reliability and good image display can be realized.
[0184]
  As described above, the image display apparatus according to the present invention has a configuration in which the active element is formed at a temperature of 600 ° C. or lower.
[0185]
  Therefore, at a process temperature of 600 ° C. or lower, it is possible to use inexpensive and easy-to-size glass as a substrate, so that it is possible to produce a large image display device at low cost.
[Brief description of the drawings]
FIGS. 1A to 1D are a cross-sectional view and explanatory views schematically showing structures and symbols of active elements provided in a drive circuit of an image display apparatus according to an embodiment of the present invention.
FIG. 2 is a circuit diagram showing a schematic configuration of the image display device.
FIG. 3 is a circuit diagram showing a configuration of a pixel when the image display device is an active matrix liquid crystal display device.
FIG. 4 is a circuit diagram showing a schematic configuration of a data signal line driving circuit provided in the image display device.
FIG. 5 is a circuit diagram showing a schematic configuration of a scanning signal line driving circuit provided in the image display device.
FIG. 6 is a circuit diagram showing a configuration of a flip-flop circuit provided in the data signal line driving circuit and the scanning signal line driving circuit.
FIG. 7 is a circuit diagram showing a circuit configuration subsequent to the flip-flop circuit in the data signal line driving circuit.
FIGS. 8A to 8D are a sectional view and an explanatory view schematically showing another structure and symbols of the active element.
9A to 9D are a cross-sectional view and an explanatory view schematically showing still another structure and symbols of the active element. FIG.
FIG. 10 is a circuit diagram showing a schematic configuration of the scanning signal line driving circuit driven by a plurality of power supply voltages.
FIG. 11 is a circuit diagram showing a schematic configuration of an image display apparatus according to another embodiment of the present invention.
FIGS. 12A to 12C are a cross-sectional view and an explanatory view schematically showing the structure and symbols of active elements provided in the drive circuit of the image display device.
FIGS. 13A to 13K are cross-sectional views showing manufacturing steps of the active element.
FIGS. 14A to 14C are a cross-sectional view and an explanatory view schematically showing other structures and symbols of active elements provided in the drive circuit of the image display device. FIGS.
FIGS. 15A to 15K are cross-sectional views showing manufacturing steps of the active element. FIGS.
FIGS. 16A to 16C are a cross-sectional view and an explanatory view schematically showing still another structure and symbols of an active element provided in the drive circuit of the image display device. FIGS.
FIGS. 17A to 17K are cross-sectional views showing manufacturing steps of the active element.
FIG. 18 is a cross-sectional view showing a configuration of an active element provided in a drive circuit of a conventional image display device.
FIGS. 19A to 19K are cross-sectional views showing manufacturing steps of the active element. FIGS.
20A and 20B are a cross-sectional view and an explanatory view schematically showing the structure and symbols of the active element.
FIGS. 21A and 21B are a cross-sectional view and an explanatory view schematically showing another structure and symbols of the active element. FIGS.
[Explanation of symbols]
  1a pixel
  2 Scanning signal line drive circuit
  3 Data signal line drive circuit
11b NAND circuit (logic circuit)
12 Buffer circuit (logic circuit)
13 Sampling circuit
22 Polycrystalline silicon thin film
22a / 22b Impurity region
22c source region
22d drain region
25 Gate electrode
31, 32, 33 Inverter (logic circuit)
34.35 Transfer gate
36/37/38 Inverter (logic circuit)
41 n-channel transistor
42 p-channel transistor
43 n-channel transistor
44 p-channel transistor
SL data signal line
GL scanning signal line
SW Pixel transistor

Claims (12)

A plurality of pixels provided in a matrix and for displaying an image;
In an image display device comprising a drive circuit that supplies a signal for driving and displaying the pixel to the pixel,
The driver circuit includes a transistor having an asymmetric structure between the source region side and the drain region side where current flows only in one direction, and a transistor having a symmetrical structure between the source region side and the drain region side in which the current flow direction changes. Prepared,
The transistor having the asymmetric structure has an impurity region whose impurity concentration is lower than that of the source region and the drain region only on the drain region side outside the region directly under the gate electrode,
2. The image display device according to claim 1, wherein the transistor having the symmetric structure has the impurity region on both the source region side and the drain region side outside the region immediately below the gate electrode. A plurality of pixels provided in a matrix and for displaying an image;
  In an image display device including a drive circuit that supplies a signal for driving and displaying the pixel to the pixel,
The driver circuit includes a transistor having an asymmetric structure between the source region side and the drain region side where current flows only in one direction, and a transistor having a symmetrical structure between the source region side and the drain region side where the current flow direction changes. Prepared,
The transistor having the asymmetric structure has an impurity region having an impurity concentration lower than that of the source region and the drain region only on the drain region side in the region immediately below the gate electrode.
  2. The image display device according to claim 1, wherein the transistor having the symmetric structure includes the impurity region on both the source region side and the drain region side in a region immediately below the gate electrode. A plurality of pixels provided in a matrix and for displaying an image;
  In an image display device including a drive circuit that supplies a signal for driving and displaying the pixel to the pixel,
The driver circuit includes a transistor having an asymmetric structure between the source region side and the drain region side where current flows only in one direction, and a transistor having a symmetrical structure between the source region side and the drain region side where the current flow direction changes. Prepared,
The transistor having the asymmetric structure has an impurity region having a lower impurity concentration than the source region and the drain region only on the drain region side so that a part of the transistor overlaps with the gate electrode,
  2. The image display device according to claim 1, wherein the transistor having the symmetric structure includes the impurity region on both the source region side and the drain region side so as to partially overlap the gate electrode. Of the transistors constituting the driver circuit, only the n-channel transistor has the impurity region, and the p-channel transistor does not include the impurity region and has a symmetrical structure on the source region side and the drain region side. The image display device according to claim 1, wherein the image display device is an image display device. The drive circuit includes a plurality of transistors, and includes a logic circuit in which current flows only in one direction.
  5. The image display device according to claim 1, wherein at least a part of the transistor has the asymmetric structure. A plurality of pixels provided in a matrix and for displaying an image;
  In an image display device including a drive circuit that supplies a signal for driving and displaying the pixel to the pixel,
  The drive circuit includes a plurality of transistors, and includes an asymmetrical transistor having an impurity region whose impurity concentration is lower than that of the source region and the drain region only on the drain region side,
The drive circuit includes a plurality of transistors, and includes a transfer gate that changes a direction in which a current flows according to a level of an input signal.
  2. The image display device according to claim 1, wherein the transfer gate includes a transistor having a symmetric structure having the impurity regions on both the source region side and the drain region side. A plurality of pixels provided in a matrix and for displaying an image;
  In an image display device comprising a drive circuit that supplies a signal for driving and displaying the pixel to the pixel,
  The drive circuit includes a plurality of transistors, and includes an asymmetrical transistor having an impurity region whose impurity concentration is lower than that of the source region and the drain region only on the drain region side,
The drive circuit includes a sampling circuit that samples an analog video signal supplied to each pixel,
  2. The image display device according to claim 1, wherein the sampling circuit includes a symmetrical transistor having the impurity region on both the source region side and the drain region side. The drive circuit includes a plurality of circuits driven by a plurality of power supply voltages, and the width of the impurity region of the transistor in each circuit is set according to the power supply voltage corresponding to the transistor. The image display device according to claim 1. A plurality of data signal lines for supplying video data to be written to the pixels, and a plurality of scanning signal lines for controlling writing of the video data to the pixels;
  2. The drive circuit according to claim 1, wherein the drive circuit includes a data signal line drive circuit for driving the data signal line and a scan signal line drive circuit for driving the scan signal line. The image display device according to any one of 8. 10. The image display device according to claim 9, wherein at least one of the data signal line driving circuit and the scanning signal line driving circuit is formed on a substrate on which the pixels are formed. 11. The image display device according to claim 9, wherein an active element constituting at least one of the data signal line driving circuit and the scanning signal line driving circuit is a polycrystalline silicon thin film transistor. The active matrix image display device according to claim 11, wherein the active element is formed at a temperature of 600 ° C. or less.

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