JP3804596B2 - Scan line driving circuit, electro-optical device and electronic apparatus using the same - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an electro-optical device, a method of manufacturing the same, and a method of manufacturing the same, using a conductive layer different from the conductive layer constituting the scanning line and the data line in the peripheral circuit to improve the degree of freedom when designing the peripheral circuit. The present invention relates to an electronic apparatus using an electro-optical device as a display unit.
[0002]
[Prior art]
In general, an electro-optical device, for example, a liquid crystal device that performs predetermined display using liquid crystal as an electro-optical material has a configuration in which liquid crystal is sandwiched between a pair of substrates. Among these, for example, an active matrix liquid crystal device in which a pixel electrode is driven by a three-terminal switching element has the following configuration. That is, this type of liquid crystal device is provided on one of a pair of substrates so that a plurality of scanning lines and a plurality of data lines intersect with each other, and a thin film transistor ( A pair of a three-terminal switching element represented by a thin film transistor (hereinafter referred to as “TFT”) and a pixel electrode is provided. Here, the TFT is turned on when the scanning signal supplied to the scanning line corresponding to the intersecting portion becomes an active level, and supplies the image signal applied to the corresponding data line to the pixel electrode. The other substrate is provided with a transparent counter electrode facing the pixel electrode.
[0003]
On the other hand, a driving circuit for driving these scanning lines and data lines includes a scanning line driving circuit, a data line driving circuit, a sampling circuit, and the like. Among these, the scanning line driving circuit supplies a scanning signal to the scanning line at a predetermined timing, the data line driving circuit supplies a sampling signal at a predetermined timing, and the sampling circuit further includes: A sampling switch provided for each data line samples an image signal supplied via the image signal line in accordance with the sampling signal and supplies it to the corresponding data line.
[0004]
Further, an electro-optical device with a built-in peripheral circuit has been developed in which these drive circuits are provided around a region (display region) where pixel electrodes are arranged on one substrate. In this type of electro-optical device, from the viewpoint of improving the efficiency of the manufacturing process, the active elements constituting the drive circuit are formed in a common process with the switching elements connected to the pixel electrodes. For example, in the above-described liquid crystal device, the element constituting the drive circuit is a TFT formed by the same process as the switching element connected to the pixel electrode. Such an electro-optical device with a built-in peripheral circuit is advantageous in terms of downsizing and cost reduction of the entire device as compared with an electro-optical device in which a drive circuit is separately attached.
[0005]
By the way, in recent years, in general display devices, not limited to electro-optical devices, high definition such as XGA (1024 × 768 dots), SXGA (1365 × 1024 dots), UXGA (1600 × 1200 dots), etc. There is a growing demand for conversion.
[0006]
[Problems to be solved by the invention]
However, in order to reduce the size of the apparatus at the same time as increasing the definition, a technique for very narrowing the arrangement pitch of the scanning lines and the arrangement pitch of the data lines is required. That is, since the scanning line driving circuit supplies a scanning signal to each of the scanning lines, unit circuits (latch circuits) constituting the scanning line driving circuit must be within the arrangement pitch of the scanning lines. . Similarly, since the data line driving circuit supplies a sampling signal to a sampling switch provided for each data line in order, the unit circuit constituting the data line driving circuit has an arrangement pitch of data lines or It must be within an integer multiple of the pitch. As described above, in an electro-optical device with a built-in peripheral circuit, when trying to achieve high definition and miniaturization, unit circuits and the like in the scanning line driving circuit and the data line driving circuit are accommodated in a very limited space. There is a problem that the design becomes very difficult because it must be formed.
[0007]
The present invention has been made in view of the above-described circumstances, and an object of the present invention is to provide an electro-optical device, a manufacturing method thereof, and a display unit for improving the degree of freedom of design in a peripheral circuit. It is to provide an electronic device used for the above.
[0008]
[Means for Solving the Problems]
In order to achieve the object described above, in the scanning line driving circuit according to the present invention, the clock signal line or the inverted clock signal line and the clock signal line or the inverted clock signal line are crossed with respect to the first direction. There are a plurality of columns in which one transistor and a second transistor are sequentially arranged in the column direction, and the second transistors in one column are arranged between the plurality of columns so as to extend along the column. A first layer wiring connected to the gate electrode of the first transistor in the column adjacent to the one column, the clock signal line or the inverted clock signal line, and Between the plurality of columns, it is disposed so as to overlap the wiring of the first layer and extend along the column, and one of the electric currents of the semiconductor layer of the first transistor in the one column A second-layer wiring connected to one electrode of the semiconductor layer of the second transistor in the same row via another wiring layer formed in an upper layer, and the same layer as the other wiring layer The semiconductor layer of the first transistor in the adjacent column is arranged so as to overlap the first layer wiring and the second layer wiring between the plurality of columns and to extend along the column. And a third layer wiring connected to the other electrode.
[0014]
In addition, the electro-optical device includes the above-described scanning line driving circuit.
[0015]
In addition, Reference invention In the electro-optical device according to the present invention, a plurality of scanning lines and a plurality of data lines, a pair of switching elements and pixel electrodes provided corresponding to intersections of the scanning lines and the data lines, and the switching elements A peripheral circuit for driving each of the switching elements, comprising: an intermediate conductive film electrically connecting corresponding pixel electrodes; and a wiring made of the same layer as the conductive layer constituting the intermediate conductive film; It is characterized by comprising.
[0016]
According to this configuration, in the region where the pixel electrodes are arranged (display region), the intermediate conductive film is used to connect the switching element and the pixel electrode. It will also be used in circuits. That is, the intermediate conductive film originally used in the display region is Reference invention Then, it is also used as a part of the wiring of the peripheral circuit. For this reason, in the peripheral circuit, the number of new wiring layers is increased, so that the degree of freedom in design is improved accordingly.
[0017]
here, Reference invention The intermediate conductive film is electrically connected via a first contact hole provided corresponding to the electrode of the switching element, while the pixel electrode is electrically connected via a second contact hole. The configuration connected to is desirable. In this configuration, the electrode of the switching element is connected to the intermediate conductive film through the first contact hole, while the pixel electrode is connected to the intermediate conductive film through the second contact hole. For this reason, the intermediate conductive film functions as a barrier film when the pixel electrode is connected to the other end of the switching element, so that it is possible to reduce defects that occur when the contact hole extends over a long distance.
[0018]
Also, Reference invention A storage capacitor having one end connected to the pixel electrode and the other end connected in common to each pixel electrode, and the intermediate conductive film may be a part of an electrode constituting the storage capacitor. desirable. According to this configuration, the voltage holding characteristic in the pixel electrode is improved by the storage capacitor. At this time, the intermediate conductive film functions as a part of the electrode constituting the storage capacitor.
[0019]
further, Reference invention The intermediate conductive film may have a light shielding property, and a part of light transmitted or reflected by the pixel electrode may be defined by the intermediate conductive film. According to this configuration, since at least a dedicated light-shielding film can be omitted in a portion defined by the intermediate conductive film in the light transmission or reflection region, the configuration can be simplified correspondingly.
[0020]
In addition, Reference invention In this electro-optical device, the first, second, and third conductive layers are formed in this order, and the third conductive layer has a lower resistance than the first conductive layer. An electro-optical device, comprising a plurality of scanning lines made of the first conductive layer and a plurality of data made of the third conductive layer and formed to intersect each other with respect to the plurality of scanning lines. A line, a pair of switching elements and pixel electrodes provided corresponding to the intersections of the scanning lines and the data lines, and a second conductive layer between the switching elements and the corresponding pixel electrodes. And a peripheral circuit for driving each of the switching elements. The intermediate conductive film is electrically connected, and the wiring is formed of the first, second, and third conductive layers.
[0021]
According to this configuration, in the display region, the intermediate conductive film is used for connection between the switching element and the pixel electrode. The wiring made of the second conductive layer that is the same as the intermediate conductive film is connected to the first and third wirings. In addition to the wiring made of the conductive layer, it is also used in peripheral circuits. That is, the intermediate conductive film originally used in the display region is also used as part of the wiring in the peripheral circuit in the present invention. For this reason, in the peripheral circuit, the number of new wiring layers is increased by one layer, and the degree of freedom in design is improved accordingly.
[0022]
here, Reference invention The intermediate conductive film is electrically connected via a first contact hole provided corresponding to the electrode of the switching element, while the pixel electrode is electrically connected via a second contact hole. The configuration connected to is desirable. In this configuration, the electrode of the switching element is connected to the intermediate conductive film through the first contact hole, while the pixel electrode is connected to the intermediate conductive film through the second contact hole. For this reason, the intermediate conductive film functions as a barrier film when the pixel electrode is connected to the other end of the switching element, so that it is possible to reduce defects that occur when the contact hole extends over a long distance.
[0023]
by the way, Reference invention In this case, since the third conductive layer has a lower resistance than the first conductive layer, it is desirable that the entire wiring is formed of the third conductive layer. However, since there are always wiring intersections and branching portions in the peripheral circuit, it is impossible to form all of the wiring by the third conductive layer. Therefore, Reference invention In this case, for example, when the wiring made of the first conductive layer having high resistance must be used, the peripheral circuit is electrically connected to the wiring made of the first conductive layer and the wiring made of the second conductive layer. A configuration having parallel wires connected in parallel to each other is desirable. As described above, when the parallel wiring in which the wiring made of the first conductive layer and the wiring made of the second conductive layer are electrically connected in parallel is used, the wiring made of the first or second conductive layer is isolated. The wiring resistance can be suppressed lower than that used in the above.
[0024]
As a portion where such parallel wiring should be used, for example, a branch wiring branched from the wiring made of the third conductive layer and a portion intersecting with a wiring different from the wiring can be considered. Such a branch wiring should be made of a third conductive layer having a low resistance, but is a wiring made of the third conductive layer, and a portion intersecting with a wiring different from the wiring is the same. This is because the third conductive layer cannot be formed.
[0025]
In addition, the peripheral circuit includes the third conductive layer, and h image signal lines that supply image signals corresponding to h (h is an integer of 2 or more) data lines, and the data A sampling switch provided corresponding to each of the lines, sampling a corresponding one of the image signals supplied to the h image signal lines according to a predetermined sampling signal, and supplying the sampled data to the corresponding data line; As a part where parallel wiring should be used, at least a part of the wiring branched from the image signal line to the sampling switch can be considered. Since such a wiring supplies an image signal applied to the pixel electrode, it should be composed of a third conductive layer having a low resistance, but is the same because it intersects with other image signal lines. This is because the third conductive layer cannot be formed.
[0026]
Now, Reference invention In the case of forming the parallel wiring, the third wiring and the fourth wiring exposing the wiring composed of the second conductive layer among the parallel wiring and the wiring composed of the first conductive layer among the parallel wiring, respectively. Between the first and second contact holes, and the wiring made of the third conductive layer is provided at a position corresponding to the third or fourth contact hole to expose the wiring made of the second conductive layer. Of the parallel wiring, the first conductive layer electrically connected to the fifth contact hole and the wiring made of the second conductive layer are made of the first conductive layer of the parallel wiring. Conductivity is established between the third and fourth contact holes exposing the wiring, respectively, and the wiring made of the third conductive layer is provided at a position different from the third and fourth contact holes. 1 conductivity A second arrangement which is electrically connected to a sixth contact hole exposing a wiring made are considered. Here, when a stress due to warpage or the like is applied to the second conductive layer, if a contact hole that exposes the wiring made of the second conductive layer is provided, a crack may occur. In the second configuration, since it is not necessary to provide a contact hole that exposes the second conductive layer, it is possible to reduce defects due to the occurrence of cracks.
[0027]
Further, in the first or second configuration, one or a plurality of contact holes in which the wiring made of the second conductive layer among the parallel wirings is provided between the third and fourth contact holes. In this case, it is desirable that the conductive layer is electrically connected to the wiring made of the first conductive layer. As a result, in parallel wiring, contact holes other than the third and fourth contact holes are also connected in parallel.
[0028]
Now, Reference invention The peripheral circuit may include a wiring including the first, second, and third conductive layers in a partial region thereof. According to this configuration, since different three-layer wirings are laid out in the same region, it is possible to reduce the space.
[0029]
Also, Reference invention A storage capacitor having one end connected to the pixel electrode and the other end commonly connected to each pixel electrode, wherein the intermediate conductive film is a part of an electrode constituting the storage capacitor. desirable. According to this configuration, the voltage holding characteristic in the pixel electrode is improved by the storage capacitor. At this time, the intermediate conductive film functions as a part of the electrode constituting the storage capacitor.
[0030]
Such a storage capacitor includes a first capacitor in which the gate oxide film of the switching element is sandwiched between the electrode of the switching element and a capacitor line made of the second conductive layer, the intermediate conductive film, and the capacitor. A configuration including a second capacitor in which an interlayer insulating film is sandwiched between lines is desirable. According to this configuration, since the storage capacitor includes the first capacitor and the second capacitor, the capacity can be increased as compared with the single capacitor configuration.
[0031]
Now, Reference invention In this case, the first conductive layer is preferably made of polysilicon. This is because when the scanning line is formed from a metal thin film or metal silicide, inconveniences such as peeling occur in a subsequent high-temperature process.
[0032]
Also, Reference invention The third conductive layer is preferably made of aluminum. As a result, the resistance of the third conductive layer can be easily reduced.
[0033]
In addition, Reference invention The second conductive layer is preferably made of a material having a melting point higher than that of the material forming the third conductive layer. This is because it is necessary to prevent melting and peeling by a high-temperature process after forming the second conductive layer. Such high melting point materials include polysilicon, Ti (titanium), Cr (chromium), W (tungsten), Ta (tantalum), Mo (molybdenum), or Pb (lead). Alloys, metal silicides, and the like.
[0034]
In addition, Reference invention In the electro-optical device according to the present invention, a plurality of scanning lines and a plurality of data lines, a pair of switching elements and pixel electrodes provided corresponding to intersections of the scanning lines and the data lines, and the switching elements An intermediate conductive film electrically connecting the corresponding pixel electrodes; a peripheral circuit for driving each of the switching elements; and a conductive layer connected to the peripheral circuit and constituting the intermediate conductive film. And a single-layer wiring.
[0035]
Reference invention The wiring connected to the peripheral circuit is formed of the same conductive layer as the intermediate conductive film used for connecting the switching element and the pixel electrode. For this reason, since it can utilize as a new wiring layer, the freedom degree of design improves.
[0036]
here, Reference invention In the above, the wiring intersects with an image signal line composed of the same layer as the conductive layer constituting the data line in a lower layer. In this configuration, the wiring intersecting with the image signal line can be used as the wiring in the same conductive layer as the intermediate conductive film.
[0037]
In addition, the image signal lines are provided with a plurality of image signal lines, the wirings are connected corresponding to the respective image signal lines, and the sizes of the respective wirings are substantially the same. In this configuration, the resistance values of the respective wirings connected to the image signal can be made equal, and variations in the image signal due to the resistance difference between the respective wirings can be prevented, and a good display can be achieved.
[0038]
Also, Reference invention The first conductive layer made of the same layer as the conductive layer constituting the data line and the second conductive made of the same layer as the conductive layer constituting the data line and formed away from the first conductive layer. And a third conductive layer made of the same layer as the semiconductor layer of the switching element is electrically connected to the first conductive layer and the second conductive layer through a contact hole. Features. According to this configuration, the third conductive layer made of the same layer as the semiconductor layer of the switching element can be formed as a bypass.
[0039]
Also, Reference invention The wiring is electrically connected to the third conductive layer through a contact hole. According to this configuration, since the wiring and the third conductive layer are connected in parallel, the resistance of the wiring can be reduced.
[0040]
Also, Reference invention The third conductive layer is made of polysilicon. According to this configuration, even if the wiring is formed of a refractory metal or the like, the wiring is electrically connected to the third conductive layer of polysilicon through the contact hole, so that the wiring is not cracked. Absent. The third conductive layer is electrically connected to the first conductive layer and the second conductive layer through a contact hole. However, since the third conductive layer is formed of polysilicon, the polysilicon does not crack. .
[0041]
Also, Reference invention The contact hole electrically connecting the wiring and the third conductive layer has at least three. According to this configuration, since the redundant wiring can be formed between the wiring and the third conductive layer, the crack between the wiring and the third conductive layer is generated between the wiring and the third conductive layer. A short circuit can be prevented.
[0042]
Also, Reference invention The image signal line made of the same layer as the conductive layer constituting the data line is disposed between the first conductive layer and the second conductive layer. According to this configuration, the image signal line made of the same layer as the conductive layer constituting the data line can be arranged without interfering with the first conductive layer and the second conductive layer.
[0043]
In addition, since the electronic apparatus of the present case includes the above-described electro-optical device, the degree of freedom when designing peripheral circuits is improved.
[0044]
In addition, Reference invention In the electro-optical device manufacturing method according to the above, the electro-optical device manufacturing method includes a pair of switching elements and pixel electrodes corresponding to the intersections of the plurality of scanning lines and the plurality of scanning lines, Forming a switching element at a portion where the scanning line and the data line should cross, an intermediate conductive film connected to the switching element, and a wiring used for a peripheral circuit for driving each of the switching elements And a step of forming each of the same conductive layer and a step of forming a pixel electrode connected to the intermediate conductive film. According to this manufacturing method, since the number of new wiring layers is increased in the peripheral circuit, the degree of freedom in design is improved accordingly.
[0045]
In addition, Reference invention In the electro-optical device manufacturing method according to the above, the electro-optical device manufacturing method includes a pair of switching elements and pixel electrodes corresponding to the intersections of the plurality of scanning lines and the plurality of scanning lines, After forming the scanning line and the wiring used for the peripheral circuit for driving each of the switching elements from the first conductive layer, respectively, and at the portion where the scanning line and the data line should intersect After forming the switching element, forming the intermediate conductive film connected to the switching element and the wiring used for the peripheral circuit from the second conductive layer, respectively, and the data line and the wiring used for the peripheral circuit Each of the method includes a step of forming from a third conductive layer and a step of forming a pixel electrode connected to the intermediate conductive film. According to this manufacturing method, since the number of new wiring layers is increased by one in the peripheral circuit, the degree of design freedom is improved accordingly.
[0046]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0047]
<Schematic configuration of electro-optical device>
First, the electro-optical device according to this embodiment will be described. This electro-optical device uses a liquid crystal as an electro-optical material and performs predetermined display by electro-optical change. FIG. 1A is a perspective view showing a configuration of the liquid crystal panel 100 excluding an external circuit in the electro-optical device, and FIG. 1B is a cross-sectional view taken along line AA ′ in FIG. It is sectional drawing.
[0048]
As shown in these drawings, in the liquid crystal panel 100, an element substrate 101 on which various elements, pixel electrodes 118, and the like are formed, and a counter substrate 102 on which the counter electrodes 108 and the like are provided have spacers (not shown). A sealing material 104 is included so that the electrode forming surfaces face each other while maintaining a certain gap, and a TN (Twisted Nematic) type liquid crystal 105, for example, is sealed in the gap as an electro-optical material. ing.
[0049]
Here, glass, a semiconductor, quartz, or the like is used for the element substrate 101, but glass or the like is used for the counter substrate 102. When an opaque substrate is used as the element substrate 101, it is used as a reflective type instead of a transmissive type. Further, the sealant 104 is formed along the periphery of the counter substrate 102, but a part of the sealant 104 is opened to enclose the liquid crystal 105. For this reason, after the liquid crystal 105 is sealed, the opening is sealed with the sealing material 106.
[0050]
Next, a data line driving circuit, which will be described later, is formed in a region 140 a on the opposite surface of the element substrate 101 and on the outer side of the sealing material 104 to output a sampling signal. Further, an image signal line, a sampling circuit, or the like may be formed in a region 150a in the vicinity where the sealant 104 is formed on one side. On the other hand, a plurality of mounting terminals 107 are formed on the outer peripheral portion of this side, and various signals are input from an external circuit (not shown).
[0051]
A scanning line driving circuit is formed in each of the two side regions 130a adjacent to the one side, and the scanning lines are driven from both sides. Note that if the delay of the scanning signal supplied to the scanning line is not a problem, a configuration in which the scanning line driving circuit is formed on only one side may be employed.
[0052]
A precharge circuit (to be described later) is formed in the remaining region 160a, and a wiring shared by the two scanning line driver circuits may be formed outside the precharge circuit.
[0053]
On the other hand, the counter electrode 108 provided on the counter substrate 102 is configured to be electrically connected to the element substrate 101 by a conductive material in at least one of the four corners of the bonding portion with the element substrate 101.
[0054]
In addition, although not particularly illustrated, the counter substrate 102 is provided with a colored layer (color filter) in a region facing the pixel electrode 118 as necessary. However, it is not necessary to form a colored layer on the counter substrate 102 when applied to a color light modulation application like a double-plate projector described later.
[0055]
Conventionally, in the counter substrate 102, regardless of whether or not a colored layer is provided, a light shielding film is formed on a portion other than the region facing the pixel electrode 118 in order to prevent a decrease in contrast ratio due to light leakage. However, in the present embodiment, as described later, since the light shielding region in the pixel portion is defined on the element substrate 101 side, the light shielding film provided on the counter substrate 102 is omitted.
[0056]
Further, on the opposing surfaces of the element substrate 101 and the counter substrate 102, as will be described later, an alignment film (rubbing treatment is performed so that the major axis direction of molecules in the liquid crystal 105 is continuously twisted by about 90 degrees between the two substrates). 1 is provided), and a polarizer (not shown) corresponding to the orientation direction is provided on each back side thereof. In FIG. 1B, the counter electrode 108, the pixel electrode 118, the mounting terminal 107, and the like have a thickness, but this is a convenient measure for indicating the formation position. Is sufficiently thin with respect to the substrate to be negligible.
[0057]
<Electrical configuration>
Next, an electrical configuration of the element substrate 101 in the liquid crystal panel 100 described above will be described. FIG. 2 is a schematic diagram showing this configuration.
[0058]
As shown in this figure, the element substrate 101 is provided with a plurality of mounting terminals 107 for inputting various signals from an external circuit. A signal input via these mounting terminals 107 is supplied to each part via various wirings. Therefore, these signals will be briefly described.
[0059]
First, as shown in FIG. 4, VID1 to VID6 distribute one image signal VID supplied in synchronization with the dot clock DCLK to six systems and expand it six times on the time axis. And is supplied to the sampling circuit 150 via the six image signal lines 122.
[0060]
Note that the polarities of the image signals VID1 to VID6 are appropriately inverted by an external circuit. Here, polarity reversal in the present embodiment refers to reversing the voltage level alternately between positive polarity and negative polarity based on the voltage LCcom applied to the counter electrode 108, but whether or not the polarity is reversed. In general, whether the application method of the image signal to the data line is (1) polarity inversion in scanning line units, (2) polarity inversion in data line units, or (3) polarity inversion in pixel units Or (4) polarity inversion in frame units, and the inversion period is set to one horizontal scanning period, dot clock DCLK or one vertical scanning period. However, in this embodiment, for convenience of explanation, (1) the case of polarity reversal in units of scanning lines will be described as an example, but the present invention is not limited to this.
[0061]
Second, VssY and VssX are low-side voltages (ground potentials) of the power supplies in the scanning line driving circuit 130 and the data line driving circuit 140, respectively. VddY and VddX are high-side voltages of the power supply in the scanning line driving circuit 130 and the data line driving circuit 140, respectively. Among these, the lower voltage VssY of the power supply is a ground potential of a storage capacitor described later, and is also supplied to each pixel via the capacitor line 175.
[0062]
Third, LCcom is a voltage signal applied to the counter electrode 108. For this reason, the two electrodes 109 to which the voltage signal LCcom is supplied are provided at points corresponding to the corners of the sealing material 104 (see FIG. 1) used for bonding to the counter substrate 102. Therefore, when the element substrate 101 is actually bonded to the counter substrate 102, the electrode 109 and the counter electrode 108 are connected via the conductive material, and the voltage signal LCcom is applied to the counter electrode 108. Note that the voltage signal LCcom is a constant voltage with respect to the time axis, and the external circuit sets the image signals VID1 to VID6 to the high-order side and the low-order side for each horizontal scanning period on the basis of the voltage signal LCcom. It is configured to distribute and perform AC driving. In addition, there are two points where the electrode 109 is provided in the present embodiment, but the reason why the electrode 109 is provided is to apply the voltage signal LCcom to the counter electrode 108 through the conductive material. It is sufficient that at least one point is provided for the electrode 109. For this reason, the number of points where the electrode 109 is provided may be one or three or more.
[0063]
Fourth, as shown in FIG. 4, DY is a transfer start pulse supplied at the beginning of one vertical effective scanning period, and CLY is a clock signal used in the scanning line driving circuit 130. CLYinv is an inverted clock signal obtained by inverting the level of the clock signal CLY.
[0064]
Fifth, DX is a transfer start pulse supplied at the beginning of one horizontal effective scanning period as shown in FIG. 4, and CLX is a clock signal used in the data line driving circuit 140. Note that CLXinv is an inverted clock signal obtained by inverting the level of the clock signal CLX. ENB1 and ENB2 are enable signals used to limit each output signal of the shift register in the data line driving circuit 140 to a predetermined pulse width, as will be described later. In addition, NRG is a precharge control signal, and NRS is a precharge voltage signal, which will be described in detail later.
[0065]
In the display region 100a of the element substrate 101, a plurality of scanning lines 112 are arranged in parallel along the row (Y) direction, and a plurality of data lines 114 are arranged along the column (X) direction. Pixels are provided corresponding to each of these intersecting portions.
[0066]
Specifically, as shown in FIG. 3, at the intersection of the scanning line 112 and the data line 114, the gate of the TFT 116 serving as a switching element for controlling the pixel is connected to the scanning line 112, while the TFT 116. Are connected to the data line 114, and the drain of the TFT 116 is connected to a rectangular transparent pixel electrode 118.
[0067]
As described above, in the liquid crystal panel 100, since the liquid crystal 105 is sandwiched between the electrode formation surfaces of the element substrate 101 and the counter substrate 102, the liquid crystal capacitance of each pixel includes the pixel electrode 118, the counter electrode 108, The liquid crystal 105 is sandwiched between the two electrodes. Here, for convenience of explanation, if the total number of scanning lines 112 is “m” and the total number of data lines 114 is “6n” (m and n are integers), the pixels are the same as the scanning lines 112. Corresponding to each intersection with the data line 114, it is arranged in a matrix with m rows × 6n columns.
[0068]
In addition, in the display area 100a, a storage capacitor 119 for preventing leakage of the liquid crystal capacitor is provided for each pixel. One end of the storage capacitor 119 is connected to the pixel electrode 118 (the drain of the TFT 116), and the other end is commonly connected by a capacitor line 175. Therefore, since the storage capacitor 119 is electrically in parallel with the liquid crystal capacitor, the retention characteristic of the liquid crystal capacitor is improved, and a display with a high contrast ratio is achieved. In this embodiment, the lower voltage VssY of the power source is applied to the capacitor line 175. However, since a constant voltage may be applied to the capacitor line 175 in this embodiment, the higher voltage side of the power source is used. The voltage VddY, the voltage LCcom, or the like may be applied. A detailed configuration of the pixel including the storage capacitor 119 will be described later.
[0069]
Returning to FIG. 2 again, the scanning line driving circuit 130 applies scanning signals G1, G2,..., Gm that sequentially become active levels in each horizontal scanning period 1H to each scanning line within one vertical effective display period. 112 is output. Although the detailed configuration is not directly related to the present invention and is not shown in the figure, it is composed of a shift register and a plurality of logical product circuits (or negative logical product circuits). Among these, as shown in FIG. 4, the shift register shifts the transfer start pulse DY supplied at the beginning of one vertical effective scanning period every time the level of the clock signal CLY (and the inverted clock signal CLYinv) changes ( (Both rising and falling), sequentially shifted and output as signals G1 ′, G2 ′, G3 ′,..., Gm ′, and each AND circuit outputs signals G1 ′, G2 ′, G3 ′,. A logical product signal of adjacent signals among Gm ′ is obtained and output as scanning signals G1, G2, G3,..., Gm.
[0070]
The data line driving circuit 140 outputs sampling signals S1, S2,..., Sn that sequentially become active levels within one horizontal effective scanning period. Although this detailed configuration is not directly related to the present invention and is not shown, it is composed of a shift register and a plurality of AND circuits. Among them, the shift register sequentially shifts the transfer start pulse DX supplied at the beginning of one horizontal effective scanning period every time the level of the clock signal CLX (and the inverted clock signal CLXinv) changes, as shown in FIG. Shift and output as signals S1 ′, S2 ′, S3 ′,..., Sn ′, and each AND circuit sets the pulse width of the signals S1 ′, S2 ′, S3 ′,. Alternatively, the ENB2 is used to output the sampling signals S1, S2, S3,..., Sn narrowed to the period SMPa so that adjacent ones do not overlap each other.
[0071]
Subsequently, the sampling circuit 150 includes a sampling switch 151 provided for each data line 114. On the other hand, the data lines 114 are divided into blocks of six, and among the six data lines 114 belonging to the jth block (j is 1, 2,..., N) from the left in FIG. The sampling switch 151 connected to one end of the leftmost data line 114 samples the image signal VID1 supplied via the image signal line 122 in a period in which the sampling signal Sj is active, and the data line 114 is provided. Similarly, the sampling switch 151 connected to one end of the second data line 114 among the six data lines 114 belonging to the i-th block also receives the image signal VID2 supplied through the image signal line 122. Are sampled during a period in which the sampling signal Sj is active and supplied to the data line 114.
[0072]
Similarly, each of the sampling switches 151 connected to one end of the third, fourth, fifth, and sixth data lines 114 among the six data lines 114 belonging to the jth block is connected to the image signal line 122. Each of the image signals VID3, VID4, VID5, and VID6 supplied via the signal is sampled during a period in which the sampling signal Sj is active and supplied to the corresponding data line 114. That is, when the sampling signal Sj becomes an active level, the image signals VID1 to VID6 are sampled simultaneously on each of the six data lines 114 belonging to the i-th block.
[0073]
On the other hand, a precharge circuit 160 is provided in a region opposite to the data line driving circuit 140 across the display region 100a. The precharge circuit 160 includes a precharging switch 161 provided for each data line 114. Each precharging switch 161 has a precharge control signal NRG supplied via the precharge control line 163 at an active level. In this case, the precharge voltage signal NRS supplied via the precharge signal line 165 is precharged to the corresponding data line 114.
[0074]
Here, as shown in FIG. 5, the precharge control signal NRG is an active level signal in a period isolated from the temporal front and rear ends of one horizontal blanking period. Further, as shown in the figure, the precharge voltage signal NRS is a signal whose level is inverted by the voltages Vg + and Vg− with respect to the voltage LCcom every horizontal scanning period 1H.
[0075]
On the other hand, the voltage LCcom is a temporally constant voltage applied to the counter electrode 108 as described above, and is the amplitude center voltage of the image signals VID1 to VID6. The voltages Vg + and Vg− are voltages in which the effective values of the differential voltage with respect to the voltage LCcom are the same (the absolute values are equal), and are higher and lower voltages than the voltage LCcom, respectively. Here, when the present embodiment is a normally white mode in which white display is performed with no voltage applied, voltages to be applied to the pixel electrode 118 for black display on the positive electrode side and the negative electrode side are represented as Vb + and Vb−. Then, the voltage Vg + is set to an intermediate voltage between the voltage Vb + and the voltage LCcom, and the voltage Vg− is set to an intermediate voltage between the voltage Vb− and the voltage LCcom. That is, the voltage Vg + and the voltage Vb− correspond to intermediate (gray) voltages in writing on the positive electrode side and the negative electrode side, respectively.
[0076]
According to the precharge circuit 160 having such a configuration, each data line 114 is displayed in one horizontal blanking period before one horizontal effective display period in which the sampling signals S1, S2, S3,. Since the voltage Vg + or Vg− is precharged in advance, the load when the image signals VID1 to VID6 are sampled on the data line 114 in one horizontal effective display period immediately after that is reduced.
[0077]
Note that the scanning line driving circuit 130, the data line driving circuit 140, the sampling circuit 150, the precharge circuit 160, and the like are formed around the display region 100a together with an inspection circuit for determining the presence or absence of defects after manufacturing. Therefore, it is called a peripheral circuit. However, since the inspection circuit is not directly related to this case, the description thereof will be omitted.
[0078]
<Operation of electro-optical device>
Next, the operation of the electro-optical device according to the above configuration will be described. First, attention is focused on one horizontal scanning period 1H in which the scanning signal G1 is at an active level. Note that in this one horizontal scanning period, for the sake of convenience of explanation, if writing on the positive electrode side is performed, the image signals VID1 to VID6 become higher voltages than the voltage LCcom applied to the counter electrode 108.
[0079]
Prior to this, as shown in FIG. 5, the precharge control signal NRG becomes active level in a period isolated from the front and rear ends of the blanking period. At this time, the precharge voltage signal NRS becomes the voltage Vg + corresponding to the writing on the positive electrode side. For this reason, all the data lines 114 are precharged to the voltage Vg + during the period.
[0080]
Next, when one horizontal blanking period ends and one horizontal effective display period starts, a transfer start pulse DX is first supplied to the data line driving circuit 140 as shown in FIG. 4 or FIG. . The transfer start pulse DX is output as signals S1 ′, S2 ′, S3 ′,..., Sn ′ that are sequentially shifted every time the level of the clock signal CLX changes. Then, the pulse widths of the signals S1 ′, S2 ′, S3 ′,..., Sn ′ are narrowed to the period SMPa so that adjacent ones do not overlap each other, and the sampling signals S1, S2, S3,. , Sn.
[0081]
On the other hand, the image signal VID of one system is distributed to the image signals VID1 to VID6 by an external circuit as shown in FIG. 4 and is expanded to 6 times with respect to the time axis and supplied to the liquid crystal panel 100. Is done.
[0082]
Here, when the sampling signal S1 becomes the active level during the period when the scanning signal G1 becomes the active level, all the first TFTs 116 counted from the top in FIG. 2 are turned on, and 6 belonging to the first block from the left. The image signals VID1 to VID6 are sampled on the data lines 114, respectively. The sampled image signals VID1 to VID6 are applied to the corresponding pixel electrodes 118 by the TFTs 116 of the pixels that intersect the first scanning line 112 and the six data lines 114, respectively.
[0083]
Thereafter, when the sampling signal S2 becomes an active level, the image signals VID1 to VID6 are sampled on the six data lines 114 belonging to the second block, respectively, and these image signals VID1 to VID6 are The pixel is applied to the corresponding pixel electrode 118 by the TFT 116 of the pixel that intersects the first scanning line 112 and the six data lines 114.
[0084]
Similarly, when the sampling signals S3, S4,..., Sn sequentially become active levels, the image signal VID1 is respectively applied to the six data lines 114 belonging to the third, fourth,. ~ VID6 are sampled, and these image signals VID1 to VID6 are applied to the corresponding pixel electrodes 118 by the first scanning lines 112 and the TFTs 116 of the pixels intersecting the six data lines 114, respectively. It becomes. As a result, writing to all the pixels in the first row is completed.
[0085]
Next, a period during which the scanning signal G2 is active will be described. In this embodiment, as described above, since polarity inversion is performed in units of scanning lines, writing on the negative electrode side is performed in this one horizontal scanning period. For this reason, the image signals VID <b> 1 to VID <b> 6 become lower voltages than the voltage LCcom applied to the counter electrode 108. Prior to this, since the voltage of the precharge voltage signal NRS in the blanking period becomes Vg−, when the precharge control signal NRG becomes active level, all the data lines 114 are precharged to the voltage Vg−. The Rukoto.
[0086]
Other operations are the same, and the sampling signals S1, S2, S3,..., Sn are sequentially set to the active level, and writing to all the pixels in the second row is completed.
[0087]
Similarly, the scanning signals G3, G4,..., Gm become active, and writing is performed on the pixels in the third row, fourth row,. As a result, the pixels on the odd-numbered rows are written on the positive electrode side, while the pixels on the even-numbered rows are written on the negative electrode side. In this one vertical scanning period, Writing over all the pixels in the m-th row is completed.
[0088]
In the next one vertical scanning period, similar writing is performed, but at this time, the writing polarity for the pixels in each row is switched. That is, in the next one vertical scanning period, the pixels on the odd-numbered rows are written to the pixels on the negative side, while the pixels on the even-numbered rows are written on the positive side.
[0089]
As described above, since the writing polarity for the pixel is switched every vertical scanning period, a direct current component is not applied to the liquid crystal 105, and its deterioration is prevented.
[0090]
Further, in such driving, the time for sampling the image signal by each sampling switch 151 is six times that of the method of driving the data lines 114 one by one, so that the writing power time in each pixel is sufficient. Secured. For this reason, a high contrast ratio is obtained. Further, since the number of stages of the shift register in the data line driving circuit 140 and the frequency of the clock signal CLX are each reduced to 1/6, the power consumption can be reduced along with the reduction in the number of stages.
[0091]
Further, the active period of the sampling signals S1, S2,..., Sn is narrowed to a half period of the clock signal CLX and is limited to the period SMPa, so that overlapping of adjacent sampling signals is prevented in advance. The Therefore, it is possible to prevent the image signals VID1 to VID6 to be sampled on the six data lines 114 belonging to a certain block from being simultaneously sampled on the six data lines 114 belonging to the adjacent blocks. High quality display is possible.
[0092]
<Detailed configuration of pixel>
Next, details of the pixel will be described with reference to FIGS. FIG. 6 is a plan view showing a detailed configuration of the pixel portion, and FIG. 7A is a cross-sectional view taken along the line BB ′ in FIG. In FIG. 6, only the outline of the pixel electrode 118 serving as the uppermost conductive layer is indicated by a broken line for the sake of understanding.
[0093]
First, as shown in FIG. 7A, a substrate 10 as a base material of the element substrate 101 is provided with a semiconductor layer 30 made of polysilicon through a base insulating film 40, and the surface thereof is formed by thermal oxidation. The insulating film 32 is covered.
[0094]
On the other hand, as shown in FIG. 6, the data line 114 extends in the Y direction, and the scanning line 112 extends in the X direction. The capacitor line 175 is provided close to and parallel to the scanning line 112, but protrudes to the previous stage (upper side in FIG. 6) so as to overlap the data line 114 at a portion intersecting the data line 114. Is formed.
[0095]
Here, the semiconductor layer 30 extends from the portion where the data line 114 and the capacitor line 175 intersect from the extending direction of the capacitor line 175 (right direction in FIG. 6) and the protruding direction of the capacitor line 175 below the data line 114 (same as the same). , Upward direction) and the opposite direction (same, downward direction) extending in a total of three directions so as to be substantially T-shaped and covered with these wirings.
[0096]
Furthermore, a portion of the semiconductor layer 30 that overlaps with the scanning line 112 is a channel region 30a. In other words, a portion of the scanning line 112 that intersects the semiconductor layer 30 is used as the gate electrode 116G. Note that the scanning line 112 and the capacitor line 175 including the gate electrode 116G are formed of, for example, polysilicon or the like as will be described later.
[0097]
In the semiconductor layer 30, a low concentration (translation is expressed by lightly doped) source region 30 b and a high concentration (translation is expressed by heavily doped) source region 116 S are provided on the source side of the channel region 30 a. On the drain side, a low concentration drain region 30c and a high concentration drain region 116D are provided to form a so-called LDD (Lightly Doped Drain) structure.
[0098]
Among these, the high-concentration source region 116S is connected to the data line 114 made of aluminum or the like through a contact hole 52 that opens the insulating film 32, the first interlayer insulating film 41, and the second interlayer insulating film 42. .
[0099]
On the other hand, the high-concentration drain region 116D is connected to one end of an intermediate conductive film 181 made of a refractory metal, polysilicon, or the like by a contact hole 51 that opens the insulating film 32 and the first interlayer insulating film 41. On the other hand, the other end of the intermediate conductive film 181 is connected to the pixel electrode 118 by a contact hole 53 that opens the second interlayer insulating film 42 and the third interlayer insulating film 43. That is, the pixel electrode 118 is connected to the high-concentration drain region 116D of the TFT 116 through the intermediate conductive film 181.
[0100]
Here, the reason why the pixel electrode 118 is indirectly connected through the intermediate conductive film 181 without being directly connected to the high-concentration drain region 116D is as follows. That is, since the pixel electrode 118 is an electrode for applying a voltage to the liquid crystal capacitance, the pixel electrode 118 is formed in a portion close to the liquid crystal 105, and on the contrary, the semiconductor layer 30 is formed in a distant portion. Furthermore, between the semiconductor layer 30 and the pixel electrode 118, if the TFT 116 is a planar type as in this embodiment, wiring layers such as the scanning lines 112 and the data lines 114 are stacked via an interlayer insulating film. Therefore, the distance between the semiconductor layer 30 and the pixel electrode 118 inevitably increases. For this reason, in the configuration in which the pixel electrode 118 is directly connected to the high-concentration drain region 116D, a contact hole having a relatively deep depth must be formed by dry etching, for example. However, when the contact hole having such a depth is formed, if the etching is performed excessively, the semiconductor layer 30 is broken. In particular, there is no great difference in the selection ratio between the semiconductor layer 30 and the insulating film, and the thickness of the semiconductor layer 30 is extremely small compared to the thickness of the insulating film to be etched. Making it more difficult.
[0101]
Therefore, first, a contact hole 51 is provided at a position corresponding to the high-concentration drain region 116 </ b> D, and the insulating film 32 and the first interlayer insulating film 41 are opened. An intermediate conductive film 181 that is electrically connected is formed, and this intermediate conductive film 181 functions as a barrier film for the high-concentration drain region 116D. Thus, when the contact hole 53 is opened before the pixel electrode 118 is formed, the intermediate conductive film 181 is used as an etching stopper, thereby preventing the semiconductor layer 30 from being pierced by excessive etching.
[0102]
As shown in FIG. 6 in particular, the intermediate conductive film 181 substantially covers the capacitor line 175 between the adjacent data lines 114, and part of the intermediate conductive film 181 covers the scanning line 112 (however, electrically). Is insulated). Further, the region where the pixel electrode 118 is not formed is covered with the data line 114 in the Y direction and covered with the scanning line 112 and the intermediate conductive film 181 in the X direction. Here, the intermediate conductive layer 181 may be polysilicon, Ti (titanium), Cr (chromium), W (tungsten), Ta (tantalum), Mo (molybdenum) or Pb (lead) alone or an alloy thereof, metal Silicide may be used. Therefore, since the light shielding region in the pixel portion is completely defined by the data line 114, the scanning line 112, and the intermediate conductive film 181, a light shielding film separately provided on the counter substrate 102 can be omitted. In addition, since the semiconductor layer 30 is covered with the data line 114, the scanning line 112, the capacitor line 175, and the intermediate conductive film, light from the upper side of the substrate is prevented from entering the TFT. Further, a light shielding film may be formed below the semiconductor layer 30 and between the substrate 10 and the base insulating film 40. Accordingly, it is possible to prevent light from the lower side of the substrate from entering the TFT 116, and thus it is possible to prevent a change in characteristics of the TFT 116 due to light irradiation.
[0103]
Next, a detailed configuration of the storage capacitor 119 will be described with reference to FIGS. 7B and 7C in addition to FIGS. 6 and 7A. Here, FIG. 7B is a cross-sectional view taken along the line CC ′ in FIG. 6, and FIG. 7C is a diagram showing an equivalent circuit of the storage capacitor 119.
[0104]
First, in the semiconductor layer 30, the region 30f adjacent to the high-concentration drain region 116D is reduced in resistance by high-concentration doping, and has a substantially L-shape in the lower layer of the capacitor line 175 in plan view. . On the other hand, the intermediate conductive film 181 is formed so as to cover the capacitor line 175 in the X direction with the capacitor line 175 through the first interlayer insulating film 41 as described above. Therefore, as shown in FIG. 7B or FIG. 7C, the storage capacitor 119 is obtained by paralleling two capacitors. Specifically, the storage capacitor 119 includes a first capacitor formed by sandwiching the insulating film 32 formed on the surface of the semiconductor layer 30 with the region 30f as one electrode and the capacitor line 175 as the other electrode, The conductive film 181 is used as one electrode and the capacitor line 175 is used as the other electrode, so that the conductive film 181 is connected in parallel with a second capacitor sandwiching the first interlayer insulating film 41. For this reason, the storage capacitor 119 increases in capacity as compared with the case of a single capacitor, so that the retention characteristic of the liquid crystal capacitor is improved and the display quality is improved.
[0105]
Note that an alignment film 61 made of an organic film such as polyimide is formed on the entire surface of the uppermost layer (that is, the surface in contact with the liquid crystal 108), and is rubbed before being bonded to the counter substrate 102.
[0106]
<Detailed configuration of peripheral circuit>
Next, details of the peripheral circuit will be described using a partial region of the sampling circuit 150 and a partial region of the scanning line driving circuit 130 as examples. Note that active elements and wirings constituting the peripheral circuit are common to the TFT 116, the scanning line 112 (and the capacitor line 175), the intermediate conductive film 181, and the data line 114 in the display region as described in detail in a later manufacturing process. Formed in the process.
[0107]
Among these, in the display region 101a, the wiring is formed in the order of the scanning line 112 (and the capacitor line 175), the intermediate conductive film 181, and the data line 114. Therefore, in the following description, scanning among the wiring in the peripheral circuit is performed. A wiring made of the same layer as the conductive layer constituting the line 112 is called a first layer wiring, and a wiring made of the same layer as the conductive layer making up the intermediate conductive film 181 is called a second layer wiring. Further, a wiring made of the same layer as the conductive layer constituting the data line 114 is referred to as a third layer wiring. Since the conductive layer constituting the intermediate conductive film 181 has not been conventionally used in the peripheral circuit region, the third layer wiring in this embodiment corresponds to the second layer wiring in the conventional electro-optical device. Will do.
[0108]
As described above, when wiring for three layers from the first layer to the third layer is used in the peripheral circuit, the degree of freedom in designing the peripheral circuit is higher than that in the conventional case where only two layers of wiring are used. Improve to each stage. Further, by using the second layer wiring as described below, it is possible to reduce the wiring resistance and the circuit formation region.
[0109]
<Near area of sampling circuit>
First, a partial region of the sampling circuit 150 will be described with reference to FIGS. 8 (a) and 8 (b). Here, the relationship between the sampling signal Sj output corresponding to the jth block from the left and the path from the six image signal lines 122 to the six data lines 114 belonging to the block is shown. The explanation will be centered. Note that j is a generalized description of the block as in the description of FIG. 2, and is an integer from “1” to “n” in the present embodiment.
[0110]
FIG. 8A is a plan view showing the detailed configuration of this area. First, the sampling signal Sj output from the data line driving circuit 140 is supplied through a path of a third layer wiring 391, a lower layer wiring 191, a third layer wiring 393, and six first layer wirings 412. . Here, the wirings are connected to each other through a contact hole, and the wiring 412 in the first layer serves as a gate electrode of the TFT constituting the sampling switch 151 as it is.
[0111]
On the other hand, among the image signals VID1 to VID6, the image signal VID1 is supplied to the sampling switch 151 through the following path. That is, the image signal VID1 is sent to the sampling switch 151 via the path of the image signal line 122 made of the third layer, the lower layer wiring 193, the third layer wiring 395, the lower layer wiring 195, and the third layer wiring 397. It is supplied to the source region of the TFT to be constructed. The other image signals VID2 to VID6 are also supplied to the source region of the TFT constituting the sampling switch 151 through the same path. A third layer data line 114 is connected to the drain region of the TFT constituting each sampling switch 151.
[0112]
As described above, the third-layer wiring is used in principle for the various wirings of the sampling circuit 150, but the lower-layer wiring is used as an exception for the portion intersecting with the third-layer wiring and the portion used as the gate electrode. ing.
[0113]
Here, a cross-sectional structure taken along line DD ′ in FIG. 8A will be described with reference to FIG. As shown in this figure, the wiring 193 branched from the image signal line 122 to which the image signal VID1 is supplied and intersects with the other image signal lines 122 in the lower layer is the first layer wiring 112b and the second layer. The wiring 181b is a parallel wiring connected in parallel. Specifically, the wiring 181b has a contact hole 55 that opens the first interlayer insulating film 41 at both ends thereof. ₁ , 56 ₁ Are connected in parallel with the wiring 112b. Further, the image signal line 122 to which the image signal VID1 is supplied is connected to the contact hole 55. ₁ Contact hole 55 provided at the same position as ₂ The wiring 395 is connected to the wiring 181b via the contact hole 56. ₁ Contact hole 56 provided at the same position as ₂ Is connected to the wiring 181b.
[0114]
Note that the wiring 193 branched from the image signal line 122 to which the image signals VID2 to VID6 other than the image signal VID1 are supplied is similarly connected in parallel with the first layer wiring 112b and the second layer wiring 181b. Parallel wiring. Further, in addition to the wiring 193 branching / intersecting from the image signal line 122, the wiring 195 for intersecting the wiring 393 supplied with the sampling signal Sj is similarly applied to the first layer wiring 112c and the second layer wiring 181c. Are connected in parallel.
[0115]
Here, in the sampling circuit 150, the parallel wiring of the first layer wiring and the second layer wiring is used for the wirings 193 and 195 for the following reason. That is, since the image signals VID1 to VID6 are analog signals that are finally applied to the pixel electrode 118 and directly define the display state, it is desirable that the supply path be as low as possible. For this reason, the third layer made of aluminum is used for the image signal line 122, but for the wiring branched from here, a layer other than the third layer must be used. For this reason, conventionally, a wiring made of a conductive layer constituting the scanning line 112, that is, a first-layer wiring is used for this portion. However, since the first layer is polysilicon or the like as described above, it has a much higher resistance than aluminum or the like constituting the third layer. For this reason, even if the wiring length of the first layer is very small, the influence of the resistance is so large that it cannot be ignored.
[0116]
Therefore, in the present embodiment, the second layer that was originally used in the display area is the periphery of the supply path of the image signals VID <b> 1 to VID <b> 6 where the wiring composed of layers other than the third layer must be used. In addition to being used in the circuit area, the second layer wiring and the first layer wiring are connected in parallel. For this reason, the resistance value of the part is reduced to about half as compared with the case of a single layer wiring. Therefore, in the present embodiment, the image signals VID1 to VID6 are supplied to the data line 114 after preventing waveform blunting and voltage drop in the supply path, and thus, good display is possible.
[0117]
The parallel wiring 193 branched from the image signal line 122 has substantially the same length and the same width over each of the image signals VID1 to VID6, as shown in FIG. In this embodiment, although the wiring 193 is configured by parallel connection of the first layer wiring 112b and the second layer wiring 181b and the wiring resistance is reduced, the wiring of the third layer This is a measure for making the resistance value of the wiring 193 equal to each other over each of the image signals VID1 to VID6 because it is still large if compared.
[0118]
Further, the wiring 191 that supplies the sampling signal Sj so as to cross the image signal line 122 is deviated from the supply path of the image signals VID <b> 1 to VID <b> 6, and the first layer wiring and the second layer wiring are similarly arranged in parallel. Connected. This is because the supply path of the sampling signal Sj is required to have a low resistance as much as possible from the viewpoint of preventing a delay due to the blunting of the waveform of the sampling signal Sj.
[0119]
As described above, in the present embodiment, the low-resistance third-layer wiring is used for the various wirings of the sampling circuit 150 in principle, while the first layer is not included in the portion that must cross the third-layer wiring. Parallel wiring of layer wiring and second layer wiring is used. Here, in terms of the entire peripheral circuit, there are many portions where the parallel wiring should be used in addition to the wirings 191, 193, and 195 in the sampling circuit 150. For example, the precharge control line 163 in FIG. 2 has to branch to the gate electrodes of the TFTs constituting each precharging switch 161, but after the branch, a portion that must cross the precharge voltage signal line 165. Exists. The capacitor line 175 is the same first layer wiring as the scanning line 112 in the display region 100a. However, in the other region, the capacitor line 175 is connected to the mounting terminal 107 so as to be connected in common. It must be composed of three layers of wiring. The precharge control line 163 and the precharge voltage signal line 165 have a portion that must intersect with the capacitor line 175 as shown in FIG. Further, in the scanning line driving circuit 130, it is necessary to supply the clock signal CLY and the inverted clock signal CLYinv together with the power supply voltages VddY and VssY to the unit circuit constituting the shift register. For this reason, as for the wiring branched from the main wiring of the clock signal CLY and the inverted clock signal CLYinv, there is a portion that must cross at least the wiring to which the power supply voltages VddY and VssY are supplied. Similarly, in the data line driving circuit 140, the unit circuit constituting the shift register includes the power supply voltages VddX and VssX, the clock signal CLX and the inverted clock signal CLXinv, and each AND circuit includes the power supply voltages VddX and VssX. , Enable signals ENB1 and ENB2 need to be supplied. For this reason, the wiring branching from the main wiring of the clock signal CLX and the inverted clock signal CLXinv and the wiring branching from the main wiring of the enable signals ENB1, ENB2 are wirings to which at least the power supply voltages VddY, VssY are supplied There are parts that must intersect. Then, by using a parallel wiring in which the first layer wiring and the second layer wiring are connected in parallel to the portion that must cross the third layer wiring in this way, the resistance of the portion is reduced. It becomes possible.
[0120]
<Partial region of scan line driver circuit>
Next, a partial region of the scanning line driving circuit 130 will be described with reference to FIGS. 9A and 9B. Here, FIG. 9A is a plan view showing a configuration of a partial region of the scanning line driving circuit 130, and FIG. 9B is a diagram showing an equivalent circuit thereof. The region shown in the drawing is a partial extraction of a circuit for transferring the transfer start pulse DY in accordance with the clock signal CLY and the inverted clock signal CLYinv from the shift register constituting the scanning line driving circuit 130. is there.
[0121]
As shown in FIG. 9A, the scanning line driving circuit 130 uses first-layer, second-layer, and third-layer wirings. Also in this region, the third layer wiring is used in principle, except that the first layer wiring is used for the portion intersecting with the third layer wiring and the portion used as the gate electrode. In addition, the second layer wiring 181d is used for a part of the wiring from the source electrode of one TFT to the drain electrode of the other TFT. In particular, in the region 132, the first-layer wiring 112d, the second-layer wiring 181d, and the third-layer wiring 114d are stacked on each other via an interlayer insulating film (not shown here).
[0122]
Here, in the scanning line driving circuit 130, unlike the sampling circuit 150 described above, the second-layer wiring 181d is used alone and the three-layer wiring is formed in the same region for the following reason. . That is, since the data line driving circuit 130 supplies the sampling signals S1, S2,..., Sn to each of the six data lines 114, each unit circuit or logical product circuit of the shift register constituting the data line driving circuit 130 is provided. Is required to be within a pitch of 6 times the data line pitch in FIG. On the other hand, since the scanning line driving circuit 130 must supply the scanning signals G1, G2,..., Gm to each of the m scanning lines 112, the shift register constituting the scanning line driving circuit 140 is provided. These unit circuits and logical product circuits must be accommodated within a pitch equal to the scanning line pitch in FIG. That is, in the scanning line driving circuit 130, the unit circuit and the AND circuit must be formed in a narrower area than the data line driving circuit 140. Here, if three wirings are formed only from the first layer and the third layer without using the second layer wiring 181d, one wiring is formed from the first layer and the remaining two wirings are formed from the third layer. Each layer must be formed from each layer, but in this case, it is impossible to form two third layer wirings in the same region. For this reason, the third layer wiring must be formed side by side in different regions, so that a wider region is required. Therefore, in such a configuration, the unit circuit and the logical product circuit constituting the scanning line driving circuit 130 must be formed in a narrower region. On the other hand, in the present embodiment, the second layer wiring 181d is used alone, and the first layer wiring 112d, the second layer wiring 181d, and the third layer wiring 114d are (interlayer) in the same region 132. By forming the layers so as to overlap each other (with insulation through an insulating film), the width of a region necessary for circuit formation can be reduced.
[0123]
Note that in the scan line driver circuit 130, a portion that is not required to have a narrow width of a region necessary for circuit formation, and a portion that must intersect with a third-layer wiring, Of course, parallel wiring with the wiring of the second layer may be used.
[0124]
<Manufacturing process>
Next, the manufacturing process of the electro-optical device according to the present embodiment will be described focusing on the display area and the peripheral circuit area of the element substrate 101. As the peripheral circuit region here, in FIG. 8B, a region near a wiring 193 branched from one image signal line 122 and intersecting with another image signal line 122 is illustrated. .
[0125]
First, as shown in FIG. 10A, a base insulating film 40 is formed on the surface of a substrate 10 such as a quartz substrate, a glass substrate, or a silicon substrate. More specifically, the base insulating film 40 is formed by NSG (non-doped silicate glass), PSG (phosphorus silicate glass), BSG (boron silicate glass), BPSG (BPSG) by, for example, an atmospheric pressure method or a low pressure CVD (Chemical Vapor Deposition) method. The film is formed from a highly insulating glass such as boron phosphorus silicate glass), a silicon oxide film, a silicon nitride film, or the like with a thickness of about 50 to 1500 nm, preferably about 600 to 800 nm.
[0126]
Subsequently, an amorphous silicon layer is formed with a thickness of about 100 nm on the entire upper surface of the base insulating film 40 by, for example, a low pressure CVD method, and a polysilicon layer is formed by solid phase growth by heat treatment or the like. At this time, when an N-channel TFT is formed, impurities of group V elements such as Sb (antimony), As (arsenic), and P (phosphorus) are slightly doped by ion implantation or the like. In the case of forming a channel type TFT, impurities of group III elements such as Al (aluminum), B (boron), and Ga (gallium) are similarly doped slightly by ion implantation or the like. Then, as shown in FIG. 2B, the polysilicon layer is patterned by photolithography, etching, or the like to form the semiconductor layer 30 of the TFT 116 in the display region in an island shape. At this time, in the entire peripheral circuit, the TFT semiconductor layers constituting the scanning line driving circuit 130, the data line driving circuit 140, the sampling circuit 150, and the precharge circuit 160 are similarly formed. In addition, in the semiconductor layer 30 of the TFT 116, the region 30f where the capacitor line 175 is formed may be doped with an impurity such as P (phosphorus) at a high concentration to reduce the resistance in advance.
[0127]
Further, as shown in FIG. 10 (3), the surface of the semiconductor layer 30 is thermally oxidized to form a gate insulating film 32 on the surface of the semiconductor layer 30. By this step, the semiconductor layer 30 finally has a thickness of about 30 to 150 nm, preferably about 35 to 45 nm, while the gate insulating film 32 has a thickness of about 60 to 150 nm, preferably about 30 nm. It becomes.
[0128]
Next, a polysilicon layer is deposited on the upper surfaces of the gate insulating film 32 and the base insulating film 40 by a low pressure CVD method or the like. Then, as shown in FIG. 11 (4), this polysilicon layer is patterned by photolithography, etching, or the like, and in the display area, the scanning line 112 that also serves as the gate electrode of the TFT 116, and the storage capacitor 119 The capacitor line 175 forming the other electrode is formed, and one wiring 112b of the parallel wiring 193 is formed in the peripheral circuit region. That is, in the entire peripheral circuit, the first layer wiring including the gate electrode is formed.
[0129]
Subsequently, as shown in FIG. 5 (5), the semiconductor layer 30 is doped with appropriate impurities. Specifically, in the case where the TFT 116 in the display region is an N-channel type, P or the like using a gate electrode which is a part of the scanning line 112 as a diffusion mask for a region adjacent to the channel region 30a in the source / drain region The impurity of the V group element is doped at a low concentration. At the same time, the N-channel TFT in the entire peripheral circuit is similarly doped with impurities at a low concentration using the gate electrode which is a part of the first layer wiring as a diffusion mask. Subsequently, a resist having a width wider than that of the gate electrode is formed, and using this as a mask, impurities of a V group element such as P are doped at a high concentration. Thus, in the N-channel TFT, the low concentration source region 30b and the high concentration source region 116S are provided on the source side of the channel region 30a, while the low concentration drain region 30c and the high concentration drain region 116D are provided on the drain side. An LDD structure is provided. Although illustration is omitted, after masking the semiconductor layer 30 of these N-channel TFTs with a resist, the P-channel TFTs in the entire peripheral circuit are similarly formed in the first layer with respect to the region adjacent to the channel region. Using the gate electrode that is a part of the wiring as a mask, doping a group III element impurity such as B (boron), for example, to form a low concentration region, and subsequently using a resist wider than the gate electrode as a mask, Similarly, a high concentration region is formed by doping an impurity of a group III element such as B. Further, each channel type TFT may not be an LDD structure, but may be an offset structure TFT, or a simple self-aligned (self-aligned) TFT.
[0130]
Next, as shown in FIG. 6 (6), the first interlayer insulating film 41 is formed so as to cover the scanning line 112, the first layer wiring 112b, the semiconductor layer 30, the base insulating film 40, etc. Deposited by CVD or the like. As the material of the first interlayer insulating film 41, similarly to the base insulating film 40, silicate glass films such as NSG, PSG, BSG, and BPSG, silicon nitride films, silicon oxide films, and the like can be given.
[0131]
Further, as shown in FIG. 12 (7), the contact hole 51 for connecting the contact hole 51 in the display region and the first layer wiring 112 b in the peripheral circuit region. ₁ , 56 ₁ Are formed by dry etching or the like. Specifically, the contact hole 51 is formed so as to open the first interlayer insulating film 41 and the gate insulating film 32 at a position corresponding to the high-concentration drain region 116D of the TFT 116, while the contact hole 55 ₁ , 56 ₁ Are formed so as to open the first interlayer insulating film 41 at both end positions of the first layer wiring 112b. Note that, in the entire peripheral circuit, when conduction between the first layer wiring and the second layer wiring is intended, a contact hole (not shown) is similarly formed corresponding to the conduction portion.
[0132]
Next, a conductive layer made of refractory metal, metal silicide, polysilicon, or the like is formed on the first interlayer insulating film 41 to a thickness of about 50 to 500 nm, preferably about 200 nm, by sputtering or the like. Sedimentation. Needless to say, the conductive layer may be formed of multiple layers of refractory metal or metal silicide and polysilicon. As a result, the stress relaxation of the conductive layer and the resistance reduction of the contact hole can be realized. Then, as shown in FIG. 8 (8), this conductive layer is patterned by photolithography, etching or the like, and in the display region, the intermediate conductive film 181 connected to the high-concentration drain region 116D of the TFT 116. On the other hand, in the peripheral circuit region, the other wiring 181b of the parallel wiring 193 is formed. That is, the second layer wiring is formed in the entire peripheral circuit.
[0133]
Subsequently, as shown in FIG. 9 (9), the second interlayer insulating film 42 is formed by a CVD method so as to cover the intermediate conductive film 181, the second layer wiring 18b, and the first interlayer insulating film 41. Etc. to a thickness of about 500-1500 nm. As the material of the second interlayer insulating film 42, a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, an oxide, etc., like the base insulating film 40 and the first interlayer insulating film 41. Examples thereof include a silicon film.
[0134]
Next, as shown in FIG. 13 (10), the contact hole 52 for connecting the contact hole 52 in the display area and the second layer wiring 181 b in the peripheral circuit area. ₂ , 56 ₂ Are formed respectively. Specifically, the contact hole 52 is formed so as to open the second interlayer insulating film 42, the first interlayer insulating film 41, and the gate insulating film 32 at a position corresponding to the high concentration source region 116 </ b> S of the TFT 116. On the other hand, contact hole 55 ₂ , 56 ₂ Are formed so as to open the second interlayer insulating film 42 at both end positions of the second layer wiring 181b. Note that, in the entire peripheral circuit, when conduction between the second layer wiring and the third layer wiring is attempted, a contact hole (not shown) is similarly formed corresponding to the conduction portion.
[0135]
Further, contact holes 52 and 55 ₂ , 56 ₂ A conductive film made of a low-resistance metal such as aluminum is deposited on the second interlayer insulating film 42 formed with a thickness of about 50 to 500 nm by sputtering or the like. Then, as shown in FIG. 11 (11), this conductive film is patterned by photolithography, etching, or the like to form data lines 114 that also serve as the source electrode of the TFT 116 in the display area, In the circuit area, the wiring 391 and the image signal line 122 are formed. That is, the third layer wiring is formed in the entire peripheral circuit.
[0136]
Subsequently, as shown in FIG. 12 (12), the third interlayer insulating film 43 is formed by a CVD method or the like so as to cover the third layer wiring such as the data line 114 and the image signal line 122. Deposit to a thickness of 1500 nm. The material of the third interlayer insulating film 43 is silicate such as NSG, PSG, BSG, BPSG, as in the case of the base insulating film 40, the first interlayer insulating film 41, and the second interlayer insulating film 42. A glass film, a silicon nitride film, a silicon oxide film, or the like can be given.
[0137]
Next, as shown in FIG. 14 (13), the contact hole 53 is opened at a predetermined position in the intermediate conductive film 181 so as to open the third interlayer insulating film 43 and the second interlayer insulating film 42. In addition, it is formed by dry etching or the like.
[0138]
Then, a transparent conductive film such as ITO is deposited on the surface of the third interlayer insulating film 42 in which the contact hole 53 is formed to a thickness of about 50 to 200 nm by sputtering or the like, and then by photolithography or etching or the like. The pixel electrode 118 is formed by patterning into a predetermined shape (see FIG. 5), as shown in FIG. Although the illustration of the subsequent steps is omitted, an organic solution such as polyimide is applied and baked on the entire surface of the pixel electrode 118 and the third interlayer insulating film 43 which are opposing surfaces in the substrate 10. Thereby, the alignment film 61 is formed. The alignment film 61 is rubbed in a predetermined direction.
[0139]
The element substrate 101 formed in this manner is bonded to the counter substrate 102 rubbed in a direction rotated by about 90 degrees with the sealing material 104, and then the liquid crystal 105 is sealed and sealed. Thus, an electro-optical device as shown in FIG. 1 is obtained.
[0140]
Note that in the element substrate 101, the alignment film 61 is formed over the entire surface. However, after liquid crystal sealing, the alignment film formed in the peripheral circuit region and the portion protruding from the counter substrate 102 is formed by plasma treatment or the like. Removed. Therefore, the uppermost layer in the peripheral circuit region is not the alignment film 61 but the third interlayer insulating film 43.
[0141]
According to such a manufacturing method, the conductive film in the same layer as the intermediate conductive film 181 used as the barrier film for the high-concentration drain region 116D of the TFT 116 is used as the second layer wiring in the peripheral circuit in the display region. This is possible without adding a special process. Further, by using three layers of wiring, the degree of freedom in designing the peripheral circuit can be improved in each stage. In addition, by connecting in parallel with the first layer wiring, it is possible to reduce the resistance of the wiring, and by using the second layer wiring alone, three layers wiring in the same region Can be formed.
[0142]
<Application example>
In the above-described embodiment, when the third layer wiring is connected to the parallel wiring of the first layer wiring and the second layer wiring, the third layer wiring is connected to the second layer wiring. It became the composition to be. For example, in FIG. 8B, the image signal line 122 is configured to be connected to the second layer wiring 181b in the parallel wiring 193.
[0143]
As described above, when the conductive layer of the second layer is made of a refractory metal or the like that is likely to generate stress (easy to warp), the contact hole 55 for connecting to the wiring 181b of such a refractory metal. ₂ , 56 ₂ When the holes are opened, cracks and the like may occur in the second interlayer insulating film 42 due to stress concentration accompanying the opening. Contact hole 55 ₂ , 56 ₂ Therefore, when the second layer wiring 181b is exposed, impurities are diffused from the wiring 181b, which may cause a defect.
[0144]
Therefore, when connecting the third layer wiring to one end of the parallel wiring 193 of the first layer wiring 112b and the second layer wiring 181b, for example, as shown in FIG. The wiring 181b of the contact hole 57 slightly inside ₁ , 58 ₁ The first wiring 112b is connected to the first wiring 112b as a parallel wiring 193, and the third layer wiring is connected to the outer contact hole 57. ₂ Or 58 ₂ It is considered desirable to be connected to the first layer wiring 112b via the first layer. In this configuration, after the second interlayer insulating film 42 is formed, the second-layer wiring 181b is not exposed. For this reason, stress concentration due to the opening of the contact hole does not occur, so that cracks in the second interlayer insulating film 42 are prevented, and impurities are prevented from being diffused from the wiring 181b.
[0145]
Further, the parallel wiring 193 is configured to be connected only at both ends of the first wiring 112b and the second wiring 181b. However, as shown in FIG. 15B, at one or more points other than both ends. Contact holes 58 and 59 may be provided and connected at this point so that the connection between both wirings can be made more reliable. Even in such a configuration in which the first wiring 112b and the second wiring 181b are connected through one or more contact holes other than both ends, the third-layer wiring is connected through the outer contact hole. May be connected to the first layer wiring 112b.
[0146]
<Others>
In the above-described embodiment, the six data lines 114 are grouped into one block, and the image signals VID1 to VID6 converted into six systems with respect to the six data lines 114 belonging to one block. However, the number of conversions and the number of data lines applied simultaneously (that is, the number of data lines constituting one block) are not limited to “6”. For example, if the response speed of the sampling switch 151 in the sampling circuit 150 is sufficiently high, the image signal is serially transmitted to one image signal line without being converted into parallel, and is point-sequentially for each data line 114. You may comprise so that it may sample. In such a configuration, since the shift register and the AND circuit constituting the data line driving circuit 140 must be formed at the same magnification as the data line pitch, the second layer as in the scanning line driving circuit 130 is formed. It may be necessary to use a single wire.
[0147]
Further, the number of data lines to be converted and simultaneously applied is “3”, “12”, “24”, etc. A configuration may be adopted in which image signals subjected to conversion, 24-system conversion, and the like are simultaneously supplied. The number of conversions and the number of data lines to be applied simultaneously are multiples of 3 in order to simplify the control and the circuit because the color image signal is composed of signals related to the three primary colors. preferable. However, it is not necessary to be a multiple of 3 in the case of a simple light modulation application such as a projector described later. Furthermore, instead of simultaneously controlling a plurality of sampling switches, the image signals VID1 to VID6 converted in parallel may be sequentially shifted and supplied to control the sampling switches 151 in order.
[0148]
In the above-described embodiment, the scanning line 112 is scanned from the top to the bottom, while the block is selected from the left to the right. However, the configuration may be selected in the opposite direction. A configuration in which one of the directions can be selected according to the application may be used.
[0149]
Further, in the above-described embodiment, the planar type TFT 116 and the like are formed on the element substrate 101, but the present invention is not limited to this. For example, the TFT 116 may be a bottom gate type. Further, the element substrate 101 may be a semiconductor substrate, and a field effect transistor may be formed here instead of the TFT 116. Further, an SOI (Silicon On Insulator) technique may be applied to form a silicon single crystal film on an insulating substrate such as sapphire, quartz, or glass, and various elements may be formed therein to form the element substrate 101. However, when the element substrate 101 does not have transparency, it is necessary to use the liquid crystal panel 100 as a reflective type by forming the pixel electrode 118 with aluminum or separately forming a reflective layer.
[0150]
In the embodiment described above, the TN type is used as the liquid crystal. However, a bistable type having a memory property such as a BTN (Bi-stable Twisted Nematic) type or a ferroelectric type, a polymer dispersed type, and a molecule A dye (guest) having anisotropy in absorption of visible light in the major axis direction and the minor axis direction is dissolved in a liquid crystal (host) having a certain molecular arrangement, and the dye molecules are arranged in parallel with the liquid crystal molecules. A guest host type liquid crystal may be used.
[0151]
In addition, the liquid crystal molecules are arranged in a vertical direction with respect to both substrates when no voltage is applied, while the liquid crystal molecules are arranged in a horizontal direction with respect to both substrates when a voltage is applied. The liquid crystal molecules are aligned in the horizontal direction with respect to both substrates when no voltage is applied, while the liquid crystal molecules are aligned in the vertical direction with respect to both substrates when a voltage is applied. It is good also as a structure. As described above, the present invention can be applied to various liquid crystal and alignment methods.
[0152]
In addition to the liquid crystal device, the electro-optical device can be applied to various electro-optical devices that display by the electro-optical effect using electroluminescence (EL), plasma emission or fluorescence by electron emission. It is. In this case, the electro-optical material is EL, mirror device, gas, phosphor, or the like. Note that in the case where EL is used as the electro-optical material, the EL is interposed between the pixel electrode 118 and the counter electrode 108 of the transparent conductive film in the element substrate 101, so that the counter substrate 102 is not necessary. Thus, the present invention can be applied to all electro-optical devices having a configuration similar to the above-described configuration.
[0153]
<Electronic equipment>
Next, some electronic apparatuses using the electro-optical device according to the above-described embodiment will be described.
[0154]
<Part 1: Projector>
First, a projector using the liquid crystal panel 100 described above as a light valve will be described. FIG. 16 is a plan view showing the configuration of the projector. As shown in this figure, a lamp unit 2102 made of a white light source such as a halogen lamp is provided inside the projector 2100. The projection light emitted from the lamp unit 2102 is separated into three primary colors of RGB by three mirrors 2106 and two dichroic mirrors 2108 disposed therein, and light valves 100R, 100G corresponding to the primary colors and 100B, respectively. Here, the configuration of the light valves 100R, 100G, and 100B is the same as that of the liquid crystal panel 100 according to the above-described embodiment, and R, G, and B primary colors supplied from a processing circuit (not shown) that inputs an image signal. Each is driven by a signal. In addition, B light has a long optical path compared to other R colors and G colors, and therefore, in order to prevent the loss, B light passes through a relay lens system 2121 including an incident lens 2122, a relay lens 2123, and an exit lens 2124. Led.
[0155]
The light modulated by the light valves 100R, 100G, and 100B is incident on the dichroic prism 2112 from three directions. In the dichroic prism 2112, the R and B light beams are refracted at 90 degrees, while the G light beam travels straight. Therefore, after the images of the respective colors are combined, a color image is projected onto the screen 2120 by the projection lens 2114.
[0156]
Since light corresponding to the primary colors R, G, and B is incident on the light valves 100R, 100G, and 100B by the dichroic mirror 2108, it is not necessary to provide a color filter as described above. In addition, the transmission images of the light valves 100R and 100B are projected after being reflected by the dichroic mirror 2112, whereas the transmission image of the light valve 100G is projected as it is. The display image is horizontally reversed with respect to the display image by 100G.
[0157]
<Part 2: Mobile computer>
Next, an example in which the liquid crystal panel 100 described above is applied to a mobile personal computer will be described. FIG. 17 is a perspective view showing the configuration of this personal computer. In the figure, a computer 2200 includes a main body portion 2204 provided with a keyboard 2202 and a liquid crystal panel 100 used as a display portion. Note that a backlight unit (not shown) for improving visibility is provided on the back surface of the liquid crystal panel 100.
[0158]
<Part 3: Mobile phone>
Further, an example in which the above-described liquid crystal panel 100 is applied to a display unit of a mobile phone will be described. FIG. 18 is a perspective view showing the configuration of this mobile phone. In the figure, a mobile phone 2300 is provided with the above-described liquid crystal panel 100 together with an earpiece 2304 and a mouthpiece 2306 in addition to a plurality of operation buttons 2302. Note that a backlight unit (not shown) for enhancing visibility is also provided on the back surface of the liquid crystal panel 100.
[0159]
In addition to the electronic devices described with reference to FIGS. 16, 17 and 18, the electronic devices include a liquid crystal television, a viewfinder type / direct monitor type video tape recorder, a car navigation device, a pager, an electronic notebook, Examples include calculators, word processors, workstations, videophones, POS terminals, digital still cameras, and devices equipped with touch panels. Needless to say, the electro-optical device according to the embodiment or the application mode can be applied to these various electronic devices.
[0160]
【The invention's effect】
As described above, according to the present invention, since a wiring made of the same conductive layer as the intermediate conductive film used for connecting the other end of the switching element and the pixel electrode in the display region can be used, the peripheral circuit is designed. It is possible to improve the degree of freedom when doing so.
[Brief description of the drawings]
FIG. 1A is a perspective view illustrating a configuration of a liquid crystal panel of an electro-optical device according to an embodiment of the invention, and FIG. 1B is a cross-sectional view taken along line AA ′ in FIG. .
FIG. 2 is a block diagram showing an electrical configuration of the liquid crystal panel.
FIG. 3 is a diagram showing an equivalent circuit in a display area of the liquid crystal panel.
FIG. 4 is a timing chart for explaining the operation of the liquid crystal panel.
FIG. 5 is a timing chart for explaining the operation of the liquid crystal panel.
FIG. 6 is a plan view showing a detailed configuration of a pixel in a display area of the liquid crystal panel.
7A is a cross-sectional view taken along the line BB ′ in FIG. 6, FIG. 7B is a cross-sectional view taken along the line CC ′ in FIG. 5, and FIG. 2 is an equivalent circuit showing a configuration of a storage capacitor in FIG.
8A is a plan view showing a configuration in the vicinity of a sampling circuit of the liquid crystal panel, and FIG. 8B is a cross-sectional view taken along the line DD ′.
9A is a plan view showing a partial configuration of a scanning line driving circuit of the liquid crystal panel, and FIG. 9B is a diagram showing an electrical configuration thereof.
FIGS. 10A to 10C are cross-sectional views showing a process for manufacturing an element substrate in the liquid crystal panel.
FIGS. 11A to 11D are cross-sectional views showing a process for manufacturing an element substrate in the liquid crystal panel. FIGS.
12 (7) to (9) are cross-sectional views showing a process for manufacturing an element substrate in the same liquid crystal panel. FIG.
FIGS. 13A to 13E are cross-sectional views showing a process for manufacturing an element substrate in the liquid crystal panel. FIGS.
FIGS. 14A and 14B are cross-sectional views showing a process for manufacturing an element substrate in the liquid crystal panel, respectively. FIGS.
FIGS. 15A and 15B are cross-sectional views each showing a configuration in the vicinity of a sampling circuit of an electro-optical device according to a modification of the invention. FIGS.
FIG. 16 is a plan view illustrating a configuration of a projector as an example of an electronic apparatus to which the electro-optical device according to the embodiment is applied.
FIG. 17 is a perspective view showing a configuration of a personal computer as an example of the electronic apparatus.
FIG. 18 is a perspective view showing a configuration of a mobile phone as an example of the electronic apparatus.
[Explanation of symbols]
10 ... Board
30 ... Semiconductor layer
40: Underlying insulating film
41. First interlayer insulating film
42. Second interlayer insulating film
43 ... Third interlayer insulating film
61 ... Alignment film
100 ... Liquid crystal panel
101: Element substrate
102. Counter substrate
105 ... Liquid crystal
108 ... Counter electrode
112 ... Scanning line
112b, 112c, 112d ... wiring
114 ... data line
114b, 114c, 114d ... wiring
116 ... TFT
118: Pixel electrode
119 ... Storage capacity
122: Image signal line
130: Scanning line driving circuit
140 Data line driving circuit
150 ... Sampling circuit
151. Sampling switch
160: Precharge circuit
161: Precharging switch
175 ... Capacity line
181: Intermediate conductive film
191 193 195 wiring
181b, 181c, 181d ... wiring
391, 393, 395 ... wiring
2100 ... Projector
2200 ... Personal computer
2300 ... Mobile phone

Claims (3)

A clock signal line or an inverted clock signal line;
A plurality of columns formed by sequentially arranging a first transistor and a second transistor in a column direction in a direction crossing the clock signal line or the inverted clock signal line;
A gate electrode of the second transistor in one column, and a gate electrode of the first transistor in a column adjacent to the one column, arranged to extend along the column between the plurality of columns. A first layer wiring connected to each of the clock signal line or the inverted clock signal line;
One of the electrodes of the semiconductor layer of the first transistor in the one column is disposed between the plurality of columns so as to overlap the wiring of the first layer and extend along the column, A second layer wiring connected to one electrode of the semiconductor layer of the two transistors via another wiring layer formed on each upper layer;
It is the same layer as the other wiring layer, and is arranged so as to overlap the wiring of the first layer and the wiring of the second layer and extend along the column between the plurality of columns, and the adjacent column A third-layer wiring connected to the other electrode of the semiconductor layer of the first transistor in
A scanning line driving circuit comprising:   An electro-optical device comprising the scanning line driving circuit according to claim 1.   An electronic apparatus comprising the electro-optical device according to claim 2.

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