JP3832492B2 - Electro-optical device drive circuit, electro-optical device, and electronic apparatus - Google Patents

Description

  The present invention relates to an electro-optical device that inputs a digital image signal and performs display using an electro-optical effect, a drive circuit for the electro-optical device, and an electronic apparatus in which the electro-optical device is applied to a display unit.

  A conventional electro-optical device, for example, an active matrix liquid crystal display device, mainly includes an element substrate in which switching elements are provided on each of the pixel electrodes arranged in a matrix, a color filter, and the like as necessary. And a liquid crystal filled between these two substrates. In such a configuration, when a scanning signal is applied to the switching element via the scanning line, the switching element becomes conductive. In this conductive state, when an image signal is applied to the pixel electrode via the data line, a predetermined charge is accumulated in the liquid crystal layer between the pixel electrode and the counter electrode (common electrode). Even if the switching element is turned off after the charge accumulation, if the resistance value of the liquid crystal layer is sufficiently high, the charge accumulation in the liquid crystal layer is maintained. In this way, by controlling the amount of charge to be accumulated by driving each switching element, the alignment state of the liquid crystal changes for each pixel, and predetermined information can be displayed.

  At this time, the charge can be accumulated in the liquid crystal layer of each pixel for a certain period. First, each scanning line is sequentially selected by the scanning line driving circuit, and second, the scanning line is selected. In the period, the data lines are sequentially selected by the data line driving circuit, and thirdly, the scanning lines and the data lines are made common to a plurality of pixels by sampling and supplying the image signals to the selected data lines. Time division multiplex drive becomes possible. Note that the scanning line driving circuit and the data line driving circuit are generally composed of shift register circuits, respectively, and the scanning line driving circuit performs vertical scanning based on signals transferred by these shift register circuits. The data line driving circuit is configured to perform horizontal scanning.

  By the way, in recent years, in an electro-optical device as a display device, it has been studied to display based on a received digital image signal for reasons such as the start of digital broadcasting. Here, the electro-optical device eventually converts the digital image signal into an analog image signal in relation to displaying based on the analog signal, and then supplies the analog image signal to the interface of the display panel in the electro-optical device. Can be considered.

  However, with such a configuration, after all, an analog image signal is supplied to the display panel, so that the analog image signal is deteriorated before being supplied to the display panel, and the display quality can be lowered. There is sex. Even if a D / A conversion circuit is incorporated in the display panel, there are problems such as how far a digital signal is used and how it is built.

  The present invention has been made in view of such a problem. The object of the present invention is to prevent a deterioration in display quality by incorporating a D / A conversion circuit in a display panel of an electro-optical device. To provide an electro-optical device in which the configuration of a D / A conversion circuit is defined in relation to a display panel of an electro-optical device, a drive circuit for the electro-optical device, and an electronic apparatus using the electro-optical device. is there.

  In order to achieve the above object, in the drive circuit for the electro-optical device according to the present invention, a substrate is connected to a plurality of scanning lines, a plurality of data lines, and the switching lines connected to the data lines. A driving circuit for an electro-optical device including an element and a pixel electrode connected to the switching element, the driving circuit including a D / A conversion circuit that converts a digital image signal into an analog image signal, and the D / A conversion circuit A part or all of the constituent elements are composed of elements formed using a manufacturing process common to the switching elements.

  According to the present invention, since the D / A conversion circuit is configured by an element formed by a common manufacturing process with the switching element connected to the pixel electrode, the D / A conversion circuit is formed with the pixel electrode. It becomes possible to arrange in the vicinity of the area, that is, the display area. For this reason, the state of the digital image signal is maintained and supplied until just before the display area, so that the display quality is prevented from deteriorating. In addition, since part or all of the constituent elements of the D / A conversion circuit are formed in combination with the manufacturing process of the switching element connected to the pixel electrode, the formation process of the D / A conversion circuit is complicated. Nor.

  Here, in the present invention, the switching element connected to the pixel electrode is a transistor, and at least one resistor constituting the D / A conversion circuit is made of an electrode wiring material of the transistor. Is desirable. As a resistor, a semiconductor film that forms a channel of a transistor, or a thin film in which resistance is adjusted by doping ions therein is a high-resistance resistor, which is effective. It is difficult to control. In contrast, since the electrode wiring material has a relatively large film thickness, the resistance value can be controlled more easily than when the semiconductor film is also used as a resistor. However, since the sheet resistance of the electrode wiring material is uniquely determined, the resistance is actually controlled by the width and length of the wiring material.

  In the present invention, the switching element connected to the pixel electrode is a transistor, and at least one or more switching elements constituting the D / A conversion circuit are common to the transistor connected to the pixel electrode. It is desirable that the transistor be formed using a manufacturing process. That is, in the D / A converter circuit, in addition to the resistor, a switching element for performing weighting corresponding to each bit is usually provided, but according to this, weighting is performed. Since the switching element is formed using a manufacturing process common to the transistor connected to the pixel electrode, the formation process of the switching element is not complicated.

  In addition, in the present invention, the switching element connected to the pixel electrode is a transistor, and at least one resistor constituting the D / A conversion circuit is common to the transistor connected to the pixel electrode. It is desirable to use a resistance between a source and a drain of a transistor formed by using a manufacturing process. That is, since the on-resistance in the transistor is used as a resistor of the D / A conversion circuit, a higher specific resistance than that of the wiring material can be obtained, so that the element can be downsized. Here, the resistance value can be controlled by the width of the channel. If the resistance value is increased, the resistance value decreases accordingly. In addition, since it is relatively easy to form a transistor with high accuracy in a certain region, variation in resistance value formed in the region can be suppressed.

  Furthermore, in the present invention, the switching element connected to the pixel electrode is a transistor, and at least one or more sets of switching elements and resistors constituting the D / A conversion circuit are connected to the pixel electrode. It is desirable that the transistor be formed using a common manufacturing process with the transistor and formed as one element by using a resistance between the source and drain of the transistor. That is, in the D / A conversion, the switching element and the resistor for weighting are shared by the same transistor, so that the configuration can be simplified.

  Here, the switching element constituting the D / A conversion circuit is for generating a voltage or current corresponding to the weight of each bit in the digital image signal using a reference potential or a constant current source. Is desirable. In other words, in the D / A conversion, the switching element for weighting is formed by the same manufacturing process as the transistor connected to the pixel electrode, so that the configuration can be simplified.

  On the other hand, in the present invention, a data line driving circuit that sequentially outputs a sampling signal for selecting the data line, and an analog image signal converted by the D / A conversion circuit are sampled according to the sampling signal and It is desirable to provide a sampling circuit for supplying each of the data lines. According to this, the D / A converted analog image signal is supplied to each of the data lines in accordance with the sampling signal, so that only one D / A conversion circuit is required. For this reason, the structure can be simplified as well as the display quality can be prevented from being deteriorated and the process of forming the D / A conversion circuit can be prevented from becoming complicated.

  Here, in the present invention, it is desirable that the sampling circuit has two or more stages per one data line, and the data lines are collectively written in synchronization with a horizontal scanning cycle. As a result, writing to the data lines is performed line-sequentially for each horizontal scanning period, so that display unevenness is reduced, and deterioration of a clear digital image can be prevented.

  In the present invention, in the D / A conversion circuit, the resistor for generating a current or voltage corresponding to the weight of each bit in the digital image signal, and the other resistor, It is desirable that they are formed to face each other across the sampling circuit. According to this, a resistor (ladder circuit) for generating a current or voltage corresponding to the weight of each bit and other resistors such as a resistor for current-voltage conversion and a resistor such as a pull-down resistor Since they are formed to face each other across the sampling circuit, the resistance necessary for D / A conversion is dispersed. For this reason, it is not necessary to concentrate the resistors necessary for D / A conversion, which is advantageous when the area restriction is large.

  In the present invention, the D / A conversion circuit is provided for each of the data lines, and includes a data line driving circuit that sequentially outputs a latch signal to each of the D / A conversion circuits. Each D / A conversion circuit latches the digital image signal in accordance with the latch signal, converts the latched digital image signal into an analog image signal at a predetermined timing, and supplies the analog image signal to a corresponding data line. Is desirable. According to this, a D / A conversion circuit is provided corresponding to each of the data lines, and each D / A conversion circuit latches the digital image signal, so that it is supplied in the state of the digital image signal to the vicinity of the data line. It becomes possible to do. For this reason, deterioration of display quality is further prevented. The timing at which each D / A conversion circuit supplies the analog image signal to the corresponding data line is the first case where it is simultaneously with the latch, or all D / A conversion circuits are digital in one horizontal scanning period. A second case may be considered after the image signal is latched. Here, in the first case, the analog image signal is sequentially supplied for each data line. On the other hand, in the second case, analog signals are supplied to all data lines at once.

  Further, the present invention provides a plurality of scanning lines on the substrate, a plurality of data lines, a plurality of switching elements provided corresponding to the intersections of the scanning lines and the data lines, and each of the switching elements. A drive circuit for an electro-optical device including a plurality of pixel electrodes provided, and a D / A conversion circuit that converts a digital image signal into an analog image signal, and the digital image signal is expanded on a time axis The D / A conversion circuit is provided for each of the data lines and is shifted in a staggered manner for each of the data lines corresponding to each of the systems. It is characterized by being arranged in. According to this, since the D / A conversion circuit can be arranged across a plurality of rows in a direction intersecting the data line, the data line pitch is narrow or the formation area of the D / A conversion circuit is large. Even if necessary, it can be configured relatively easily. Above all, the drive frequency on the data line side is substantially reduced to the reciprocal of the number of systems, so it is possible to cope with higher resolution without improving the performance of the elements constituting the drive circuit. It becomes.

  Further, the present invention provides a plurality of scanning lines on the substrate, a plurality of data lines, a plurality of switching elements provided corresponding to the intersections of the scanning lines and the data lines, and each of the switching elements. A drive circuit for an electro-optical device including a plurality of pixel electrodes provided, and a D / A conversion circuit that converts a digital image signal into an analog image signal, wherein the digital image signal in the D / A conversion circuit A position where a resistor for generating a current corresponding to the weight of each bit and a resistor for converting the sum of the generated currents into a voltage are opposed to each other across the formation region of the plurality of pixel electrodes And are respectively electrically connected to the data lines. According to this, a resistor (ladder circuit) for generating a current or voltage corresponding to the weight of each bit and other resistors such as a resistor for current-voltage conversion and a resistor such as a pull-down resistor Since the pixel electrodes are formed so as to face each other with the pixel electrode formation region interposed therebetween, the resistance necessary for D / A conversion is dispersed. For this reason, it is not necessary to concentrate the resistors necessary for D / A conversion, which is advantageous when the area restriction is large.

  Furthermore, in order to achieve the above object, the electro-optical device according to the present invention is driven by the above-described drive circuit of the electro-optical device according to the present invention, so that the display quality is prevented from being deteriorated and high quality is achieved. In addition, the manufacturing process can be simplified and can be easily formed.

  In addition, since the electronic apparatus according to the present invention includes the electro-optical device, it is possible to provide an electro-optical device that can be easily formed with high-quality display.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
First, an electro-optical device driven by the drive circuit according to the first embodiment of the present invention will be described. FIG. 1 is a block diagram showing an electrical configuration of a liquid crystal panel using liquid crystal as an electro-optic material. The liquid crystal panel 100 shown in this figure has a configuration in which an element substrate and a counter substrate are pasted with their electrode formation surfaces facing each other, as will be described later. Among these, in the element substrate, a plurality of scanning lines 112 are formed in parallel along the X direction in FIG. 1, and n (n is parallel to the Y direction orthogonal to the scanning line 112). , Even) data lines 114 are formed. At each intersection of the scanning line 112 and the data line 114, a gate electrode of a thin film transistor (hereinafter referred to as “TFT”) 116 is connected to the scanning line 112, while a source electrode of the TFT 116 is In addition to being connected to the data line 114, the drain electrode of the TFT 116 is connected to the pixel electrode 118. Each pixel includes a pixel electrode 118, a common electrode formed on a counter substrate, which will be described later, and a liquid crystal sandwiched between the two electrodes, and corresponds to each intersection of the scanning line 112 and the data line 114. Thus, the display area 110 is formed in a matrix. In addition, a storage capacitor (not shown) is formed for each pixel in parallel with the liquid crystal sandwiched between the pixel electrode 118 and the common electrode, but is omitted in the drawing. ing.

  The peripheral circuit 120 includes a scanning line driving circuit 130 and a data line driving circuit 140, a pulse width limiting circuit 150, a D / A conversion circuit 160, a sampling circuit 170, and the like. It is on the opposite surface and is formed in the periphery of the display area. The active elements of these circuits are formed by a combination of a TFT 116 for switching pixels and a p-channel TFT and an n-channel TFT formed by a common manufacturing process.

  Here, among the peripheral circuits 120, the scanning line driving circuit 130 includes a shift register, and the scanning signal is output based on the clock signal CLY supplied from the outside, the inverted clock signal CLYINV, the transfer start pulse DY, and the like. The data is sequentially output to each scanning line 112. Specifically, the scanning line driving circuit 130 first sequentially shifts the transfer start pulse DY supplied at the beginning of the vertical scanning period by a half cycle of the clock signal CLY and the inverted clock signal CLYINV, and secondly, These shifted signals are sequentially output as scanning signals to each scanning line 112 every horizontal scanning period.

  The data line driving circuit 140 has substantially the same configuration as the scanning line driving circuit 130, but the supplied signals are different. That is, the data line driving circuit 140 is supplied with the clock signal CLX and the inverted clock signal CLXINV instead of the clock signal CLY and the inverted clock signal CLYINV, and at the beginning of the horizontal scanning period instead of the transfer start pulse DY. The transfer start pulse DX is supplied. Therefore, first, the data line driving circuit 140 sequentially shifts the transfer start pulse DX supplied at the beginning of the horizontal scanning period by a half cycle of the clock signal CLX and the inverted clock signal CLXINV, and secondly, The shifted signals S1 ′ to Sn ′ are sequentially output. Note that detailed configurations of the scanning line driving circuit 130 and the data line driving circuit 140 will be described later using the data line driving circuit 140 as an example.

  Next, the pulse width limiting circuit 150 includes n sets of NAND circuits 152 and inverters 154 provided corresponding to the data lines 114, and the pulse widths of the signals S1 ′ to Sn ′ are respectively determined by the enable signals ENB1 and ENB2. It is limited and output as sampling signals S1 to Sn. Here, the NAND circuit 152 located at the i-th stage from the left in FIG. 1 inverts the logical product of the signal Si ′ and the signal ENB1 if i is an odd number, whereas if i is an even number, The logical product of the signal Si ′ and the signal ENB2 is inverted. Each inverter 154 inverts the output signal of the corresponding NAND circuit 152. The output signals of these inverters 154 are sequentially output as sampling signals S1, S2,..., Sn.

  On the other hand, the D / A conversion circuit 160 converts an externally supplied 8-bit digital image signal VID into an analog image signal and outputs it to the line L. The detailed configuration will be described later. .

  The sampling circuit 170 includes n TFTs 171 provided corresponding to the respective data lines 114, and analog image signals supplied to the lines L are respectively applied to the corresponding data lines 114 in accordance with the sampling signals S1 to Sn. Sampled and supplied. Specifically, each of the TFTs 171 as a switch is provided at one end of each data line 114, the source electrode of each TFT 171 is connected to a line L to which an analog image signal is supplied, and the drain electrode of each TFT 171 is Are connected to corresponding data lines 114. The gate electrodes of the TFTs 171 are connected to signal lines to which sampling signals S1 to Sn are supplied in order from the left in the drawing.

<Configuration of data line driving circuit>
Here, the configuration of the data line driving circuit 140 in FIG. 1 will be described in detail. FIG. 2 is a circuit diagram showing a configuration of the data line driving circuit 140. In this figure, a clock signal CLX, its inverted signal CLXINV, and a transfer start pulse DX are all supplied in synchronization with the digital image signal VID by a timing generator (not shown).

  As shown in FIG. 2, the data line driving circuit 140 is formed by cascading (n + 1) stages of unit circuits R1 to Rn + 1 of a shift register, that is, 1 than the number n of data lines 114. An odd number of stages are connected, and the pulse DX supplied at the beginning of the horizontal scanning period is changed from the preceding (left) unit circuit to the following (right) unit circuit according to the clock signal CLX and its inverted clock signal CLXINV. Are sequentially shifted and output as signals S1 ′ to Sn ′. Therefore, the clock signal CLX and the inverted clock signal CLXINV are supplied to the unit circuits R1 to Rn + 1, respectively.

  Among these unit circuits R1 to Rn + 1, odd-numbered unit circuits R1, R3,..., Rn−1, Rn + 1 are used when the clock signal CLX is at “H” level (the inverted clock signal CLX is at “L” level). A clocked inverter 142 that inverts the input signal, an inverter 144 that reinverts the inverted signal by the clocked inverter 142 and outputs the unit circuit, and the clock signal CLX is at the “L” level ( A clocked inverter 146 that inverts the output signal of the inverter 144 and feeds it back to the input of the inverter 144 (when the inverted clock signal CLXINV is at “H” level).

  Here, the specific configuration of the clocked inverter 142 in the odd-numbered unit circuit will be described. As shown in FIG. 3A, the gate electrode is inverted between the high power supply Vdd and the low power supply Vss. A p-channel TFT for inputting the clock signal CLXINV, a complementary p-channel TFT / n-channel TFT for inputting the input signal to the gate electrode, and an n-channel TFT for inputting the clock signal CLX to the gate electrode. The configuration is connected in series. In addition, the clocked inverter 146 in the odd-numbered stage is as shown in FIG. 3B, and the TFT to which the clock signal CLX and the inverted clock signal CLXINV are supplied is opposite to that in FIG. Yes. Further, for the inverter 144, as shown in FIG. 4, a p-channel TFT and an n-channel TFT for inputting an input signal to the gate electrode, respectively, between the high-side power supply Vdd and the low-side power supply Vss, It is configured to be connected in a complementary manner in series.

  On the other hand, among the unit circuits R1 to Rn + 1, the even-numbered unit circuits R2, R4,..., Rn-2, Rn are basically similar in configuration to the odd-numbered unit circuits, but are clocked inverters. 142 is different in that the input signal is inverted when the clock signal CLX is at “L” level, whereas the clocked inverter 146 is inverted when the clock signal CLX is at “H” level. Therefore, the clocked inverter 142 in the even stage has the configuration shown in FIG. 3B, and the clocked inverter 146 in the even stage has the configuration shown in FIG. It is in a relationship that has been replaced.

  In FIG. 2, only the clock signal CLX is supplied to each of the odd-numbered clocked inverters 142 and the even-numbered clocked inverters 146, but in reality, as shown in FIG. A clock signal CLXINV is also supplied. Similarly, in FIG. 2, only the inverted clock signal CLXINV is supplied to the odd-numbered clocked inverter 146 and the even-numbered clocked inverter 142, but actually, as shown in FIG. The clock signal CLX is also supplied. Further, since these clocked inverters and inverters are connected between the high-order power supply Vdd and the low-order power supply Vss, these power supply wirings are routed in the unit circuits R1 to Rn + 1.

<D / A conversion circuit>
Next, the detailed configuration of the D / A conversion circuit 160 in FIG. 1 will be described. FIG. 5 is a diagram showing an equivalent circuit of the D / A conversion circuit 160.

  As shown in this figure, the D / A conversion circuit 160 performs D / A conversion using a so-called R-2R ladder circuit, and each bit (the most significant bit) of the digital image signal VID. , MSB, 2SB, 3SB,..., 7SB, and the least significant bit is LSB). Each of the switches Sw1 to Sw8 is connected to the terminal a when the corresponding bit is “1”, and is connected to the terminal b when the corresponding bit is “0”. Here, for convenience of explanation, it is assumed that the switch is on when connected to the terminal a, and the switch is off when connected to the terminal b. The terminals a of the switches Sw1 to Sw8 are connected to signal lines to which the reference potential Vref is supplied, respectively, while the terminals b are connected to the reference potential.

  Further, the common terminals of the switches Sw1 to Sw8 are connected to the connection points A to H through resistors having a resistance value of 2R, respectively. Further, at each of the connection points A to H, the connection points adjacent to each other are connected via a resistor having a resistance value of R. Therefore, in a ladder circuit composed of a resistor having a resistance value of 2R and a resistor having a resistance value of R, the upper bit direction, the lower bit direction, and the switch direction from each of the connection points A to H of the resistors. In any case, the resistance value is 2R. The connection point A is connected to the line L and serves as the output terminal Eout of the D / A conversion circuit 160.

  In such a configuration, when a switch corresponding to an input bit of “1” is turned on, a voltage corresponding to the weight of each bit is output to the output terminal Eout. For example, if the most significant bit MSB is “1”, the switch Sw1 is turned on, so that the voltage of Vref / 2 is set, and if the 3SB lower by 2 bits is “1”, the switch Sw3 is set. By turning on, a voltage of Vref / 8 is generated at Eout.

  Next, actual components in the D / A conversion circuit 160 will be described. As already described with reference to FIG. 5, the D / A conversion circuit 160 includes the switches Sw <b> 1 to Sw <b> 8 and the resistance of the ladder circuit. Of these, in the present embodiment, the resistance is mainly composed of polysilicon as a gate electrode wiring material in the TFT [1], and the resistance between the source and drain in the TFT is used [2]. Are assumed.

  First, the case [1] in which the resistance component is formed from polysilicon will be described. Here, a portion 1600 indicated by a broken line in FIG. 5, that is, a portion 1600 including a switch Sw1 and a resistor having a resistance value of 2R is considered. When the resistance component is formed of polysilicon, as shown in FIG. 6A, the most significant bit MSB signal of the digital image signal VID is input as a gate signal for the portion 1600 and the portions 1600 are mutually exclusive. And n-channel TFT 1601 and p-channel TFT 1602 that are turned on and off, and a resistor 1603 made of polysilicon as a gate electrode wiring material.

  Here, as the resistor, the semiconductor film of the TFT is a high resistor, so that it may be used. However, since the film thickness is thin, it is difficult to control the resistance value. On the other hand, since the gate electrode wiring material has a relatively large thickness, it is easier to control the resistance than when the semiconductor film itself is used as a resistor. However, since the film thickness of the gate electrode wiring material is uniquely determined by the TFT to be formed, the resistance is actually controlled by the width and length of the wiring material.

  The on-resistances of the TFTs 1601 and 1602 are desirably sufficiently lower than the resistance 1603, but the resistance values between these sources and drains are often not negligible. Therefore, the TFTs 1601 and 1602 and the resistor 1603 are formed so that the series resistance value of the resistance between the source and the drain when the TFT 1601 or 1602 is turned on and the resistor 1603 made of polysilicon is 2R. That is, the switching function of the switch Sw1 in the portion 1600 is handled by the TFTs 1601 and 1602, and the function of the resistance having a resistance value of 2R is the series resistance of the resistance between the source and drain of the TFT and the resistance 1603. It bears. The portion 1600 is similarly formed corresponding to the bits other than the most significant bit MSB. In addition, at each of the connection points A to H, a resistance connecting between adjacent connection points may be formed of polysilicon so that the resistance value is R, or the channel of the TFTs 1601 and 1602 A dummy TFT having a half width compared to the width may be formed so that the resistance value between the source and drain becomes R. Note that the terminals a, b, c, and d in FIG. 6A correspond to the terminals having the same reference numerals in FIG.

  On the other hand, the case of using the resistance between the source and drain in the TFT [2] will be described. Here, as in the case of forming the resistance component from polysilicon [1], in FIG. 5, a portion 1600 composed of the switch Sw1 and a resistance having a resistance value of 2R will be considered. When the resistance is formed by using the resistance between the source and drain of the TFT, as shown in FIG. 6B, for the portion 1600, the signal of the most significant bit MSB is inputted as a gate signal and mutually exclusive. The p-channel TFT 1607 and the n-channel TFT 1608 that are turned on and off simultaneously perform the switching function of the switch Sw1 in the portion 1600 and the function of the resistance having a resistance value of 2R. That is, when the TFT 1607 (1608) is turned on, the resistance between the source and the drain is positively used as the resistance in the ladder circuit so as to be 2R. The portion 1600 is similarly formed corresponding to the bits other than the most significant bit MSB. In addition, at each of the connection points A to H, a dummy TFT is provided for the resistance connecting between adjacent connection points, and the resistance value between the source and the drain is set to R.

  When formed in this manner, the on-resistance of the TFT, which is a switch, does not need to be low, so that the channel width can be reduced and a resistor is not formed, so that the circuit size can be greatly reduced. It should be noted that the variation in resistance value in the ladder resistor directly affects the accuracy of the D / A conversion, so that it is necessary to devise in patterning. This is effective in the case of / A conversion or when the D / A conversion circuit is integrated in a narrow area. Note that the terminals a, b, c, and d in FIG. 6B correspond to the terminals having the same symbols in FIG.

  In addition, the n-channel TFT 1602 in FIG. 6A and the n-channel TFT 1608 in FIG. 6B can be combined with an exclusive switch such as a depletion type and an enhancement type, and the corresponding bit signal Is inverted by an inverter and input as a gate signal, an n-channel TFT can be used, and conversely, a p-channel TFT can be used. Further, by replacing the n-channel and p-channel TFTs with transmission gates connected in parallel and inverting the reference potential positively and negatively with respect to the reference potential, inversion driving can be supported.

<Manufacturing process [1]>
Next, the manufacturing process of the constituent elements in the peripheral circuit 120 and the display area 110 will be described. As described above, the resistance in the D / A conversion circuit 160 in the peripheral circuit 120 is the resistance between the source and the drain of the TFT when formed using polysilicon and TFT (see FIG. 6A). There are two possible cases: a case where the film is formed using only (see FIG. 6B). First, the case where the former is formed using polysilicon and TFT will be described. The following process is based on the TFT 116 in the display region 110, that is, the TFT 116 connected to the pixel electrode 118. The peripheral circuit 120 will be described by taking the series part of the TFT 1602 and the resistor 1603 in FIG. 6A as an example, but other than the resistor 1603, that is, the data line driving circuit 140 and the sampling circuit 170 are configured. The TFT is basically formed in the same manner as the TFT 1602.

First, as shown in step (1) of FIG. 7, the polysilicon layer 1 is preferably deposited on the entire upper surface of the substrate 101 such as glass or quartz by a low-pressure CVD method or the like with a thickness of about 50 to 200 nm. Is solid-phase grown to a thickness of about 100 nm. At this time, when an n-channel TFT is formed, a dopant of a group V element such as Sb (antimony), As (arsenic), or P (phosphorus) is slightly doped by ion implantation or the like. When a p-channel TFT is formed, a dopant of a group III element such as Al (aluminum), B (boron), and Ga (gallium) is similarly doped slightly by ion implantation or the like.
Next, as shown in step (2) of FIG. 7, the polysilicon layer 1 is patterned by a photolithography process, an etching process, or the like, and in the display region 110, the active layer 1a in the TFT 116 is replaced with a peripheral circuit. In 120, the active layer 1b in the TFT 1601 or the like is formed in an island shape.

  Further, as shown in step (3) of FIG. 7, the surfaces of the active layers 1a and 1b are thermally oxidized to form gate insulating films 2a and 2b on the surfaces of the active layers 1a and 1b, respectively. By this step, the active layers 1a and 1b finally have a thickness of about 30 to 150 nm, preferably about 35 to 45 nm, while the gate insulating films 2a and 2b have a thickness of about 60 to 150 nm, preferably The thickness is about 30 nm.

  Then, as shown in step (4) in FIG. 7, a polysilicon layer 12 is deposited on the upper surfaces of the gate insulating films 2a and 2b and the substrate 101 by a low pressure CVD method or the like. The polysilicon layer 12 is a portion to be a scanning line that also serves as the gate electrode of the TFT 116 in the display region 110, and in the peripheral circuit 120, the gate electrode in various TFTs such as the TFT 1601, and This is the part that should become the resistor 1603. Note that the portion to be the scanning line 112 may be formed from a metal film such as Al or a metal silicide film instead of polysilicon, or a multilayer of these metal films or metal silicide films and polysilicon may be formed. May be. As the wiring material for the gate electrode, in addition to polysilicon, refractory metals such as Mo (molybdenum), Ta (tantalum), Ti (titanium), W (tungsten), and metal silicides thereof can be used. However, it should be noted that it is difficult to increase the resistance if a low-resistance material is used as far as the portion to be the resistance 1603 is concerned.

Next, as shown in step (5) of FIG. 8, the polysilicon layer 12 is patterned by a photolithography process, an etching process, or the like, and in the display region 110, scanning that also serves as the gate electrode of the TFT 116. A line 112 is formed, and in the peripheral circuit 120, a gate electrode 12b of the TFT 1601 and a resistor 1603 are formed. Note that the gate electrode 12b corresponds to the terminal d in FIG. At this time, in the peripheral circuit 120, gate electrodes in TFTs other than the TFT 1601 are formed in the same manner.
Further, as shown in step (6) of FIG. 8, an impurity (for example, phosphorus) dopant is doped using the scanning line 112 (gate electrode) and the gate electrode 12b as a mask to make the active layer 1a of the n-channel TFT. In 1b, semiconductor regions to be self-aligned source and drain regions are formed. When the TFT is a p-channel type, a dopant of a group III element such as B is doped to form a source region and a drain region in the active layer 1b.

In the source / drain region, first, a dopant is light-doped with a dose of 1 × 10 ^{13 to} 3 × 10 ¹³ [atms / cm ² ] to form a low concentration region, and secondly A mask layer wider than the scanning line 112 (gate electrode) or the gate electrode 12b is formed on the scanning line 112 and the gate electrode 12b, and thirdly, the same dopant is 1 × 10 ^{15 to} 3 × 10 ^15. A high concentration region may be formed by doping at a dose of [atms / cm ² ], and thereby the masked region may be formed to be a TFT having a lightly doped drain (LDD) structure. . Further, a pattern is formed by using a mask wider than the scanning line 112 and the gate electrode 12b without lightly doping, and then the source and drain are formed by doping impurities, and then the gate electrode is overlaid. An TFT having an offset structure may be formed by etching.

  Subsequently, as shown in step (7) of FIG. 8, the interlayer insulating film 3 is deposited to a thickness of about 500 to 1500 nm by, for example, a CVD method so as to cover the scanning line 112, the gate electrode 12b, and the like. To do. Examples of the material of the interlayer insulating film 3 include silicate glass films such as NSG, PSG, BSG, and BPSG, silicon nitride films, and silicon oxide films.

  Then, as shown in step (8) of FIG. 8, in the display region 110, a contact hole 41 is formed in the position corresponding to the source region of the TFT 116 with respect to the interlayer insulating film 3 by dry etching or the like. To do. On the other hand, in the peripheral circuit 120, contact holes 42, 43, 44, 45 for connecting to the drain region, the source region, and the resistor 1603 of the TFT 1601 are similarly formed in the interlayer insulating film 3. The contact holes 41, 42, and 43 are used to open an overlap film of the interlayer insulating film 3 and the gate insulating film 2a or 2b.

  Next, as shown in step (9) of FIG. 9, a conductive layer 14 of a low resistance metal such as aluminum or a metal silicide is formed on the interlayer insulating film 3 by a sputtering process or the like to a thickness of about 100 to 500 nm. Sedimentation. The conductive layer 14 is a portion to be the data line 114 that also serves as the source electrode of the TFT 116 in the display region 110, and the source electrode and drain electrode of the TFT including the TFT 1601 in the peripheral circuit 120. , A portion to be a wiring portion for connecting the resistor 1603 and the like.

  Further, as shown in step (10) of FIG. 9, the conductive layer 14 is patterned by a photolithography process, an etching process, or the like, and in the display region 110, the data line 114 that also serves as the source electrode of the TFT 116. Form. Further, by patterning the conductive layer 14, in the peripheral circuit 120, the source electrode a ′ of the TFT 1601, the connection wiring e ′ between the drain electrode of the TFT 1601 and one terminal of the resistor 1603, and the other terminal of the resistor 1603. Various wirings such as a lead-out wiring c ′ are formed. In FIG. 9 (10), the source electrode a ′ of the TFT 1601 corresponds to the terminal a in FIG. 6A, and the connection wiring e ′ of the drain electrode of the TFT 1601 is shown in FIG. ) And the lead-out line c ′ corresponds to the terminal c in FIG. 6A.

  Subsequently, as shown in step (11) of FIG. 9, the insulating film 5 is covered with the data line 114, the wirings a ′, e ′, c ′, etc. by, for example, about 500 to 1500 nm by the CVD method or the like. To a thickness of. As the material of the insulating film 5, similarly to the interlayer insulating film 3, silicate glass films such as NSG, PSG, BSG, and BPSG, silicon nitride films, and silicon oxide films are exemplified.

  Next, as shown in step (12) in FIG. 9, a contact hole 61 is formed in the insulating film 5 in the display region 110 at a position corresponding to the drain region of the TFT 116 by dry etching or the like.

  Then, as shown in step (13) of FIG. 10, a transparent conductive thin film 18 such as ITO is deposited on the upper surface of the insulating film 5 to a thickness of about 50 to 200 nm by sputtering or the like. As shown in (14), the pixel electrode 118 is formed by patterning through a photolithography process, an etching process, or the like. When the liquid crystal panel 100 is of a reflective type, the pixel electrode 118 is formed from an opaque conductive thin film having a high reflectance such as aluminum instead of the transparent conductive thin film 18.

Through the steps (1) to (14), the components of the peripheral circuit 120, particularly the switches of the D / A conversion circuit 160 and various resistors, switch the pixels using the manufacturing process of the TFT 116 in the display region 110. The TFT 116 is formed at the same time.
Note that when light enters the TFT, the performance deteriorates due to leakage, so the light shielding layer is actually formed in accordance with the shape of the TFT, but it is omitted in the figure because it is not directly related to the present invention. Shall.

<Manufacturing process [2]>
Next, a manufacturing process in the case where the resistance in the D / A conversion circuit 160 in the peripheral circuit 120 is formed using only the resistance between the source and drain of the TFT (see FIG. 6B) will be described. Here, as the peripheral circuit 120, the TFT 1607 in the portion 1600 in FIG. 6B will be described as an example. The manufacturing process thereof is from step (1) in FIG. 11 to step (14) in FIG. As shown. However, these steps are the same as the steps (1) in FIG. 7 to the step (14) in FIG. 10 excluding the resistor 1603 made of polysilicon, and therefore detailed description thereof will be omitted. .

  Through these steps (1) to (14), using the manufacturing process of the TFT 116 in the display region 110, the components of the peripheral circuit 120, in particular, the switches and various resistors of the D / A conversion circuit 160, The TFTs 116 to be switched are simultaneously formed by a common process. The resistance between the source and the drain is controlled by the channel width, channel length, LDD length, etc. of the TFT. Specifically, the higher the resistance, the narrower the channel width, the longer the channel length, or the LDD length. It needs to be long.

<Operation of First Embodiment>
Next, the operation of the liquid crystal panel according to the first embodiment will be described with reference to the timing chart shown in FIG.

  First, at timing t11, when the pulse DX is input at the beginning of the horizontal scanning period and the clock signal CLX rises (when the inverted clock signal CLXINV falls), the data line driving circuit 140 uses the first stage unit. The clocked inverter 142 in the circuit R1 inverts the “H” level of the transfer start pulse DX. Similarly, the inverter 144 in the first stage unit circuit R1 inverts the inversion result of the clocked inverter 142. The output signal S1 ′ from the unit circuit R1 at the first stage becomes “H” level.

  Next, when the clock signal CLX falls (when the inverted clock signal CLXINV rises) during the period when the transfer start pulse DX is input at the timing t12, the clocked inverter 146 in the unit circuit R1 in the first stage , The output signal S1 ′ at “H” level is inverted and fed back to the inverter 144, so that the output signal S1 ′ maintains the “H” level. The clocked inverter 142 in the second-stage unit circuit R2 inverts the “H” level of the output signal S1 ′ from the first-stage unit circuit R1, and similarly the inverter in the second-stage unit circuit R2. 144 inverts the inversion result of the clocked inverter 142, so that the output signal S2 ′ of the second-stage unit circuit R2 becomes “H” level.

  At time t13, when the input of the transfer start pulse DX ends and the clock signal CLX rises again (when the inverted clock signal CLXINV falls), the clocked inverter 142 in the first stage unit circuit R1 Since the “L” level of the transfer start pulse DX is captured, the output signal S1 ′ of the unit circuit R1 becomes the “L” level. On the other hand, the clocked inverter 146 in the second-stage unit circuit R2 inverts and feeds back the “H” level output signal S2 ′ to the inverter 144, so that the output signal S2 ′ maintains the “H” level. . Also, the clocked inverter 142 in the third stage unit circuit R3 inverts the “H” level of the output signal S2 ′ from the second stage unit circuit R2, and similarly the inverter of the second stage unit circuit R2. 144 inverts the inversion result of the clocked inverter 142, so that the output signal S3 ′ from the unit circuit R3 at the third stage becomes the “H” level.

  Thereafter, as a result of repeating the same operation, the first input transfer start pulse DX is sequentially shifted by a half cycle of the clock signal CLX and its inverted clock signal CLXINV, and the output signal S1 from the unit circuits R1 to Rn of each stage. It will be output as '˜Sn'.

  Among such signals S1 ′ to Sn ′, the output signal from the odd-numbered unit circuit has the pulse width of the signal ENB1, and the output signal from the even-numbered unit circuit has the pulse width of the signal ENB2. After being limited by the NAND circuit 152 at each stage, it is re-inverted by the inverter 154 at each stage and output as sampling signals S1 to Sn. For this reason, the sampling signals S1 to Sn are output without the signals adjacent to each other being simultaneously at the “H” level.

  On the other hand, the scanning line driving circuit 130 has the same configuration as that of the data line driving circuit 140 and thus operates in the same manner. However, since the supplied signals are different, the horizontal scanning period is changed from top to bottom in the figure. The scanning signal is supplied to each scanning line 112 in the direction.

  Here, when the sampling signal S1 is output in a period in which a certain one scanning line 112 is selected, the analog image signal converted at that time, that is, the digital image signal is converted by the D / A conversion circuit 160. The analog image signal which is D / A converted from VID and supplied to the line L is sampled with respect to the data line corresponding to the sampling signal S1, and a pixel intersecting the currently selected scanning line is applied to the pixel by the TFT 116. Will be written.

  Thereafter, when the sampling signal S2 is output, this time, the analog image signal is sampled on the next data line 114 and written to the pixel intersecting with the scanning line selected at that time by the TFT 116. Become.

  Similarly, when the sampling signals S3, S4,..., Sn are sequentially output, the analog image signals are sampled on the data lines 114 belonging to the respective sampling signals, and intersect with the scanning line selected at that time. Will be written to the pixel. Thereafter, the next scanning line is selected, the sampling signals S1 to Sn are sequentially output again, and similar writing is repeatedly executed.

  Note that the signals S1 ′ to Sn ′ are limited to the pulse widths of the signals ENB1 and ENB2 because the adjacent sampling signals are output at the same time and the TFTs 171 as the switches corresponding to the adjacent data lines 114 are simultaneously turned on. This is to prevent the analog image signal supplied to the line L from being sampled at an overlapping timing between the adjacent data lines 114. Therefore, if the sampling signals S1 to Sn that are adjacent to each other are not substantially overlapped by setting the frequency of the clock signal CLX and its inverted clock signal CLXINV to be low, in the subsequent stage of the data line driving circuit 140. The pulse width limiting circuit 150 for narrowing the pulse width can be omitted. The same applies to the scanning line driving circuit 130.

  As described above, according to the first embodiment, in the case where the resistance component is mainly formed of polysilicon for wiring [1], the D / A conversion circuit 160 is manufactured in common with the TFT 116 in the display region 110. Therefore, the D / A conversion circuit 160 can be disposed in the vicinity of the display area 110. For this reason, since the image signal is inputted digitally and the state of the digital image signal is maintained until just before the display area, it is possible to prevent the display quality from being deteriorated and suppress the variation of the resistance value. It is also possible to improve the accuracy of / A conversion. Further, in the case of using the resistance between the source and drain of the TFT as the resistance [2], it is possible to prevent the display quality from being deteriorated, as in the case where the resistance is formed from polysilicon. It is possible to increase the density by downsizing the element. Further, in any of the above cases [1] and [2], the constituent elements in the D / A conversion circuit 160 are formed by the same manufacturing process as the TFT 116 in the display region 110. There is no need for a separate process for formation.

<Other examples of D / A conversion circuit>
The D / A conversion circuit 160 described above is configured to divide the reference potential Vref corresponding to the weight of each bit in the digital image signal VID. However, the present invention is not limited to this, and various methods are used. The present invention can be applied to the D / A conversion circuit.

  For example, as in the D / A conversion circuit 162 shown in FIG. 16, the reference constant current Iref is divided and added corresponding to the weight of each bit in the digital image signal VID. May be. In such a configuration, since a current obtained by adding the weight of each bit in the digital image signal VID to the output line L flows in the line L, it is necessary to convert this into a voltage to be an analog image signal. Normally, such current-voltage conversion can be easily configured by using an operational amplifier, but it is generally difficult to configure a highly accurate operational amplifier only by TFTs. For this reason, the line L is provided with a reference resistor Rref that pulls down to the reference potential instead of the operational amplifier, whereby the current flowing through the line L is converted into a voltage. Here, since it is not necessary to provide the reference resistor Rref in the vicinity of the ladder circuit of the D / A conversion circuit 162, the reference resistor Rref is formed at a position facing the sandwiching region of the sampling circuit 170 as shown in FIG. Is desirable. As described above, when the resistance between the source and drain of a TFT is increased, the size of the TFT increases. However, if the reference resistor Rref is formed at a distance from the resistance of the ladder circuit, the resistance can be dispersed accordingly. This is particularly effective when space is limited or when heat generation is a problem. For the same reason, the constant current source may be provided on the Rref side instead of the D / A conversion circuit 162 side.

Even in the voltage division type D / A converter circuit 160 as shown in FIG. 5, in order to prevent the potential of the line L from becoming unstable, the reference resistor Rref as shown in FIG. The line L may be pulled down to the reference potential. Also in this configuration, it is needless to say that the reference resistor Vref is preferably formed at a distance from the ladder circuit resistor.
In the D / A conversion circuit, in addition to the configuration using the R-2R resistance ladder, the digital image signal VID is the m-th counted from the most significant bit MSB (m is in the present embodiment). 1, 2, 3,..., 8) are input via a resistor having a resistance of 2 (m−1) R, and then the signals of each bit are added, that is, The present invention may be applied to a so-called n-bit weighting resistance type configuration. However, since the required resistance value increases exponentially as the digital image signal becomes multi-bit, a large area is required. Therefore, it can be said that the configuration using the R-2R ladder circuit described above is preferable.

Furthermore, in the D / A converter circuit, a configuration using a switched capacitor instead of a resistor, that is, combining a switch and a capacitor, and turning on and off the switch, the capacitor becomes an apparent resistor. You may apply to the structure which replaces.
In addition, although the digital image signal VID described above is 8 bits, this is merely for convenience of explanation and is not limited to this. When the digital image signal VID is set to 8 bits as in the embodiment and color display is performed corresponding to the three primary colors of RGB, 8 bits correspond to one primary color. 24 bits corresponding results, it is possible to color display 16.7 million colors (more precisely, ^{2 24} colors).

<Polarity reversal>
By the way, in an electro-optical device, when a direct current is applied to an electro-optical material such as a liquid crystal, the electro-optical material is deteriorated. Therefore, an AC driving method in which positive polarity driving and negative polarity driving are alternately performed is common. is there. Further, in order to prevent flicker, luminance unevenness, crosstalk, and the like, data signals are applied by [1] polarity inversion for each scanning line, [2] polarity inversion for each data unit, [3] Measures such as polarity inversion for each pixel are taken. For these reasons, it is necessary to invert the polarity of the analog image signal supplied to the data line 114 in accordance with any one of [1], [2], and [3].

  When polarity inversion is performed in this way, in the D / A conversion circuit 160 shown in FIG. 5, the reference potential is set to + Vref during positive polarity driving and the reference potential is set to −Vref during negative polarity driving. It may be configured to supply as. On the other hand, in the D / A conversion circuit 162 shown in FIG. 16, a reference constant current is supplied as + Iref during positive polarity driving, and a reference constant current is supplied as -Iref during negative polarity driving. Just do it. Note that the polarity inversion here refers to alternately inverting the voltage level or current direction with the amplitude center potential of the analog image signal as the reference potential, as described above.

  Further, it is of course possible to adopt a configuration in which one bit of the digital image signal VID is assigned as polarity information instead of inverting the reference potential Vref or the reference constant current Iref. However, with this configuration, the number of gradations is substantially reduced by 1 bit.

<Configuration example of liquid crystal panel>
Next, the overall configuration of the liquid crystal panel 100 according to the electrical configuration described above will be described with reference to FIGS. 17 and 18. Here, FIG. 17 is a perspective view showing a configuration of the liquid crystal panel 100, and FIG. 18 is a cross-sectional view taken along the line AA ′ in FIG.

  As shown in these drawings, in the liquid crystal panel 100, a spacer 103 is mixed between an element substrate 101 on which pixel electrodes 118 and the like are formed and a transparent counter substrate 102 such as glass on which a common electrode 108 and the like are formed. The sealing material 104 is bonded so that the electrode forming surfaces face each other while maintaining a certain gap, and a liquid crystal 105 as an electro-optic material is sealed in the gap. Note that the sealant 104 is formed along the periphery of the counter substrate 102, but a part thereof is opened to enclose the liquid crystal 105. Therefore, after the liquid crystal 105 is injected, the opening is sealed with the sealing material 106.

  Here, the data line driving circuit 140, the pulse width limiting circuit 150, and the sampling circuit 170 described above are formed on the opposite surface of the element substrate 101 and on the outer side of the sealing material 104, and extend in the Y direction. The data line 114 is driven. Further, a plurality of connection electrodes 107 are formed on this side, and the various timing signals described above, the digital image signal VID, and the like are input. In addition, two scanning line driving circuits 130 and a D / A conversion circuit 160 are formed on two sides adjacent to the one side, and the scanning line 112 and the line L extending in the X direction are driven from both sides. It is the composition to do. Note that if the delay of the scanning signal supplied to the scanning line 112 and the delay of the analog image signal supplied to the line L are not a problem, the scanning line driving circuit 130 and the D / A conversion circuit 160 are arranged on one side of one side. The structure formed in only one may be sufficient. Further, if the ladder circuit of the D / A conversion circuit 160 is provided on one side on one side, for example, at the position indicated by * 3 in FIG. 17 or FIG. 18, it is indicated by * 4 (see FIG. 18) facing this. The reference resistor Rref is provided at the position where the signal is to be transmitted. In addition, in the element substrate 101, in order to reduce the writing load of the image signal to the data line 114, each data line 114 is precharged to a predetermined potential at a timing preceding the supply of the analog image signal. A circuit may be formed.

  On the other hand, the common electrode 108 of the counter substrate 102 is electrically connected to the element substrate 101 by a conductive material provided in at least one of the four corners of the bonding portion with the element substrate 101. In addition, the counter substrate 102 is provided with color filters arranged in a stripe shape, a mosaic shape, a triangle shape, or the like according to the use of the liquid crystal panel 100, and secondly, for example, chromium. A metal material such as aluminum or aluminum, or a black matrix such as resin black in which carbon or the like is dispersed in a photoresist, is provided, and third, a transparent conductive film is provided. In the case of color light modulation, a black matrix and a transparent conductive film are provided on the counter substrate 102 without forming a color filter. Furthermore, when improving the light utilization efficiency, microlenses corresponding to each pixel are arranged in an array.

In addition, the opposing surfaces of the element substrate 101 and the counter substrate 102 are each provided with an alignment film that has been subjected to a predetermined alignment process, and a polarizer (not shown) corresponding to the alignment direction is provided on each back side thereof. Provided. However, if the polymer dispersion type liquid crystal dispersed as fine particles in the polymer is used as the liquid crystal 105, the alignment film, the polarizer and the like described above are not necessary, so that the light use efficiency is increased, resulting in higher luminance. This is advantageous in terms of reducing power consumption.
Instead of forming part or all of the peripheral circuit 120 on the element substrate 101, for example, a driving IC chip mounted on a film by using a TAB (Tape Automated Bonding) technique is used. The driving IC chip itself may be connected to a predetermined position of the element substrate 101 using COG (Chip On Grass) technology. It is good also as a structure electrically and mechanically connected through an anisotropic conductive film.

<Modification of First Embodiment>
Here, a modification of the above-described first embodiment will be described with reference to FIG. FIG. 19 is a block diagram showing an overall configuration of a liquid crystal panel according to this modification. In the first embodiment shown in FIG. 1, the analog image signal converted by the D / A conversion circuit 160 is sampled by the TFTs 171 of the sampling circuit 170 according to the sampling signals S <b> 1 to Sn, and is applied to the data lines 114. In this modification, as shown in FIG. 19, the first latch circuit 181 and the second latch circuit 182 latch the data and supply the data lines 114. ing.

Here, the first latch circuit 181 sequentially latches the analog image signal by the D / A conversion circuit 160 in accordance with the sampling signals S1 to Sn output by the data line driving circuit 140, and the second The latch circuit 182 supplies each analog image signal latched in the first latch circuit 181 to the data lines 114 all at once according to the latch signal LP output in the horizontal blanking period.
In this configuration, the analog image signals sequentially latched by the first latch circuit 181 are supplied to all the data lines 114 at the same time and written to the pixels intersecting with the selected scanning lines 112, so that the clock signals CLX and Display unevenness caused by the duty ratio of the inverted clock signal CLXINV is reduced. For this reason, it is possible to prevent the sharp image by the digital image signal from being deteriorated to some extent.

  Note that the latch signal LP need not be supplied during the horizontal blanking period, and may be a signal that is synchronized with the horizontal scanning. In addition, a configuration in which three or more latch circuits are further provided for one data line 114 may be employed.

(Second Embodiment)
In the first embodiment described above, the digital image signal VID is converted into an analog image signal by the D / A conversion circuit 160 formed in the liquid crystal panel 100 and supplied to the line L. However, the line L Is easily affected by these capacitive couplings because it intersects the signal lines to which the sampling signals S1 to Sn are supplied. For this reason, in the first embodiment, although the digital image signal VID is directly input, there is a problem that the converted analog image signal is deteriorated and the display quality is deteriorated. .

  Therefore, a second embodiment that solves this problem will be described. FIG. 20 is a block diagram showing an electrical configuration of a liquid crystal panel to which the drive circuit according to the second embodiment is applied. The liquid crystal panel shown in this figure is different from the liquid crystal panel of the first embodiment (see FIG. 1) in that the pulse width limiting circuit 150 and the sampling circuit 170 are eliminated, and the D / A conversion circuit 162 This is in the point provided corresponding to the data line 162. Since the other points are the same as those of the liquid crystal panel shown in FIG.

  Here, the D / A conversion circuit 162 will be described taking the D / A conversion circuit 162 corresponding to the data line 114 at the i-th stage (i = 1, 2, 3,..., N) from the left in FIG. 20 as an example. To do. FIG. 21 is a diagram showing an equivalent circuit of the D / A conversion circuit 162. The D / A conversion circuit 162 shown in this figure has D / A conversion shown in FIG. 5 in that it has switches Sw1 to Sw8 corresponding to each bit and a ladder circuit having resistance values R and 2R. Although it is common to the circuit 160, it is shown in FIG. 5 in that it further includes a switch / control unit 1620 that controls switching of each of the switches Sw1 to Sw8 and that the output terminal Eout is directly connected to the data line 114. This is different from the D / A conversion circuit 160.

  Here, the switch control unit 1620 latches each bit signal of the digital image signal VID at the falling edge of the signal Si ′ output from the corresponding unit circuit Ri in the data line driving circuit 140, and latches the latch. The switches Sw1 to Sw8 are turned on / off according to each bit signal.

  The D / A conversion circuit 162 is a voltage division type in the example shown in FIG. 21, but a current addition type as shown in FIG. 22 may be used. However, as in the example shown in FIG. 16, a reference resistor Rref is provided for converting a current obtained by adding corresponding to the weight of each bit in the digital image signal VID into a voltage. The reference resistance Rref is provided at a position facing the display area 110 from the viewpoint of dispersing the resistance. That is, if the ladder circuit of the D / A conversion circuit 160 is provided at a position indicated by * 3 in FIG. 18, for example, the reference resistor Rref is provided at a position indicated by * 4 opposite to the ladder circuit. . Here, if the reference resistance Vref is formed by the resistance between the source and drain in the TFT, the TFT can be switched if the source of the TFT can be switched to a signal line that supplies a precharge signal. It can also be used as a switch for the precharge circuit, which contributes to simplification of the configuration.

  Next, the operation of the liquid crystal panel according to the second embodiment will be described with reference to the timing chart shown in FIG. As already described in the first embodiment, from the unit circuits R1 to Rn in the data line driving circuit 140, the signal S1 ′ to which the transfer start pulse DX is sequentially shifted by the half cycle of the clock signal CLX and its inverted clock signal CLXINV. Sn 'is output.

  Here, at the falling timing t13 of the signal S1 ', the first-stage D / A conversion circuit 162 latches the digital image signal VID. As a result, the analog image signal converted corresponding to the weight of each latched bit signal is supplied to the first-stage data line 114, and the pixel crossing the currently selected scan line is It is written by the TFT 116.

  Next, at the falling timing t14 of the signal S2 ', the second-stage D / A conversion circuit 162 latches the digital image signal VID. As a result, the analog image signal converted corresponding to the weight of each latched bit signal is supplied to the second-stage data line 114, and the pixel crossing the currently selected scan line is It is written by the TFT 116.

  Similarly, at the falling timing of the signals S3 ′, S4 ′,..., Sn ′, the D / A conversion circuit 162 to which the signals are supplied latches the digital image signal VID, thereby latching. The analog image signal converted in accordance with the weight of each bit signal is supplied to the corresponding data line 114 and sequentially written by the TFT 116 in the pixel intersecting with the currently selected scanning line. Become.

  As described above, according to the second embodiment, the digital image signal VID is supplied to the D / A conversion circuit 162 provided corresponding to each of the data lines 114, so that the conversion is performed as in the first embodiment. It is possible to further reduce the possibility that the later analog image signal will deteriorate.

  By the way, in the second embodiment, when one of the scanning lines 112 is selected, each of the D / A conversion circuits 162 is sequentially digitalized at each falling timing of the signals S1 ′ to Sn ′. Although the image signal VID is latched and the analog image signal is supplied to the corresponding data line 114 each time, the present invention is not limited to this. For example, if each of the D / A conversion circuits 162 latches the digital image signal VID after each of the D / A conversion circuits 162 sequentially latches the digital image signal VID, the analog image signal is converted into all data. A configuration may be used in which the lines 114 are supplied collectively. That is, instead of the dot sequential driving method as in the embodiment, a line sequential driving method may be used.

(Third embodiment)
In the second embodiment described above, the D / A conversion circuit 162 is simply provided corresponding to each of the data lines 114, but in order to form one D / A conversion circuit 162, Since it is necessary to form a large number of resistors constituting the ladder circuit, a relatively large area is required. Therefore, as in the second embodiment, the D / A conversion circuits 162 corresponding to each of the data lines 114 are arranged in a line in a direction intersecting the signal lines to which the signals S1 ′ to Sn ′ are supplied. This configuration is disadvantageous when the pitch of the data lines 114 is narrow or when the substrate area is largely limited.

  Therefore, a third embodiment that solves this problem will be described. FIG. 24 is a block diagram showing an electrical configuration of a liquid crystal panel to which the drive circuit according to the third embodiment is applied. The liquid crystal panel shown in this figure is different from the liquid crystal panel of the second embodiment (see FIG. 20) in that the D / A conversion circuit 162 is alternately arranged with respect to each data line 114 and is odd. The digital image signal VID1 is supplied to the D / A conversion circuit 162 located at the stage, while the digital image signal VID2 is supplied to the D / A conversion circuit 162 located at the even stage. In FIG. 24, digital image signals VID1 and VID2 are obtained by extending a digital image signal originally supplied from one system to two systems by extending the time axis. Since the other points are the same as those of the liquid crystal panel shown in FIG. 1 or 20, description thereof will be omitted.

  Next, the operation of the liquid crystal panel according to the third embodiment will be described with reference to the timing chart shown in FIG. As already described in the first embodiment, from the unit circuits R1 to Rn in the data line driving circuit 140, the signal S1 ′ to which the transfer start pulse DX is sequentially shifted by the half cycle of the clock signal CLX and its inverted clock signal CLXINV. Sn 'is output.

  Here, at the falling timing t13 of the signal S1 ', the D / A conversion circuit 162 located at the first stage in FIG. 24 latches the digital image signal VID1. As a result, the analog image signal converted in accordance with the weight of each latched bit signal is supplied to the data line 114 located in the first stage, and is supplied to the pixel intersecting with the currently selected scanning line. The data is written by the TFT 116.

  Next, at the falling timing t14 of the signal S2 ', the D / A conversion circuit 162 located at the second stage in FIG. 24 latches the digital image signal VID2. As a result, the analog image signal converted in accordance with the weight of each latched bit signal is supplied to the data line 114 located in the second stage, and the pixel intersecting with the currently selected scanning line is supplied to the pixel. The data is written by the TFT 116.

  Similarly, at the falling timing of the signals S3 ′, S4 ′,..., Sn ′, the D / A conversion circuit 162 located at the odd-numbered stage latches the digital image signal VID1 and outputs each bit signal. After the analog image signal converted in accordance with the weight is supplied to the corresponding data line 114, the D / A conversion circuit 162 located in the subsequent even number stage latches the digital image signal VID2 and outputs each bit signal. The analog image signal converted in accordance with the weight is supplied to the corresponding data line 114, and is sequentially written by the TFT 116 in the pixel intersecting with the scanning line selected at that time.

  According to the third embodiment, the D / A conversion circuit 162 located at the odd-numbered stage and the D / A conversion circuit 162 located at the even-numbered stage are staggered with respect to the arrangement of the data lines 114. The D / A conversion circuit 162 is formed even when the pitch of the data lines 114 is narrow and the pitch of the signal lines to which the signals S1 ′ to Sn ′ are supplied correspondingly is narrow. For this reason, it is possible to secure a necessary area relatively easily.

  Also, as the resolution is increased, the clock frequency in the electro-optical device generally increases, so that the sampling ability of the analog image signal is insufficient, and the delay of the TFTs constituting the drive circuit may adversely affect the display quality. . On the other hand, according to the third embodiment, since the digital image signals VID1 and VID2 expanded on the time axis and expanded into two systems are input, the drive frequency on the data line side is substantially reduced to ½. Will do. For this reason, it is possible to cope with higher resolution without improving the performance of the TFT constituting the drive circuit.

  In the third embodiment, the digital image signal is developed and supplied in two systems, but the number of development may be three or more. In view of the fact that the color image signal is composed of signals corresponding to the three primary colors, the number of expansions is preferably a multiple of 3 in order to simplify the control and the circuit.

  Further, in the third embodiment, as in the second embodiment, each of the D / A conversion circuits 162 sequentially latches the digital image signal VID, and all the D / A conversion circuits 162 are digital. If the image signal VID is latched, an analog image signal may be supplied all at once, so that the scanning lines 112 are sequentially driven.

<Scanning direction, element substrate configuration, etc.>
In each of the embodiments described above, the scanning line driving circuit 130 selects the scanning line 112 from the top to the bottom in FIG. 1, FIG. 20, or FIG. 24, and the data line driving circuit 140 selects the data line 114 in FIG. 20 or FIG. 24, in which all are supplied in only one direction, such as selecting from left to right, the scanning line 112 is also moved upward using a shift register capable of bidirectional transfer. It is possible to select the data line 114 in the downward direction and select the data line 114 in the left direction or the right direction.

  Further, in each of the above-described embodiments, the element substrate 101 of the liquid crystal panel 100 is configured by a transparent insulating substrate such as glass, and a polysilicon layer is formed on the substrate, and a source, Although it has been described that the TFT in which the drain and the channel are formed constitutes the switching element (TFT 116) of the pixel and the constituent element (including the resistor) of the peripheral circuit 120, the present invention is not limited to this.

  For example, the element substrate 101 is formed of a semiconductor substrate, and a switching element of the pixel or a component of the peripheral circuit 120 is formed by an insulated gate field effect transistor in which a source, a drain, and a channel are formed on the surface of the semiconductor substrate. May be. When the element substrate 101 is formed of a semiconductor substrate as described above, it cannot be used as a transmissive display panel. Therefore, the pixel electrode 118 is formed of aluminum or the like and used as a reflective type. Alternatively, the element substrate 101 may be a transparent substrate and the pixel electrode 118 may be a reflection type.

  Furthermore, as an electro-optic material, in addition to liquid crystal, an electroluminescence element or the like can be used for a display device that performs display by the electro-optic effect. That is, the present invention is applicable to all electro-optical devices having a configuration similar to that of the liquid crystal display device described above.

<Electronic equipment>
Next, the case where the above-described liquid crystal display device is applied to various electronic devices will be described. In this case, as shown in FIG. 26, the electronic device is mainly configured by a display information output source 1000, a display information processing circuit 1002, a power supply circuit 1004, a liquid crystal panel 100, a peripheral circuit 120, and a timing generator 200. The Among these, the display information output source 1000 includes a memory such as a ROM (Read Only Memory) and a RAM (Random Access Memory), a storage unit such as various disks, a tuning circuit that tunes and outputs a digital image signal, and the like. Display information such as an image signal in a predetermined format is supplied to the display information processing circuit 1002 based on the various clock signals generated by 200. Next, the display information processing circuit 1002 includes well-known various circuits such as an amplification / inversion circuit, a rotation circuit, a gamma correction circuit, and a clamp circuit in addition to the time axis expansion circuit and the distribution circuit used in the third embodiment. And processing the inputted display information, and supplying the image signal to the peripheral circuit 120 together with the clock signal CLK. The power supply circuit 1004 supplies predetermined power to each component.

  Next, some examples in which the above-described liquid crystal display device is used in a specific electronic device will be described.

<Part 1: Projector>
First, a projector using this liquid crystal panel as a light valve will be described. FIG. 27 is a plan view showing a configuration example of the projector.

  As shown in this figure, a lamp unit 1102 including a white light source such as a halogen lamp is provided inside the projector 1100. The projection light emitted from the lamp unit 1102 is separated into three primary colors of RGB by four mirrors 1106 and two dichroic mirrors 1108 arranged in the light guide 1104, and serves as a light valve corresponding to each primary color. The light enters the liquid crystal panels 1110R, 1110B, and 1110G.

  The configuration of the liquid crystal panels 1110R, 1110B, and 1110G is the same as that of the liquid crystal panel 100 described above, and is driven by R, G, and B primary color signals supplied from an image signal processing circuit (not shown). The light modulated by these liquid crystal panels enters the dichroic prism 1112 from three directions. In this dichroic prism 1112, R and B light is refracted at 90 degrees, while G light travels straight. Accordingly, as a result of the synthesis of the images of the respective colors, a color image is projected onto the screen or the like via the projection lens 1114.

  Note that since light corresponding to the primary colors R, G, and B is incident on the liquid crystal panels 1110R, 1110B, and 1110G by the dichroic mirror 1108, it is not necessary to provide a color filter.

<Part 2: Mobile computer>
Next, an example in which the liquid crystal panel is applied to a mobile personal computer will be described. FIG. 28 is a perspective view showing the configuration of this personal computer. In the figure, a personal computer 1200 includes a main body 1204 having a keyboard 1202 and a liquid crystal display unit 1206. The liquid crystal display unit 1206 is configured by adding a backlight to the back surface of the liquid crystal panel 100 described above.

<Part 3: Mobile phone>
Further, an example in which this liquid crystal panel is applied to a mobile phone will be described. FIG. 29 is a perspective view showing the configuration of this mobile phone. In the figure, a mobile phone 1300 includes a reflective liquid crystal panel 100 together with a plurality of operation buttons 1302. In the reflective liquid crystal panel 100, a front light is provided on the front surface thereof as necessary.

  In addition to the electronic devices described with reference to FIGS. 27 to 29, a liquid crystal television, a viewfinder type, a monitor direct view type video tape recorder, a car navigation device, a pager, an electronic notebook, a calculator, a word processor, a work Examples include a station, a videophone, a POS terminal, a device equipped with a touch panel, and the like. Needless to say, the present invention can be applied to these various electronic devices.

1 is a block diagram illustrating an overall configuration of a liquid crystal panel to which a drive circuit according to a first embodiment of the present invention is applied. It is a circuit diagram which shows the structure of the data line drive circuit in the drive circuit. (A), (b) is a circuit diagram which shows the structure of the clocked inverter in the unit circuit of the data line drive circuit, respectively. It is a circuit diagram which shows the structure of the inverter in the unit circuit of the data line drive circuit. It is a circuit diagram which shows the structure of the D / A converter in the drive circuit. (A), (b) is a figure which shows the equivalent circuit of the component in a D / A converter, respectively. It is a figure which shows the manufacturing process of the component in a peripheral circuit and a display area. It is a figure which shows the manufacturing process of the component in a peripheral circuit and a display area. It is a figure which shows the manufacturing process of the component in a peripheral circuit and a display area. It is a figure which shows the manufacturing process of the component in a peripheral circuit and a display area. It is a figure which shows another example of the manufacturing process of the component in a peripheral circuit and a display area. It is a figure which shows another example of the manufacturing process of the component in a peripheral circuit and a display area. It is a figure which shows another example of the manufacturing process of the component in a peripheral circuit and a display area. It is a figure which shows another example of the manufacturing process of the component in a peripheral circuit and a display area. 4 is a timing chart for explaining the operation of the drive circuit. It is a circuit diagram which shows the structure of another form of the same D / A converter. It is a perspective view which shows the structure of the liquid crystal panel. 4 is a partial cross-sectional view for explaining the structure of the liquid crystal panel. FIG. It is a block diagram which shows the whole structure of the liquid crystal panel which concerns on the modification of 1st Embodiment. It is a block diagram which shows the whole structure of the liquid crystal panel to which the drive circuit which concerns on 2nd Embodiment of this invention is applied. It is a circuit diagram which shows the structure of the D / A converter in the drive circuit. It is a circuit diagram which shows the structure of another form of the same D / A converter. 4 is a timing chart for explaining the operation of the drive circuit. It is a block diagram which shows the whole structure of the liquid crystal panel to which the drive circuit which concerns on 3rd Embodiment of this invention is applied. 4 is a timing chart for explaining the operation of the drive circuit. It is a block diagram which shows schematic structure of the electronic device to which the liquid crystal display device is applied. It is sectional drawing which shows the structure of the projector which is an example of the electronic device to which the liquid crystal display device is applied. It is a perspective view which shows the structure of the personal computer which is an example of the electronic device to which the liquid crystal display device is applied. It is a perspective view which shows the structure of the mobile telephone which is an example of the electronic device to which the liquid crystal display device is applied.

Explanation of symbols

12 ... Polysilicon 100 ... Liquid crystal panel 101 ... Element substrate 102 ... Counter substrate 105 ... Liquid crystal 110 ... Display area 112 ... Scan line 114 ... Data lines 116, 161, 162, 167, 168, 171 ...... TFT
118... Pixel electrode 120... Peripheral circuit 130... Scan line drive circuit 140... Data line drive circuit 150... Pulse width limiting circuit 160 and 162. 1 latch circuit 182, second latch circuit

Claims (5)

Driving an electro-optical device including a plurality of scanning lines, a plurality of data lines, a plurality of switching elements and a plurality of pixel electrodes provided corresponding to intersections of the scanning lines and the data lines on a substrate A circuit,
A D / A conversion circuit for converting a digital image signal into an analog image signal;
The D / A conversion circuit includes:
A resistor that generates a current corresponding to the weight of each bit in the digital image signal and a reference resistor that converts the sum of the generated currents into a voltage are sandwiched between the plurality of pixel electrode formation regions. A drive circuit for an electro-optical device, wherein the drive circuit is electrically connected to each of the data lines at opposing positions. The D / A conversion circuit is provided for each of the data lines,
A data line driving circuit for sequentially outputting a latch signal to each of the D / A conversion circuits;
Each D / A conversion circuit latches the digital image signal according to the latch signal, converts the latched digital image signal into an analog image signal at a predetermined timing, and supplies the analog image signal to a corresponding data line. The drive circuit of the electro-optical device according to claim 1, wherein The digital image signal is expanded in the time axis and supplied in two or more systems shifted sequentially,
2. The D / A conversion circuit is provided for each of the data lines, and is arranged in a staggered manner with a position shifted for each of the data lines corresponding to each of the systems. A drive circuit for the electro-optical device according to claim 1. An electro-optical device that is driven by the drive circuit for the electro-optical device according to claim 1. An electronic apparatus comprising the electro-optical device according to claim 4.

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