JP2000305527A - Driving circuit of electrooptic device, electrooptic device and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent degradation of a display quality by inputting directly a digital image signal into a display panel of an electrooptic device. SOLUTION: This circuit is equipped, on an element substrate of a pair of substrates between which a liquid crystal as electrooptic material is interposed, with a TFT 116 connected to a scanning line 112 and a data line 114, a pixel electrode 118 connected to the TFT 116, and a D/A conversion circuit 160 for converting a digital image signal VID into an analog image signal and for supplying a line L with the signal. In this case, a resistance and a switch composing the D/A conversion circuit 160 are composed of a TFT formed by using a manufacturing process common with the TFT 116.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electro-optical device for inputting a digital image signal and displaying by an electro-optical effect, a driving circuit of the electro-optical device, and the electro-optical device as display means. The present invention relates to an applied electronic device.

[0002]

2. Description of the Related Art A conventional electro-optical device, for example, an active matrix type liquid crystal display device mainly requires an element substrate in which switching elements are provided for each of pixel electrodes arranged in a matrix and a color filter. And a liquid crystal filled between these two substrates. In such a configuration, when a scanning signal is applied to a switching element via a scanning line, the switching element is turned on. In this conductive state, when an image signal is applied to the pixel electrode via the data line, the pixel electrode and the counter electrode (common electrode)
A predetermined charge is accumulated in the liquid crystal layer during the period. After charge accumulation,
Even when the switching element is turned off, if the resistance value of the liquid crystal layer is sufficiently high, accumulation of charge in the liquid crystal layer is maintained. As described above, when the amount of electric charge to be accumulated by driving each switching element is controlled, the alignment state of the liquid crystal changes for each pixel, so that predetermined information can be displayed.

At this time, it is only necessary to accumulate charges in the liquid crystal layer of each pixel for a part of the period. First, each scanning line is sequentially selected by a scanning line driving circuit, and secondly,
In the scanning line selection period, the data lines are sequentially selected by the data line driving circuit, and thirdly, an image signal is sampled and supplied to the selected data line.
Time-division multiplex driving in which a scanning line and a data line are shared for a plurality of pixels can be performed. Note that the scanning line driving circuit and the data line driving circuit generally each include a shift register circuit, and the scanning line driving circuit performs vertical scanning based on a signal transferred by each of the shift register circuits. , The data line driving circuit performs horizontal scanning.

In recent years, for an electro-optical device as a display device, it has been studied to display a received digital image signal based on a received digital image signal, for example, for starting digital broadcasting. Here, in view of the fact that the electro-optical device is finally displayed based on an analog signal,
A configuration is conceivable in which a digital image signal is converted into an analog image signal, and thereafter, is supplied to an interface of a display panel in the electro-optical device.

[0005]

However, in such a configuration, after all, since the analog image signal is supplied to the display panel, the degradation of the analog image signal before the signal is supplied to the display panel. This may cause display quality to deteriorate. In addition, even if a D / A conversion circuit is built in the display panel, it is necessary to determine how far the digital signal is to be built and how to build the digital signal.
Is a problem.

The present invention has been made in view of such a problem, and an object thereof is to prevent a deterioration in display quality by incorporating a D / A conversion circuit in a display panel of an electro-optical device. In addition, an electro-optical device in which the configuration of the D / A conversion circuit is defined in relation to a display panel of the electro-optical device, a driving circuit of the electro-optical device, and
An object of the present invention is to provide an electronic apparatus using the electro-optical device.

[0007]

In order to achieve the above object, a driving circuit for an electro-optical device according to the present invention comprises:
A driving circuit for an electro-optical device, comprising: a plurality of scanning lines on a substrate; a plurality of data lines; a switching element connected to the scanning line and the data line; and a pixel electrode connected to the switching element. A D / A conversion circuit for converting a digital image signal into an analog image signal, wherein a part or all of the elements constituting the D / A conversion circuit are:
It is characterized by comprising an element formed by using a common manufacturing process with the switching element.

According to the present invention, since the D / A conversion circuit is constituted by an element formed by a common manufacturing process with the switching element connected to the pixel electrode, the D / A conversion circuit is formed by the pixel electrode. It can be arranged in the area to be formed, that is, in the vicinity of the display area. For this reason,
Since the state of the digital image signal is supplied until just before the display area, the deterioration of the display quality is prevented. Further, since some or all of the constituent elements of the D / A conversion circuit are formed also as a manufacturing process of the switching element connected to the pixel electrode, the formation process of the D / A conversion circuit is complicated. Nor.

Here, in the present invention, the switching element connected to the pixel electrode is a transistor,
It is preferable that at least one or more resistors constituting the D / A conversion circuit are made of a wiring material for an electrode of the transistor. As a resistor, a semiconductor film that forms a channel of a transistor or a thin film in which the resistance is adjusted by doping ions into the transistor is a high-resistance material, and is effective. It is difficult to control. On the other hand, since the electrode wiring material has a relatively large thickness, it is easier to control the resistance value than when the semiconductor film is also used as a resistor. However, since the sheet resistance of the electrode wiring material is uniquely determined, the resistance is actually controlled by the width and length of the wiring material.

[0010] In the present invention, the switching element connected to the pixel electrode is a transistor, and at least one switching element constituting the D / A conversion circuit is a transistor connected to the pixel electrode. And a transistor formed using a common manufacturing process. That is, in the D / A conversion circuit, a switching element for performing weighting corresponding to each bit is usually provided in addition to the resistor, but according to this, the weighting is performed. Is formed using the same manufacturing process as that of the transistor connected to the pixel electrode, so that the process of forming the switching element does not become complicated.

In addition, in the present invention, the switching element connected to the pixel electrode is a transistor, and at least one resistor constituting the D / A conversion circuit is connected to the transistor connected to the pixel electrode. It is desirable to use the resistance between the source and the drain of a transistor formed using a common manufacturing process.
That is, since the on-resistance of the transistor is used as the resistor of the D / A conversion circuit, a higher specific resistance than that of the wiring material can be obtained, so that the size of the element can be reduced.
Here, the resistance value can be controlled by the width of the channel, and the wider the width, the lower the resistance value. Further, since it is relatively easy to form a transistor accurately in a certain region, it is possible to suppress variations in resistance values formed in the region.

Further, in the present invention, the switching element connected to the pixel electrode is a transistor,
At least one set of a switching element and a resistor constituting the D / A conversion circuit are formed using a common manufacturing process with a transistor connected to the pixel electrode, and a resistance between a source and a drain of the transistor is formed. Is desirably formed as one element. That is, in the D / A conversion, the switching element and the resistor for weighting are shared by the same transistor, so that the configuration can be simplified.

Here, the switching element constituting the D / A conversion circuit uses a reference potential or a constant current source.
It is desirable to generate a voltage or a current corresponding to the weight of each bit in the digital image signal. That is, in the D / A conversion, a switching element for performing weighting is formed in the same manufacturing process as that of the transistor connected to the pixel electrode.
The configuration can be simplified.

On the other hand, in the present invention, a data line driving circuit for sequentially outputting a sampling signal for selecting the data line, and an analog image signal converted by the D / A conversion circuit are sampled in accordance with the sampling signal. And a sampling circuit for supplying the data lines to each of the data lines. According to this, D
Since the / A converted analog image signal is supplied to each of the data lines according to the sampling signal, the D / A
Only one conversion circuit is required. Therefore, the display quality is prevented from deteriorating, the process for forming the D / A conversion circuit is not complicated, and the configuration is simplified.

Here, in the present invention, it is desirable that the data line has two or more stages for each data line, and the data lines are collectively written in synchronization with the horizontal scanning cycle. Thus, writing to the data lines is performed line-sequentially in each horizontal scanning period, so that display unevenness is reduced, and deterioration of a clear digital image is prevented.

Further, according to the present invention, in the D / A conversion circuit, a resistor for generating a current or a voltage corresponding to a weight of each bit in the digital image signal, and a resistor other than the resistor for generating a current or a voltage. However, it is preferable that they are formed to face each other with the sampling circuit interposed therebetween. According to this, a resistor (ladder circuit) for generating a current or a voltage corresponding to the weight of each bit, and other resistors, such as a resistor for current-voltage conversion and a resistor such as a pull-down resistor, are used. Are formed opposite to each other with the sampling circuit interposed therebetween, so that the resistance required for the D / A conversion is dispersed. For this reason, it is not necessary to form the resistance necessary for the D / A conversion in a concentrated manner, which is advantageous in a case where the area restriction is large.

In the present invention, the D / A conversion circuit is provided for each of the data lines, while the data line drive circuit sequentially outputs a latch signal to each of the D / A conversion circuits. Circuit, and each D / A conversion circuit
It is preferable that the digital image signal is latched in accordance with the latch signal, the latched digital image signal is converted into an analog image signal at a predetermined timing, and supplied to a corresponding data line. According to this, a D / A conversion circuit is provided corresponding to each of the data lines, and each D / A conversion circuit latches a digital image signal. It is possible to do. Therefore, the deterioration of the display quality is further prevented. The timing at which each D / A conversion circuit supplies an analog image signal to the corresponding data line is determined in the first case, which is simultaneous with latching, or when all D / A conversion circuits are digital during one horizontal scanning period. A second case where the image signal is latched may be considered. Here, in the first case, the analog image signals are sequentially supplied for each data line. On the other hand, in the second case, the analog signal is supplied to all the data lines at once.

On the other hand, in the present invention, the D / A conversion circuit is provided for each of the data lines, while the digital image signal is expanded on a time axis.
The D / A conversion circuit, which is supplied by two or more systems sequentially shifted and provided for each of the data lines,
It is desirable that one of the above systems corresponds to one digital image signal in order. According to this, D / A
Since the conversion circuits can be arranged in a plurality of rows in a direction intersecting the data lines, even when the pitch of the data lines is narrow or the formation area of the D / A conversion circuit is large, the comparison can be performed. It can be easily configured. Above all, the driving frequency on the data line side is substantially reduced to the reciprocal of the number of systems, so that it is possible to cope with higher resolution without improving the performance of the elements constituting the driving circuit. Becomes

According to the present invention, in the D / A conversion circuit, a resistor for generating a current or a voltage corresponding to a weight of each bit in the digital image signal, and a resistor other than the resistor for generating a current or a voltage. However, it is preferable that they are formed to face each other with the formation region of the pixel electrode therebetween.
According to this, a resistor (ladder circuit) for generating a current or a voltage corresponding to the weight of each bit, and other resistors, such as a resistor for current-voltage conversion and a resistor such as a pull-down resistor, are used. Are formed facing each other with the pixel electrode formation region interposed therebetween, so that the resistance required for D / A conversion is dispersed. For this reason, it is not necessary to form the resistance necessary for the D / A conversion in a concentrated manner, which is advantageous in a case where the area restriction is large.

Furthermore, in order to achieve the above object, in the electro-optical device according to the present invention, since the electro-optical device is driven by the above-described driving circuit of the electro-optical device, deterioration of display quality is prevented. In addition, high-quality display is possible, and the manufacturing process is simplified, and the display can be easily formed.

In addition, since the electronic apparatus according to the present invention includes the above-described electro-optical device, it is possible to provide an electro-optical device that can be easily formed with high-quality display.

[0022]

Embodiments of the present invention will be described below with reference to the drawings.

First Embodiment First, an electro-optical device driven by a drive circuit according to a first embodiment of the present invention will be described. FIG. 1 is a block diagram showing an electrical configuration of a liquid crystal panel using liquid crystal as an electro-optical material.
The liquid crystal panel 100 shown in this figure has a structure in which an element substrate and a counter substrate are attached to each other with their electrode forming surfaces facing each other, as described later. Among them, in the element substrate, a plurality of scanning lines 112 are formed in parallel in the X direction in FIG. 1 and formed in parallel, and n (n is , Even number) data lines 114 are formed. At each intersection between the scanning line 112 and the data line 114, a gate electrode of a thin film transistor (hereinafter, referred to as “TFT”) 116 is connected to the scanning line 112, while a source electrode of the TFT 116 is connected to the scanning line 112. The drain electrode of the TFT 116 is connected to the pixel electrode 118 while being connected to the data line 114. Each pixel is composed of a pixel electrode 118, a common electrode formed on a counter substrate described later, and a liquid crystal sandwiched between these electrodes, and corresponds to each intersection of the scanning line 112 and the data line 114. To form a display area 110. In addition, a storage capacitor (not shown) is formed for each pixel in parallel with the liquid crystal sandwiched between the pixel electrode 118 and the common electrode, but is omitted in the figure. ing.

The peripheral circuit 120 includes a pulse width limiting circuit 150, a D / A conversion circuit 160, a sampling circuit 170, and the like, in addition to the scanning line driving circuit 130 and the data line driving circuit 140. It is formed on the opposing surface of the element substrate and around the display area. The active elements of these circuits are formed by a combination of a TFT 116 for switching pixels and a p-channel TFT and an n-channel TFT formed by a common manufacturing process.

Here, the scanning line driving circuit 130 of the peripheral circuit 120 has a shift register, and supplies a clock signal CLY supplied from outside and its inverted clock signal C
A scanning signal is sequentially output to each scanning line 112 based on LYINV, a transfer start pulse DY, and the like.
Specifically, the scanning line drive circuit 130 first shifts the transfer start pulse DY supplied at the beginning of the vertical scanning period by a half cycle of the clock signal CLY and the inverted clock signal CLYINV, and secondly, These shifted signals are sequentially output as scanning signals to the scanning lines 112 every horizontal scanning period.

The data line driving circuit 140 has substantially the same configuration as the scanning line driving circuit 130, but is supplied with different signals. That is, the data line driving circuit 140
Has a clock signal CLY and an inverted clock signal CL
A clock signal CLX and an inverted clock signal CLXINV are supplied instead of YINV, and a transfer start pulse DX is supplied at the beginning of the horizontal scanning period instead of the transfer start pulse DY. Therefore, first, the data line driving circuit 140 transmits the transfer start pulse DX supplied at the beginning of the horizontal scanning period to the clock signal CL.
X and a half cycle of the inverted clock signal CLXINV, and secondly, the shifted signals S1 'to S1'
n ′ are sequentially output. Note that the detailed configurations of the scanning line driving circuit 130 and the data line driving circuit 140 will be described later using the data line driving circuit 140 as an example.

Next, the pulse width limiting circuit 150 includes n sets of NAND circuits 1 provided corresponding to the respective data lines 114.
52 and an inverter 154, and the signals S1'-S
The pulse width of n 'is changed to enable signals ENB1, ENB2.
And the sampling signals S1 to Sn
Is output as Here, the NAND circuit 152 located at the i-th stage counted from the left in FIG. 1 inverts the logical product of the signal Si ′ and the signal ENB1 when i is an odd number, and Signal Si 'and signal E
This is to invert the logical product with NB2. Each inverter 154 inverts the output signal of the corresponding NAND circuit 152. And these inverters 1
The 54 output signals are sampled signals S1, S2,
.., And output as Sn.

On the other hand, the D / A conversion circuit 160 converts an 8-bit digital image signal VID supplied from the outside into an analog image signal and outputs the analog image signal to the line L. The detailed configuration will be described later. It shall be.

The sampling circuit 170 is composed of n TFTs 171 provided corresponding to each data line 114, and converts the analog image signal supplied to the line L according to the sampling signals S1 to Sn into the corresponding data line. 114 is supplied to each of them after sampling. Specifically, each of the TFTs 171 as switches is provided at one end of each data line 114 and
One source electrode is connected to a line L to which an analog image signal is supplied, and a drain electrode of each TFT 171 is connected to a corresponding data line 114. The gate electrodes of the TFTs 171 are connected to signal lines to which the sampling signals S1 to Sn are supplied in order from the left in the figure.

<Structure of Data Line Drive Circuit> Here, FIG.
Will be described in detail. FIG. 2 is a circuit diagram showing a configuration of the data line driving circuit 140. In this figure, a clock signal CL
X, its inverted signal CLXINV, and the transfer start pulse DX are all supplied by a timing generator (not shown) in synchronization with the digital image signal VID.

Now, as shown in FIG. 2, the data line driving circuit 140 includes unit circuits R1 to Rn of the shift register.
+1 are connected in cascade (n + 1) stages, that is, odd-numbered stages are connected by one more than n, which is the number of data lines 114, and a pulse DX supplied at the beginning of the horizontal scanning period is In accordance with the signal CLX and its inverted clock signal CLXINV, the circuit is sequentially shifted from the preceding (left) unit circuit to the succeeding (right) unit circuit and output as signals S1 ′ to Sn ′. Therefore, each unit circuit R1 to Rn + 1 has a clock signal CLX and an inverted clock signal CLXINV
Are supplied, respectively.

Of these unit circuits R1 to Rn + 1,
Odd-numbered unit circuits R1, R3,..., Rn-1, Rn +
Reference numeral 1 denotes a clocked inverter 142 that inverts an input signal when the clock signal CLX is at the “H” level (when the inverted clock signal CLX is at the “L” level), and reinverts the inverted signal from the clocked inverter 142. When the clock signal CLX is at the “L” level and the inverter 144 as the output of the unit circuit (the inverted clock signal C
When LXINV is at “H” level), the inverter 144
And a clocked inverter 146 that inverts the output signal of the inverter 144 and feeds back the input signal of the inverter 144.

Here, the concrete configuration of the clocked inverter 142 in the odd-numbered unit circuits will be described. As shown in FIG. 3A, a gate is connected between the higher power supply Vdd and the lower power supply Vss. A p-channel TFT that inputs an inverted clock signal CLXINV to the electrode, a complementary p-channel TFT / n-channel TFT that inputs the input signal to the gate electrode, and an n-channel TFT that inputs the clock signal CLX to the gate electrode The configuration is such that a TFT and a TFT are connected in series. The clocked inverter 146 in the odd-numbered stages is as shown in FIG. 3B, and the TFT to which the clock signal CLX and the inverted clock signal CLXINV are supplied is the same as that shown in FIG.
The opposite is true. Further, as shown in FIG. 4, a p-channel TFT and an n-channel TFT for inputting an input signal to a gate electrode between a higher power supply Vdd and a lower power supply Vss, as shown in FIG.
FT and FT are connected in series in a complementary manner.

On the other hand, among the unit circuits R1 to Rn + 1,
Even-numbered unit circuits R2, R4, ..., Rn-2, Rn
Has basically the same configuration as the odd-numbered unit circuits, but the clocked inverter 142
Clocked inverter 146 is different from clocked inverter 146 in that it inverts the input signal when clock signal CLX is at “H” level, while inverting the input signal when X is at “L” level. Therefore, the clocked inverter 142 in the even-numbered stages has the configuration shown in FIG.
The clocked inverter 146 in the even-numbered stages corresponds to FIG.
The configuration shown in (a) is in a relationship in which each of the configurations is replaced with an odd-numbered configuration.

In FIG. 2, only the clock signal CLX is supplied to each of the odd-numbered clocked inverter 142 and the even-numbered clocked inverter 146, but actually, as shown in FIG. , An inverted clock signal CLXINV is also supplied. Similarly, in FIG. 2, only the inverted clock signal CLXINV is supplied to the odd-numbered clocked inverter 146 and the even-numbered clocked inverter 142, but actually, as shown in FIG. , Clock signal CLX is also supplied. Further, since these clocked inverters and inverters are connected between the higher power supply Vdd and the lower power supply Vss, these power wirings are routed in each of the unit circuits R1 to Rn + 1.

<D / A Conversion Circuit> Next, the D / A conversion circuit shown in FIG.
The detailed configuration of the / A conversion circuit 160 will be described. FIG.
9 is a diagram showing an equivalent circuit of the D / A conversion circuit 160.

As shown in the figure, the D / A conversion circuit 160 performs a D / A conversion using a so-called R-2R ladder (ladder) circuit, and each bit (bit) of the digital image signal VID is The most significant bit is the MSB, below, 2
, SB,..., 7SB, and the least significant bit is LSB). These switches Sw1 to Sw8 are connected to the terminal a when the corresponding bit is "1", and are connected to the terminal b when the corresponding bit is "0". Here, for convenience of explanation, the case of connecting to the terminal a is as follows.
It is assumed that the switch is on, and when the switch is connected to the terminal b, the switch is off. The terminals a of the switches Sw1 to Sw8 are connected to the reference potential V, respectively.
ref is connected to the signal line to which the
Are connected to a reference potential.

The common terminals of the switches Sw1 to Sw8 are connected to the connection points A to H via resistors having a resistance value of 2R, respectively. In each of the connection points A to H, connection points adjacent to each other are connected via a resistor having a resistance value of R. Therefore, in a ladder circuit composed of a resistor having a resistance value of 2R and a resistor having a resistance value of R, each of the connection points A to H of each resistor has an upper bit direction, a lower bit direction, and a switch direction. In any case, the resistance value is formed to be 2R. Further, the connection point A is connected to the line L, and serves as an output terminal Eout of the D / A conversion circuit 160.

In such a configuration, when the switch corresponding to the input bit of "1" is turned on, the output terminal Eo
A voltage corresponding to the weight of each bit is output to ut. For example, if the most significant bit MSB is "1", the switch Sw1 is turned on, and the voltage of Vref / 2 and the 3 SBs two bits lower than that are "1".
If the switch Sw3 is turned on, Vr
A voltage of ef / 8 is generated at Eout.

Next, actual components of the D / A conversion circuit 160 will be described. As already described with reference to FIG. 5, the D / A conversion circuit 160 includes the switch Sw.
1 to Sw8 and the resistance of the ladder circuit. Of these, in the present embodiment, it is assumed that the resistance component is mainly composed of polysilicon, which is a gate electrode wiring material in the TFT, and that the resistance between the source and drain in the TFT is used. ing.

First, the case where the resistance is formed from polysilicon will be described. Here, in FIG. 5, a portion 1600 indicated by a broken line, that is, a portion 16 including the switch Sw1 and a resistor having a resistance value of 2R.
Consider 00. When the resistance component is formed from polysilicon, as for the portion 1600, as shown in FIG. 6A, a signal of the most significant bit MSB of the digital image signal VID is input as a gate signal and mutually exclusive. N-channel TFT 1601
It comprises a p-channel type TFT 1602 and a resistor 1603 made of polysilicon as a gate electrode wiring material.

Here, since the semiconductor film of the TFT is a high-resistance material, it may be used as the resistor, but it is difficult to control the resistance value because the film thickness is small. On the other hand, the wiring material for the gate electrode is relatively thick, so that the semiconductor film itself is used as a resistor as well.
It is easy to control the resistance. However, since the film thickness of the gate electrode wiring material is uniquely determined by the TFT to be formed, the resistance is actually controlled by the width and length of the wiring material.

It is desirable that the on-resistances of the TFTs 1601 and 1602 are sufficiently lower than the resistance 1603.
In many cases, the resistance between the source and the drain cannot be ignored. Therefore, the TFT 1601 or 1602
Between the source and drain when
The series resistance value with the resistor 1603 made of polysilicon is 2
TFTs 1601 and 1602 and a resistor 1603 are formed so as to be R, respectively. That is, the portion 160
The switching function of the switch Sw1 at 0 is performed by the TFTs 1601 and 1602, and the function of a resistor having a resistance value of 2R is performed by the series resistance of the resistance between the source and drain of the TFT and the resistor 1603. . The portion 1600 is similarly formed corresponding to bits other than the most significant bit MSB.
In addition, at each of the connection points A to H, the resistance connecting between the adjacent connection points may be formed from polysilicon so that the resistance value becomes R,
A dummy TFT that is half the channel width of the FTs 1601 and 1602 may be formed so that the resistance between the source and the drain becomes R. FIG.
Terminals a, b, c, and d in (a) respectively correspond to the terminals having the same reference numerals in FIG.

On the other hand, a case where a resistance between a source and a drain in a TFT is used as a resistance will be described. Here, as in the case where the resistor is formed from polysilicon, a portion 1600 including the switch Sw1 and the resistor having the resistance value of 2R in FIG. 5 will be considered. In the case where the resistance is formed using the resistance between the source and drain of the TFT, as shown in FIG. 6B, the signal of the most significant bit MSB is input as a gate signal and mutually exclusive for the portion 1600. The p-channel TFT 1607 and the n-channel TFT 1608 that are turned on and off at the same time have the switching function of the switch Sw1 in the portion 1600 and the function of a resistor having a resistance value of 2R at the same time. That is, the resistance between the source and the drain when the TFT 1607 (1608) is turned on is positively used as the resistance in the ladder circuit, and each is formed to have 2R. The portion 1600 is similarly formed corresponding to bits other than the most significant bit MSB. In addition, at each connection point A to H,
As for a resistor connecting between adjacent connection points, a dummy TFT is provided so that the resistance value between the source and the drain becomes R.

When formed in this manner, the switch T
Since the on-resistance of the FT does not need to be low, the channel width can be reduced, and the circuit size can be significantly reduced since no resistor is intentionally formed. It should be noted that the variation in the resistance value of the ladder resistor directly affects the accuracy of the D / A conversion, so that it is necessary to devise a patterning technique. This is effective in the case of / A conversion or when the D / A conversion circuit is integrated in a small area. Note that the terminals a, b, c, and d in FIG. 6B respectively correspond to the terminals having the same reference numerals in FIG.

Further, the n-channel type T shown in FIG.
For the FT 1602 and the n-channel TFT 1608 in FIG. 6B, a combination of exclusive switches such as a depletion type and an enhancement type is also possible, and a signal of a corresponding bit is inverted by an inverter and input as a gate signal. In the configuration, n
It is also possible to use a channel type TFT, and conversely, it is also possible to use a p-channel type TFT.
Further, by replacing the n-channel and p-channel TFTs with transmission gates connected in parallel and inverting the reference potential to positive or negative with respect to the reference potential, it is possible to cope with inversion driving.

<Manufacturing Process> Next, the peripheral circuit 120
A description will be given of a manufacturing process of a component in the display region 110. As described above, among the peripheral circuits 120, the resistance in the D / A conversion circuit 160 is as follows.
When using polysilicon and TFT (FIG. 6)
(See FIG. 6A) and a case of forming using only the resistance between the source and drain of the TFT (see FIG. 6B). Therefore, first, the former case using polysilicon and TFT will be described. Note that the following steps are based on the TFT 116 in the display area 110, that is, the TFT 116 connected to the pixel electrode 118. Further, as the peripheral circuit 120, the TFT 1602 in FIG.
The description will be made by taking the series part of the resistor 1603 as an example. However, the TFTs other than the resistor 1603, that is, the TFTs forming the data line driving circuit 140 and the sampling circuit 170 are basically formed in the same manner as the TFT 1602.

First, as shown in step (1) of FIG. 7, a polysilicon layer 1 is formed to a thickness of about 50 to 200 nm on the entire upper surface of a substrate 101 such as glass or quartz by, for example, a low pressure CVD method. Then, the solid phase is grown preferably to a thickness of about 100 nm. At this time, when forming an n-channel type TFT, Sb (antimony),
A dopant of a V element such as As (arsenic) or P (phosphorus) is slightly doped by ion implantation or the like. In the case of forming a p-channel TFT, a dopant of a Group III element such as Al (aluminum), B (boron), or Ga (gallium) is similarly slightly doped by ion implantation or the like.

Next, as shown in step (2) of FIG. 7, the polysilicon layer 1 is patterned by a photolithography step, an etching step, or the like to form a display region 1.
In 10, the active layer 1 a of the TFT 116 is formed in an island shape, and in the peripheral circuit 120, the active layer 1 b of the TFT 1601 is formed in an island shape.

Further, as shown in step (3) of FIG. 7, the surfaces of the active layers 1a and 1b are thermally oxidized to form gate insulating films 2a and 2b on the surfaces of the active layers 1a and 1b, respectively. . By this step, the active layers 1a, 1b finally have a thickness of about 30-150 nm, preferably about 35-45 nm.
while the thickness of the gate insulating films 2a and 2b is about 6 nm.
It will be between 0 and 150 nm thick, preferably about 30 nm thick.

Then, as shown in step (4) of FIG. 7, a polysilicon layer 12 is deposited on the upper surfaces of the gate insulating films 2a and 2b and the substrate 101 by a low pressure CVD method or the like. The polysilicon layer 12 is a portion to be a scanning line which also serves as a gate electrode of the TFT 116 in the display area 110, and is a TFT in the peripheral circuit 120.
It is a portion to be a gate electrode and a resistor 1603 in various TFTs such as 1601. Note that a portion to be the scanning line 112 may be formed of a metal film of Al or the like or a metal silicide film instead of polysilicon, or a multilayer of these metal film or metal silicide film and polysilicon. May be. Further, as a wiring material of the gate electrode, in addition to polysilicon, a high melting point metal such as Mo (molybdenum), Ta (tantalum), Ti (titanium), W (tungsten), or a metal silicide thereof can be used. However, it should be noted that it is difficult to increase the resistance if a low-resistance material is used, as far as the portion to be the resistor 1603 is concerned.

Next, as shown in step (5) of FIG. 8, the polysilicon layer 12 is patterned by a photolithography step, an etching step, or the like, and in the display region 110, the gate electrode of the TFT 116 is formed. A scanning line 112 which is also used as a scanning line is formed.
The gate electrode 12b of the TFT 1601 and the resistor 1603 are formed. Note that the gate electrode 12b corresponds to the terminal d in FIG. At this time, the peripheral circuit 1
In the case of 20, the gate electrodes of the TFTs other than the TFT 1601 are formed similarly.

Further, as shown in step (6) of FIG. 8, an impurity (for example, phosphorus) dopant is doped using the scanning line 112 (gate electrode) and the gate electrode 12b as a mask to form an n-channel type TFT. Active layers 1a, 1b
In the step (a), semiconductor regions to be self-aligned source and drain regions are formed. When the TFT is a p-channel type, a dopant of a group III element such as B is doped to form a source region and a drain region in the active layer 1b.

First, the source / drain regions are:
The dopant is lightly doped at a dose of 1 × 10 ^{13 to} 3 × 10 ¹³ [atms / cm ² ] to form a low concentration region. Second, the scanning line 112 (gate electrode) and the gate electrode 12b are formed. A wider mask layer is formed on the scanning line 112 and the gate electrode 12b. Third, the same dopant is doped at a dose of 1 × 10 ^{15 to} 3 × 10 ¹⁵ [atms / cm ² ]. To form a high concentration area,
The masked region may be formed to be a TFT having a lightly doped drain (LDD) structure.
In addition, a pattern is formed using a mask wider than the scanning line 112 and the gate electrode 12b without performing lightly doping. Then, after forming a source / drain by doping an impurity, the gate electrode is overlaid. By etching, a TFT having an offset structure may be formed.

Subsequently, as shown in a step (7) of FIG. 8, the interlayer insulating film 3 is formed on the scanning line 112 and the gate electrode 12b.
About 50% by CVD, for example.
Deposit to a thickness of 0-1500 nm. The material of the interlayer insulating film 3 is NSG, PSG, BSG, BPSG
Such as a silicate glass film, a silicon nitride film, and a silicon oxide film.

Then, as shown in step (8) of FIG. 8, in the display region 110, the contact hole 41 is dry-etched in the interlayer insulating film 3 at a position corresponding to the source region of the TFT 116. And the like. On the other hand, in the peripheral circuit 120, the contact holes 42, 43, 44, and 45 for connecting the drain region, the source region, and the resistor 1603 of the TFT 1601 are formed in the interlayer insulating film 3. The contact holes 41, 42, and 43 are provided for opening a layered film of the interlayer insulating film 3 and the gate insulating film 2a or 2b.

Next, as shown in step (9) of FIG. 9, a conductive layer 14 such as a low-resistance metal such as aluminum or metal silicide is formed on the interlayer Deposit to a thickness of 500 nm. This conductive layer 14 is in the display area 110
This is a portion to be the data line 114 also serving as the source electrode of the TFT 116, and the peripheral circuit 120 has a TF
This is a portion to be a wiring portion for connecting a source electrode, a drain electrode, a resistor 1603, and the like of the TFT including T1601.

Further, as shown in a step (10) of FIG. 9, the conductive layer 14 is patterned by a photolithography step, an etching step, or the like to form a display region 110.
In the above, the data line 114 also serving as the source electrode of the TFT 116 is formed. Also, by patterning the conductive layer 14, in the peripheral circuit 120, the TFT 16
Various wirings such as a source electrode a ′ of No. 01, a connection wiring e ′ between the drain electrode of the TFT 1601 and one terminal of the resistor 1603, and a lead wiring c ′ of the other terminal of the resistor 1603 are formed. Note that in (10) of FIG.
The source electrode a ′ of the TFT 1601 corresponds to the terminal a in FIG. 6A, and the connection wiring e ′ of the drain electrode of the TFT 1601 corresponds to the terminal e in FIG. Further, the lead wiring c 'is the same as that shown in FIG.
This corresponds to the terminal c in FIG.

Subsequently, as shown in step (11) of FIG. 9, the insulating film 5 is formed by forming the data line 114 and the wirings a ′ and e ′,
The film is deposited to a thickness of about 500 to 1500 nm by, for example, a CVD method so as to cover c ′ and the like. The material of the insulating film 5 is NSG, P, as in the case of the interlayer insulating film 3.
Silicate glass film such as SG, BSG, BPSG,
Examples include a silicon nitride film and a silicon oxide film.

Next, as shown in step (12) of FIG. 9, the TFT 1 is applied to the insulating film 5 in the display area 110.
Contact holes 61 are formed at positions corresponding to the 16 drain regions by dry etching or the like.

Then, as shown in step (13) of FIG. 10, a transparent conductive thin film 18 such as ITO is formed on the upper surface of
After being deposited to a thickness of 00 nm, the pixel electrode 118 is formed by patterning by a photolithography step, an etching step, or the like, as shown in FIG.
When the liquid crystal panel 100 is of a reflective type, the pixel electrode 118 is formed of an opaque conductive thin film having a high reflectance such as aluminum instead of the transparent conductive thin film 18.

According to the steps (1) to (14),
By using the manufacturing process of the TFT 116 in the display area 110, the components of the peripheral circuit 120, in particular, the switches and various resistors of the D / A conversion circuit 160 are formed simultaneously with the TFT 116 that switches the pixels.

When light enters the TFT, the performance is reduced due to leakage. Therefore, the light-shielding layer is actually formed according to the shape of the TFT, but is not directly related to the present invention in the figure. Therefore, it is omitted.

<Manufacturing Process> Next, the peripheral circuit 120
Of the D / A conversion circuit 160 is a TFT
(FIG. 6 (b)) will be described.
Here, the peripheral circuit 120 will be described by taking the TFT 1607 of the portion 1600 in FIG. 6B as an example. The manufacturing process will be described in steps (1) of FIG. 11 to step (14) of FIG. It is as shown. However, since these steps are the same as steps (1) in FIG. 7 to step (14) in FIG. 10 except for the resistor 1603 made of polysilicon, a detailed description thereof will be omitted. .

Through these steps (1) to (14), the constituent elements of the peripheral circuit 120, particularly, the D /
The switches and various resistors of the A conversion circuit 160 are formed at the same time by the same process as the TFT 116 for switching the pixels. The resistance between the source and the drain depends on the channel width of the TFT, the channel length, and the LDD.
It is controlled by length and the like. Specifically, as the resistance becomes higher, it is necessary to narrow the channel width, increase the channel length, or increase the LDD length.

<Operation of First Embodiment> Next, the operation of the liquid crystal panel according to the first embodiment will be described with reference to a timing chart shown in FIG.

First, at timing t11, when the pulse DX is input at the beginning of the horizontal scanning period and the clock signal CLX rises (inverted clock signal CL).
When XINV falls), in the data line driving circuit 140, the clocked inverter 142 in the first-stage unit circuit R1 inverts the “H” level of the transfer start pulse DX, and similarly the first-stage unit circuit. Since the inverter 144 in R1 inverts the inversion result of the clocked inverter 142, the output signal S1 ′ from the first-stage unit circuit R1 becomes “H” level.

Next, at timing t12, during the period when the transfer start pulse DX is being input, the clock signal C
When LX falls (when the inverted clock signal CLXINV rises), the clocked inverter 146 in the first-stage unit circuit R1 outputs the "H" level output signal S
Since 1 'is inverted and fed back to the inverter 144, the output signal S1' maintains the "H" level. The clocked inverter 1 in the second-stage unit circuit R2
42 is an output signal S1 'from the first-stage unit circuit R1.
"H" level of the second unit circuit R
2, the inverter 144 inverts the inverted result of the clocked inverter 142, so that the output signal S2 ′ of the second-stage unit circuit R2 becomes “H” level.

Then, at timing t13, when the input of the transfer start pulse DX is completed and the clock signal CLX rises again (when the inverted clock signal CLXINV falls), the clock signal in the unit circuit R1 in the first stage is output. Since the inverter 142 takes in the "L" level of the transfer start pulse DX, the output signal S1 'of the unit circuit R1 becomes "L" level. On the other hand, the clocked inverter 146 in the second-stage unit circuit R2
Since the "H" level output signal S2 'is inverted and fed back to the inverter 144, the output signal S2' maintains the "H" level. Further, the clocked inverter 142 in the third-stage unit circuit R3 inverts the “H” level of the output signal S2 ′ from the second-stage unit circuit R2, and similarly outputs the inverter of the second-stage unit circuit R2. 144 inverts the inversion result of the clocked inverter 142, so that the output signal S3 'of the third-stage unit circuit R3 becomes "H" level.

Thereafter, the same operation is repeated, and as a result, the first input transfer start pulse DX is applied to clock signal CL.
X and its inverted clock signal CLXINV are sequentially shifted by a half cycle and output as output signals S1 'to Sn' from the unit circuits R1 to Rn at each stage.

Of the signals S1 'to Sn', the output signal from the odd-numbered unit circuit is the pulse width of the signal ENB1, and the output signal from the even-numbered unit circuit is the pulse width of the signal ENB2. After being limited by the NAND circuit 152 of each stage to the width, the inverter 154 of each stage
, And output as sampling signals S1 to Sn. Therefore, the sampling signals S1 to S
n means that signals adjacent to each other are output at the same time without being at the “H” level.

On the other hand, the scanning line driving circuit 130 also
Since the configuration is the same as that of the data line driving circuit 140, the operation is the same as that of the data line driving circuit 140. However, since the supplied signal is different, the scanning signal is sent from the top to the bottom of the It will be supplied for each book.

Here, when the sampling signal S 1 is output during a period in which one certain scanning line 112 is selected, the analog image signal converted at that time, that is, the D / A conversion circuit 160 An analog image signal D / A-converted from the digital image signal VID and supplied to the line L is sampled with respect to a data line corresponding to the sampling signal S1, and a pixel that intersects a currently selected scanning line is provided to a pixel. The TFT1
16 will be written.

Thereafter, when the sampling signal S2 is output, the analog image signal is sampled on the next data line 114, and written into the pixel intersecting the scanning line selected at that time by the TFT 116. It will be.

The sampling signal S3,
When S4,..., Sn are sequentially output, the analog image signals are sampled on the data lines 114 belonging to the respective sampling signals, and written to the pixels intersecting the scanning line selected at that time. Thereafter, the next scanning line is selected, sampling signals S1 to Sn are sequentially output again, and the same writing is repeatedly performed.

The signals S1 'to Sn' are changed to the signal ENB.
1, the pulse width of ENB2 is limited because the adjacent sampling signals are simultaneously output and the TFTs 171 as switches corresponding to the adjacent data lines 114 are prevented from turning on at the same time, and supplied to the line L. This is to prevent the analog image signal from being sampled at an overlapping timing between adjacent data lines 114. Therefore, by setting the frequency of the clock signal CLX and its inverted clock signal CLXINV low, the sampling signals S1
If the configuration is such that Sn does not substantially overlap,
In the subsequent stage of the data line driving circuit 140, the pulse width limiting circuit 150 for narrowing the pulse width can be omitted.
This also applies to the scanning line driving circuit 130.

As described above, according to the first embodiment, when the resistance component is mainly formed of wiring polysilicon, the D / A conversion circuit 160 uses the same manufacturing process as the TFT 116 in the display area 110. TFT formed by
And polysilicon resistor 1603,
The D / A conversion circuit 160 can be arranged near the display area 110. For this reason, since the image signal is input digitally and the state of the digital image signal is maintained until immediately before the display area, it is possible to prevent the display quality from deteriorating, and to suppress the variation in the resistance value.
It is also possible to improve the accuracy of D / A conversion. Also,
In the case of using the resistance between the source and drain of the TFT as the resistance, it is possible to prevent the display quality from deteriorating, as in the case of forming the resistance from polysilicon, and to reduce the size of the element. It is possible to increase the density. Further, in any of the above cases, since the constituent elements of the D / A conversion circuit 160 are formed by the same manufacturing process as that of the TFT 116 in the display region 110, the steps for forming the D / A conversion circuit 160 are omitted. There is no need for it separately.

<Another Example of D / A Conversion Circuit>
The A conversion circuit 160 divides the reference potential Vref according to the weight of each bit in the digital image signal VID, but the present invention is not limited to this.
The present invention is applicable to D / A conversion circuits using various methods.

For example, like the D / A conversion circuit 162 shown in FIG. 16, a current addition type configuration in which the reference constant current Iref is divided and added in accordance with the weight of each bit in the digital image signal VID. May be applied.
In such a configuration, since a current obtained by adding the weight of each bit in the digital image signal VID to the output line L flows through the line L, it is necessary to convert the current into a voltage so as to be converted into an analog image signal. Normally, such current-voltage conversion can be easily configured by using an operational amplifier, but generally, it is difficult to configure a high-precision operational amplifier using only TFTs. Therefore, the line L
Is provided with a reference resistor Rref that pulls down to a reference potential instead of the operational amplifier, so that the current flowing through the line L is converted into a voltage. Here, regarding the reference resistance Rref, the D / A conversion circuit 16
2 because it is not necessary to provide it near the ladder circuit of FIG.
As shown in FIG. 6, it is desirable to form the sampling circuit 170 at a position opposing the formation region of the sampling circuit 170. As described above, when the resistance between the source and the drain of the TFT is increased, the size of the TFT is increased.
When ef is formed at a distance from the resistance of the ladder circuit,
Since the resistance can be dispersed accordingly, this is a particularly effective measure when space is limited or heat generation is a problem. For the same reason, the constant current source may be provided on the Rref side instead of the D / A conversion circuit 162 side.

Incidentally, even in the voltage division type D / A conversion circuit 160 as shown in FIG. 5, in order to prevent the potential of the line L from becoming unstable, the reference resistor Rref as shown in FIG. May be similarly provided to pull down the line L to the reference potential. Also in this configuration,
Needless to say, it is desirable to form the reference resistance Vref at a distance from the resistance of the ladder circuit.

In the D / A conversion circuit, R-2
In addition to the configuration using the R resistance ladder, the m-th digital image signal VID counted from the most significant bit MSB (m is 1, 2, 3,..., 8 in the present embodiment)
Is input through a resistor having a resistance of 2 (m-1) R, and then the signal of each bit is added, that is, the present invention is applied to a so-called n-bit weighted resistance type configuration. good. However, as the number of bits of the digital image signal increases, the required resistance value increases exponentially, so that a large area is required. For this reason,
It can be said that the configuration using the R-2R ladder circuit described above is more preferable.

Further, in the D / A conversion circuit, a configuration using a switched capacitor instead of a resistor, that is, a combination of a switch and a capacitor, and turning on and off the switch makes the capacitor appear apparent. It may be applied to a configuration in which the resistor is replaced with a resistor.

In addition, the above-described digital image signal VI
D is 8 bits, but this is only for convenience of explanation and is not limited to this. In addition,
When the digital image signal VID is set to 8 bits as in the embodiment and color display is performed corresponding to the three primary colors RGB, 8 bits correspond to one primary color. There corresponding results, it is possible to color display 16.7 million colors (more precisely, 2 ²⁴ colors).

<Polarity Reversal> In an electro-optical device, when a direct current is applied to an electro-optical material such as a liquid crystal,
Since the electro-optical material is deteriorated, an AC driving method in which positive driving and negative driving are alternately performed is generally used. In addition, in order to prevent flicker, uneven brightness, crosstalk, and the like, the application of a data signal is performed by inverting the polarity in scanning line units, inverting the polarity in data units, and inverting the polarity in pixel units. Measures will be taken. For these reasons, it is necessary to invert the polarity of the analog image signal supplied to the data line 114 according to one of the above.

When the polarity inversion is performed as described above, in the D / A conversion circuit 160 shown in FIG. 5, the reference potential is set to + Vref during the positive drive, and the reference potential is set during the negative drive. May be supplied as -Vref. On the other hand, the D / A conversion circuit 162 shown in FIG. 16 supplies a reference constant current as + Iref during positive polarity driving and supplies a reference constant current as −Iref during negative polarity driving. Just do it. Note that the polarity inversion here refers to alternately inverting the voltage level or current direction using the amplitude center potential of the analog image signal as a reference potential, as described above.

Further, it is needless to say that, instead of inverting the reference potential Vref or the reference constant current Iref, one bit of the digital image signal VID is assigned as the polarity information. However, in this configuration, the number of gradations is substantially reduced by one bit.

<Configuration Example of Liquid Crystal Panel> Next, the overall configuration of the liquid crystal panel 100 according to the above-described electrical configuration will be described with reference to FIGS. Here, FIG.
FIG. 1 is a perspective view showing a configuration of a liquid crystal panel 100, and FIG.
FIG. 8 is a sectional view taken along line AA ′ in FIG.

As shown in these figures, the liquid crystal panel 100 has an element substrate 10 on which a pixel electrode 118 and the like are formed.
1 and a transparent opposing substrate 102 made of glass or the like on which the common electrode 108 and the like are formed, with a constant gap kept by a sealant 104 mixed with a spacer 103 so that the electrode forming surfaces face each other. In addition, a liquid crystal 105 as an electro-optical material is sealed in the gap. Note that the sealant 104 is formed along the periphery of the opposing substrate 102, but has a partly opened opening for enclosing the liquid crystal 105. Therefore, after the liquid crystal 105 is injected, the opening is sealed by the sealing material 106.

Here, the data line driving circuit 140, the pulse width limiting circuit 150, and the sampling circuit 170 described above are formed on the opposite surface of the element substrate 101 and on one side outside the sealing material 104, and are formed in the Y direction. The configuration is such that the extending data lines 114 are driven. Further, a plurality of connection electrodes 107 are formed on one side,
The above-described various timing signals, digital image signals VID, and the like are input. Two scanning line driving circuits 130 and a D / A conversion circuit 160 are formed on two sides adjacent to this one side to drive the scanning lines 112 and the lines L extending in the X direction from both sides, respectively. Configuration. If the delay of the scanning signal supplied to the scanning line 112 and the delay of the analog image signal supplied to the line L do not matter, the scanning line driving circuit 130 and the D / A conversion circuit 160 may be connected to one side.
A configuration in which only one side is formed may be used. Also, the ladder circuit of the D / A conversion circuit 160 is, for example, the one shown in FIG.
8, if provided on one side on one side at the position indicated by * 3, the reference resistor Rref will be provided at the position indicated by * 4 (see FIG. 18) opposed thereto.
In addition, in the element substrate 101, in order to reduce the load of writing an image signal to the data line 114, each data line 1
14 may be formed with a precharge circuit for precharging to a predetermined potential at a timing prior to the supply of the analog image signal.

On the other hand, the common electrode 108 of the opposite substrate 102
Of the four corners of the portion to be bonded to the element substrate 101
By the conductive material provided in at least one place,
Electrical conduction with the element substrate 101 is achieved. In addition, depending on the use of the liquid crystal panel 100, for example, first, a stripe shape, a mosaic shape,
Color filters arranged in a triangle or the like are provided. Second, a black matrix such as a resin material in which a metal material such as chromium or aluminum or carbon is dispersed in a photoresist is provided.
, A transparent conductive film is provided. In the case of color light modulation, a black matrix and a transparent conductive film are provided on the opposite substrate 102 without forming a color filter. Further, when improving the light use efficiency, microlenses corresponding to each pixel are arranged in an array.

In addition, on the opposing surfaces of the element substrate 101 and the opposing substrate 102, an alignment film or the like that has been subjected to a predetermined alignment treatment is provided, and on the back side thereof, a polarizer (not shown) corresponding to the alignment direction is provided. ) Are provided. However, when a polymer-dispersed liquid crystal in which fine particles are dispersed in a polymer is used as the liquid crystal 105, the above-described alignment film, polarizer, and the like are not required, so that the light use efficiency is increased, resulting in higher brightness. And low power consumption.

Instead of forming part or all of the peripheral circuit 120 on the element substrate 101, for example, a TA
A driving IC chip mounted on a film using B (Tape Automated Bonding) technology may be electrically and mechanically connected via an anisotropic conductive film provided at a predetermined position on the element substrate 101. And drive IC
The chip itself may be configured to be electrically and mechanically connected to a predetermined position on the element substrate 101 via an anisotropic conductive film using a COG (Chip On Grass) technique.

<Modification of First Embodiment> Here, a modification of the above-described first embodiment will be described with reference to FIG. FIG. 19 is a block diagram showing the overall configuration of a liquid crystal panel according to this modification. In the first embodiment shown in FIG. 1, the analog image signal converted by the D / A
71, the sampling is performed according to the sampling signals S1 to Sn and supplied to each data line 114. In this modification, as shown in FIG. 2 latch circuit 182
And the data is supplied to each data line 114.

Here, the first latch circuit 181 sequentially latches the analog image signals from the D / A conversion circuit 160 in accordance with the sampling signals S1 to Sn output from the data line driving circuit 140. The second latch circuit 182 simultaneously supplies the analog image signals latched in the first latch circuit 181 to the data lines 114 in accordance with the latch signal LP output during the horizontal flyback period.

In this configuration, the analog image signals sequentially latched by the first latch circuit 181 are simultaneously supplied to all the data lines 114 and written to the pixels intersecting the selected scanning line 112, so that the clock Display unevenness caused by the duty ratio of the signal CLX and the inverted clock signal CLXINV is reduced. For this reason, it is possible to prevent a clear image from being deteriorated by the digital image signal at all.

The latch signal LP does not need to be supplied during the horizontal flyback period, but only needs to be a signal synchronized with horizontal scanning. Further, a configuration in which three or more latch circuits are provided for one data line 114 may be employed.

<Second Embodiment> In the first embodiment described above, the digital image signal VID is converted into an analog image signal by the D / A conversion circuit 160 formed in the liquid crystal panel 100, and is converted to a line L. However, since the line L intersects with the signal line to which the sampling signals S1 to Sn are supplied, the line L is easily affected by the capacitive coupling. Therefore, in the first embodiment, although the digital image signal VID is directly input, the analog image signal after conversion is deteriorated, and the display quality is considerably reduced. .

Therefore, a second embodiment which solves this problem will be described. FIG. 20 is a block diagram showing an electrical configuration of a liquid crystal panel to which the drive circuit according to the second embodiment is applied. The liquid crystal panel shown in this figure is different from the liquid crystal panel of the first embodiment (see FIG. 1) in that the pulse width limiting circuit 150 and the sampling circuit 170 are eliminated and the D / A conversion circuit 162 The point is that it is provided corresponding to the data line 162.
The other points are the same as those of the liquid crystal panel shown in FIG. 1, and the description will be omitted.

Here, regarding the D / A conversion circuit 162,
In FIG. 20, the i-th stage from the left (i = 1, 2, 3,...,
n) D / A conversion circuit 162 corresponding to data line 114
Will be described as an example. FIG. 21 is a diagram showing an equivalent circuit of the D / A conversion circuit 162. D shown in this figure
/ A conversion circuit 162 switches S corresponding to each bit.
w1 to Sw8 and a ladder circuit having a resistance value of R and 2R are common to the D / A conversion circuit 160 shown in FIG. 5, but include switches for controlling the switching of the switches Sw1 to Sw8. The difference from the D / A conversion circuit 160 shown in FIG. 5 is that a control unit 1620 is further provided and an output end Eout is directly connected to the data line 114.

Here, the switch control unit 1620 latches each bit signal of the digital image signal VID at the falling edge of the signal Si ′ output from the corresponding unit circuit Ri in the data line driving circuit 140, The switches Sw1 to Sw8 are turned on / off according to the latched bit signals.

The D / A conversion circuit 162 is of the voltage division type in the example shown in FIG. 21, but may be of the current addition type as shown in FIG. However, FIG.
As in the example shown in FIG. 6, a reference resistor Rref for converting a current added according to the weight of each bit in the digital image signal VID into a voltage is provided. The reference resistance Rref is provided at a position facing the display region 110 from the viewpoint of dispersing the resistance. That is,
If the ladder circuit of the D / A conversion circuit 160 is provided, for example, at the position indicated by * 3 in FIG. 18, the reference resistor Rref will be provided at the position indicated by * 4 opposite to this. Here, the reference resistance Vref is
If the source of the TFT is formed by a resistance between the source and the drain, the source of the TFT can be switched to a signal line for supplying a precharge signal.
The FT can also be used as a switch of the precharge circuit, which contributes to simplification of the configuration.

Next, the operation of the liquid crystal panel according to the second embodiment will be described with reference to a timing chart shown in FIG. As already described in the first embodiment, the unit circuit R1 in the data line driving circuit 140
To Rn, the transfer start pulse DX is output from the clock signal CL.
Signals S1 'to Sn' sequentially shifted by a half cycle of X and its inverted clock signal CLXINV are output.

Here, at the falling timing t13 of the signal S1 ', the first stage D / A conversion circuit 162
Latches the digital image signal VID. As a result, the analog image signal converted in accordance with the weight of each latched bit signal is supplied to the first-stage data line 114, and is applied to the pixel that intersects the currently selected scanning line. The data is written by the TFT 116.

Next, at the falling timing t14 of the signal S2 ', the second stage D / A conversion circuit 162
Latches the digital image signal VID. As a result, the analog image signal converted according to the weight of each latched bit signal is supplied to the second-stage data line 114, and is applied to the pixel that intersects the currently selected scanning line. The data is written by the TFT 116.

Similarly, signals S3 ', S4',.
.., At the falling timing of Sn ′, the D / A conversion circuit 162 to which the signal is supplied latches the digital image signal VID, thereby converting the digital image signal VID in accordance with the weight of each latched bit signal. The analog image signal supplied to the corresponding data line 114 is supplied to a pixel intersecting the currently selected scanning line, and
Are written sequentially.

As described above, according to the second embodiment, the digital image signal VID is supplied to the D / A conversion circuit 162 provided corresponding to each of the data lines 114, and therefore, as in the first embodiment. Furthermore, it is possible to further reduce the possibility that the converted analog image signal is deteriorated.

In the second embodiment, when one of the scanning lines 112 is selected, the D / A conversion circuit 1
62, the digital image signals VID are sequentially latched at the falling timings of the signals S1 'to Sn', and the analog image signals are supplied to the corresponding data lines 114 each time. The invention is not limited to this. For example, after each of the D / A conversion circuits 162 sequentially latches the digital image signal VID, all the D / A conversion circuits 162
, The analog image signal may be collectively supplied to all the data lines 114. That is, instead of the dot sequential driving method as in the embodiment, a line sequential driving method may be used.

<Third Embodiment> In the above-described second embodiment, D / D is simply applied to each data line 114.
The A / A conversion circuit 162 is provided, but one D / A
In order to form the conversion circuit 162, it is necessary to form a large number of resistors constituting the ladder circuit, so that a relatively large area is required. Therefore, as in the second embodiment,
D / A conversion circuit 162 corresponding to each of data lines 114
Are arranged in one row in a direction crossing the signal lines to which the signals S1 ′ to Sn ′ are supplied.
4 is disadvantageous when the pitch is small, or when the restriction on the substrate area is large.

Therefore, a third embodiment which solves this problem will be described. FIG. 24 is a block diagram showing an electrical configuration of a liquid crystal panel to which the drive circuit according to the third embodiment is applied. The liquid crystal panel shown in this figure is different from the liquid crystal panel of the second embodiment (see FIG. 20) in that the D / A conversion circuit 162
4 and the D / A conversion circuit 162 located at the odd-numbered stage has a digital image signal VI.
While D1 is supplied, the digital image signal VID2 is supplied to the D / A conversion circuit 162 located at the even-numbered stage. In FIG. 24, the digital image signals VID1 and VID2 are obtained by extending a digital image signal originally supplied by one system into two systems by extending the time axis. The other points are the same as those of the liquid crystal panel shown in FIG. 1 or FIG. 20, and the description is omitted.

Next, the operation of the liquid crystal panel according to the third embodiment will be described with reference to a timing chart shown in FIG. As already described in the first embodiment, the unit circuit R1 in the data line driving circuit 140
To Rn, the transfer start pulse DX is output from the clock signal CL.
Signals S1 'to Sn' sequentially shifted by a half cycle of X and its inverted clock signal CLXINV are output.

Here, at the falling timing t13 of the signal S1 ', the signal D located at the first stage in FIG.
/ A conversion circuit 162 latches digital image signal VID1. As a result, the analog image signal converted in accordance with the weight of each latched bit signal is supplied to the data line 114 located at the first stage, and is supplied to the pixel intersecting the currently selected scanning line. Is written by the TFT 116.

Next, at the falling timing t14 of the signal S2 ', the D / D signal located at the second stage in FIG.
A conversion circuit 162 latches digital image signal VID2. As a result, the analog image signal converted in accordance with the weight of each latched bit signal is supplied to the data line 114 located at the second stage, and the analog image signal is supplied to the pixel intersecting the currently selected scanning line. Is written by the TFT 116.

Similarly, signals S3 ', S4',...
.., At the falling timing of Sn ′, the D / A conversion circuit 162 located at the odd-numbered stage latches the digital image signal VID1 and converts the analog image signal converted according to the weight of each bit signal into the corresponding data. After the signal is supplied to the line 114, the D / A conversion circuit 162 located at the even-numbered stage following the line 114 latches the digital image signal VID2 and converts the analog image signal corresponding to the weight of each bit signal into a corresponding analog image signal. The data is supplied to the data line 114, and the pixel intersecting the scanning line selected at that time is applied to the TFT 116.
Are written sequentially.

According to the third embodiment, the D / A conversion circuit 162 located at the odd-numbered stage and the D / A conversion circuit 162 located at the even-numbered stage are arranged with respect to the arrangement of the data lines 114. Since the pitch of the data lines 114 is narrow because of the staggered arrangement, even if the pitch of the signal lines to which the signals S1 ′ to Sn ′ are supplied is narrow, the D / A
An area required for forming the conversion circuit 162 can be relatively easily secured.

In general, as the resolution becomes higher, the clock frequency in the electro-optical device becomes higher. Therefore, the sampling ability of the analog image signal becomes insufficient, and the delay of the TFT constituting the drive circuit adversely affects the display quality. Sometimes. On the other hand, according to the third embodiment, since the digital image signals VID1 and VID2 expanded in the time axis and expanded into two systems are input, the driving frequency on the data line side is substantially reduced to １ ／. Will do. For this reason, it is possible to cope with higher resolution without improving the performance of the TFT constituting the driving circuit.

In the third embodiment, the digital image signal is developed in two systems and supplied.
The number of expansions may be three or more. The number of developments is preferably a multiple of 3 in view of the fact that the color image signal is composed of signals corresponding to the three primary colors, from the viewpoint of simplifying the control and the circuit.

Further, in the third embodiment, similarly to the second embodiment, each of the D / A conversion circuits 162 sequentially latches the digital image signal VID and all the D / A conversion circuits. 162 is the digital image signal VI
When D is latched, a configuration in which analog image signals are supplied collectively may be adopted, in which a method of sequentially driving each scanning line 112 is used.

<Scanning Direction and Configuration of Element Substrate> In each of the above-described embodiments, the scanning line driving circuit 130
The scanning line 112 is selected from top to bottom in FIG. 1, FIG. 20, or FIG. 24, and the data line driving circuit 140 selects the data line 114 from left to right in FIG. 1, FIG. 20, or FIG. In both cases, the configuration is such that the scanning lines 112 are supplied in only one direction. However, using a shift register capable of transferring data in both directions, the scanning lines 112 can be selected upward and downward, and the data lines 114 Or to the right.

In each of the above embodiments, the element substrate 101 of the liquid crystal panel 100 is formed of a transparent insulating substrate such as glass, and a polysilicon layer is formed on the substrate and the polysilicon layer is formed on the substrate. The switching element (TFT 116) of the pixel and the peripheral circuit 120 are formed by a TFT having a source, a drain, and a channel formed therein.
Although the description has been made on the configuration element (including the resistor) described above, the present invention is not limited to this.

For example, the element substrate 101 is composed of a semiconductor substrate, and the switching element of the pixel and the peripheral circuit 1 are formed by an insulated gate field effect transistor having a source, a drain and a channel formed on the surface of the semiconductor substrate.
Twenty constituent elements may be formed. When the element substrate 101 is formed using a semiconductor substrate as described above, it cannot be used as a transmissive display panel. Therefore, the pixel electrode 118 is formed of aluminum or the like and used as a reflective type. Alternatively, the element substrate 101 may simply be a transparent substrate and the pixel electrode 118 may be of a reflection type.

Further, as the electro-optical material, in addition to the liquid crystal, an electroluminescent element or the like is used.
The present invention can also be applied to a display device that performs display using the electro-optic effect. That is, the present invention is applicable to all electro-optical devices having a configuration similar to the above-described liquid crystal display device.

<Electronic Equipment> Next, the case where the above-described liquid crystal display device is applied to various electronic equipment will be described.
In this case, the electronic device mainly includes a display information output source 1000 and a display information processing circuit 100, as shown in FIG.
2, power supply circuit 1004, liquid crystal panel 100, peripheral circuit 1
20 and a timing generator 200. Of these, the display information output source 1000 is RO
M (Read Only Memory) and RAM (Random Access Me
mory), a storage unit such as various disks, a tuning circuit for synchronizing and outputting a digital image signal, and the like. Based on various clock signals generated by the timing generator 200, display information such as an image signal in a predetermined format. Display information processing circuit 1002
Is to be supplied to Next, the display information processing circuit 100
Reference numeral 2 denotes a well-known various circuit such as an amplification / inversion circuit, a rotation circuit, a gamma correction circuit, and a clamp circuit, in addition to the time axis expansion circuit and the distribution circuit used in the third embodiment. The processing is executed, and the image signal is transmitted to the peripheral circuit 1 together with the clock signal CLK.
20. The power supply circuit 1004
Supplies a predetermined power to each component.

Next, some examples in which the above-described liquid crystal display device is used in specific electronic devices will be described.

<Part 1: Projector> First, a projector using this liquid crystal panel as a light valve will be described. FIG. 27 is a plan view showing a configuration example of the projector.

As shown in this figure, the projector 1
Inside 100, a lamp unit 1102 composed of a white light source such as a halogen lamp is provided. The projection light emitted from the lamp unit 1102 is separated into three primary colors of RGB by four mirrors 1106 and two dichroic mirrors 1108 arranged in the light guide 1104, and is used as a light valve corresponding to each primary color. Liquid crystal panels 1110R, 1110B and 1110
G is incident.

The configuration of the liquid crystal panels 1110R, 1110B, and 1110G is the same as that of the liquid crystal panel 100 described above, and is driven by R, G, and B primary color signals supplied from an image signal processing circuit (not shown). It is. The light modulated by these liquid crystal panels enters the dichroic prism 1112 from three directions. In the dichroic prism 1112, the R and B lights are refracted at 90 degrees, while the G light travels straight. Therefore, as a result of combining the images of each color,
A color image is projected on a screen or the like via the projection lens 1114.

Note that the liquid crystal panels 1110R, 1110B
And 1110G have a dichroic mirror 1108
Accordingly, light corresponding to each of the primary colors R, G, and B is incident, so that it is not necessary to provide a color filter.

<Part 2: Mobile Computer> Next, an example in which the liquid crystal panel is applied to a mobile personal computer will be described. FIG. 28 is a perspective view showing the configuration of this personal computer. In the figure, a personal computer 1200 includes a main body 1204 having a keyboard 1202 and a liquid crystal display unit 1206. The liquid crystal display unit 1206 is configured by adding a backlight to the back of the liquid crystal panel 100 described above.

<Part 3: Mobile phone> Further, an example in which this liquid crystal panel is applied to a mobile phone will be described. FIG.
FIG. 9 is a perspective view showing the configuration of the mobile phone. In the figure, a mobile phone 1300 has a plurality of operation buttons 1302
In addition, a reflective liquid crystal panel 100 is provided. In this reflection type liquid crystal panel 100, a front light is provided on the front surface as needed.

Note that, in addition to the electronic devices described with reference to FIGS. 27 to 29, a liquid crystal television, a viewfinder type, a monitor direct-view type video tape recorder, a car navigation device, a pager, an electronic notebook, a calculator, Examples include a word processor, a workstation, a videophone, a POS terminal, and a device having a touch panel. It goes without saying that the present invention can be applied to these various electronic devices.

[0131]

As described above, according to the present invention, the D / A conversion circuit can be arranged in the area where the pixel electrode is formed, that is, in the vicinity of the display area. It can be supplied in the form of a signal to prevent display quality from deteriorating. Further, some or all of the components of the D / A conversion circuit are formed by a manufacturing process of a switching element connected to a pixel electrode. Therefore, the D / A conversion circuit can be easily formed without adding a separate step for forming the D / A conversion circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an overall configuration of a liquid crystal panel to which a drive circuit according to a first embodiment of the present invention is applied.

FIG. 2 is a circuit diagram showing a configuration of a data line driving circuit in the driving circuit.

FIGS. 3A and 3B are circuit diagrams each showing a configuration of a clocked inverter in a unit circuit of the data line driving circuit.

FIG. 4 is a circuit diagram showing a configuration of an inverter in a unit circuit of the data line driving circuit.

FIG. 5 is a circuit diagram showing a configuration of a D / A converter in the drive circuit.

FIGS. 6A and 6B are diagrams showing equivalent circuits of components in the D / A converter, respectively.

FIG. 7 is a diagram showing a manufacturing process of a component in a peripheral circuit and a display area.

FIG. 8 is a diagram showing a manufacturing process of a constituent element in a peripheral circuit and a display area.

FIG. 9 is a diagram illustrating a manufacturing process of a component in a peripheral circuit and a display area.

FIG. 10 is a diagram illustrating a manufacturing process of a component in a peripheral circuit and a display area.

FIG. 11 is a diagram showing another example of the manufacturing process of the constituent elements in the peripheral circuit and the display area.

FIG. 12 is a diagram showing another example of the manufacturing process of the constituent elements in the peripheral circuit and the display area.

FIG. 13 is a diagram showing another example of the manufacturing process of the constituent elements in the peripheral circuit and the display area.

FIG. 14 is a diagram showing another example of the manufacturing process of the constituent elements in the peripheral circuit and the display area.

FIG. 15 is a timing chart for explaining the operation of the driving circuit.

FIG. 16 is a circuit diagram showing a configuration of another form of the D / A converter.

FIG. 17 is a perspective view showing the structure of the liquid crystal panel.

FIG. 18 is a partial cross-sectional view illustrating the structure of the liquid crystal panel.

FIG. 19 is a block diagram illustrating an overall configuration of a liquid crystal panel according to a modification of the first embodiment.

FIG. 20 is a block diagram illustrating an overall configuration of a liquid crystal panel to which a drive circuit according to a second embodiment of the present invention is applied.

FIG. 21 is a circuit diagram showing a configuration of a D / A converter in the drive circuit.

FIG. 22 is a circuit diagram showing a configuration of another form of the D / A converter.

FIG. 23 is a timing chart for explaining the operation of the driving circuit.

FIG. 24 is a block diagram illustrating an overall configuration of a liquid crystal panel to which a drive circuit according to a third embodiment of the present invention is applied.

FIG. 25 is a timing chart for explaining the operation of the driving circuit.

FIG. 26 is a block diagram illustrating a schematic configuration of an electronic device to which the liquid crystal display device is applied.

FIG. 27 is a cross-sectional view illustrating a configuration of a projector as an example of an electronic apparatus to which the liquid crystal display device is applied.

FIG. 28 is a perspective view illustrating a configuration of a personal computer as an example of an electronic apparatus to which the liquid crystal display device is applied.

FIG. 29 is a perspective view illustrating a configuration of a mobile phone as an example of an electronic apparatus to which the liquid crystal display device is applied.

[Explanation of symbols]

12 ... Polysilicon 100 ... Liquid crystal panel 101 ... Element substrate 102 ... Counter substrate 105 ... Liquid crystal 110 ... Display area 112 ... Scanning line 114 ... Data line 116,161,162,167,168,171 ......
TFT 118 pixel electrode 120 peripheral circuit 130 scanning line driving circuit 140 data line driving circuit 150 pulse width limiting circuit 160, 162 D / A conversion circuit 170 sampling circuit 181 First latch circuit 182... Second latch circuit

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2H092 JA01 JA24 JA31 JA32 JA34 JA37 JA41 JB22 JB31 JB69 KA04 KA10 KB25 MA07 MA13 MA17 MA19 MA27 NA01 NA25 PA06 PA07 PA08 PA13 QA15 RA05 2H093 NA31 NA41 NC16 NC22 NC23 NC26 NC34 ND01 ND49ND NE06 NF11 NG02 5C006 AA16 AC27 AF42 AF83 BB16 BC06 BC08 BC12 BC20 BF03 BF04 BF11 BF25 BF26 BF27 BF32 BF34 BF43 EB05 FA41 FA51 5C080 AA10 BB05 DD25 DD28 EE29 FF11 JJ02 JJ03 JJ04 JJ06 KK06 KK

Claims (14)

[Claims] 1. An electro-optical device comprising a substrate having a plurality of scanning lines, a plurality of data lines, switching elements connected to the scanning lines and the data lines, and pixel electrodes connected to the switching elements. And a D / D converter for converting a digital image signal into an analog image signal.
Driving the electro-optical device, comprising: an A / A conversion circuit, wherein part or all of the elements constituting the D / A conversion circuit are elements formed by using a common manufacturing process with the switching element. circuit. 2. The switching element connected to the pixel electrode is a transistor, and at least one or more resistors constituting the D / A conversion circuit are made of a wiring material for an electrode of the transistor. The driving circuit for an electro-optical device according to claim 1. 3. The switching element connected to the pixel electrode is a transistor, and at least one switching element forming the D / A conversion circuit is manufactured in common with the transistor connected to the pixel electrode. 2. The driving circuit for an electro-optical device according to claim 1, comprising a transistor formed by using a process. 4. The switching element connected to the pixel electrode is a transistor, and at least one or more resistors constituting the D / A conversion circuit are manufactured in common with the transistor connected to the pixel electrode. 2. The driving circuit for an electro-optical device according to claim 1, wherein a resistance between a source and a drain of the transistor formed by using a process is used. 5. The switching element connected to the pixel electrode is a transistor, and at least one set of a switching element and a resistor constituting the D / A conversion circuit are connected to the pixel electrode by a transistor. 2. The driving circuit for an electro-optical device according to claim 1, wherein the driving circuit is formed as a single element by using a common manufacturing process and by using a resistance between a source and a drain of the transistor. 6. The switching element constituting the D / A conversion circuit is for generating a voltage or a current corresponding to the weight of each bit in the digital image signal using a reference potential or a constant current source. 4. The method according to claim 3, wherein
Or a driving circuit of the electro-optical device according to 5. 7. A data line drive circuit for sequentially outputting a sampling signal for selecting the data line, and an analog image signal converted by the D / A conversion circuit, which is sampled according to the sampling signal to generate the data signal. 2. The driving circuit for an electro-optical device according to claim 1, further comprising a sampling circuit for supplying each of the lines. 8. The data line 1 according to claim 1, wherein
8. The driving circuit for an electro-optical device according to claim 7, wherein the driving circuit has two or more stages, and writes the data lines collectively in synchronization with a horizontal scanning cycle. 9. The D / A conversion circuit, wherein a resistor for generating a current or a voltage corresponding to a weight of each bit in the digital image signal and another resistor sandwich the sampling circuit. 8. The driving circuit for an electro-optical device according to claim 7, wherein the driving circuits are formed so as to face each other. 10. The D / A conversion circuit is provided for each of the data lines, and includes a data line drive circuit for sequentially outputting a latch signal to each of the D / A conversion circuits, Each D / A conversion circuit latches the digital image signal in accordance with the latch signal, converts the latched digital image signal into an analog image signal at a predetermined timing, and supplies the analog image signal to a corresponding data line. The driving circuit for an electro-optical device according to claim 1, wherein the driving circuit is characterized in that: 11. The D / A conversion circuit is provided for each of the data lines, while the digital image signal is supplied in two or more systems that are expanded on a time axis and sequentially shifted. 2. The electro-optical device according to claim 1, wherein the D / A conversion circuit provided for each of the data lines sequentially corresponds to one digital image signal of the two or more systems. The drive circuit of the device. 12. The D / A conversion circuit, wherein a resistor for generating a current or a voltage corresponding to a weight of each bit in the digital image signal and another resistor are formed on the pixel electrode. The driving circuit for an electro-optical device according to claim 10, wherein the driving circuit is formed to face each other with the region interposed therebetween. 13. An electro-optical device driven by the driving circuit of the electro-optical device according to claim 1. Description: 14. An electronic apparatus comprising the electro-optical device according to claim 13.