JP2015004911A - Electro-optic panel and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To ensure uniformity of display when intervals of data lines are not even.SOLUTION: A display panel 10 includes a first data line 34G, a second data line 34R adjoining to the first data line 34G, a third data line 34B adjoining to the first data line 34G, a fourth data line 34B adjoining to the second data line 34R, and a data line drive circuit 24 that supplies a data signal Vd to each data line 34. The data line drive circuit 24 includes a first sampling transistor Ts supplying the data signal Vd to the first data line 34G, and a second sampling transistor Ts supplying the data signal Vd to the second data line 34R. An interval between the second data line 34R and the third data line 34B is larger than an interval between the first data line 34G and the fourth data line 34B. A drive ability of the second sampling transistor Ts is higher than a drive ability of the first sampling transistor Ts.

Description

  The present invention relates to an electro-optical panel and an electronic apparatus.

  In recent years, various electro-optical panels such as a display panel including electro-optical elements such as liquid crystal elements and light-emitting elements have been proposed. The electro-optical panel defines a plurality of scanning lines, a plurality of data lines, a plurality of pixels provided corresponding to the intersection of the scanning lines and the data lines, and a gradation to be displayed by each of the plurality of pixels. A data line driving circuit that supplies a data signal to be supplied to each pixel via a data line is generally used (see, for example, Patent Document 1).

JP 2008-008942 A

  By the way, capacitance is parasitic between the data lines and various wirings constituting the pixel circuit, between two adjacent data lines, and the like. Therefore, when a plurality of data lines are not equally spaced, such as when a pixel provided corresponding to one data line is made larger than a pixel provided corresponding to another data line, a plurality of data lines The capacitance value of the parasitic capacitance in each data line varies from data line to data line. When the capacitance value of the parasitic capacitance varies from data line to data line, the pixel value corresponding to the data line corresponding to the data line having a small capacitance value of the parasitic capacitance is compared with the pixel provided corresponding to the data line having a large capacitance value of the parasitic capacitance. Since the writing of the data signal becomes insufficient, there is a problem that the display of the electro-optical panel becomes non-uniform.

  The present invention has been made in view of the above-described circumstances, and one of its purposes is to realize a high-quality display that ensures display uniformity even when the intervals of the data lines are not equal. It is to be.

  In order to achieve the above object, an electro-optical panel according to the present invention includes a first data line and a second data line extending along the first data line so as to be adjacent to the first data line. A data line, a third data line extending along the first data line so as to be adjacent to the first data line on the opposite side of the second data line, and the second data line A fourth data line extending along the second data line is provided corresponding to the first data line so as to be adjacent to the data line on the opposite side to the first data line. A first data signal is supplied to the first pixel via the first pixel, the second pixel provided corresponding to the second data line, and the first data line. A second data signal is sent to the second pixel via the first sampling transistor and the second data line. A second sampling transistor to be supplied, and an interval between the second data line and the third data line is larger than an interval between the first data line and the fourth data line, The driving capability of the second sampling transistor is higher than the driving capability of the first sampling transistor.

In the electro-optical panel according to the present invention, the sum of the interval between the second data line and the first data line and the interval between the second data line and the fourth data line is equal to the first data line and the second data line. This is smaller than the sum of the interval between the data lines and the interval between the first data line and the third data line. For this reason, the capacitance value of the capacitance parasitic on the second data line is larger than the capacitance value of the capacitance parasitic on the first data line.
In the present invention, the driving capability of the second sampling transistor provided corresponding to the second data is higher than the driving capability of the first sampling transistor provided corresponding to the first data. Therefore, the second pixel provided corresponding to the second data line has less data signal writing than the first pixel provided corresponding to the first data line. Therefore, it is possible to ensure display uniformity.

In the above electro-optical panel, a value obtained by dividing the channel width of the second sampling transistor by the channel length is larger than a value obtained by dividing the channel width of the first sampling transistor by the channel length. It is preferable that
According to this aspect, the driving capability of the second sampling transistor can be made higher than the driving capability of the first sampling transistor. Therefore, the second pixel provided corresponding to the second data line has less data signal writing than the first pixel provided corresponding to the first data line. Therefore, it is possible to ensure display uniformity.

In the electro-optical panel described above, each of the first sampling transistor and the second sampling transistor includes a source region, a drain region, and a channel region provided between the source region and the drain region. A first LDD region provided between the source region and the channel region, and a second LDD region provided between the drain region and the channel region. The total length of the length of the first LDD region included in the first sampling transistor and the length of the second LDD region in the direction of the channel length toward the first line is equal to that of the first LDD region included in the second sampling transistor. Longer than the total length of the length and the length of the second LDD region Masui.
According to this aspect, the driving capability of the second sampling transistor can be made higher than the driving capability of the first sampling transistor.

The electro-optical panel described above can display at least a first color and a second color, and the first pixel is provided between the first data line and the third data line, and The first color can be displayed, and the second pixel is provided between the second data line and the first data line, and can display the second color. The light preferably has a higher spectral sensitivity than the light of the second color.
According to this aspect, since the interval between the first data line and the third data line can be made larger than the interval between the first data line and the second data line, the first pixel is It can be made larger than the second pixel. Therefore, in the electro-optical panel according to this aspect, it is possible to emit more first light with high spectral sensitivity than in the case where the size of the first pixel is equal to or smaller than the size of the second pixel. It becomes possible, and the brightness of the whole screen can be improved.

  The electro-optical panel according to the present invention is an electro-optical panel capable of displaying the first color, the second color, and the third color, and is adjacent to the first data line and the first data line. The second data line extending along the first data line, and the first data line adjacent to the first data line on the opposite side of the second data line. A third data line extending along the data line; a first pixel provided corresponding to the first data line and capable of displaying the first color; and corresponding to the second data line. A second pixel capable of displaying the second color, a third pixel corresponding to the third data line and capable of displaying the third color, and the first data line. A first sampling transistor for supplying a first data signal to the first pixel, and a second data line. A second sampling transistor that supplies a second data signal to the second pixel; and a third sampling signal that supplies a third data signal to the third pixel via the third data line. And the first pixel is provided between the first data line and the third data line, and an interval between the first data line and the third data line. Is larger than the interval between the first data line and the second data line, the driving capability of the second sampling transistor is higher than the driving capability of the first sampling transistor, and the first It is characterized by being higher than the driving capability of the sampling transistor No. 3.

  In the electro-optical panel described above, it is preferable that the wiring resistance of the first data line is higher than the wiring resistance of the second data line.

  In addition to the electro-optical panel, the present invention can be conceptualized as an electronic apparatus having the electro-optical panel. Typically, the electronic device includes a display device such as a head mounted display (HMD) or an electronic viewfinder.

1 is a perspective view illustrating a configuration of an electro-optical device according to an embodiment. 2 is a block diagram illustrating a configuration of the electro-optical device. FIG. It is a figure which shows the pixel circuit in the same electro-optical apparatus. 2 is a plan view illustrating a configuration of a pixel circuit in the electro-optical device. FIG. 2 is a partial cross-sectional view illustrating a configuration of a pixel circuit in the same electro-optical device. FIG. FIG. 3 is a block diagram illustrating a configuration of a data line driving circuit in the electro-optical device. FIG. 3 is a plan view illustrating a configuration of a pixel and a sampling transistor in the same electro-optical device. FIG. 3 is a partial cross-sectional view illustrating a configuration of a sampling transistor in the same electro-optical device. FIG. 3 is a plan view illustrating a configuration of a sampling transistor in the same electro-optical device. FIG. 3 is a partial cross-sectional view illustrating a configuration of a sampling transistor in the same electro-optical device. 10 is a plan view illustrating a configuration of a sampling transistor in an electro-optical device according to Modification Example 1. FIG. 10 is a plan view illustrating a configuration of a sampling transistor in an electro-optical device according to Modification Example 1. FIG. 12 is a block diagram illustrating a configuration of a data line driving circuit in an electro-optical device according to Modification Example 2. FIG. 10 is a block diagram illustrating a configuration of an electro-optical device according to Modification 3. FIG. 14 is an explanatory diagram for explaining an arrangement of pixels according to Modification Example 4. FIG. 14 is an explanatory diagram for explaining an arrangement of pixels according to Modification Example 4. FIG. It is a perspective view of an electronic device (HMD). It is a figure which shows the optical structure of HMD. It is a perspective view of an electronic device (personal computer). It is a perspective view of an electronic device (cellular phone).

  Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings. However, in each figure, the size and scale of each part are appropriately changed from the actual ones. Further, since the embodiments described below are preferable specific examples of the present invention, various technically preferable limitations are attached thereto. However, the scope of the present invention is particularly limited in the following description. Unless otherwise stated, the present invention is not limited to these forms.

<A. Embodiment>
FIG. 1 is a perspective view showing a configuration of an electro-optical device 1 according to an embodiment of the present invention.
As shown in FIG. 1, the electro-optical device 1 includes a display panel 10 (an example of an “electro-optical panel”) and a control circuit 50 that controls the operation of the display panel 10.
The display panel 10 includes a plurality of pixels and a drive circuit that drives the pixels (pixel circuits provided corresponding to the pixels). The display panel 10 is housed in, for example, a frame-shaped case 201 that opens in the display unit, and one end of an FPC (Flexible Printed Circuits) substrate 202 is connected to the display panel 10. On the FPC board 202, a semiconductor chip control circuit 50 is mounted by COF (Chip On Film) technology, and a plurality of terminals 203 are provided, which are connected to an upper circuit (not shown).

FIG. 2 is a block diagram illustrating a configuration of the electro-optical device 1 according to the embodiment. As described above, the electro-optical device 1 includes the display panel 10 and the control circuit 50.
Digital image data Video is supplied to the control circuit 50 from an upper circuit (not shown) in synchronization with the synchronization signal. Here, the image data Video is digital data that defines a gradation level to be displayed by each pixel when the image is displayed on the display panel 10 by, for example, 8 bits. The synchronization signal is a signal including a vertical synchronization signal, a horizontal synchronization signal, and a dot clock signal.
The control circuit 50 generates a control signal Ctr that is a signal for controlling the operation of the display panel 10 based on the synchronization signal, and supplies the control signal Ctr to the display panel 10. The control circuit 50 generates an analog image signal Vid based on the image data Video and supplies it to the display panel 10. The image signal Vid is a signal indicating a potential that defines the transmittance of a liquid crystal element (a liquid crystal element CL described later) included in the pixel Px so that the pixel Px displays a gradation specified by the image data Video.

As shown in FIG. 2, the display panel 10 has a plurality of pixels Px arranged in the display region 30.
Specifically, in the display area 30, M rows of scanning lines 32 are provided so as to extend in the X direction (an example of “second direction”) in the figure, and N columns of data lines 34 are Y in the figure. It extends in the direction (an example of “first direction”) and is provided so as to be electrically insulated from each scanning line 32. Pixels Px are provided corresponding to the intersections of the M rows of scanning lines 32 and the N columns of data lines 34. That is, in the present embodiment, the pixels Px are arranged in a matrix form of M vertical rows × N horizontal columns. Here, M and N are both natural numbers.
Although not shown in FIG. 2, in the display region 30, M rows of power supply lines 38 extend in the X direction in the drawing and are provided so as to be electrically insulated from each data line 34. Yes.

  In the following, in order to distinguish the scanning line 32, the power supply line 38, and the row (row) of the pixel Px, they may be referred to as a first row, a second row,. Similarly, in order to distinguish the columns of the data lines 34 and the pixels Px, they may be referred to as a first column, a second column, a third column,... In addition, the pixel Px in the n-th column may be represented as a pixel Px [n] (n is an integer from 1 to N).

The plurality of pixels Px provided in the display area 30 include a pixel PxG that can display green G (an example of “first color”) and a pixel PxR that can display red R (an example of “second color”). , And a pixel PxB that can display blue B (an example of “third color”).
More specifically, k is an integer that is a multiple of 3 that satisfies 3 ≦ k, and as shown in FIG. 2, among the first to Nth columns, the (k−2) th column has M rows. Pixels PxR are arranged, M rows of pixels PxG are arranged in the (k−1) th column, and M rows of pixels PxB are arranged in the kth column.
In the following description, the data line 34 corresponding to the pixel PxG is denoted by reference numeral “34G”, the data line 34 corresponding to the pixel PxR is denoted by reference numeral “34R”, and the data line 34 corresponding to the pixel PxB is denoted by reference numeral It may be represented by “34B”.
In the present embodiment, in order to brighten the display of the entire display region 30, the color corresponding to the light having the highest spectral sensitivity among the colors (red R, green G, and blue B) that can be displayed by the electro-optical device 1. The area of the region where the green G (first color) is displayed is increased. Specifically, the width in the X direction of the pixel PxG is made larger than the width in the X direction of the pixel PxR and the pixel PxG. The widths of the pixels PxR and PxG in the X direction are substantially the same width.

  As shown in FIG. 2, the display panel 10 includes a drive circuit 20. The pixel Px includes a pixel circuit 110 provided corresponding to the pixel Px. The drive circuit 20 drives each pixel circuit 110 corresponding to each pixel Px.

The drive circuit 20 includes a scanning line drive circuit 22 and a data line drive circuit 24.
The scanning line driving circuit 22 is means for sequentially scanning (selecting) the first to Mth scanning lines 32 in units of rows. Specifically, the scanning line driving circuit 22 applies horizontal scanning signals Gw [1] to Gw [M] to be output to the first to Mth scanning lines 32 in the period of one frame. By sequentially setting a predetermined selection potential for each scanning period, the scanning lines 32 are sequentially selected in units of rows. The period of one frame is a period required for the electro-optical device 1 to display an image for one cut (frame).
Based on the image signal Vid and the control signal Ctr supplied from the control circuit 50, the data line driving circuit 24 defines data signals Vd [1] to Vd [1] to define a gradation to be displayed by the pixel Px corresponding to each pixel circuit 110. Vd [N] is generated and output to N columns of data lines 34 every horizontal scanning period.
In this embodiment, the image signal Vid output from the control circuit 50 is an analog signal, but the control circuit 50 may output a digital image signal. In this case, the data signal Vd [1] to Vd [N] may be generated by D / A converting the digital image signal in the data line driving circuit 24.

  FIG. 3 shows an example of an equivalent circuit diagram of the pixel circuit 110 included in the pixel Px. Note that the pixel circuits 110 have the same configuration when viewed electrically, and therefore, here, the pixel circuit 110 in the m-th row and the n-th column will be described as an example. Here, m is an integer from 1 to M, and n is an integer from 1 to N.

As shown in FIG. 3, the pixel circuit 110 is formed on a substrate 150 (not shown in FIG. 3), and includes a P-channel transistor 112, a liquid crystal element CL, and a capacitor 114.
The liquid crystal element CL is an electro-optical element that includes the pixel electrode 122, the common electrode 124, and the liquid crystal 126 provided between the pixel electrode 122 and the common electrode 124. The transmittance of the liquid crystal 126 changes according to the voltage applied between the pixel electrode 122 and the common electrode 124, and as a result, the display gradation of the pixel Px corresponding to the pixel circuit 110 changes. The common electrode 124 is set to a constant potential Vcom.
The capacitor 114 has two electrodes, one electrode is electrically connected to the pixel electrode 122 and the other electrode is electrically connected to the power supply line 38 maintained at a constant voltage.

The pixel circuit 110 is supplied with a scanning signal Gw [m] from the scanning line driving circuit 22 via the m-th scanning line 32.
The transistor 112 has a gate electrically connected to the m-th row scanning line 32, and one of a source and a drain electrically connected to the n-th column data line 34. In the transistor 112, the other of the source and the drain is electrically connected to one of the two electrodes of the capacitor 114 and the pixel electrode 122. That is, the transistor 112 is electrically connected between the pixel electrode 122 and the data line 34, and controls the electrical connection between the pixel electrode 122 and the data line 34.

The structure of the pixel circuit 110 will be described with reference to FIGS. Since each pixel circuit 110 is configured in the same manner, FIGS. 4 and 5 will be described by taking one pixel circuit 110 (for example, the pixel circuit 110 in the mth row and the nth column) as an example. FIG. 4 is a plan view showing a wiring structure of the pixel circuit 110 when the pixel circuit 110 having the top emission structure is viewed from the surface side. 5 is a partial cross-sectional view taken along the line D-d in FIG. In FIG. 4 and FIG. 5, for the sake of simplification, a structure formed on the surface side of the pixel electrode 122 described later is omitted.
Note that the “front side” is a direction in which the pixel circuit 110 is provided when viewed from the substrate 150 in FIG. The direction opposite to the front side, that is, the direction in which the substrate 150 is provided when viewed from the pixel electrode 122 may be expressed as “back side”. Further, viewing the electro-optical device 1 from the surface side (that is, viewing the electro-optical device 1 from a direction perpendicular to the substrate 150) may be expressed as “plan view”.

As shown in FIG. 5, each element constituting the pixel circuit 110 is formed on a substrate 150. The substrate 150 is a plate-like member made of a transparent insulating material such as glass or plastic.
On the substrate 150, semiconductor layers 112a, 112b, and 112c of the transistor 112 are provided. The semiconductor layer 112a corresponds to one of a source region and a drain region of the transistor 112, the semiconductor layer 112b corresponds to the other of the source region and the drain region of the transistor 112, and the semiconductor layer 112c corresponds to a channel region of the transistor 112. To do.

As shown in FIG. 5, a gate insulating layer L0 made of a transparent non-conductive material is formed so as to cover the semiconductor layers 112a, 112b, and 112c and the substrate 150.
A first wiring layer made of a conductive material is formed on the surface side of the gate insulating layer L0 by patterning. The first wiring layer includes a scanning line 32 provided for each row and a gate node 112g provided for each pixel Px. The gate node 112g is electrically connected to the scanning line 32. A portion of the gate node 112g that overlaps the semiconductor layer 112c in plan view corresponds to the gate of the transistor 112.

As shown in FIG. 5, a first interlayer insulating layer L1 made of a transparent nonconductive material is formed so as to cover the first wiring layer and the gate insulating layer L0.
On the surface side of the first interlayer insulating layer L1, a second wiring layer made of a conductive material is formed by patterning. The second wiring layer includes a data line 34 provided for each column and relay nodes N1 and N2 provided for each pixel Px. The relay node N1 is electrically connected to the data line 34 and is also electrically connected to the semiconductor layer 112a through a contact hole Ha1 that penetrates the first interlayer insulating layer L1 and the gate insulating layer L0. The relay node N2 is electrically connected to the semiconductor layer 112b through the contact hole Ha2. In FIG. 4, the contact hole is shown as a portion where “□” marks are added to the “□” marks where the different wiring layers overlap.

As shown in FIG. 5, a second interlayer insulating layer L2 made of a transparent non-conductive material is formed so as to cover the second wiring layer and the first interlayer insulating layer L1.
A third wiring layer made of a conductive material is formed by patterning on the surface side of the second interlayer insulating layer L2. The third wiring layer includes a power supply line 38 provided for each row and a relay node N3 provided for each pixel Px. The relay node N3 is electrically connected to the feeder line 38. The relay node N2 and the relay node N3 sandwich the second interlayer insulating layer L2, so that the capacitor 114 is formed.

As shown in FIG. 5, a third interlayer insulating layer L3 made of a transparent non-conductive material is formed so as to cover the third wiring layer and the second interlayer insulating layer L2.
A fourth wiring layer made of a conductive material is formed on the surface side of the third interlayer insulating layer L3 by patterning. The fourth wiring layer includes a pixel electrode 122 provided for each pixel Px. The pixel electrode 122 is made of a transparent conductive material, and is electrically connected to the relay node N2 through the contact hole Ha3.

Although not shown, a liquid crystal 126 is provided on the surface side of the pixel electrode 122, and a common electrode 124 formed of a transparent conductive material is further provided on the surface side of the liquid crystal 126 in the plurality of pixel circuits 110. Commonly provided. Then, on the surface side of the common electrode 124, one of red R, green G, and blue B color filters is overlaid corresponding to the color displayed by the pixel Px.
A light source is provided on the back side of the substrate 150. The light emitted from the light source passes through the substrate 150, various insulating layers (L0 to L3), the pixel electrode 122, the liquid crystal 126, and the common electrode 124, and is colored by a color filter. It will be visually recognized as an image | video by the observer located in. That is, the pixel PxG modulates light emitted from a light source, which will be described later, according to the data signal Vd [n] to emit green G light, and the pixel PxR emits light emitted from the light source to the data signal Vd [ n] is modulated to emit red R light, and the pixel PxB modulates light emitted from the light source according to the data signal Vd [n] to emit blue B light.
In addition to the above description, a sealing material for shielding the light emitting layer from the atmosphere is provided, but the description thereof is omitted.

  4 and 5, the transistor 112, the capacitor 114, and the power supply line 38 are provided at positions that do not overlap the data line 34 or the scanning line 32 in plan view. You may provide in the position which overlaps with the line 32. FIG.

Next, the data line driving circuit 24 will be described with reference to FIG.
As shown in FIG. 6, the data line driving circuit 24 includes a shift register 241 and N sampling transistors Ts (hereinafter simply referred to as “transistor Ts”). Further, the data line driving circuit 24 includes a signal line 242 to which the image signal Vid is supplied from the control circuit 50, and N columns of connection wirings 243.

  The N transistors Ts are provided to correspond to the N columns of data lines 34 on a one-to-one basis and to correspond to the N columns of connection wirings 243 on a one-to-one basis. Specifically, one of the source and the drain of the transistor Ts [n] is electrically connected to the data line 34 in the nth column, and the other of the source and the drain is connected to the signal line 242 to which the image signal Vid is supplied. Electrically connected. The gate of the transistor Ts [n] is electrically connected to the connection wiring 243 in the nth column.

The shift register 241 divides one horizontal scanning period into at least N periods, and in each divided period, N transistors Ts [1] to Ts [N] one by one in order (exclusively). It is a means to turn on. Specifically, the shift register 241 outputs the selection signals X [1] to X [N] to each of the N connection wirings 243. Then, the selection signal X [n] among the selection signals X [1] to X [N] is set to the selection potential in the nth period among the N periods obtained by dividing one horizontal scanning period.
When the selection signal X [n] is set to the selection potential, the transistor Ts [n] is turned on, and the signal line 242 and the nth column data line 34 are electrically connected. As a result, among the data signals Vd [1] to Vd [N] obtained by time-dividing the image signal Vid, the data signal Vd [n] is output to the data line 34 in the nth column.
As described above, the data line driving circuit 24 outputs the data signals Vd [1] to Vd [N] obtained by time-division of the image signal Vid to the data lines 34 in the first column to the Nth column, respectively. To do.
In the following, the transistor Ts provided corresponding to the data line 34R is represented as “TsR”, the transistor Ts provided corresponding to the data line 34G is represented as “TsG”, and provided corresponding to the data line 34B. The transistor Ts may be expressed as “TsB”.

Next, referring to FIGS. 7 and 8, the width of the pixel Px in the X direction (that is, the interval between two adjacent data lines 34) and the driving capability of the transistor Ts (that is, the transistor size of the transistor Ts). Will be described.
FIG. 7 shows four transistors Ts that are continuous in the X direction, four columns of data lines 34 provided corresponding to the four transistors Ts, and a plurality of columns provided corresponding to the four columns of data lines. It is a top view when the pixel Px is viewed in plan. Specifically, in FIG. 7, the four transistors Ts [k] to Ts [k + 3] from the kth column to the (k + 3) th column, the four data lines 34, and the kth column to the (k + 3) th column. 8 pixels Px corresponding to two rows arranged in FIG. FIG. 8 is a partial cross-sectional view taken along line E-e in FIG.

  As shown in FIGS. 7 and 8, semiconductor layers 244, 245, and 246 are provided on the substrate 150 corresponding to the respective transistors Ts. The data line 34 is electrically connected to the semiconductor layer 244 via the contact hole Hb, and the signal line 242 is electrically connected to the semiconductor layer 245 via the contact hole Hc. The connection wiring 243 is provided so as to overlap with the semiconductor layer 246 in a plan view. That is, the semiconductor layer 244 corresponds to one of a source region and a drain region of the transistor Ts, the semiconductor layer 245 corresponds to the other of the source region and the drain region of the transistor Ts, and the semiconductor layer 246 corresponds to a channel region of the transistor Ts. It corresponds to. In addition, a portion of the connection wiring 243 that overlaps the semiconductor layer 246 in plan view corresponds to the gate of the transistor Ts.

As described above, the width in the X direction of the pixel PxG is larger than the width in the X direction of the pixel PxR and the pixel PxG. The widths of the pixels PxR and PxG in the X direction are substantially the same width.
Here, as shown in FIG. 7, the data line 34B (for example, the data line 34 in the (k) th column) and the data line 34R (for example, the data line 34 in the (k + 1) th column) adjacent to the data line 34B. ) Is represented by DBR. Further, the distance between the data line 34R (for example, the (k + 1) th column data line 34) and the data line 34G (for example, the (k + 2) th column data line 34) adjacent to the data line 34R is represented by DRG. . Further, the distance between the data line 34G (for example, the (k + 2) th column data line 34) and the data line 34B adjacent to the data line 34G (for example, the (k + 3) th column data line 34) is represented by DGB. . At this time, the following formula (1) is established between these three intervals.
DGB> DBR ≒ DRG (1)
Therefore, the following formula (2) can be derived from the formula (1).
DGB + DRG> DBR + DRG (2)
In Equation (1), “DBR≈DRG” is set because the manufacturing error is taken into consideration, and when the manufacturing error is not taken into consideration, it can be expressed as “DBR = DRG”. In the following description, “equal” includes both “exactly equal” and “substantially the same” cases. In addition, when “substantially the same” or “substantially equal” is used, the case of “strictly equal” and the case of “equal within the range of manufacturing error”, that is, it can be considered that they are equal considering the manufacturing error. Both are included.

4 and 5, each configuration of the pixel circuit 110 such as between the data line 34 and the scanning line 32, between the data line 34 and the power supply line 38, and between the data line 34 and the transistor 112. A capacitance Cp is parasitic between each element.
In addition to the capacitor Cp, the data line 34 has parasitic capacitance between the data line 34 adjacent to the data line 34. Specifically, as shown in FIG. 7, a capacitor CGB is parasitic between the data line 34G and the data line 34B adjacent to the data line 34G, and is adjacent to the data line 34B and the data line 34B. A capacitance CBR is parasitic between the matching data lines 34R, and a capacitance CRG is parasitic between the data lines 34R and the data lines 34G adjacent to the data lines 34R.

The total capacitance value Cp_all of the capacitance Cp parasitic between the scanning line 32, the power supply line 38, the pixel circuit 110, etc., and the data line 34 varies among the data line 34R, the data line 34G, and the data line 34B. Are small and can be considered to be approximately equal.
That is, except for the first column and the N-th column, the capacitance value of the capacitor CR parasitic on the data line 34R is “CBR + CRG + Cp_all”, and the capacitance value of the capacitor CG parasitic on the data line 34G is “CGB + CRG + Cp_all”. The capacitance value of the capacitance CB parasitic to 34B is “CGB + CBR + Cp_all” (hereinafter, for convenience of description, the capacitance value may be expressed by using a symbol representing the capacitance).

On the other hand, since the interval DGB is larger than the interval DBR and the interval DRG, the relationship of the following equation (3) is established among the capacitance value of the capacitor CGB, the capacitance value of the capacitor CBR, and the capacitance value of the capacitor CRG. To establish.
CGB <CBR ≒ CRG (3)
That is, except for the first column and the N-th column, the following equation (4) is established among the capacitance value of the capacitor CR, the capacitance value of the capacitor CG, and the capacitance value of the capacitor CB.
CR> CG≈CB (4)

For this reason, if the transistor TsR, the transistor TsG, and the transistor TsB have the same (substantially equal) driving ability, only the pixel PxR corresponding to the data line 34R cannot write the data signal Vd [n]. It becomes sufficient and the display becomes uneven.
Note that the driving capability of the transistor Ts is the capability of defining the magnitude of current that can be supplied by the transistor Ts. That is, even when the potential indicated by the data signal Vd [n] is the same, the current supplied from the transistor Ts is higher when the driving capability of the transistor Ts is higher than when the driving capability of the transistor Ts is low. growing.

In the present embodiment, in order to prevent the occurrence of an event that writing to the pixel PxR becomes insufficient and red R is not sufficiently displayed, the driving capability of the transistor TsR is higher than the driving capability of the transistor TsG, and Each transistor Ts is provided so as to be higher than the driving capability of the transistor TsB.
Specifically, as shown in FIG. 7, each transistor Ts is provided such that the channel length LR of the transistor TsR is shorter than the channel length LG of the transistor TsG and shorter than the channel length LB of the transistor TsB. Thus, the drive capability of the transistor TsR is made higher than the drive capability of the other transistors Ts (TsG, TsB).
In the present embodiment, each transistor Ts is provided such that the channel widths of the transistors TsR, TsG, and TsB are equal (substantially equal) channel widths W0. In the present embodiment, the N transistors Ts are provided so that their positions in the Y direction are equal (substantially equal) to each other.

  Thus, in this embodiment, in order to make the driving capability of the transistor TsR higher than the driving capability of the other transistors Ts (TsG, TsB), the interval between the adjacent data lines 34 as viewed from the data line 34R. The sum “DBR + DRG” is smaller than the sum “DRG + DGB” of the distance to the adjacent data line 34 as viewed from the data line 34G, and the sum of the distance to the adjacent data line 34 as viewed from the data line 34B “ Even if it is smaller than “DGB + DBR”, the writing of the data signal Vd [n] to the pixel PxR can be prevented from becoming insufficient compared to the other pixels Px (PxB, PxG). Therefore, it is possible to prevent the display from becoming uneven.

  Note that the driving capability of the transistor TsR is such that when the data signal Vd [n] indicates the same potential, the magnitude of the current supplied by the transistor TsR is the magnitude of the current supplied by the other transistors Ts (TsB, TsG). Is preferably set to be equal (substantially equal). In this case, the uniformity of display can be made higher.

  In the present embodiment, the area (width in the X direction) of the pixel PxG when viewed in plan is larger than the area of the pixel PxB and the area of the pixel PxR. Since the green G light has higher spectral sensitivity than the light of the pixel PxB and the light of the pixel PxR, the brightness of the entire display region 30 can be increased. In other words, the present embodiment can achieve both improvement of the overall brightness of the display area 30 and prevention of deterioration of display non-uniformity.

  In this embodiment, the width of the transistor TsR in the X direction, that is, the channel length LR of the transistor TsR is made shorter than the channel length LG of the transistor TsG and the channel length LB of the transistor TsB. In order to make the driving capability higher than that of the other transistors Ts (TsB, TsG), for example, by increasing the width in the Y direction of the transistor TsR, that is, the channel width of the transistor TsR, the driving capability of the transistor Ts. Compared with the case where the height is increased, the frame can be narrowed.

In this embodiment, the (k + 2) th column data line 34G shown in FIG. 7 is an example of a “first data line”, and the (k + 1) th column data line 34R is “second data”. The (k + 3) th column data line 34B is an example of a “third data line”, and the kth column data line 34B is an example of a “fourth data line”. .
In the following, the pixel Px provided corresponding to the first data line is referred to as “first pixel”, and the pixel Px provided corresponding to the second data line is referred to as “second pixel”. The pixel Px provided corresponding to the third data line may be referred to as a “third pixel”. In the following description, the transistor Ts provided corresponding to the first data line is referred to as a “first sampling transistor”, and the transistor Ts provided corresponding to the second data line is referred to as “second sampling line”. The transistor Ts which is referred to as a “transistor” and is provided corresponding to the third data line may be referred to as a “third sampling transistor”. In the following description, the data signal Vd [n] supplied to the first pixel by the first sampling transistor is referred to as a first data signal, and the data signal Vd [ n] may be referred to as a second data signal, and the data signal Vd [n] supplied by the third sampling transistor to the third pixel may be referred to as a third data signal.

That is, Expression (2) exemplifies that the interval between the second data line and the third data line is larger than the interval between the first data line and the fourth data line. Expression (4) exemplifies that the capacitance value of the capacitance parasitic on the second data line is larger than the capacitance value of the capacitance parasitic on the first data line.
That is, according to the present embodiment, since the interval between the second data line and the third data line is larger than the interval between the first data line and the fourth data line, the second data line Even if the capacitance value of the capacitance parasitic to the first data line is larger than the capacitance value of the capacitance parasitic to the first data line, the driving capability of the second sampling transistor provided corresponding to the second data line Is made higher than the driving capability of the first sampling transistor provided corresponding to the first data line, the data signal Vd [n] for the second pixel is written to the data signal for the first pixel. It can be prevented from becoming insufficient as compared with writing Vd [n], and the uniformity of display can be improved.

By the way, in the present embodiment, as shown in FIG. 7, by shortening the channel length LR of the transistor TsR, the driving capability of the transistor TsR is made higher than the driving capability of the other transistors Ts (TsB, TsG). The present invention is not limited to such an embodiment. That is, any means may be used as a specific means for making the driving ability of the transistor TsR higher than the driving ability of the other transistors Ts (TsG, TsB).
For example, as shown in FIG. 9, by setting the channel width WR of the transistor TsR to be longer than the channel width WG of the transistor TsG and the channel width WB of the transistor TsB, the driving capability of the transistor TsR can be increased. It may be higher than the driving capability of (TsB, TsG).
In this case, as shown in FIG. 9, the channel lengths of the transistors Ts may be equal lengths L0, and as shown in FIG. 7, the channel lengths L are different between the transistors TsR, TsG, and TsB. It may be a length.
In short, the value obtained by dividing the channel width of the transistor TsR by the channel length is larger than the value obtained by dividing the channel width of the transistor TsG by the channel length, and larger than the value obtained by dividing the channel width of the transistor TsB by the channel length. In this way, any transistor Ts may be provided.

Various transistors such as the transistor Ts may have an LDD (Lightly Doped Drain) structure. That is, as shown in FIG. 10, each transistor Ts includes an LDD region Ld1 (an example of a “first LDD region”) between the semiconductor layer 244 and the semiconductor layer 246, and the semiconductor layer 245 and the semiconductor layer An LDD region Ld2 (an example of a “second LDD region”) may be provided between the H.S.
In this case, in addition to adjusting at least one of the channel width and the channel length of the transistor Ts, or instead of adjusting at least one of the channel width and the channel length of the transistor Ts, the source region or the drain region of the transistor Ts By adjusting the sum “ΔLd1 + ΔLd2” of the length ΔLd1 of the LDD region Ld1 and the length ΔLd2 of the LDD region Ld2 in the direction from one to the other (an example of “channel length direction”) The ability may be adjusted.
More specifically, the sum of the length ΔLd1 and the length ΔLd2 in the transistor TsR is smaller than the sum of the length ΔLd1 and the length ΔLd2 in the transistor TsG, and the sum of the length ΔLd1 and the length ΔLd2 in the transistor TsB. By providing each transistor Ts so as to be smaller than that, the driving capability of the transistor TsR may be made higher than the driving capability of the other transistors Ts (TsB, TsG).

  The data line 34 in the first column is adjacent to only the data line 34 in the second column, and the data line 34 in the Nth column is adjacent to only the data line 34 in the (N−1) th column. Therefore, the capacitance value of the capacitance parasitic on each of the data lines 34 in the first column and the Nth column is larger than the capacitance of the capacitance parasitic on each of the data lines 34 in the second column to the (N−1) th column. ,small. For this reason, the driving capability of the transistor Ts corresponding to the first column and the driving capability of the transistor Ts corresponding to the Nth column are set to the transistor Ts corresponding to the data line 34 of the second column to the (N−1) th column. It may be made smaller than the driving ability.

<B: Modification>
The present invention is not limited to the above-described embodiments, and various modifications as described below are possible, for example. Moreover, the aspect of the deformation | transformation described below can also combine suitably arbitrarily selected 1 or several.

<Modification 1>
In the above-described embodiment, the N transistors Ts are arranged in one row in the X direction, and the N transistors Ts are arranged so that the positions in the X direction are different from each other. The N transistors Ts may be arranged in two rows or three rows or more in the X direction.

For example, as shown in FIG. 11, of the N transistors Ts, the transistors TsB, TsG, and TsR are arranged so as to be in different rows (that is, different positions in the Y direction). It may be.
In this case, as shown in FIG. 11, three transistors Ts (TsR, TsG, and TsB) corresponding to three data lines 34 continuous in the X direction are set as one set, and three transistors constituting each set The three transistors Ts (TsR, TsG, and TsB) may be arranged so that the positions in the X direction of Ts are equal to each other. In this case, as shown in FIG. 11, the driving capability of the transistor Ts may be adjusted by adjusting the channel width W of the transistor Ts.
As shown in FIG. 11, when the transistors TsB, TsG, and TsR are arranged at different positions (different rows) in the Y direction, N transistors Ts are arranged in one row (for example, Compared to the case shown in FIG. 7 or FIG. 9, the width in the X direction required for arranging the N transistors Ts can be reduced. As a result, the data lines 34 can be narrowed without any restriction on the width of the transistor Ts in the X direction.

Further, for example, as shown in FIG. 12, N transistors Ts may be arranged in two rows.
In the example shown in FIG. 12, the channel length LR of the transistor TsR is made shorter than the channel length LG of the transistor TsG and the channel length LB of the transistor TsB, so that the driving capability of the transistor TsR is changed to another transistor Ts (TsB , TsG). Therefore, in this case, by arranging the transistors TsB and TsG having a long channel length in different rows, the width in the X direction necessary for arranging the N transistors Ts can be reduced. As a result, it is possible to reduce the pitch of the data lines 34 without being restricted by the width of the transistor Ts in the X direction, and it is possible to reduce the frame as compared with the case shown in FIG. Become.
In the example shown in FIG. 12, the transistors TsR and TsG are arranged in one row and the transistor TsB is arranged in another row. However, the transistors TsR and TsB are arranged in one row and the transistor TsG is arranged. May be placed in other rows.

<Modification 2>
In the embodiment and the modification described above, the data line driving circuit 24 generates the data signals Vd [1] to Vd [N] by time-sharing one system of the image signal Vid. The data signals Vd [1] to Vd [N] may be generated based on a plurality of image signals Vid obtained by serial-parallel development (phase development) of the image signal Vid. . In the following, a case where N is a multiple of 6 and six image signals Vid1 to Vid6 obtained by serial-parallel development of the image signal Vid are supplied to the data line driving circuit will be described as an example.

FIG. 13 shows a block diagram of a data line driving circuit 24s according to this modification. As illustrated in FIG. 13, the data line driving circuit 24 s includes a shift register 241 s, six signal lines 242 a to 242 f, and connection wiring 243 s instead of including the shift register 241, the signal line 242, and the connection wiring 243. This is different from the data line driving circuit 24 shown in FIG. Each of the six signal lines 242a to 242f is supplied with six systems of image signals Vid1 to Vid6 obtained by serial-parallel development of the image signal Vid. The shift register 241 s divides one horizontal scanning period into at least (N ÷ 6) periods, and in order of each divided period, six N transistors Ts [1] to Ts [N] are sequentially ordered. Turn on. In other words, the shift register 241 s selects the selection signal X [s] among the selection signals Xs [1] to Xs [N ÷ 6] in the s-th period among (N ÷ 6) periods dividing one horizontal scanning period. ] Is set to the selected potential (where s is an integer satisfying 1 ≦ s ≦ (N ÷ 6)). When the selection signal Xs [s] is set to the selection potential, the six transistors Ts [6s-5] to Ts [6s] are turned on all at once, and each of the six signal lines 242a to 242f is The 6 data lines 34 from the 6s-5) th column to the (6s) th column are electrically connected. Thereby, for example, each of the data signals Vd [6s-5] to Vd [6s] corresponding to the image signals Vid1 to Vid6 on a one-to-one basis includes six (6s-5) th to (6s) th columns. Is output to each of the data lines 34.
As described above, in this modification, the data line driving circuit 24 s can supply the data signal Vd [n] to each data line 34 for about 6 times as long as the data line driving circuit 24. Therefore, sufficient writing can be performed for each pixel Px.

<Modification 3>
In the embodiment and the modification described above, the magnitude of the current supplied to each data line 34 is made uniform by adjusting the driving capability of the transistor Ts. However, the present invention is limited to such a mode. For example, in addition to adjusting the driving capability of the transistor Ts, the magnitude of the current supplied to each data line 34 is adjusted by adjusting the resistance value of the resistor Rs of each data line 34. May be made uniform.

  FIG. 14 is a block diagram of an electro-optical device 1a according to this modification. The electro-optical device 1a is different from the electro-optical device 1 shown in FIG. 2 in that a display panel 10a is provided instead of the display panel 10. The display panel 10a is provided with a resistor RsR in series with the data line 34R, a resistor RsG in series with the data line 34G, and a resistor RsB in series with the data line 34R. It is comprised similarly. Each of the resistors RsR, RsG, and RsB is provided in series with the data line 34 between the data line driving circuit 24 and the display region 30. More specifically, each of the resistors RsR, RsG, and RsB is connected from the connection point of the data line 34 to the relay node N1 of the pixel Px of the Mth row to the connection point of the semiconductor layer 244 of the transistor Ts. Are provided in series with the data line 34.

In this modification, the relationship shown in the following formula (5) is established among the resistance value of the resistor RsR, the resistance value of the resistor RsG, and the resistance value of the resistor RsB.
RsR <RsG≈RsB (5)
For this reason, even when the driving capability of the transistor TsR cannot be sufficiently increased, when the data signal Vd [n] indicates the same potential, the data line 34R is connected to the data line 34G and the data line 34B. It is possible to prevent a large current from being supplied. Thereby, the magnitude of the current supplied to each data line 34 can be made uniform, and the display can be made uniform.

<Modification 4>
In the embodiment and the modification described above, the electro-optical device 1 (or 1a) includes the pixel PxR, the pixel PxG, and the pixel PxB, and can display red R, green G, and blue B. The invention is not limited to such an embodiment, and the electro-optical device may be any device that can display at least two colors. Specifically, the electro-optical device may be capable of displaying colors other than red R, green G, and blue B, or part or all of red R, green G, and blue B. May not be displayed.
In the embodiment and the modification described above, the width of the pixel PxG in the X direction is larger than the width of the pixel PxR and the pixel PxG in the X direction. However, the present invention is not limited to such a mode. Among the two or more colors that can be displayed by the electro-optical device, the width in the X direction of the pixels Px corresponding to some colors is larger than the width in the X direction of the pixels Px corresponding to other colors If it is. The driving capability of the transistor Ts may be determined based on the interval between the data line 34 provided corresponding to the transistor Ts and the data line 34 adjacent to the data line 34.

  FIG. 15 is a plan view of a part of the display area of the electro-optical device according to this modification. As shown in this figure, the electro-optical device according to this modification includes a pixel PxG, a pixel PxB, a pixel PxR, and a pixel PxW that can display white W. More specifically, if q is an integer that is a multiple of 4 that satisfies 4 ≦ q, among the first to Nth columns, M rows of pixels PxG are arranged in the (q−3) th column, M rows of pixels PxB are arranged in the (q-2) -th column, M rows of pixels PxR are arranged in the (q-1) -th column, and M rows of pixels PxW are arranged in the q-th column. . In the following description, the data line 34 corresponding to the pixel PxW is represented by reference numeral “34W”. Further, the transistor Ts provided corresponding to the data line 34W is represented by the symbol “TsW”.

In this modification, the width of the pixel PxG, the pixel PxB, and the pixel PxR in the X direction is larger than the width of the pixel PxW in the X direction. That is, the interval DGB between the adjacent data lines 34G and 34B, the interval DBR between the adjacent data lines 34B and 34R, the interval DRW between the adjacent data lines 34R and 34W, and the adjacent data The distance DWG between the line 34W and the data line 34G satisfies the relationship of the following formula (6).
DWG <DGB ≒ DBR ≒ DRW (6)
Therefore, the following formulas (7) and (8) can be derived from the formula (6).
DGB + DBR> DWG + DGB (7)
DBR + DRW> DRW + DWG (8)
Therefore, except for the first column and the Nth column, the capacitance value of the capacitance CR parasitic on the data line 34R, the capacitance value of the capacitance CG parasitic on the data line 34G, the capacitance value of the capacitance CB parasitic on the data line 34B, and The following equation (9) is established between the capacitance values of the capacitance CW parasitic on the data line 34W.
CR ≒ CB> CG ≒ CW (9)

Therefore, in the present modification, each transistor Ts is provided such that the driving capability of the transistors TsG and TsW is higher than the driving capability of the transistors TsB and TsR.
Specifically, the value obtained by dividing the channel width of the transistor TsG by the channel length and the value obtained by dividing the channel width of the transistor TsW by the channel length are larger than the value obtained by dividing the channel width of the transistor TsB by the channel length. Further, by making the channel width of the transistor TsR larger than the value obtained by dividing the channel width by the channel length, the driving capability of the transistors TsG and TsW may be made higher than the driving capability of the transistors TsB and TsR. The sum of the length ΔLd1 and the length ΔLd2 and the sum of the length ΔLd1 and the length ΔLd2 in the transistor TsW is smaller than the sum of the length ΔLd1 and the length ΔLd2 in the transistor TsB and the length ΔLd1 in the transistor TsR. By making it smaller than the sum of the length ΔLd2, the transistor The driving capability of TsG and TSW, may be higher than the driving capability of the transistor TsB and TSR.
Thereby, it is possible to prevent the writing of the data signal Vd [n] to the pixel PxG and the pixel PxW from becoming insufficient compared to the writing of the data signal Vd [n] to the pixel PxB and the pixel PxR. It becomes possible to prevent the display from becoming uneven.

In the present modification, when the data line 34B is the “first data line”, the data line 34G adjacent to the data line 34B corresponds to the “second data line”, and the data line 34B The adjacent data line 34R corresponds to the “third data line”, and the data line 34W adjacent to the data line 34G adjacent to the data line 34B corresponds to the “fourth data line”. In this case, the pixel PxB corresponds to the “first pixel”, and the pixel PxG corresponds to the “second pixel”. In this case, the blue B displayed by the pixel PxB corresponds to the “first color”, and the green G displayed by the pixel PxG corresponds to the “second color”.
When the data line 34R is a “first data line”, the data line 34W adjacent to the data line 34R corresponds to the “second data line”, and the data line 34B adjacent to the data line 34R The data line 34G that corresponds to the “third data line” and that is adjacent to the data line 34W that is adjacent to the data line 34R corresponds to the “fourth data line”.

<Modification 5>
In the embodiment and the modification described above, M rows of pixels Px corresponding to one display color are arranged in one column in the display area 30, but the present invention is limited to such an aspect. Instead, the pixel Px corresponding to two or more display colors may be provided for one column.
For example, as illustrated in FIG. 16, q is an integer that is a multiple of 4 that satisfies 4 ≦ q, and among the first to Nth columns, the (q−3) th column includes a plurality of pixels PxB and a plurality of pixels PxB. Pixels PxR, a plurality of pixels PxB and a plurality of pixels PxR are arranged in the (q-2) -th column, and a plurality of pixels PxG and a plurality of pixels are arranged in the (q-1) -th column. PxW may be arranged, and a plurality of pixels PxG and a plurality of pixels PxW may be arranged in the q-th column.

In this figure, the distance D12 between the data line 34 [1] in the (q-3) th column, for example, the first column, and the data line 34 [2] in the (q-2) th column, for example, the second column. , The distance (D23) between the data line 34 [2] in the (q-2) th column, for example, the second column, and the data line 34 [3] in the (q-1) th column, for example, the third column, 1) The distance D34 between the data line 34 [3] in the column, for example the third column, and the data line 34 [4] in the qth column, for example the fourth column, and the data line in the qth column, for example the fourth column An interval D45 between 34 [4] and the (q + 1) -th column, for example, the data line 34 [5] in the fifth column satisfies the relationship of the following formula (10).
D12 ≒ D23 <D34 ≒ D45 ...... (10)
That is, the following formula (11) is established.
D12 + D23 <D23 + D34 <D34 + D45 (11)
That is, between the capacitance value of the capacitance C2 parasitic on the data line 34 [2], the capacitance value of the capacitance C3 parasitic on the data line 34 [3], and the capacitance value of the capacitance C4 parasitic on the data line 34 [4]. The following equation (12) is established.
C2>C3> C4 (12)

For this reason, in this modification, the driving capability of the transistor Ts corresponding to the data line 34 [2] is made higher than the driving capability of the transistor Ts corresponding to the data line 34 [3], and the data line 34 [3]. Is made higher than the driving capability of the transistor Ts corresponding to the data line 34 [4].
As a result, in the pixel PxB, the pixel PxR, the pixel PxG, and the pixel PxW, the pixel Px in which the writing of the data signal Vd [n] is insufficient is prevented from occurring, and the display becomes uneven. It becomes possible to prevent.

<Modification 6>
In the embodiment and the modification described above, the color filter corresponding to the display color displayed by each pixel Px is provided corresponding to each pixel Px. However, the present invention is not limited to such an aspect, A light source that emits light of a color corresponding to the display color displayed by the pixel Px may be provided corresponding to each pixel Px. In this case, the electro-optical device may not include a color filter.

<Modification 7>
In the embodiment and the modification described above, the pixel circuit 110 corresponding to the pixel Px includes the liquid crystal element CL and the transistor 112 as shown in FIGS. 3 to 5, but this is only an example, and the electro-optical device. The pixel circuit 110 included in may have any configuration.
For example, instead of the liquid crystal element CL, an organic light emitting diode, an inorganic light emitting diode, an LED (Light Emitting Diode), or the like may be provided. In this case, the substrate 150 may be made of a transparent insulating material such as glass or plastic, or may be a semiconductor substrate. The pixel circuit 110 may include an N-channel transistor instead of the P-channel transistor, or may include a plurality of transistors including one or both of the P-channel and N-channel transistors. It may be. In addition, the transistor included in the pixel circuit 110 may be a thin film transistor, or may be a MOS transistor when a semiconductor substrate is employed as the substrate 150.

<Modification 8>
In the embodiment and the modification described above, the entire data line driving circuit 24 (or 24s) is provided in the display panel 10 (or 10a), but a part of the data line driving circuit is provided in the display panel. The other part may be provided outside the display panel. For example, in the data line driver circuit, the transistor Ts may be provided in the display panel, and the shift register 241 (241s) may be provided outside the display panel.

<C: Application example>
Next, an electronic apparatus to which the electro-optical device according to the embodiment or the modification is applied will be described.
FIG. 17 is a diagram showing the external appearance of a head mounted display (HMD), and FIG. 18 is a diagram showing its optical configuration. First, as shown in FIG. 17, the head mounted display 300 has a temple 310, a bridge 320, and lenses 301L and 301R in the same manner as general glasses. Further, as shown in FIG. 18, the head mounted display 300 is in the vicinity of the bridge 320 and on the back side (lower side in the drawing) of the lenses 301L and 301R, the electro-optical device 1L for the left eye and the right eye. Electro-optical device 1R. The image display surface of the electro-optical device 1L is arranged on the left side in FIG. Accordingly, the display image by the electro-optical device 1L is emitted in the direction of 9 o'clock in the drawing through the optical lens 302L. The half mirror 303L reflects the display image by the electro-optical device 1L in the 6 o'clock direction, and transmits light incident from the 12 o'clock direction. The image display surface of the electro-optical device 1R is disposed on the right side opposite to the electro-optical device 1L. As a result, the display image by the electro-optical device 1R is emitted in the direction of 3 o'clock in the drawing through the optical lens 302R. The half mirror 303R reflects the display image by the electro-optical device 1R in the 6 o'clock direction, and transmits light incident from the 12 o'clock direction.
In this configuration, the wearer of the head mounted display 300 can observe the display image by the electro-optical devices 1L and 1R in a see-through state superimposed on the outside. Further, in the head-mounted display 300, when the left-eye image is displayed on the electro-optical device 1L and the right-eye image is displayed on the electro-optical device 1R among the binocular images with parallax, the wearer is notified. The displayed image can be perceived as if it had a depth or a stereoscopic effect (3D display).
FIG. 19 is a perspective view of a portable personal computer employing the electro-optical device according to the embodiment or the modification. The personal computer 400 includes the electro-optical device 1 that displays various images, and a main body 403 on which a power switch 401 and a keyboard 402 are installed.
FIG. 20 is a perspective view of a mobile phone to which the electro-optical device according to the embodiment or the modification is applied. The cellular phone 500 includes a plurality of operation buttons 501 and scroll buttons 502, and the electro-optical device 1 that displays various images. By operating the scroll button 502, the screen displayed on the electro-optical device 1 is scrolled.
Note that electronic devices to which the light emitting device according to the present invention is applied include, in addition to the devices illustrated in FIGS. 17 to 20, personal digital assistants (PDAs), digital still cameras, televisions, video cameras, cars Navigation devices, in-vehicle displays (instrument panels), electronic notebooks, electronic paper, calculators, word processors, workstations, videophones, POS terminals, printers, scanners, copiers, video players, devices with touch panels, etc. It is done.

DESCRIPTION OF SYMBOLS 1 ... Electro-optical device, 10 ... Display panel, 20 ... Drive circuit, 22 ... Scan line drive circuit, 24 ... Data line drive circuit, 30 ... Display area, 32 ... Scan line, 34 ... Data line 50... Control circuit 110 110 Pixel circuit 241 Shift register 242 Signal line 243 Connection wiring Ts Transistor Px Pixel CL Liquid crystal element

Claims (7)

A first data line;
A second data line extending along the first data line so as to be adjacent to the first data line;
A third data line extending along the first data line so as to be adjacent to the first data line opposite to the second data line;
A fourth data line extending along the second data line so as to be adjacent to the second data line on the side opposite to the first data line;
A first pixel provided corresponding to the first data line;
A second pixel provided corresponding to the second data line;
A first sampling transistor for supplying a first data signal to the first pixel via the first data line;
A second sampling transistor for supplying a second data signal to the second pixel via the second data line;
With
The distance between the second data line and the third data line is:
Greater than an interval between the first data line and the fourth data line;
The driving capability of the second sampling transistor is
Higher than the driving capability of the first sampling transistor;
An electro-optical panel characterized by that. The value obtained by dividing the channel width of the second sampling transistor by the channel length is:
Greater than the channel width of the first sampling transistor divided by the channel length;
The electro-optical panel according to claim 1. Each of the first sampling transistor and the second sampling transistor includes:
A source area,
A drain region;
A channel region provided between the source region and the drain region;
A first LDD region provided between the source region and the channel region;
A second LDD region provided between the drain region and the channel region;
With
In the channel length direction from the source region to the drain region,
The total length of the first LDD region and the second LDD region included in the first sampling transistor is equal to the length of the first LDD region and the second LDD region included in the second sampling transistor. Longer than the total length of the
The electro-optical panel according to claim 1 or 2. The electro-optical panel is
At least a first color and a second color can be displayed;
The first pixel is
Provided between the first data line and the third data line and capable of displaying the first color;
The second pixel is
Provided between the second data line and the first data line and capable of displaying the second color;
The first color light is
Spectral sensitivity is higher than the second color light,
The electro-optical panel according to any one of claims 1 to 3. An electro-optical panel capable of displaying a first color, a second color, and a third color,
A first data line;
A second data line extending along the first data line so as to be adjacent to the first data line;
A third data line extending along the first data line so as to be adjacent to the first data line opposite to the second data line;
A first pixel provided corresponding to the first data line and capable of displaying the first color;
A second pixel provided corresponding to the second data line and capable of displaying the second color;
A third pixel provided corresponding to the third data line and capable of displaying the third color;
A first sampling transistor for supplying a first data signal to the first pixel via the first data line;
A second sampling transistor for supplying a second data signal to the second pixel via the second data line;
A third sampling transistor for supplying a third data signal to the third pixel via the third data line;
With
The first pixel is
Provided between the first data line and the third data line;
The distance between the first data line and the third data line is:
Greater than an interval between the first data line and the second data line;
The driving capability of the second sampling transistor is
Higher than the driving capability of the first sampling transistor and higher than the driving capability of the third sampling transistor;
An electro-optical panel characterized by that. The wiring resistance of the first data line is
Higher than the wiring resistance of the second data line,
The electro-optical panel according to claim 1, wherein the electro-optical panel is any one of the above. An electronic apparatus comprising the electro-optical panel according to claim 1.

Images