JP7014217B2 - Electro-optics and electronic devices - Google Patents

Description

The present invention relates to an electro-optic device and an electronic device.

An electro-optical device having a display panel in which a light emitting element such as an OLED (Organic Light-emitting Diode) and a pixel circuit including a transistor are arranged corresponding to the position of a pixel where a scanning line and a data transfer line intersect is generally widespread. ing. In Patent Document 1, a circuit block that supplies a data signal according to a display gradation to pixel circuits adjacent to each other in the wiring direction of the scanning line (hereinafter, row direction) is provided with a circuit block in the wiring direction of the data transfer line (hereinafter, column direction). ) Is disclosed as a layout for arranging them side by side. Further, Patent Document 1 discloses that a shielded wire is arranged between data transfer lines in order to suppress crosstalk between adjacent data transfer lines.

Japanese Unexamined Patent Publication No. 2014-186125

In recent years, with the demand for higher definition for electro-optic devices, the pitch of pixels has been narrowed. As the pitch of the pixels becomes narrower, the arrangement interval of the data transfer lines in the row direction also becomes narrower, and it becomes difficult to arrange shielded lines between the data transfer lines. Unless shielded wires are arranged between the data transfer lines, crosstalk between adjacent data transfer lines cannot be sufficiently suppressed. As a result, the pixel circuit cannot be made to emit light with a desired color and brightness, and the display quality is deteriorated. That is, in the conventional electro-optic device, there is a trade-off relationship between narrowing the pitch of pixels and suppressing crosstalk, and there is a problem that the electro-optic device cannot be made high-definition without deteriorating the display quality. there were.

In order to solve the above problems, the electro-optical device according to the present invention has a first circuit that supplies a data signal according to a display gradation to a first pixel circuit via a first data transfer line, and the first data. The second circuit that supplies a data signal according to the display gradation to the second pixel circuit via the second data transfer line arranged alongside the transfer line, and the first circuit are connected to the first data transfer line. The first signal line, the second signal line connected to the second data transfer line in the second circuit, and the first circuit and the second circuit are arranged side by side in the direction of the first data transfer line. However, one of the first signal line and the second signal line is characterized in that at least a part thereof is formed in a wiring layer different from the other.

According to this aspect, since the first circuit and the second circuit are arranged side by side in the direction of the data transfer line (that is, the column direction), it is possible to cope with narrowing the pitch of pixels, that is, increasing the definition. Further, according to this aspect, at least one of the first signal line and the second signal line is formed in a wiring layer different from the other, so that the first signal line and the second signal line are separated. Crosstalk between the first signal line and the second signal line is suppressed as compared with the mode of wiring to one wiring layer. Therefore, according to this aspect, it is possible to avoid deterioration of display quality due to narrowing of the pixel pitch and crosstalk. That is, according to this aspect, it is possible to improve the definition of the electro-optic device without causing deterioration of the display quality.

The electro-optic device described above may be characterized in that one of the first data transfer line and the second data transfer line is formed in a wiring layer different from the other at least in part.

According to this aspect, one of the first data transfer line and the second data transfer line is formed in a wiring layer different from the other at least in part, so that the first data transfer line and the second data transfer line are formed. Between the first data transfer line and the second data transfer line, even if a shielded wire is not provided between the first data transfer line and the second data transfer line, as compared with the embodiment of wiring to one wiring layer. Cross talk is suppressed.

The electro-optical device described above includes a first wiring layer and a second wiring layer, the first data transfer line is shorter than the second data transfer line, and in the first circuit, the first data transfer line. And the first signal line is formed in the first wiring layer, while the second data transfer line is formed in the second wiring layer, and in the second circuit, the second data transfer line and the second data transfer line. The two signal lines may be formed on the first wiring layer, while the first signal line may be formed on the second wiring layer.

Also in this embodiment, crosstalk between the first data transfer line and the second data transfer line is suppressed even if a shield line is not provided between the first data transfer line and the second data transfer line, and the first signal Crosstalk between the first signal line and the second signal line is suppressed even if a shielded wire is not provided between the line and the second signal line.

The electro-optic device described above may be characterized by having a metal layer to which a first fixed potential is applied between the first wiring layer and the second wiring layer. According to this aspect, since the metal layer to which the first fixed potential is given acts as a shield, the cross between the first data transfer line and the second data transfer line is compared with the embodiment in which the metal layer is not provided. The talk is further suppressed, and the crosstalk between the first signal line and the second signal line is further suppressed.

The electro-optical device described above has a first holding capacity for holding a voltage corresponding to the display gradation of the first pixel circuit and a second holding capacity for holding a voltage corresponding to the display gradation of the second pixel circuit. It may be characterized by having an electrode layer formed together with the metal layer between the metal layer and the second wiring layer. According to this aspect, the electrode layer and the metal layer between the first wiring layer and the second wiring layer can also serve as a holding capacity, and it is not necessary to separately provide a holding capacity.

The electro-optical device described above has a first shielded wire to which a second fixed potential is given between the first signal line and the second signal line in the first wiring layer, and gives the second fixed potential. The second shielded wire may be provided between the first signal line and the second signal line in the second wiring layer. The first and second shielded wires shield one of the first signal line and the second signal line from the other. Therefore, according to this aspect, the crosstalk between the first signal line and the second signal line is further suppressed as compared with the embodiment in which the first shielded wire and the second shielded wire are not provided.

The electro-optic device described above may be characterized in that the first shielded wire and the second shielded wire are connected to each other via a relay electrode formed in the metal layer and the periphery thereof is insulated.

Further, the present invention can be conceived as an electronic device provided with the electro-optic device in addition to the electro-optic device. Electronic devices typically include display devices such as head-mounted displays (HMDs) and electronic viewfinders.

It is a perspective view which shows the structure of the electro-optic device 1 which concerns on embodiment of this invention. It is a figure which shows the electrical structure of an electro-optics apparatus 1. It is a figure which shows the configuration example of a pixel circuit 110, a level shift circuit LS, and a demultiplexer DM. It is a figure which shows the arrangement example of the pixel circuit 110 and the level shift circuit LS in the display panel 10. It is a figure which shows an example of the wiring from the demultiplexer DM to the pixel circuit 110 through the level shift circuit LS in the display panel 10. It is a figure which shows the wiring example of the data transfer line 14 and the feeding line 16 in a pixel circuit 110. It is a partial cross-sectional view of the display panel 10. It is a partial cross-sectional view of the display panel 10. It is a partial cross-sectional view of the display panel 10. It is a partial cross-sectional view of the display panel 10. It is a partial cross-sectional view of the display panel 10. It is a partial cross-sectional view of the display panel 10. It is a perspective view of the head-mounted display 300 which concerns on this invention. It is a perspective view of the personal computer 400 which concerns on this invention.

<A. Embodiment>
Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings. However, in each figure, the dimensions and scale of each part are appropriately different from the actual ones. Further, since the embodiments described below are suitable specific examples of the present invention, various technically preferable limitations are attached, but the scope of the present invention particularly limits the present invention in the following description. Unless otherwise stated, it is not limited to these forms.

FIG. 1 is a perspective view showing a configuration of an electro-optic device 1 according to an embodiment of the present invention. The electro-optic device 1 is a micro-display that displays an image on, for example, a head-mounted display.

As shown in FIG. 1, the electro-optic device 1 includes a display panel 10 and a control circuit 3 for controlling the operation of the display panel 10. The display panel 10 includes a plurality of pixel circuits and a drive circuit for driving the pixel circuits. In the present embodiment, the plurality of pixel circuits and drive circuits included in the display panel 10 are formed on a silicon substrate, and an OLED, which is an example of an electro-optical element, is used for the pixel circuit. Further, the display panel 10 is housed in, for example, a frame-shaped case 82 opened at the display unit, and one end of an FPC (Flexible Printed Circuits) substrate 84 is connected to the display panel 10. A semiconductor chip control circuit 3 is mounted on the FPC substrate 84 by COF (Chip On Film) technology, and a plurality of terminals 86 are provided and connected to a higher-level circuit (not shown).

FIG. 2 is a block diagram showing the configuration of the electro-optic device 1 according to the embodiment. As described above, the electro-optic device 1 includes a display panel 10 and a control circuit 3. Digital image data Video is supplied to the control circuit 3 in synchronization with the synchronization signal from a higher-level circuit (not shown). Here, the image data Video is data that defines, for example, 8 bits the display gradation of the pixels of the image to be displayed on the display panel 10 (strictly speaking, the display unit 100 described later). The synchronization signal is a signal including a vertical synchronization signal, a horizontal synchronization signal, and a dot clock signal.

The control circuit 3 generates various control signals based on the synchronization signal and supplies them to the display panel 10. Specifically, the control circuit 3 includes control signals Ctr1 to Ctr3, Gini, / Gini, Gcpl, / Gcpl, Cell (1), Cell (2), Cell (3), / Cell (1), / Cell ( 2), / Self (3) are supplied to the display panel 10. Each of the control signal Ctr1 to the control signal Ctr3 is a signal including a plurality of signals such as a pulse signal, a clock signal, and an enable signal. The control signal Gini is a positive logic control signal, and the control signal / Gini is a negative logic control signal having a logic inversion relationship with the control signal Gini. The control signal Gcpl is also a positive logic control signal, and the control signal / Gcpl is a negative logic control signal having a logic inversion relationship with the control signal Gcpl. The control signal / Self (1) has a logical inversion relationship with the control signal Self (1). Similarly, the control signal / Self (2) has a logical inversion relationship with the control signal Self (2), and the control signal / Self (3) has a logical inversion relationship with the control signal Self (3). The control signals Self (1), Ser (2), and Cell (3) are collectively referred to as control signals Self, and the control signals / Cell (1), / Ser (2), and / Self (3) are referred to as control signals. It may be collectively referred to as / Sel. The voltage generation circuit 31 receives power from a power supply circuit (not shown) and supplies the reset potential Vost, the initial potential Vini, and the like to the display panel 10.

Further, the control circuit 3 generates an analog image signal Video based on the image data Video. Specifically, the control circuit 3 is provided with a look-up table that stores the potential indicated by the image signal Vid and the luminance of the electro-optical element included in the display panel 10 in association with each other. Then, by referring to the look-up table, the control circuit 3 generates an image signal Vid indicating a potential corresponding to the brightness of the electro-optical element defined in the image data Video, and displays this on the display panel 10. Supply.

As shown in FIG. 2, the display panel 10 includes a display unit 100 and a drive circuit (scanning line drive circuit 4 and data transfer line drive circuit 5) for driving the display unit 100. In the present embodiment, the drive circuit is divided into a scanning line drive circuit 4 and a data transfer line drive circuit 5, but these may be integrated into one circuit to form a drive circuit. As shown in FIG. 2, in the display unit 100, pixel circuits 110 corresponding to pixels of an image to be displayed are arranged in a matrix. Although detailed illustration is omitted in FIG. 2, the scanning line 12 of row M is provided so as to extend in the horizontal direction (X direction) in the figure, and is grouped by three columns. The data transfer line 14 in the (3N) column is provided so as to extend in the vertical direction (Y direction) in the figure. Each scanning line 12 and each data transfer line 14 are provided so as to maintain electrical insulation from each other. The pixel circuit 110 is provided corresponding to the intersection of the scanning line 12 in the M row and the data transfer line 14 in the (3N) column. Therefore, in the present embodiment, the pixel circuits 110 are arranged in a matrix of vertical M rows × horizontal (3N) columns.

Here, M and N are both natural numbers. In order to distinguish rows (rows) from the matrix of the scanning line 12 and the pixel circuit 110, they may be referred to as 1, 2, 3, ..., (M-1), and M rows in order from the top in the figure. Similarly, in order to distinguish the columns of the matrix of the data transfer line 14 and the pixel circuit 110, they may be referred to as 1, 2, 3, ..., (3N-1), (3N) columns in order from the left in the figure. be. Here, in order to generalize and explain the group of the data transfer line 14, if any integer of 1 or more is represented as n, the nth group counted from the left is the (3n-2) column, ( It means that the data transfer lines 14 in the 3n-1) th column and the (3n) th column belong to it. The three pixel circuits 110 corresponding to the scanning lines 12 in the same row and the data transfer lines 14 in three columns belonging to the same group correspond to the pixels of R (red), G (green), and B (blue), respectively. Then, these three pixels represent one dot of the color image to be displayed. That is, in the present embodiment, the color of one dot is expressed by additive color mixing by emitting light of the OLED corresponding to RGB.

Further, as shown in FIG. 2, the feeder line 16 of the (3N) row is provided on the display unit 100 so as to extend in the vertical direction and maintain electrical insulation from each scanning line 12. A predetermined reset potential Voltage is commonly supplied to each feeder line 16 from the voltage generation circuit 31. In order to distinguish the rows of the feeder lines 16, the feeder lines 16 in the first, second, third, ..., (3N) rows may be referred to in order from the left in the figure. Each of the feeder lines 16 in the first row to the (3N) row is provided corresponding to the data transfer line 14 in the first row to the (3N) row. As shown in FIG. 2, a capacity 50 is provided between the feeder line 16 in the jth column (j = 1 to 3N) and the data transfer line 14 in the jth column. The capacitance 50 may be a parasitic capacitance generated between the feeder line 16 and the data transfer line 14. Alternatively, one electrode connected to the feeder line 16 and the other electrode connected to the feeder line 16 may be arranged so as to face each other, and the capacitance 50 may be formed by the one electrode and the other electrode. good.

The scanning line drive circuit 4 generates a scanning signal Gwr for sequentially selecting the scanning lines 12 of M lines line by line within one frame period according to the control signal Ctr1. In FIG. 2, the scanning signals Gwr supplied to the scanning lines 12 on the first, second, third, ..., Mth lines are Gwr (1), Gwr (2), Gwr (3), ..., Gwr (M-), respectively. 1), it is written as Gwr (M). In addition to the scanning signals Gwr (1) to Gwr (M), the scanning line drive circuit 4 generates various control signals synchronized with the scanning signal Gwr line by line and supplies them to the display unit 100. In FIG. 2, the illustration is omitted. The frame period is the period required for the electro-optic device 1 to display an image for one cut (frame). For example, if the frequency of the vertical synchronization signal included in the synchronization signal is 120 Hz, it is for one cycle. The period is 8.3 milliseconds.

As shown in FIG. 2, the data transfer line drive circuit 5 includes (3N) level shift circuits LS provided one-to-one with each of the data transfer lines 14 in the (3N) column, and each group. It includes N demultiplexers DM provided for each of the three rows of data transfer lines 14 and a data signal supply circuit 70.

The data signal supply circuit 70 generates data signals Vd (1), Vd (2), ..., Vd (N) based on the image signal Vid supplied from the control circuit 3 and the control signal Ctr2. That is, the data signal supply circuit 70 is based on the image signal Vid in which the data signals Vd (1), Vd (2), ..., Vd (N) are time-division-multiplexed, and the data signals Vd (1), Vd (2) , ..., Vd (N) is generated. Then, the data signal supply circuit 70 transmits the data signals Vd (1), Vd (2), ..., Vd (N) to the demultiplexer DM corresponding to the 1, 2, ..., Nth group. Supply each.

The configuration of the pixel circuit 110, the level shift circuit LS, and the demultiplexer DM will be described with reference to FIG. In order to generally indicate the rows arranged by the pixel circuit 110, any integer of 1 or more and M or less is represented as m. Since each pixel circuit 110 has the same electrical configuration as each other, here, the pixel circuit in the m-row (3n-2) column is located in the m-th row and the (3n-2) column. 110 will be described as an example. A scanning signal Gwr (m), a control signal Gcmp (m), a Gel (m), and a Gorst (m) are supplied from the scanning line drive circuit 4 to the pixel circuit 110 on the m-th row.

In FIG. 3, the pixel circuit 110 in the m row (3n-2) column is indicated by the code “110 (m, 3n-2)”, and the data transfer line 14 in the (3n-2) column is represented by the code “14”. (3n-2) ”. Further, in FIG. 3, the level shift circuit LS connected to the data transfer line 14 (3n-2) is indicated by the reference numeral “LS (3n-2)” and is connected to the level shift circuit LS (3n-2). The demultiplexer DM to be used is indicated by the reference numeral "DM (n)". The pixel circuit 110 (m, 3n-2) is connected to the data transfer line 14 (3n-2). A gradation voltage corresponding to the display gradation is supplied to the pixel circuit 110 (m, 3n-2) via the data transfer line 14 (3n-2) of the connection destination. The pixel circuit 110 (m, 3n-2) includes a first transistor 121, a second transistor 122, a third transistor 123, a fourth transistor 124, a fifth transistor 125, and an OLED 130, which are P-channel MOS type transistors, respectively. Includes a pixel capacity of 132. Hereinafter, the first transistor 121, the second transistor 122, the third transistor 123, the fourth transistor 124, and the fifth transistor 125 may be collectively referred to as "transistors 121 to 125".

The gate of the second transistor 122 is electrically connected to the scanning line 12 (in the case of the pixel circuit 110 (m, 3n-2), the scanning line 12 on the mth line). Further, one of the source and drain of the second transistor 122 is electrically connected to the data transfer line 14 (in the case of the pixel circuit 110 (m, 3n-2), the data transfer line 14 (3n-2)), and the other is electrically connected. The gate of the first transistor 121 and one electrode of the pixel capacitance 132 are electrically connected to each other. The second transistor 122 functions as a switching transistor that controls the electrical connection between the gate of the first transistor 121 and the data transfer line 14 (3n-2).

The drain of the first transistor 121 is electrically connected to the feeder line 116. A potential Vel on the higher side of the power supply in the pixel circuit 110 is supplied to the feeder line 116 from a power supply circuit (not shown). The first transistor 121 functions as a drive transistor for passing a current corresponding to the voltage between the gate and the drain to the OLED 130.

One of the source or drain of the third transistor 123 is electrically connected to the gate of the first transistor 121, and the other is electrically connected to the source of the first transistor. A control signal Gcmp (m) is given to the gate of the third transistor 123. The third transistor 123 is a transistor for conducting conduction between the gate and the source of the first transistor 121. That is, the third transistor 123 functions as a switching transistor that controls the electrical connection between the gate and the source of the first transistor 121.

The drain of the fourth transistor 124 is electrically connected to the source of the first transistor 121, and the source of the fourth transistor 124 is electrically connected to the anode of the OLED 130. A control signal Gel (m) is given to the gate of the fourth transistor 124. The fourth transistor 124 functions as a switching transistor that controls the electrical connection between the source of the first transistor 121 and the anode of the OLED 130.

One of the source and drain of the fifth transistor 125 is electrically connected to the feeder line 16 in the (3n-2) row (hereinafter referred to as the feeder line 16 (3n-2)), that is, the potential line for feeding the reset potential Vost. The other is connected to the anode of the OLED 130. A control signal Gost (m) is supplied to the gate of the fifth transistor 125. The fifth transistor 125 functions as a switching transistor that controls the electrical connection between the feeder line 16 (3n-2) and the anode of the OLED 130.

Since the display panel 10 is formed on a silicon substrate in this embodiment, the substrate potential of the transistors 121 to 125 is set to the potential Vel. Further, the source and drain of the transistors 121 to 125 in the above may be replaced depending on the relationship between the channel type and the potential of the transistors 121 to 125. Further, the transistor may be a thin film or a field effect transistor.

In the pixel capacitance 132, one electrode is electrically connected to the gate of the first transistor 121, and the other electrode is electrically connected to the feeder line 116. Therefore, the pixel capacity 132 functions as a holding capacity for holding the voltage between the gate and drain of the first transistor 121. As the pixel capacitance 132, a capacitance parasitic on the gate of the first transistor 121 may be used, or a capacitance formed by sandwiching an insulating layer between different conductive layers on a silicon substrate may be used.

The anode of the OLED 130 is a pixel electrode individually provided for each pixel circuit 110. On the other hand, the cathode of the OLED 130 is a common electrode commonly provided over all of the pixel circuits 110 and is connected to the feeder line 63. A potential Vct, which is a fixed potential, is supplied to the feeder line 63. Here, the potential Vct may correspond to the L level of the scanning signal or the control signal which is a logic signal. The OLED 130 is an element in which a white organic EL layer is sandwiched between an anode of the OLED 130 and a cathode having light transmission in the silicon substrate. Then, a color filter corresponding to any of RGB is superimposed on the emission side (cathode side) of the OLED 130. The optical distance between the two reflection layers arranged so as to sandwich the white organic EL layer may be adjusted to form a cavity structure, and the wavelength of the light emitted from the OLED 130 may be set. In this case, it may or may not have a color filter.

When a current flows from the anode to the cathode of the OLED 130, the holes injected from the anode and the electrons injected from the cathode recombine in the organic EL layer to generate excitons, and white light is generated. The white light generated at this time passes through the cathode on the opposite side of the silicon substrate (anode), is colored by a color filter, and is visually recognized by the observer.

As shown in FIG. 3, the demultiplexer DM (n) is an aggregate of transmission gates 34 provided for each column, and data signals are sequentially supplied to the three columns constituting each group. The input ends of the transmission gates 34 corresponding to the rows (3n-2), (3n-1), and (3n) belonging to the nth group are commonly connected to each other, and the data signal Vd (n) is connected to the common terminals, respectively. Will be supplied. The output end of the transmission gate 34 corresponding to the (3n-2) column is connected to the level shift circuit LS (3n-2) via the signal line 140 (3n-2). Although detailed illustration is omitted in FIG. 3, the output end of the transmission gate 34 corresponding to the (3n-1) column is connected to the level shift circuit LS (3n-1) via the signal line 140 (3n-1). The output end of the transmission gate 34 corresponding to the (3n) column is connected to the level shift circuit LS (3n) via the signal line 140 (3n). The transmission gate 34 provided in the leftmost column (3n-2) in the nth group is when the control signal Ser (1) is at the H level (when the control signal / Self (1) is at the L level). ) Turns on (conducts). Similarly, in the nth group, the transmission gate 34 provided in the (3n-1) column, which is the central column, has an L level when the control signal Self (2) is H level (control signal / Self (2) is L level. (When) is turned on, and the transmission gate 34 provided in the (3n) column, which is the rightmost column in the nth group, is set when the control signal Cell (3) is at the H level (control signal / Ser (3)). Turns on when is at L level).

The level shift circuit LS (3n-2) has holding capacities 41 and 44, a transmission gate 42, an N-channel MOS type transistor 43, and a P-channel MOS type transistor 45, and has a 3n-2 row transmission gate. It shifts the potential of the data signal output from the output end of 34. One end of the holding capacity 44 is connected to the data transfer line 14 (3n-2) of the corresponding column and the drain of the transistor 45, while the other end of the holding capacity 44 is the output end of the transmission gate 42 and the transistor 43. Connected to the drain.

The source of the transistor 45 is connected to a feeder line 61 to which a predetermined initial potential Vini is supplied. The control circuit 3 supplies a control signal / Gini to the gate of the transistor 45. The transistor 45 electrically connects the data transfer line 14 (3n-2) and the feeder line 61 when the control signal / Gini is at the L level, and is electrically disconnected when the control signal / Gini is at the H level. And.

The source of the transistor 43 is connected to the feeder line 62 to which the potential Vref is supplied. A control signal Gref is supplied to the gate of the transistor 43. The transistor 43 electrically connects the other end of the holding capacity 44 and the feeder line 62 when the control signal Gref is at H level, and is electrically disconnected when the control signal Gref is at L level.

One electrode of the holding capacity 41 is connected to the signal line 140 (3n-2), and the signal line 140 (3n-2) is electrically connected to the input end of the transmission gate 42. The other electrode of the holding capacity 41 in each row is commonly connected to the feeder line 64. A potential VSS, which is a fixed potential, is supplied to the feeder line 64. Here, the potential VSS may correspond to the L level of the scanning signal or the control signal which is a logic signal. When the transmission gate 34 is turned on, the data signal Vd (j) is supplied from the output end of the transmission gate 34 to one of the electrodes of the holding capacity 41 via the signal line 140 (3n-2). That is, the data signal Vd (j) is supplied to one of the electrodes of the holding capacity 41. A control signal Gcpl and a control signal / Gcpl are supplied to the transmission gate 42 from the control circuit 3. The transmission gate 42 is turned on when the control signal Gcpl is at the H level (when the control signal / Gcpl is at the L level).

FIG. 4 shows the pixel circuit 110 (pixel circuit 110 (m, 3n-2), 110 (m, 3n-1) and 110 (m, 3n)) on the mth row belonging to the nth group, and the level shift circuit. It is a figure which shows the arrangement example in the display panel 10 of LS (3n-2), LS (3n-1) and LS (3n). As shown in FIGS. 2, 3 and 4, the level shift circuits LS (3n-2), LS (3n-1) and LS (3n) are located between the display unit 100 and the demultiplexer DM (n). Arranged side by side in the column direction. More specifically, the level shift circuits LS (3n), LS (3n-1), and LS (3n-2) are arranged in this order in the direction from the demultiplexer DM (n) toward the display unit 100. In the present embodiment, the level shift circuits LS (3n), LS (3n-1) and LS (3n-2) are arranged in order from the demultiplexer DM (n) toward the display unit 100, but the level shift is performed. Circuits LS (3n-2), LS (3n-1) and LS (3n) may be in this order. In short, the level shift circuits LS (3n-2), LS (3n-1) and LS (3n) may be arranged side by side in the column direction between the display unit 100 and the demultiplexer DM (n). The arrangement order of the level shift circuits LS (3n-2), LS (3n-1) and LS (3n) does not matter. Hereinafter, the side far from the display unit 100 in the column direction (Y direction) is referred to as “upstream side”, and the side closer to the display unit 100 is referred to as “downstream side”.
As shown in FIG. 4, in the present embodiment, the length of each of the pixel circuits 110 (m, 3n-2), 110 (m, 3n-1) and 110 (m, 3n) in the X direction is W1. , The length of each of the level shift circuits LS (3n-2), LS (3n-1) and LS (3n) in the X direction is W2. As shown in FIG. 4, the magnitude relationship between W1 and W2 is W1 <W2 <3 × W1, and each of the level shift circuits LS (3n-2), LS (3n-1), and LS (3n). The length in the Y direction is longer than W2.
As shown in FIGS. 2 and 3, for the level shift circuits LS (3n-2), LS (3n-1) and LS (3n), the display unit 100 corresponds to the pixel circuit 110 belonging to the nth group. It needs to be placed between the demultiplexer DM (n) and the demultiplexer DM (n). However, since W1 <W2, the level shift circuits LS (3n-2), LS (3n-1), and LS (3n) cannot be arranged side by side in the row direction (X direction). In the present embodiment, since W2 <3 × W1, if the level shift circuits LS (3n-2), LS (3n-1) and LS (3n) are arranged in the column direction, the level shift circuit LS (3n) -2), LS (3n-1) and LS (3n) can be arranged between the display unit 100 and the demultiplexer DM (n). Therefore, in the present embodiment, as shown in FIG. 4, the level shift circuits LS (3n-2), LS (3n-1), and LS (3n) are arranged in the column direction (Y direction) on the upstream side of the display unit 100. That is, they are provided side by side in the direction of the data transfer line 14.

FIG. 5 shows pixel circuits 110 (m, 3n-2), 110 (m, 3n-1) and 110 (from each of the level shift circuits LS (3n-2), LS (3n-1) and LS (3n). It is a figure which shows an example of the wiring which reaches each of m, 3n). In FIG. 5, one of the two transistors forming the transmission gate 42 (specifically, N) among the components of the level shift circuits LS (3n-2), LS (3n-1), and LS (3n). Only the channel transistor) is shown. Further, in FIG. 5, in order to avoid complication of the drawing, the level shift circuit LS (3n-2) has a reference numeral LSR, the level shift circuit LS (3n-1) has a reference numeral LSG, and the level shift circuit LS (3n) has a reference numeral LSG. ) Is indicated by the symbol LSB. Similarly, for the pixel circuit 110, the pixel circuit 110 (m, 3n-2) has a reference numeral 110R, the pixel circuit 110 (m, 3n-1) has a reference numeral 110G, and the pixel circuit 110 (m, 3n) has a reference numeral 110R. It is shown by 110B respectively. Similarly, for the data transfer line 14, the data transfer line 14 (3n-2) is indicated by the reference numeral 14R, the data transfer line 14 (3n-1) is indicated by the reference numeral 14G, and the data transfer line 14 (3n) is indicated by the reference numeral 14B. Has been done. Similarly, for the feeder line 16, the feeder line 16 (3n-2) is indicated by the reference numeral 16R, the feeder line 16 (3n-1) is indicated by the reference numeral 16G, and the feeder line 16 (3n) is indicated by the reference numeral 16B. There is.

FIG. 6 is a diagram showing a wiring example of the data transfer line 14R and the feeding line 16R in the pixel circuit 110R. In FIG. 6, of the five transistors included in the pixel circuit 110R, the second transistor 122 in which the source or drain is connected to the data transfer line 14R and the fifth transistor in which the source or drain is connected to the feeder line 16R. Only 125 are schematically shown. The data transfer line 14R extends in the Y direction over the plurality of pixel circuits 110 in the (3n-2) row, and the feeder line 16R also extends in the Y direction over the plurality of pixel circuits 110 in the (3n-2) row. It extends along. As shown in FIG. 6, in the display unit 100, the feeder line 16R is formed in parallel with the data transfer line 14R at a predetermined interval from the data transfer line 14R, and is reset to the feed line 16R as a second fixed potential. The potential Reset is given. Therefore, the feeder line 16R serves as a shielded wire that shields the data transfer line 14R. Similarly, the feeder line 16G is formed parallel to the data transfer line 14G with a predetermined interval from the data transfer line 14G, and the feeder line 16B is formed with a predetermined interval from the data transfer line 14B with the data transfer line 14B. It is formed in parallel. Therefore, the feeder line 16G serves as a shielded wire that shields the data transfer line 14G, and the feeder line 16B serves as a shielded wire that shields the data transfer line 14B.

7A, 7B, 8B, 9, 10 and 11 each along the AA'line, aa' line, BB' line, CC'line, DD' line, and EE' line in FIG. It is a cross-sectional view. In FIGS. 5 to 11, the signal line 140 from the demultiplexer DM (n) to the level shift circuit LSR is indicated by reference numeral 140R. Similarly, the signal line 140 from the demultiplexer DM (n) to the level shift circuit LSG is indicated by reference numeral 140G, and the signal line 140 from the level shift circuit LSB) is indicated by reference numeral 140B.

As shown in FIGS. 7A to 11, the silicon substrate on which the display panel 10 is formed has a first layer S1, a second layer S2, a third layer S3, and a fourth layer S4, which are metal layers, respectively. Note that FIG. 7A omits the illustration of the fourth layer S4. An insulating inorganic material such as a silicon compound (typically silicon nitride or silicon oxide) is filled between the second layer S2 and the third layer S3, and between the third layer S3 and the fourth layer S4. Will be done. Although the details will be described later, a signal line 180 connected to one of the two transistors forming the transmission gate 42 is formed on the first layer S1. A control signal Gcpl is given to the signal line 180 from the control circuit 3. The first fixed potential VSS is given to the portion of the first layer S1 other than the signal line 180. The first fixed potential VSS is also given to the third layer S3. The first fixed potential VSS and the reset potential Worst, which is the second fixed potential described above, may be equal.

The second layer S2 and the fourth layer S4 are wiring layers in which wiring is formed from the demultiplexer DM (n) to each of the pixel circuits 110R, 110G and 110B via the level shift circuits LSR, LSG and LSB. Play a role. As shown in FIG. 7A, the signal line 140R, the signal line 140G, and the signal line 140B are formed in the second layer S2 in the vicinity of the cutting line AA'. More specifically, as shown in FIGS. 5 and 7A, in the vicinity of the cutting line AA', the feeder line 16R is provided on the second layer S2 along the signal line 140R, and the feeder line 16G is provided along the signal line 140G. However, the feeder line 16B is formed along the signal line 140B. The feeder 16R serves as a shielded wire that shields the signal line 140R, the feeder 16G serves as a shielded wire that shields the signal line 140G, and the feeder 16B serves as a shielded wire that shields the data transfer line 14B. Fulfill. Further, as is clear from comparing FIGS. 8 to 11 with FIG. 7A, an electrode layer 190 is formed between the fourth layer S4 and the third layer S3 in the vicinity of the cutting line AA'. In the present embodiment, the holding capacity 41 is formed by the electrode layer 190 and the third layer S3.

As shown in FIG. 7B, the signal line 140R is drawn from the second layer S2 to the fourth layer S4 via the relay electrode 160R (see FIG. 5) formed in the third layer S3 and the periphery thereof is insulated, and downstream. It extends to the side. Similarly, the signal line 140G is drawn from the second layer S2 to the fourth layer S4 via the relay electrode 160G formed in the third layer S3 and the periphery thereof is insulated, and extends to the downstream side. Further, the feeder line 16R is drawn from the second layer S2 to the fourth layer S4 via the relay electrode 161R formed in the third layer S3 and the periphery thereof is insulated, and extends to the downstream side. Similarly, the feeder line 16G is drawn from the second layer S2 to the fourth layer S4 via the relay electrode 161G formed in the third layer S3 and the periphery thereof is insulated, and extends to the downstream side.

Since the feed line 16R and the feeder line 16G are given a reset potential Vorst which is a second fixed potential, the feeder line 16R and the feeder line 16G function as shielded wires. If the feeder line 16G upstream of the cutting line aa'is the first shielded wire and the feeder line 16G downstream of the cutting wire aa' is the second shielded wire, the first shielded wire to which the second fixed potential is given is the first shielded wire. It is located between the signal line 140R and the signal line 140G in the second layer S2 corresponding to one wiring layer. Further, the second shielded wire to which the second fixed potential is given is located between the signal line 140R and the signal line 140G in the fourth layer S4 corresponding to the second wiring layer. That is, the first shielded wire and the second shielded wire shield between the signal line 140R corresponding to the first signal line and the signal line 140G corresponding to the second signal line.
Further, the feeder line 16G formed in the second layer S2 which is the first shielded wire and the feeder line 16G formed in the fourth layer S4 which is the second shielded wire are formed in the third layer S3 which is a metal layer. It is connected via a relay electrode 161G whose perimeter is insulated.

As shown in FIG. 8, the fourth layer S4 is formed with a feeder line 16R that shields the signal line 140R and a feeder line 16G that shields the signal line 140G. The feeder line 16R and the feeder line 16G formed on the fourth layer S4 function as shielded wires. The signal line 140B extends toward the level shift circuit LSB in the second layer S2 and is connected to the input end of the transmission gate 42 in the level shift circuit LSB as shown in FIGS. 5 and 8. As shown in FIGS. 5 and 8, a data transfer line 14B formed in the second layer S2 and extending toward the downstream side is connected to the output end of the transmission gate 42 of the level shift circuit LSB.

The signal line 140G drawn out to the fourth layer S4 via the relay electrode 160G (see FIG. 5) and extending to the downstream side is a relay electrode 162G (see FIG. 5) formed in the third layer S3 and whose surroundings are insulated. It is drawn into the second layer S2 via the above and extends to the downstream side. The signal line 140G drawn into the second layer S2 via the relay electrode 162G and extending to the downstream side is connected to the input end of the transmission gate 42 in the level shift circuit LSG as shown in FIGS. 5 and 9. As shown in FIGS. 5 and 9, a data transfer line 14G formed in the second layer S2 and extending toward the downstream side is connected to the output end of the transmission gate 42 of the level shift circuit LSG. The data transfer line 14G extending toward the downstream side in the second layer S2 reaches the pixel circuit 110G (see FIG. 5). The feeder line 16G extending to the downstream side in the fourth layer S4 is drawn into the second layer S2 via the relay electrode 163G (see FIG. 5) formed in the third layer S3 and insulated from the surroundings, and goes to the pixel circuit 110G. Reach (see Figure 5). The data transfer line 14B extending to the downstream side in the second layer S2 is drawn out to the fourth layer S4 via the relay electrode 162B (see FIG. 5) formed in the third layer S3 and insulated from the periphery, and is drawn to the downstream side. Extends to. The feeder line 16B extending to the downstream side in the second layer S2 is drawn out to the fourth layer S4 via the relay electrode 163B formed in the third layer S3 and the periphery thereof is insulated, and extends to the downstream side (FIG. FIG. 5).

The signal line 140R drawn to the fourth layer S4 via the relay electrode 160R and extending to the downstream side is the second through the relay electrode 164R (see FIG. 5) formed in the third layer S3 and the periphery thereof is insulated. It is drawn into the layer S2 and extends downstream. The signal line 140R drawn into the second layer S2 via the relay electrode 164R and extending to the upstream side is connected to the input end of the transmission gate 42 of the level shift circuit LSR as shown in FIGS. 5 and 10. .. A data transfer line 14R formed in the second layer S2 and extending toward the downstream side is connected to the output end of the transmission gate 42 of the level shift circuit LSR (see FIGS. 5 and 10). The data transfer line 14R extends downstream in the second layer S2 and reaches the pixel circuit 110R (see FIG. 5). The feeder line 16R, which is drawn out to the fourth layer S4 via the relay electrode 161R and extends to the downstream side, is also formed in the third layer S3 and the surroundings are insulated via the relay electrode 165R (see FIG. 5). It is drawn into the layer S2, extends downstream in the second layer S2, and reaches the pixel circuit 110R.

As shown in FIGS. 5 and 11, the data transfer line 14B drawn out to the fourth layer S4 via the relay electrode 162B and extending to the downstream side is formed in the third layer S3 and the periphery thereof is insulated. It is drawn into the second layer S2 via the relay electrode 166B. The data transfer line 14B drawn into the second layer S2 via the relay electrode 166B extends downstream and reaches the pixel circuit 110B (see FIG. 5). As shown in FIGS. 5 and 11, the feeder line 16B drawn out to the fourth layer S4 via the relay electrode 163B and extending to the downstream side is also a relay formed in the third layer S3 and the periphery thereof is insulated, as shown in FIGS. 5 and 11. It is drawn into the second layer S2 via the electrode 167B. The feeder line 16B drawn into the second layer S2 via the relay electrode 167B extends downstream and reaches the pixel circuit 110B (see FIG. 5).

As shown in FIGS. 7A to 10, in the present embodiment, the signal line 140B is formed only on the second layer S2, but each of the signal line 140R and the signal line 140G is partially formed on the fourth layer S4. Has been done. Specifically, the signal line 140R is formed in the fourth layer S4 in the section from the relay electrode 160R to the relay electrode 164R, and the signal line 140G is the fourth layer in the section from the relay electrode 160G to the relay electrode 162G. It is formed in S4. The cut surface by the cut line BB'is an example of the cut surface in the section from the relay electrode 160G to the relay electrode 162G. In this section, as shown in FIG. 8, the signal line 140R and the signal line 140G are formed on the fourth layer S4, and the signal line 140B and the data transfer line 14B are formed on the second layer S2. A third layer S3, which is a metal layer to which the first fixed potential VSS is given, is provided between the second layer S2 and the fourth layer S4, and the third layer S3 has a shielding function. Therefore, crosstalk between the signal line 140B or the data transfer line 14B and the signal line 140R in the section from the relay electrode 160G to the relay electrode 162G is suppressed. Similarly, crosstalk between the signal line 140B or the data transfer line 14B and the signal line 140G is also suppressed.

The cut surface by the cut line CC'is an example of the cut surface in the section from the relay electrode 162G to the relay electrode 164R. In this section, as shown in FIG. 9, the signal line 140R and the data transfer line 14B are formed in the fourth layer S4, and the signal line 140G and the data transfer line 14G are formed in the second layer S2. Therefore, crosstalk between the signal line 140G or the data transfer line 14G and the signal line 140R in the section from the relay electrode 162G to the relay electrode 164R is suppressed, and the signal line 140G or the data transfer line 14G and the data transfer line 14B are suppressed. Crosstalk between is suppressed. The cut surface formed by the cut line DD'is an example of the cut surface in the section from the relay electrode 164R to the relay electrode 166B. In this section, as shown in FIG. 10, the data transfer line 14B is formed in the fourth layer S4, and the signal line 140R and the data transfer line 14R are formed in the second layer S2. Therefore, crosstalk between the signal line 140R or the data transfer line 14R and the data transfer line 14B is suppressed. The data transfer line 14R and the data transfer line 14G are shielded by the feeder line 16G.

As described above, on the upstream side of the AA'line in FIG. 5, each of the signal lines 140R, 140G and 140B is shielded by each of the feeder lines 16R, 16G and 16B acting as shielded lines, and the cross between the signal lines is performed. Talk is suppressed. Further, on the downstream side of the EE'line in FIG. 5, each of the feeder lines 16R, 16G and 16B acting as a shielded line shields each of the data transfer lines 14R, 14G and 14B, and crosstalk is suppressed. .. In the present embodiment, crosstalk is suppressed over the entire section from the demultiplexer DM (n) to each of the pixel circuits 110R, 110G and 110B via the level shift circuits LSR, LSG and LSB. , Does not cause deterioration of display quality. Further, in the present embodiment, since the level shift circuits LSR, LSG, and LSB are arranged side by side in the column direction on the upstream side of the display unit 100, it is possible to cope with narrowing the pitch of the pixel circuit 110 in the X direction, and electro-optics. It becomes possible to improve the definition of the device 1.

The data transfer lines 14R, 14G and 14B and the feeder lines 16R, 16G and 16B are formed on the second layer S2 on the downstream side of the cutting line EE', that is, on the display unit 100. More specifically, the feeder line 16R is formed in parallel with the data transfer line 14R at a predetermined interval from the data transfer line 14R (see FIG. 6). Similarly, the feeder line 16G is formed parallel to the data transfer line 14G with a predetermined interval from the data transfer line 14G, and the feeder line 16B is formed with a predetermined interval from the data transfer line 14B with the data transfer line 14B. It is formed in parallel. The capacity 50 between the data transfer line 14R and the feeding line 16R is such that the data transfer line 14R and the feeding line 16R as a shielded line are arranged with a predetermined gap via the insulating material constituting the second layer S2. Formed by. The same applies to the capacity 50 between the data transfer line 14G and the feeder line 16G, and the capacity 50 between the data transfer line 14B and the feeder line 16B. That is, the capacity 50 between the data transfer line 14G and the feeder line 16G is such that the data transfer line 14G and the feeder line 16G as a shielded wire are arranged in a predetermined gap via the insulating material constituting the second layer S2. Formed by The capacity 50 between the data transfer line 14B and the feeding line 16B is obtained by arranging the data transfer line 14B and the feeding line 16B as a shielded wire in a predetermined gap via the insulating material constituting the second layer S2. It is formed. Since the capacity 50 is formed by two parallel wirings, it has a predetermined length in the Y direction, and a predetermined capacity can be secured. Further, since the capacity 50 is formed in the display area of the pixel circuit 110, it is possible to prevent an increase in the chip area.

<B. Modification example>
Although one embodiment of the present invention has been described above, the following modifications may be added to this embodiment.
(1) The electro-optic device 1 of the above embodiment has a third layer S3 having a shielding function between the second layer S2 which is the first wiring layer and the fourth layer S4 which is the second wiring layer. rice field. However, as shown in FIGS. 8 and 9, when the level shift circuit LSG is the first circuit, the level shift circuit LSB is the second circuit, the signal line 140G is the first signal line, and the signal line 140B is the second signal line. In addition, if crosstalk between both signal lines can be sufficiently suppressed by wiring at least one part of the first signal line to a wiring layer different from the second signal line, the third layer S3 may be omitted. good. The same applies to the feeder line 16 which plays the role of a shielded wire, and by wiring at least one part of the first signal line to a wiring layer different from the second signal line, crosstalk between both signal lines can be sufficiently achieved. If it can be suppressed, the shielded wire may be omitted. In the example shown in FIGS. 8 and 9, at least a part of the second data transfer line (for example, the data transfer line 14B) arranged alongside the first data transfer line (for example, the data transfer line 14G) is also the first. 1 It is wired to a wiring layer different from the data transfer line. The first data transfer line is a signal line for supplying a data signal indicating display gradation from the first circuit (level shift circuit LSG) to the first pixel circuit (for example, pixel circuit 110G), and is the second data. The transfer line is a signal line for supplying a data signal indicating a display gradation from the second circuit (level shift circuit LSB) to the second pixel circuit (for example, the pixel circuit 110B).

(2) The electro-optic device 1 of the above embodiment has an electrode 190 between the second wiring layer (fourth layer S4) and the third layer S3, and the holding capacity 41 is formed by the electrode 190 and the third layer S3. Was done. However, the electrode 190 may be omitted and a holding capacity 41 may be provided separately.

(3) In the electro-optic device 1 of the above embodiment, the data transfer line 14 and the feeder line 16 formed in parallel with the data transfer line 14 at a predetermined interval play the role of the capacity 50. The capacity 50 may be provided separately.

(4) In the electro-optical device 1 of the above-described embodiment, the first feeder line (feed feeder line 16 formed in the second layer S2) and the second feeder line that play the role of a shield wire in the first wiring layer (second layer S2). The second feeder line (feed feeder line 16 formed in the fourth layer S4), which acts as a shield wire in the wiring layer (fourth layer S4), is formed in the third layer, which is a metal layer, and the periphery is insulated. It was connected via a relay electrode. However, it is not necessary to connect the first feeder line and the second feeder line via the relay electrode.

<C. Application example>
The electro-optic device according to the above-described embodiment can be applied to various electronic devices, and is particularly suitable for electronic devices that are required to display high-definition images of 2K2K or higher and are required to be compact. Is. Hereinafter, the electronic device according to the present invention will be described.

FIG. 12 is a perspective view showing the appearance of the head-mounted display 300 as an electronic device adopting the electro-optic device of the present invention. As shown in FIG. 12, the head-mounted display 300 includes a temple 310, a bridge 320, a projection optical system 301L, and a projection optical system 301R. In FIG. 12, an electro-optic device for the left eye (not shown) is provided behind the projection optical system 301L, and an electro-optic device for the right eye (not shown) is provided behind the projection optical system 301R. Be done.

FIG. 13 is a perspective view of a portable personal computer 400 that employs the electro-optic device 1 according to the present invention. The personal computer 400 includes an electro-optic device 1 for displaying various images, and a main body unit 403 provided with a power switch 401 and a keyboard 402. In addition to the devices illustrated in FIGS. 12 and 13, the electronic devices to which the electro-optical device 1 according to the present invention is applied include mobile phones, smartphones, personal digital assistants (PDAs), and digital still cameras. , Video cameras. Other electronic devices to which the electro-optical device according to the present invention is applied include a television, a car navigation device, an in-vehicle display (instrument panel), an electronic viewfinder, an electronic personal organizer, electronic paper, a calculator, a word processor, and a workstation. Examples include stations, videophones, POS terminals, and the like. Further, the electro-optical device according to the present invention can be applied as a display unit provided in an electronic device such as a printer, a scanner, a copying machine, and a video player.

1 ... Electro-optical device, 10 ... Display panel, 3 ... Control circuit, 31 ... Voltage generation circuit, 5 ... Data transfer line drive circuit, 4 ... Scan line drive circuit, 12 ... Scan line, 14 ... Data transfer line, 16, 61, 62, 63, 64, and 116 ... power supply line, 50 ... shield capacity, LS ... level shift circuit, DM ... demultiplexer, 70 ... data signal supply circuit, 100 ... display unit, 110 ... pixel circuit, 121 ... 1st transistor, 122 ... 2nd transistor, 123 ... 3rd transistor, 124 ... 4th transistor, 125 ... 5th transistor, 130 ... OLED, 132 ... pixel capacitance, 140 and 180 ... signal lines, 160,161,1622 163, 164, 165, 166, and 167 ... Transistors, 300 ... Head Mounted Display, 400 ... Personal Computers.

Claims (10)

The first data transfer line and
A first circuit that supplies a data signal to the first data transfer line,
A second data transfer line arranged along the first data transfer line and
A second circuit that supplies a data signal to the second data transfer line,
Equipped with
The first circuit and the second circuit are arranged side by side in a direction in which the first data transfer line is extended.
One of the first data transfer line and the second data transfer line is provided at least partially in a wiring layer different from the other.
An electro-optic device characterized by that. In the first circuit, the first signal line electrically connected to the first data transfer line and
In the second circuit, the second signal line electrically connected to the second data transfer line and
To prepare
The electro-optic device according to claim 1. The first circuit has a first transmission gate, one end of which is electrically connected to the first signal line and the other end of which is electrically connected to the first data transfer line.
The second circuit has a second transmission gate, one end of which is electrically connected to the second signal line and the other end of which is electrically connected to the second data transfer line.
The electro-optic device according to claim 2. One of the first signal line and the second signal line is provided in a wiring layer that is at least partially different from the other.
The electro-optic device according to claim 2 or 3. The first data transfer line is shorter than the second data transfer line.
In the first circuit, the first data transfer line and the first signal line are provided in the first wiring layer , and the second data transfer line is a second wiring layer different from the first wiring layer. Provided in
In the second circuit, the second data transfer line and the second signal line are provided in the first wiring layer, and the first signal line is provided in the second wiring layer.
The electro-optic device according to any one of claims 2 to 4. A metal layer provided between the first wiring layer and the second wiring layer and having a first fixed potential is provided.
The electro-optic device according to claim 5. An electrode layer provided between the metal layer and the second wiring layer is provided.
The electro-optical device according to claim 6, wherein the metal layer and the electrode layer form a holding capacity for holding a voltage corresponding to a display gradation. In the first wiring layer, a first shielded wire provided between the first signal line and the second signal line and having a second fixed potential, and
To prepare
The electro-optic device according to claim 7. The first shielded wire is formed on the metal layer .
The electro-optic device according to claim 8. An electronic device comprising the electro-optic device according to any one of claims 1 to 9.

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