JP6822595B2 - Electro-optics and electronic equipment - Google Patents

Description

The present invention relates to electro-optical devices and electronic devices.

In recent years, various electro-optical devices have been proposed that display an image using a light emitting element such as an organic light emitting diode (hereinafter referred to as "OLED") element. In this electro-optical device, a pixel circuit including a light emitting element, a transistor, and the like is provided corresponding to the pixels of the image to be displayed. Specifically, a plurality of pixel circuits corresponding to the pixels of the image to be displayed are provided in a matrix, and a control line such as a scanning line is generally provided in each line in order to drive the plurality of pixel circuits. Is the target. (See, for example, Patent Document 1).

JP-A-2007-316462

By the way, in recent years, electro-optic devices are often required to have a smaller display size and higher definition. In this case, in order to arrange the pixel circuits at high density, it is necessary to narrow the pitch of the control lines.
The present invention has been made in view of the above circumstances, and one of the purposes thereof is to realize high-density wiring of a plurality of control lines including a plurality of scanning lines, and to increase the definition or display size of the display. It is to realize the miniaturization of.

In order to achieve the above object, the electro-optical device according to the present invention includes a scanning line, a data line intersecting the scanning line, and a pixel circuit provided corresponding to the intersection of the scanning line and the data line. The pixel circuit responds to a drive transistor, a write transistor whose gate is electrically connected to the scan line, and a data signal supplied via the data line and the write transistor. It has a first holding capacitance that holds a charge and a light emitting element that emits light with a brightness corresponding to the magnitude of the current supplied via the drive transistor, and is perpendicular to the surface of the substrate on which the pixel circuit is formed. When viewed from a different direction, the scanning line and the gate of the driving transistor overlap each other.
According to the present invention, since the scanning line is wired on the gate of the driving transistor, the space restriction when providing the scanning line is relaxed as compared with the case where the scanning line is wired so as not to intersect the gate of the driving transistor. Will be done. This makes it possible to narrow the pitch of scanning lines and increase the density of wiring. That is, according to the present invention, a plurality of pixel circuits can be arranged at a higher density, and it is possible to increase the definition of the display and reduce the display size. In the present invention, the writing transistor may be, for example, electrically connected between the gate of the driving transistor and the data line.

Further, the electro-optical device according to the present invention includes one or more control lines including scanning lines, data lines intersecting the scanning lines, and pixels provided corresponding to the intersections of the scanning lines and the data lines. The pixel circuit comprises a circuit, the pixel circuit comprises a drive transistor, a write transistor whose gate is electrically connected to the scan line, and a data signal supplied via the data line and the write transistor. It has a first holding capacitance that holds the corresponding charge and a light emitting element that emits light with a brightness corresponding to the magnitude of the current supplied through the driving transistor, and the one or more control lines include the above. It is characterized in that a control line that overlaps with the gate of the drive transistor is included when viewed from a direction perpendicular to the surface of the substrate on which the pixel circuit is formed.
According to the present invention, since the control line is wired on the gate of the drive transistor, the space restriction when providing the control line is relaxed as compared with the case where the control line is wired so as not to intersect the gate of the drive transistor. Will be done. This makes it possible to narrow the pitch of control lines and increase the density of wiring. That is, according to the present invention, a plurality of pixel circuits can be arranged at a higher density, and it is possible to increase the definition of the display and reduce the display size.

Further, the electro-optical device described above further includes a scanning line drive circuit that controls the operation of the pixel circuit, and the writing transistor is turned on when the scanning line driving circuit supplies the first potential to the scanning line. When the scanning line drive circuit is turned off when supplying a second potential to the scanning line and viewed from a direction perpendicular to the surface of the substrate on which the pixel circuit is formed, the scanning line and the driving transistor are turned off. The period in which the potential supplied to the scanning line by the scanning line driving circuit is switched from the second potential to the first potential is defined as the first switching period, and the scanning line driving circuit performs the scanning. When the period for switching the potential supplied to the line from the first potential to the second potential is set as the second switching period, the time length of the second switching period is longer than the time length of the first switching period. Is preferable.

When the gate of the drive transistor and the scanning line intersect in a plan view, a capacitance parasitizes between the gate of the driving transistor and the scanning line. When the potential of the scanning line fluctuates abruptly, the influence of the potential fluctuation extends to the gate of the drive transistor, and the potential of the gate of the drive transistor changes.
The drive transistor supplies the light emitting element with a current having a magnitude corresponding to the voltage between the gate and the source determined when the writing transistor is turned off, and the light emitting element emits light with brightness corresponding to the magnitude of the current. To do. Therefore, when the write transistor is turned off (that is, after the voltage defined for the brightness of the light emitting element is set), when the potential of the gate of the drive transistor changes, the light emitting element has a brightness different from the specified brightness. It emits light and the display quality of the electro-optical device deteriorates.
On the other hand, the scanning line drive circuit according to the present invention changes the potential of the scanning line when the writing transistor is turned off more slowly than the potential change when the writing transistor is turned on. As a result, the potential fluctuation of the scanning line when the writing transistor is turned off is prevented from propagating to the gate of the driving transistor, and the light emitting element can emit light at a specified brightness. That is, according to the electro-optical device according to the present invention, it is possible to realize a narrow pitch of the control line without deteriorating the display quality.

Further, the pixel circuit includes a first switching transistor electrically connected between the gate and the drain of the drive transistor, and the one or more control lines are electrically connected to the gate of the first switching transistor. It may include the first control line to be made.
In this case, the first switching transistor is turned on when the scanning line drive circuit supplies the first potential to the first control line, and the scanning line drive circuit supplies the second potential to the first control line. When viewed from a direction perpendicular to the surface of the substrate on which the pixel circuit is formed, the first control line and the gate of the drive transistor overlap each other, and the scanning line drive circuit becomes the first. The period for switching the potential supplied to the 1 control line from the 2nd potential to the 1st potential is defined as the 3rd switching period, and the potential supplied by the scanning line drive circuit to the 1st control line is the 1st potential. When the period for switching to the second potential is defined as the fourth switching period, the time length of the fourth switching period is preferably longer than the time length of the third switching period.

When the gate of the drive transistor and the first switching transistor intersect in a plan view, a capacitance parasitizes between the gate of the drive transistor and the first control line. When the potential of the first control line fluctuates abruptly, the influence of the potential fluctuation extends to the gate of the drive transistor, and the potential of the gate of the drive transistor changes.
By the way, when the first switching transistor is turned on, the gate and source of the drive transistor are electrically connected, and the voltage between the gate and source of the drive transistor is set to a value that compensates for the variation in the threshold voltage for each pixel circuit. .. Therefore, if the potential of the gate of the drive transistor changes when the first switching transistor is turned off (that is, after the threshold compensation is performed), the variation in the threshold voltage of the drive transistor for each pixel circuit cannot be compensated, and the display cannot be displayed. Uniformity is impaired.
On the other hand, the scanning line drive circuit according to this aspect changes the potential change of the first control line when the first switching transistor is turned off more gently than the change of the potential when the first switching transistor is turned on. As a result, the potential fluctuation of the first control line when the first switching transistor is turned off is prevented from propagating to the gate of the drive transistor, and the potential of the gate of the drive transistor changes from the threshold-compensated potential. To prevent that. That is, according to the electro-optic device according to the present invention, even when the first control line is arranged on the gate of the drive transistor, it is possible to prevent the occurrence of display unevenness that impairs the uniformity of display. Therefore, it is possible to achieve both miniaturization and high definition of the display of the electro-optic device and high-quality display.

Further, the pixel circuit includes a second switching transistor electrically connected between the driving transistor and the light emitting element, and one or more control lines are electrically connected to the gate of the second switching transistor. It may include a second control line to be connected.
In this case, the second switching transistor is turned on when the scanning line drive circuit supplies the first potential to the second control line, and the scanning line drive circuit supplies the second potential to the second control line. When viewed from a direction perpendicular to the surface of the substrate on which the pixel circuit is formed, the second control line and the gate of the drive transistor overlap each other, and the scanning line drive circuit becomes the first. The period for switching the potential supplied to the two control lines from the second potential to the first potential is set as the fifth switching period, and the potential supplied by the scanning line drive circuit to the second control line is set to the first potential. When the period for switching to the second potential is defined as the sixth switching period, the time length of the fifth switching period is preferably longer than the time length of the sixth switching period.
According to this aspect, it is possible to prevent the potential fluctuation generated in the second control line when the second switching transistor is turned on from propagating to the gate of the drive transistor. As a result, the pitch of the control line can be narrowed without deteriorating the display quality.

Further, the pixel circuit includes a third switching transistor electrically connected between a feeder line to which a predetermined reset potential is supplied and the light emitting element, and the one or more control lines are the third switching. It may include a third control line that is electrically connected to the gate of the transistor.
In this case, the third switching transistor is turned on when the scanning line drive circuit supplies the first potential to the third control line, and the scanning line drive circuit supplies the second potential to the third control line. When viewed from a direction perpendicular to the surface of the substrate on which the pixel circuit is formed, the third control line and the gate of the drive transistor overlap each other, and the scanning line drive circuit becomes the first. The period for switching the potential supplied to the 3 control lines from the 2nd potential to the 1st potential is defined as the 7th switching period, and the potential supplied by the scanning line drive circuit to the 3rd control line is the 1st potential. When the period for switching to the second potential is defined as the eighth switching period, the time length of the eighth switching period is preferably longer than the time length of the seventh switching period.
According to this aspect, it is possible to prevent the potential fluctuation generated in the third control line when the third switching transistor is turned off from propagating to the gate of the drive transistor. As a result, the pitch of the control line can be narrowed without deteriorating the display quality.

Further, the above-mentioned electro-optical device corresponds to a data line drive circuit electrically connected to the data line, a control circuit for controlling the operation of the scanning line drive circuit and the data line drive circuit, and the data line. The data line driving circuit includes a first potential line to which a predetermined initial potential is supplied from the control circuit, and a second holding capacitance for holding the potential of the data line. A second potential line to which a reference potential is supplied and a level shift circuit provided corresponding to the data line are provided, and in the level shift circuit, one electrode is electrically connected to the data line. The third holding capacity, one electrode of the third holding capacity, the first transistor electrically connected between the first potential line, the other electrode of the third holding capacity, and the second potential line. A second transistor is electrically connected between the two, and in the first period, the control circuit keeps the first transistor on and is started after the first period ends. During the period, the scanning line drive circuit keeps the writing transistor in the on state, the control circuit keeps the first transistor in the off state, and keeps the second transistor in the on state. In the third period, which is started after the second period ends, the scanning line drive circuit keeps the writing transistor on, and the control circuit turns the first transistor and the second transistor off. It is preferable that the other electrode of the third holding capacitance is supplied with a potential based on an image signal that defines the brightness of the light emitting element.

According to the present invention, the data line is connected to the second holding capacitance and the third holding capacitance, and the other electrode of the third holding capacitance is supplied with a potential based on the image signal that defines the brightness of the light emitting element. Will be done. Therefore, the fluctuation width of the potential of the data line is the width obtained by compressing the fluctuation width of the potential supplied to the other electrode of the third holding capacity according to the capacity ratio of the second holding capacity and the third holding capacity. That is, the fluctuation range of the potential of the data line is narrower than the fluctuation range of the potential based on the image signal. This makes it possible to set the potential of the gate of the drive transistor with fine accuracy without engraving the image signal with fine accuracy. Therefore, the current can be supplied to the light emitting element with high accuracy, and high-quality display becomes possible. Further, since the potential change width of the data line can be suppressed to be small, it is possible to prevent the occurrence of crosstalk, unevenness, etc. due to the potential fluctuation of the data line.

In the electro-optical device according to the present invention, the potential of the gate of the drive transistor is reached by supplying an electric charge to the first holding capacitance and the second holding capacitance from one electrode of the third holding capacitance via a data line. To determine. Specifically, the potential of the gate of the drive transistor is supplied by the capacity value of the first holding capacity, the capacity value of the second holding capacity, and the third holding capacity with respect to the first holding capacity and the second holding capacity. It is determined by the amount of charge. If the electro-optic device does not have a second holding capacitance, the potential of the gate of the drive transistor is determined by the capacitance value of the first holding capacitance and the charge supplied by the third holding capacitance. Therefore, when the capacitance value of the first holding capacitance has a relative variation for each pixel circuit due to an error in the semiconductor process, the potential of the gate of the drive transistor also varies for each pixel circuit. In this case, display unevenness occurs and the display quality deteriorates.
On the other hand, the present invention includes a second holding capacitance for holding the potential of the data line. Since the second holding capacitance is provided corresponding to each of the data lines, it can be configured to have an electrode having a larger area than the first holding capacitance provided in the pixel circuit. Therefore, the second holding capacity has a smaller relative variation in the capacity value due to an error in the semiconductor process than the first holding capacity. As a result, it is possible to prevent the potential of the gate of the drive transistor from fluctuating for each pixel circuit, and it is possible to perform high-quality display in which display unevenness is prevented from occurring.

Further, the level shift circuit includes a fourth holding capacity, and the image is attached to one electrode of the fourth holding capacity during at least a part of the period from the start of the first period to the start of the third period. It is preferable that the potential indicated by the signal is supplied and one electrode of the fourth holding capacity is electrically connected to the other electrode of the third holding capacity in the third period.

According to the present invention, in the first period and the second period, the image signal is supplied to one electrode of the fourth holding capacitance, temporarily held, and then in the third period, via the third holding capacitance. Is supplied to the gate of the drive transistor.
If the electro-optic device does not have the fourth holding capacitance, all the operations of supplying the potential indicated by the image signal to the gate of the drive transistor must be performed in the third period, and the third period must be sufficiently long. Must be set.
On the other hand, the present invention relates to an operation to be performed in one horizontal scanning period because the image signal supply operation and the data line initialization operation are performed in parallel in the first period and the second period. Time constraints can be relaxed. As a result, the speed of the image signal supply operation can be reduced, and a sufficient period for initializing the data line or the like can be secured.
Further, according to the present invention, the magnitude of the fluctuation of the potential based on the image signal is compressed by using the fourth holding capacity in addition to the first holding capacity, the second holding capacity, and the third holding capacity. Therefore, it is possible to supply the current to the light emitting element with fine accuracy.

Further, the scanning line drive circuit keeps the first switching transistor in the on state in the second period, and keeps the first switching transistor in the off state in a period other than the second period, and the first switching transistor is kept in the off state. It is preferable to keep the third switching transistor in the on state and the second switching transistor in the off state in one period, the second period, and the third period.

According to the present invention, by turning on the first switching transistor in the second period, the potential of the gate of the drive transistor can be set to the potential corresponding to the threshold voltage of the drive transistor, and each pixel circuit can be driven. It is possible to compensate for the variation in the threshold voltage of the transistor.
Further, according to the present invention, by turning on the third switching transistor in the first to third periods, the influence of the holding voltage of the capacitance parasitic on the light emitting element can be suppressed.

In addition to the electro-optical device, the present invention can also be conceived as an electronic device having the electro-optic device. Electronic devices typically include display devices such as head-mounted displays (HMDs) and electronic viewfinders.

It is a perspective view which shows the structure of the electro-optic device which concerns on embodiment of this invention. It is a figure which shows the structure of the electro-optical device. It is a figure which shows the data line drive circuit in the electro-optics device. It is a figure which shows the pixel circuit in the electro-optical device. It is a top view which shows the structure of the pixel circuit in the electro-optic device. It is a partial cross-sectional view which shows the structure of the pixel circuit in the electro-optic device. It is a timing chart which shows the operation of the electro-optic device. It is operation explanatory drawing of the electro-optic device. It is a figure explaining the potential change of the gate node of the electro-optic device. It is explanatory drawing which shows the amplitude compression of the data signal in the electro-optics device. It is explanatory drawing which shows the characteristic of the transistor in the electro-optic device. It is a top view which shows the structure of the pixel circuit in the electro-optic device which concerns on modification 1. FIG. It is a timing chart which shows the operation of the electro-optic device. It is a top view which shows the structure of the pixel circuit in the electro-optic device which concerns on modification 2. FIG. It is a timing chart which shows the operation of the electro-optic device. It is a perspective view which shows the HMD which used the electro-optic device which concerns on embodiment and the like. It is a figure which shows the optical structure of an HMD.

Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.

<Embodiment>
FIG. 1 is a perspective view showing a configuration of an electro-optical device 1 according to an embodiment of the present invention. The electro-optical device 1 is a micro-display that displays an image on, for example, a head-mounted display.
As shown in FIG. 1, the electro-optical device 1 includes a display panel 2 and a control circuit 3 that controls the operation of the display panel 2. The display panel 2 includes a plurality of pixel circuits and a drive circuit for driving the pixel circuits. In the present embodiment, the plurality of pixel circuits and drive circuits included in the display panel 2 are formed on a silicon substrate, and an OLED, which is an example of a light emitting element, is used for the pixel circuits. Further, the display panel 2 is housed in, for example, a frame-shaped case 82 opened at the display portion, and one end of an FPC (Flexible Printed Circuits) substrate 84 is connected.
A semiconductor chip control circuit 3 is mounted on the FPC substrate 84 by COF (Chip On Film) technology, and a plurality of terminals 86 are provided and connected to a higher-level circuit (not shown).

FIG. 2 is a block diagram showing the configuration of the electro-optical device 1 according to the embodiment. As described above, the electro-optical device 1 includes a display panel 2 and a control circuit 3.
Digital image data Video is supplied to the control circuit 3 in synchronization with the synchronization signal from a higher-level circuit (not shown). Here, the image data Video is data that defines, for example, 8 bits of the gradation level of the pixels of the image to be displayed on the display panel 2 (strictly speaking, the display unit 100 described later). The synchronization signal is a signal including a vertical synchronization signal, a horizontal synchronization signal, and a dot clock signal.
The control circuit 3 generates various control signals based on the synchronization signal and supplies the control signals to the display panel 2. Specifically, the control circuit 3 has a control signal Ctr, a negative logic control signal / Gini, a positive logic control signal Gref, a positive logic control signal Gcpl, and logic with respect to the display panel 2. Negative logic control signal / Gcpl that has an inversion relationship, control signals Sel (1), Sel (2), and Sel (3), and control signal / Sel (1) that has a logic inversion relationship with these signals. ), / Sel (2), / Sel (3), and so on. Here, the control signal Ctr is a signal including a plurality of signals such as a pulse signal, a clock signal, and an enable signal. The control signals Sel (1), Sel (2), and Sel (3) are collectively referred to as control signals Sel, and the control signals / Sel (1), / Sel (2), / Sel (3) are referred to as control signals. It may be generically called / Self.
Further, the control circuit 3 supplies various electric potentials to the display panel 2. Specifically, the control circuit 3 supplies the display panel 2 with a predetermined reset potential Vorst, a predetermined initial potential Vini, a predetermined reference potential Vref, and the like.
Further, the control circuit 3 generates an analog image signal Video based on the image data Video.
Specifically, the control circuit 3 is provided with a lookup table that stores the potential indicated by the image signal Vid and the brightness of the light emitting element (OLED 130 described later) included in the display panel 2 in association with each other. Then, the control circuit 3 generates an image signal Vid indicating a potential corresponding to the brightness of the light emitting element defined in the image data Video by referring to the lookup table, and supplies this to the display panel 2. To do.

As shown in FIG. 2, the display panel 2 includes a display unit 100 and a drive circuit (data line drive circuit 10 and scan line drive circuit 20) for driving the display unit 100.
In the display unit 100, pixel circuits 110 corresponding to the pixels of the image to be displayed are arranged in a matrix. Specifically, in the display unit 100, the scanning lines 12 of the m rows are provided so as to extend in the horizontal direction (X direction) in the drawing, and the data lines 14 of the (3n) columns grouped by 3 columns. Is extended in the vertical direction (Y direction) in the drawing, and is provided so as to maintain electrical insulation with each scanning line 12. A pixel circuit 110 is provided corresponding to the intersection of the scanning line 12 in the m row and the data line 14 in the (3n) column. Therefore, in the present embodiment, the pixel circuits 110 are arranged in a matrix of vertical m rows × horizontal (3n) columns.

Here, m and n are both natural numbers. In order to distinguish rows (rows) from the matrix of the scanning line 12 and the pixel circuit 110, they may be referred to as 1, 2, 3, ..., (M-1), m rows in order from the top in the figure. Similarly, in order to distinguish the columns of the matrix of the data line 14 and the pixel circuit 110, they may be referred to as 1, 2, 3, ..., (3n-1), (3n) columns in order from the left in the figure. .. Further, in order to generalize and explain the group of the data line 14, when an integer j of 1 or more and n or less is used, the jth group counted from the left includes the (3j-2) column and (3j-1). It means that the data line 14 of the) column and the (3j) column belongs to it.
The three pixel circuits 110 corresponding to the intersection of the scanning line 12 in the same row and the data line 14 in three columns belonging to the same group have R (red), G (green), and B (blue) pixels, respectively. Correspondingly, these three pixels represent one dot of the color image to be displayed. That is, in the present embodiment, the color of one dot is expressed by additive mixing by emitting light of the OLED corresponding to RGB.

Further, as shown in FIG. 2, in the display unit 100, the feeder lines 16 in the (3n) row are provided so as to extend in the vertical direction and maintain electrical insulation with each scanning line 12. A predetermined reset potential Worst is commonly fed to each feeder line 16. Here, in order to distinguish the rows of the feeder lines 16, the feeder lines 16 in the first, second, third, ..., (3n), and (3n + 1) rows may be referred to in order from the left in the figure. Each of the feeder lines 16 in the first to (3n) rows is provided corresponding to each of the data lines 14 in the first to (3n) rows.
Further, the display panel 2 is provided with (3n) holding capacities 50 corresponding to each of the data lines 14 in the first to (3n) rows. The holding capacity 50 has two electrodes. One electrode of the holding capacity 50 is connected to the data line 14, and the other electrode is connected to the feeder line 16. That is, the holding capacity 50 functions as a second holding capacity for holding the potential of the data line 14. The holding capacity 50 is preferably formed by sandwiching an insulator (dielectric) between the feeder lines 16 and the data lines 14 adjacent to each other. In this case, the distance between the feeder lines 16 and the data lines 14 adjacent to each other is determined so that a capacity of a required size can be obtained. In the following, the capacity value of the holding capacity 50 is referred to as Cdt.
In FIG. 2, the holding capacity 50 is provided outside the display unit 100, but this is merely an equivalent circuit and may be provided inside the display unit 100. Further, the holding capacity 50 may be provided from the inside to the outside of the display unit 100.

The scan line drive circuit 20 generates a scan signal Gwr for sequentially scanning the scan lines 12 line by line over a frame period according to the control signal Ctr. Here, the scanning signals Gwr supplied to the scanning lines 12 on the 1st, 2nd, 3rd, ..., Mth lines are Gwr (1), Gwr (2), Gwr (3), ..., Gwr (m-1), respectively. ), Gwr (m).
In addition to the scanning signals Gwr (1) to Gwr (m), the scanning line drive circuit 20 generates various control signals synchronized with the scanning signal Gwr line by line and supplies them to the display unit 100. The illustration is omitted in FIG. The frame period is the period required for the electro-optical device 1 to display an image for one cut (frame). For example, if the frequency of the vertical synchronization signal included in the synchronization signal is 120 Hz, that 1 It is a period of 8.3 milliseconds for the cycle.

The data line drive circuit 10 includes (3n) level shift circuits LS provided in a one-to-one correspondence with each of the data lines 14 in the (3n) column, and for each of the three columns of data lines 14 constituting each group. It includes n demultiplexers DM provided and a data signal supply circuit 70.
The data signal supply circuit 70 generates data signals Vd (1), Vd (2), ..., Vd (n) based on the image signal Vid and the control signal Ctr supplied from the control circuit 3. That is, the data signal supply circuit 70 has the data signals Vd (1), Vd (2), ..., Vd (n) based on the time-division-multiplexed image signal Vid, and the data signals Vd (1), Vd (2). , ..., generate Vd (n). Then, the data signal supply circuit 70 transmits the data signals Vd (1), Vd (2), ..., Vd (n) to the demultiplexer DM corresponding to the 1, 2, ..., Nth group, respectively. Supply. Further, the maximum value of the potential that the data signals Vd (1) to Vd (n) can take is Vmax, and the minimum value is Vmin.

FIG. 3 is a circuit diagram for explaining the configuration of the demultiplexer DM and the level shift circuit LS. Note that FIG. 3 typically shows the demultiplexer DM belonging to the j-th group and the three level shift circuits LS connected to the demultiplexer DM. In the following, the demultiplexer DM belonging to the jth group may be referred to as DM (j).

In the following, the configuration of the demultiplexer DM and the level shift circuit LS will be described with reference to FIG. 3 in addition to FIG.
As shown in FIG. 3, the demultiplexer DM is an aggregate of transmission gates 34 provided for each column, and sequentially supplies data signals to the three columns constituting each group. Here, the input terminals of the transmission gates 34 corresponding to the columns (3j-2), (3j-1), and (3j) belonging to the jth group are commonly connected to each other, and the data signal Vd ( j) is supplied. The transmission gate 34 provided in the leftmost column (3j-2) in the j-th group is when the control signal Sel (1) is at the H level (when the control signal / Sel (1) is at the L level). ) Turns on (conducts). Similarly, in the j-th group, the transmission gate 34 provided in the central row (3j-1) row has an H level when the control signal Self (2) is H level (control signal / Self (2) is L level). The transmission gate 34, which is turned on when (when) is turned on and is provided in the (3j) column, which is the rightmost column in the jth group, is used when the control signal Self (3) is at the H level (control signal / Self (3)). Turns on when is at L level).

The level shift circuit LS has a holding capacity of 41, a holding capacity of 44, a P-channel MOS type transistor 45 (first transistor), an N-channel MOS type transistor 43 (second transistor), and a set of a transmission gate 42 for each row. The potential of the data signal output from the output end of the transmission gate 34 in each row is shifted.
Here, the holding capacity 44 has two electrodes. One electrode of the retention capacity 44 is electrically connected to the data line 14 in the corresponding row and to one of the source or drain of the transistor 45. Further, the other electrode of the holding capacitance 44 is electrically connected to the output end of the transmission gate 42 and one of the source or drain of the transistor 43 via the node h1. That is, the holding capacity 44 functions as a third holding capacity in which one electrode is electrically connected to the data line 14. The capacity value of the holding capacity 44 is set to Crf1.

The other of the source or drain of the transistors 45 in each row is electrically connected to the feeder 61 (first potential line). Further, the control circuit 3 commonly supplies a control signal / Gini to the gates of the transistors 45 in each row. Therefore, the transistor 45 electrically connects one electrode (and the data line 14) of the holding capacity 44 and the feeder line 61 when the control signal / Gini is at L level, and the control signal / Gini is at H level. Sometimes it is electrically disconnected. A predetermined initial potential Vini is supplied to the feeder line 61 from the control circuit 3.
The other of the source or drain of the transistors 43 in each row is electrically connected to the feeder line 62 (second potential line). Further, the control circuit 3 commonly supplies the control signal Gref to the gates of the transistors 43 in each row. Therefore, the transistor 43 electrically connects the other electrode and node h1 of the holding capacity 44 and the feeder line 62 when the control signal Gref is H level, and is electrically connected when the control signal Gref is L level. To disconnect. A reference potential Vref is supplied to the feeder line 62 from the control circuit 3.

The holding capacity 41 has two electrodes. One electrode of the holding capacitance 41 is electrically connected to the input end of the transmission gate 42 via the node h2. Further, the output end of the transmission gate 42 is electrically connected to the other electrode of the holding capacity 44 via the node h1.
The control circuit 3 commonly supplies the control signal Gcpl and the control signal / Gcpl to the transmission gate 42 in each row. Therefore, the transmission gates 42 in each row are turned on all at once when the control signal Gcpl is at the H level (when the control signal / Gcpl is at the L level).
One electrode of the holding capacity 41 of each row is electrically connected to the output end of the transmission gate 34 and the input end of the transmission gate 42 via the node h2. Then, when the transmission gate 34 is turned on, the data signal Vd (j) is supplied to one electrode of the holding capacitance 41 via the output end of the transmission gate 34. That is, the holding capacity 41 functions as a fourth holding capacity in which the data signal Vd (j) is supplied to one of the electrodes. Further, the other electrode of the holding capacity 41 in each row is commonly connected to the feeder line 63 to which the potential Vss, which is a fixed potential, is supplied. Here, the potential Vss may correspond to the L level of the scanning signal or the control signal which is a logic signal. The capacity value of the holding capacity 41 is set to Crf2.

The pixel circuit 110 will be described with reference to FIG. Since each pixel circuit 110 has the same configuration electrically, it is located in the i-th row and is located in the (3j-2) th column of the leftmost column of the j-th group. The pixel circuit 110 in the (3j-2) column will be described as an example. Note that i is a symbol when generally indicating the rows arranged by the pixel circuit 110, and is an integer of 1 or more and m or less.

As shown in FIG. 4, the pixel circuit 110 includes P-channel MOS type transistors 121 to 125, an OLED 130, and a holding capacity 132. Scanning signals Gwr (i), control signals Gcmp (i), Gel (i), and Gorst (i) are supplied to the pixel circuit 110. Here, the scanning signal Gwr (i), the control signals Gcmp (i), Gel (i), and Gorst (i) are supplied by the scanning line drive circuit 20 corresponding to the i-th row, respectively.
Although not shown in FIG. 2, the display panel 2 (display unit 100) has m-row control lines 143 (first control lines) extending in the horizontal direction (X direction) in FIG. 2 in the horizontal direction. An extending m-line control line 144 (second control line) and a laterally extending m-line control line 145 (third control line) are provided. Then, the scanning line drive circuit 20 has control signals Gcmp (1), Gcmp (2), Gcmp (3), ..., Gcmp for the control lines 143 on the first, second, third, ..., mth lines, respectively. (m) is supplied, and the control signals Gel (1), Gel (2), Gel (3), ..., Gel (m) are supplied to the control lines 144 on the first, second, third, ..., and mth lines, respectively. ) Is supplied, and the control signals Gorst (1), Gorst (2), Gorst (3), ..., Gorst (m) are sent to the control lines 145 on the first, second, third, ..., mth lines, respectively. Supply. That is, the scanning line drive circuit 20 outputs the scanning signals Gwr (i), the control signals Gel (i), Gcmp (i), and Gorst (i) to the (3n) pixel circuits located in the i-th row. , They are commonly supplied via the scanning line 12 on the i-th line and the control lines 143, 144, 145, respectively. Hereinafter, the scanning line 12, the control line 143, the control line 144, and the control line 145 may be collectively referred to as a “control line”. That is, the display panel 2 according to the present embodiment is provided with four control lines including the scanning line 12 in each line.

In the transistor 122, the gate is electrically connected to the scanning line 12 in the i-th row, and one of the source and the drain is electrically connected to the data line 14 in the (3j-2) column. Further, the holding capacity 132 has two electrodes. In the transistor 122, the other of the source and the drain is electrically connected to the gate of the transistor 121, one electrode of the holding capacitance 132, and one of the source and the drain of the transistor 123, respectively. That is, the transistor 122 is electrically connected between the gate of the transistor 121 and the data line 14, and functions as a writing transistor that controls the electrical connection between the gate of the transistor 121 and the data line 14. In the following, the wiring for electrically connecting the gate of the transistor 121, the source or drain of the transistor 122, the source or drain of the transistor 123, and one electrode of the holding capacity 132 (of the transistor 121). ) It may be called a gate node g.
In the transistor 121, the source is electrically connected to the feeder line 116, and the drain is electrically connected to the source or the drain of the transistor 123 and the source of the transistor 124, respectively. Here, the feeding line 116 is fed with the potential Vel on the higher side of the power supply in the pixel circuit 110. The transistor 121 functions as a drive transistor for passing a current corresponding to the voltage between the gate and the source of the transistor 121.
In the transistor 123, the gate is electrically connected to the control line 143, and the control signal Gcmp (i) is supplied. The transistor 123 functions as a first switching transistor that controls the electrical connection between the gate and drain of the transistor 121.
The gate of the transistor 124 is electrically connected to the control line 144, and the control signal Gel (i) is supplied. Further, the drain of the transistor 124 is electrically connected to the source of the transistor 125 and the anode 130a of the OLED 130, respectively. The transistor 124 functions as a second switching transistor that controls the electrical connection between the drain of the transistor 121 and the anode of the OLED 130.
In the transistor 125, the gate is electrically connected to the control line 145, and the control signal Gorst (i) is supplied. Further, the drain of the transistor 125 is electrically connected to the feeder line 16 in the (3j-2) row and is maintained at the reset potential Worst. The transistor 125 functions as a third switching transistor that controls the electrical connection between the feeder line 16 and the anode 130a of the OLED 130.
Since the display panel 2 is formed on a silicon substrate in this embodiment, the substrate potential of the transistors 121 to 125 is set to the potential Vel.
The source and drain of the transistors 121 to 125 in the above may be interchanged according to the relationship between the channel type and the potential of the transistors 121 to 125. Further, the transistor may be a thin film or a field effect transistor.

The holding capacitance 132 has one electrode electrically connected to the gate of the transistor 121 and the other electrode electrically connected to the feeder line 116. Therefore, the holding capacity 132 functions as a first holding capacity for holding the voltage between the gate and source of the transistor 121. The capacity value of the holding capacity 132 is referred to as Cpix. At this time, the capacity value Cdt of the holding capacity 50, the capacity value Crf1 of the holding capacity 44, and the capacity value Cpix of the holding capacity 132 are
Cdt> Crf1 >> Cpix
Is set to be. That is, Cdt is set to be larger than Crf1 and Cpix is set to be sufficiently smaller than Cdt and Crf1. As the holding capacity 132, a capacity parasitic on the gate node g of the transistor 121 may be used, or a capacity formed by sandwiching an insulating layer between different conductive layers on a silicon substrate may be used.

The anode 130a of the OLED 130 is a pixel electrode individually provided for each pixel circuit 110. On the other hand, the cathode of the OLED 130 is a common electrode 118 commonly provided over all of the pixel circuits 110, and is maintained at a potential Vct on the lower side of the power supply in the pixel circuits 110. The OLED 130 is an element in which a white organic EL layer is sandwiched between an anode 130a and a cathode having light transmission in the silicon substrate. Then, a color filter corresponding to any of RGB is superimposed on the emission side (cathode side) of the OLED 130.
In such an OLED 130, when a current flows from the anode 130a to the cathode, the holes injected from the anode 130a and the electrons injected from the cathode are recombined in the organic EL layer to generate excitons, and white light is emitted. Occur. The white light generated at this time passes through the cathode on the opposite side of the silicon substrate (anode 130a), is colored by a color filter, and is visually recognized by the observer.

Next, the structure of the pixel circuit 110 will be described with reference to FIGS. 5 and 6.
FIG. 5 is a plan view showing the configuration of the pixel circuit 110 in rows i (3j-2). FIG. 5 shows a wiring structure when the pixel circuit 110 having a top emission structure is viewed in a plan view from the observation side, but for simplification, the structure formed after the anode 130a of the OLED 130 is omitted. ing. Further, FIG. 6 is a partial cross-sectional view taken along the line E in FIG. In FIG. 6, the anode 130a of the OLED 130 is shown, and the subsequent structures are omitted. In addition, in FIGS. 5 and 6, the scale may be different in order to make each layer, each member, each region, and the like recognizable size.

As shown in FIG. 6, each element constituting the pixel circuit 110 is formed on the silicon substrate 150. In this embodiment, a P-type semiconductor substrate is used as the silicon substrate 150. N-wells 160 are formed on the silicon substrate 150 over almost the entire surface. In FIG. 5, only the region where the transistors 121 to 125 are provided and its vicinity are hatched in the N well 160 so that the region where the transistors 121 to 125 are provided can be easily grasped when viewed in a plan view. It is shown with.
The potential Vel is supplied to the N well 160 via an N-type diffusion layer (not shown). Therefore, the substrate potential of the transistors 121 to 125 is the potential Vel.

As shown in FIGS. 5 and 6, a plurality of P-type diffusion layers are formed by doping the surface of the N well 160 with ions. Specifically, nine P-type diffusion layers P1 to P9 are formed on the surface of the N-well 160 for each pixel circuit 110. These P-type diffusion layers P1 to P9 function as sources or drains of transistors 121 to 125. Further, a gate insulating layer L0 is formed on the surfaces of the N well 160 and the P-type diffusion layers P1 to P9, and gate electrodes G1 to G5 are formed on the surface of the gate insulating layer L0 by patterning. These gate electrodes G1 to G5 function as gates for transistors 121 to 125, respectively.

As shown in FIG. 5, the transistor 121 has a gate electrode G1, a P-type diffusion layer P1, and a P-type diffusion layer P2. Of these, the P-type diffusion layer P1 functions as a source of the transistor 121, and the P-type diffusion layer P2 functions as a drain of the transistor 121.
Further, the transistor 122 has a gate electrode G2, a P-type diffusion layer P3, and a P-type diffusion layer P4. Of these, the P-type diffusion layer P3 functions as one of the source or drain of the transistor 122, and the P-type diffusion layer P4 functions as the other of the source or drain of the transistor 122.
The transistor 123 has a gate electrode G3, a P-type diffusion layer P4, and a P-type diffusion layer P5. Of these, the P-type diffusion layer P4 functions as one of the source or drain of the transistor 123, and the P-type diffusion layer P5 functions as the other of the source or drain of the transistor 123. That is, the P-type diffusion layer P4 functions as one of the source or drain of the transistor 122 and also as one of the source or drain of the transistor 123.
The transistor 124 has a gate electrode G4, a P-type diffusion layer P6, and a P-type diffusion layer P7. Of these, the P-type diffusion layer P6 functions as a source of the transistor 124, and the P-type diffusion layer P7 functions as a drain of the transistor 124.
In this embodiment, the drain of the transistor 121, the source or the drain of the transistor 123, and the source of the transistor 124 are composed of separate P-type diffusion layers P2, P5, and P6, respectively. It may be composed of one P-type diffusion layer. In this case, it is not necessary to provide the relay node N13 described later.
The transistor 125 has a gate electrode G5, a P-type diffusion layer P8, and a P-type diffusion layer P9. Of these, the P-type diffusion layer P8 functions as a source of the transistor 125, and the P-type diffusion layer P9 functions as a drain of the transistor 125.

As shown in FIG. 6, the first interlayer insulating layer L1 is formed so as to cover the gate electrodes G1 to G5 and the gate insulating layer L0.
By patterning a conductive wiring layer such as aluminum on the surface of the first interlayer insulating layer L1, scanning lines 12, feeder lines 116, and control lines 143 to 145 are formed for each row. , Relay nodes N11 to N16 and a branch portion 116a are formed for each pixel circuit 110, respectively. The wiring layer formed on the surface of the first interlayer insulating layer L1 may be collectively referred to as the first wiring layer.

As shown in FIG. 5, the feeder line 116 extends in the X direction intersecting the Y-axis direction, and has a portion (branch portion 116a) branched in the Y direction for each pixel circuit 110. When the branch portion 116a is viewed in a plan view (that is, when the pixel circuit 110 is viewed from a direction perpendicular to the surface on which the pixel circuit 110 of the silicon substrate 150 is arranged), a part of the branch portion 116a and the P-type diffusion layer P1 Are provided so that they overlap each other. Further, as shown in FIGS. 5 and 6, the branch portion 116a is electrically connected to the P-type diffusion layer P1 via the contact hole Ha1 penetrating the first interlayer insulating layer L1. In addition, in FIG. 5, the contact hole is shown as a portion where different types of wiring layers overlap each other and is marked with an “x” in the “□” mark.

As shown in FIG. 5, the scanning line 12 extends in the X direction and is provided so as to intersect the gate electrode G1 and the gate electrode G2 when viewed in a plan view. That is, when viewed in a plan view, at least a part of the scanning line 12 and at least a part of the gate electrode G1 overlap. Further, the scanning line 12 is electrically connected to the gate electrode G2 via the contact hole Ha5.
The control line 143 extends in the X direction and is provided so as to intersect the gate electrode G1 and the gate electrode G3 when viewed in a plan view. Further, the control line 143 is electrically connected to the gate electrode G3 via the contact hole Ha7.
The control line 144 extends in the X direction and is provided so as to intersect the gate electrode G4 when viewed in a plan view, and is electrically connected to the gate electrode G4 via the contact hole Ha10. The control line 145 extends in the X direction and is provided so as to intersect the gate electrode G5 when viewed in a plan view, and is electrically connected to the gate electrode G5 via the contact hole Ha14.

As shown in FIGS. 5 and 6, the relay node N11 is electrically connected to the gate electrode G1 via the contact hole Ha2 and electrically connected to the P-type diffusion layer P4 via the contact hole Ha6. Ru. That is, the relay node N11 corresponds to the gate node g that electrically connects the gate of the transistor 121, the other of the source or drain of the transistor 122, and the source or drain of the transistor 123.
The relay node N16 is provided so that the relay node N16 and a part of the gate electrode G1 overlap each other when viewed in a plan view. Then, the relay node N16 and the gate electrode G1 sandwich the first interlayer insulating layer L1 to form the holding capacity 132. That is, the gate electrode G1 corresponds to one electrode of the holding capacity 132, and the relay node N16 corresponds to the other electrode of the holding capacity 132.
The relay node N12 is electrically connected to the P-type diffusion layer P3 via the contact hole Ha4. The relay node N13 is electrically connected to the P-type diffusion layer P2 via the contact hole Ha3, and is electrically connected to the P-type diffusion layer P5 via the contact hole Ha8, and is electrically connected to the P-type diffusion layer P5 via the contact hole Ha9. It is electrically connected to the type diffusion layer P6. The relay node N14 is electrically connected to the P-type diffusion layer P7 via the contact hole Ha11 and electrically connected to the P-type diffusion layer P8 via the contact hole Ha12. The relay node N15 is electrically connected to the P-type diffusion layer P9 via the contact hole Ha13.

As shown in FIG. 6, the second interlayer insulating layer L2 is formed so as to cover the first wiring layer and the first interlayer insulating layer L1.
By patterning a conductive wiring layer such as aluminum on the surface of the second interlayer insulating layer L2, a data line 14 and a feeder line 16 are formed for each row, and each pixel circuit 110 is formed. , Relay nodes N21 and N22 are formed, respectively. The wiring layer formed on the surface of the second interlayer insulating layer L2 may be collectively referred to as the second wiring layer.
As shown in FIG. 5, the data line 14 is electrically connected to the relay node N12 via the contact hole Hb2. As a result, the P-type diffusion layer P3 is electrically connected to the data line 14 via the relay node N12. The feeder line 16 is electrically connected to the relay node N15 via the contact hole Hb3. As a result, the P-type diffusion layer P9 is electrically connected to the feeder line 16 via the relay node N15. The relay node N21 is electrically connected to the feeder line 116 via the contact hole Hb1 and electrically connected to the relay node N16 (the other electrode of the holding capacity 132) via the contact hole Hb4. As a result, the relay node N16 is electrically connected to the feeder line 116 via the relay node N21 and is maintained at the potential Vel.
Further, as shown in FIG. 6, the relay node N22 is electrically connected to the relay node N14 via the contact hole Hb5.

As shown in FIG. 6, the third interlayer insulating layer L3 is formed so as to cover the second wiring layer and the second interlayer insulating layer L2.
The anode 130a of the OLED 130 is formed on the surface of the third interlayer insulating layer L3 by patterning a wiring layer having conductivity such as aluminum or ITO (Indium Tin Oxide). The anode 130a of the OLED 130 is an individual pixel electrode for each pixel circuit 110, and is connected to the relay node N22 via the contact hole Hc1 penetrating the third interlayer insulating layer L3. That is, the anode 130a of the OLED 130 supplies electricity to the P-type diffusion layer P7 (that is, the drain of the transistor 124) and the P-type diffusion layer P8 (that is, the source of the transistor 125) via the relay node N22 and the relay node N14. Connected to.
Although not shown, a light emitting layer made of an organic EL material is laminated on the anode 130a of the OLED 130, which is divided into pixel circuits 110. A cathode (common electrode 118), which is a transparent electrode common to all of the plurality of pixel circuits 110, is provided on the light emitting layer. That is, the OLED 130 sandwiches the light emitting layer between the anode and the cathode facing each other, and emits light with brightness corresponding to the current flowing from the anode to the common electrode 118. Of the light emitted by the OLED 130, the light directed in the direction opposite to that of the silicon substrate 150 (that is, upward in FIG. 6) is visually recognized as an image by the observer (top emission structure). In addition to this, a sealing material or the like for blocking the light emitting layer from the atmosphere is provided, but the description thereof will be omitted.

<Operation of the embodiment>
The operation of the electro-optical device 1 will be described with reference to FIG. 7. FIG. 7 is a timing chart for explaining the operation of each part in the electro-optical device 1. As shown in this figure, the scanning line drive circuit 20 sequentially switches the scanning signals Gwr (1) to Gwr (m) to the L level, and sets the scanning lines 12 on the 1st to mth lines to 1 in a period of one frame. Scans are performed in order for each horizontal scanning period (H). The operation in one horizontal scanning period (H) is common throughout the pixel circuits 110 of each row. Therefore, the operation will be described below with particular attention to the pixel circuit 110 in the i-th row (3j-2) column during the scanning period in which the i-th row is horizontally scanned.

In the present embodiment, the scanning period of the i-th line is roughly divided into an initialization period shown by (b), a compensation period shown by (c), and a writing period shown by (d) in FIG. Be done. Then, after the writing period of (d), the light emitting period shown by (a) is reached, and after the period of one frame elapses, the scanning period of the i-th row is reached again. Therefore, in the order of time, the cycle of (light emitting period) → initialization period → compensation period → writing period → (light emitting period) is repeated.
In FIG. 7, the scanning signals Gwr (i-1), the control signals Gel (i-1), and Gcmp (i-1) corresponding to the (i-1) line one line before the i-th line. For each of the Gorst (i-1), one horizontal scan is performed in terms of time from the scanning signals Gwr (i), control signals Gel (i), Gcmp (i), and Gorst (i) corresponding to the i-th line. The waveform is time-advanced by the period (H).

<Light emission period>
For convenience of explanation, the light emission period, which is the premise of the initialization period, will be described first. In the light emitting period of the i-th row, the scanning line drive circuit 20 supplies a predetermined second potential V2 to the scanning line 12 of the i-th row and supplies a predetermined first potential V1 to the control line 144 of the i-th row. , The second potential V2 is supplied to the control line 143 of the i-th line, and the second potential V2 is supplied to the control line 145 of the i-th line. In this embodiment, the first potential V1 is set lower than the second potential V2. For example, the first potential V1 may be any one corresponding to the L level of the control signal (control signal Gref or the like) supplied by the control circuit 3, and the second potential VH may be the H of the control signal supplied by the control circuit 3. It may be the one corresponding to the level. That is, as shown in FIG. 7, the scanning signal Gwr (i) is set to the H level, the control signal Gel (i) is set to the L level, and the control signal Gcmp (i) is set during the light emission period of the i-th row. Is set to H level, and the control signal Gorst (i) is set to H level.
Therefore, as shown in FIG. 8, in the pixel circuit 110 of the i-row (3j-2) column, the transistor 124 is turned on, while the transistors 122, 123, 125 are turned off. Therefore, the transistor 121 supplies the OLED 130 with a current Ids corresponding to the voltage Vgs between the gate and source. As will be described later, in the present embodiment, the voltage Vgs during the light emission period is a value obtained by level-shifting the potential of the data signal. Therefore, the current corresponding to the gradation level is supplied to the OLED 130 in a state where the threshold voltage of the transistor 121 is compensated.

Since the light emitting period of the i-th row is the period during which the non-i-th row is horizontally scanned, the potential of the data line 14 fluctuates as appropriate. However, since the transistor 122 is turned off in the pixel circuit 110 on the i-th row, the potential fluctuation of the data line 14 is not considered here. Further, in FIG. 8, the routes that are important in the explanation of the operation during the light emission period are shown by thick lines.

<Initialization period>
Next, when the scanning period of the i-th row is reached, the initialization period of (b) starts as the first period.
In the initialization period of the i-th row, the scanning line drive circuit 20 supplies the second potential V2 to the scanning line 12 of the i-th row to bring the scanning signal Gwr (i) to the H level, as shown in FIG. The second potential V2 is supplied to the control line 144 on the i-th line to set the control signal Gel (i) to the H level, and the second potential V2 is supplied to the control line 143 on the i-th line to supply the control signal. Gcmp (i) is set to H level, the first potential V1 is supplied to the control line 145 on the i-th line, and the control signal Gorst (i) is set to L level. Therefore, in the pixel circuit 110 of the i-row (3j-2) column, the transistor 124 is turned off and the transistor 125 is turned on. As a result, the path of the current supplied to the OLED 130 is cut off, and the anode 130a of the OLED 130 is set to the reset potential Worst.
Since the OLED 130 has a configuration in which the organic EL layer is sandwiched between the anode 130a and the cathode as described above, the capacitance parasitizes in parallel between the anode and the cathode. When a current is flowing through the OLED 130 during the light emission period, the voltage across the anode and cathode of the OLED 130 is held by the capacitance parasitized in parallel between the anode and cathode, and this holding voltage is held by turning on the transistor 125. It will be reset. Therefore, in the present embodiment, when the current flows through the OLED 130 again in the later light emitting period, it is less affected by the voltage held by the capacitance parasitized in parallel between the anode and the cathode.

In detail, for example, when the display state changes from the high brightness display state to the low brightness display state, if the configuration is not reset, the high voltage when the brightness is high (a large current flows) is maintained. In addition, even if a small current is to be passed, an excessive current will flow, and it will not be possible to obtain a low-luminance display state. On the other hand, in the present embodiment, the potential of the anode 130a of the OLED 130 is reset by turning on the transistor 125, so that the reproducibility on the low brightness side is improved. In the present embodiment, the reset potential Vorst is set so that the difference between the reset potential Vorst and the potential Vct of the common electrode 118 is lower than the emission threshold voltage of the OLED 130. Therefore, in the initialization period (compensation period and writing period described below), the OLED 130 is in the off (non-light emitting) state.

On the other hand, in the initialization period of the i-th line, as shown in FIG. 7, the control circuit 3 sets the control signal / Gini to the L level, the control signal Gref to the H level, and the control signal Gcpl to the L level, respectively. Set. Therefore, the transistor 43 and the transistor 45 are turned on. As a result, one electrode of the holding capacity 44 and the feeder line 61 are electrically connected, and one electrode (and the data line 14) of the holding capacity 44 is initialized to the initial potential Vini. Further, the other electrode of the holding capacity 44 and the feeder line 62 are electrically connected, and the other electrode of the holding capacity 44 (and the node h1) is initialized to the reference potential Vref.
In the present embodiment, the initial potential Vini is set so that (Vel-Vini) is larger than the threshold voltage | Vth | of the transistor 121. Since the transistor 121 is a P-channel type, the threshold voltage Vth based on the potential of the source is negative. Therefore, in order to prevent confusion in the explanation of the high-low relationship, the threshold voltage is represented by the absolute value | Vth | and is specified by the magnitude relationship.

As shown in FIG. 7, the data signal supply circuit 70 includes the demultiplexer DM (1) and DM (2) in the period from the start of the scanning period of the i-th row to the start of the writing period. ), ..., DM (n), respectively, the data signals Vd (1), Vd (2), ..., Vd (n) are supplied. That is, in the data signal supply circuit 70, in the j-th group, the data signal Vd (j) is sequentially arranged in the i-row (3j-2) column, the i-row (3j-1) column, and the i-row (3j). Switch to the potential according to the gradation level of the pixels in the row.
On the other hand, the control circuit 3 exclusively sets the control signals Sel (1), Sel (2), and Sel (3) to the H level in order according to the switching of the potential of the data signal. As a result, the three transmission gates 34 provided in each demultiplexer DM are turned on in the order of the left end row, the center row, and the right end row, respectively.
Here, in the initialization period, when the transmission gate 34 in the leftmost row belonging to the j-th group is turned on by the control signal Self (1), the data signal Vd (j) is supplied to one electrode of the holding capacity 41. Therefore, the data signal Vd (j) is held by the holding capacity 41.

<Compensation period>
In the scanning period of the i-th row, the compensation period of (c) is then set as the second period. In the compensation period of the i-th line, the control circuit 3 sets the control signal / Gini to the H level, the control signal Gref to the H level, and the control signal Gcpl to the L level, respectively, as shown in FIG. Therefore, the transistor 43 is turned on, while the transistor 45 is turned off. As a result, the other electrode of the holding capacity 44 and the feeder line 62 are electrically connected, and the node h1 is set to the reference potential Vref.

Further, in the compensation period, when the transmission gate 34 in the leftmost row belonging to the j-th group is turned on by the control signal Self (1), the data signal Vd (j) is supplied to one electrode of the holding capacity 41.
If the transmission gate 34 in the leftmost row belonging to the jth group is already turned on by the control signal Sel (1) in the initialization period, the transmission gate 34 is not turned on in the compensation period. The data signal Vd (j) supplied when the transmission gate 34 in the leftmost row is turned on is held by the holding capacitance 41.

Further, during the compensation period of the i-th row, the scanning line drive circuit 20 supplies the first potential V1 to the scanning line 12 of the i-th row to set the scanning signal Gwr (i) to the L level, as shown in FIG. Is set to, the second potential V2 is supplied to the control line 144 on the i-th line, the control signal Gel (i) is set to the H level, and the first potential V1 is supplied to the control line 143 on the i-th line for control. The signal Gcmp (i) is set to the L level, the first potential V1 is supplied to the control line 145 on the i-th line, and the control signal Gorst (i) is set to the L level. Therefore, since the transistor 123 is turned on, the transistor 121 is connected by a diode. As a result, a drain current flows through the transistor 121 to charge the gate node g and the data line 14. Specifically, the current flows through the route of the feeder line 116 → the transistor 121 → the transistor 123 → the transistor 122 → the data line 14 in the (3j-2) column. Therefore, the data lines 14 and the gate node g, which are connected to each other by turning on the transistor 121, rise from the initial potential Vini. However, the current flowing in the above path becomes difficult to flow as the gate node g approaches the potential (Vel− | Vth |), so that the data line 14 and the gate node g become potential (Vel−) by the end of the compensation period. | Vth |) saturates.
Therefore, the holding capacity 132 holds the threshold voltage | Vth | of the transistor 121 at the end of the compensation period. In the following, the potential (Vel− | Vth |) of the gate node g at the end of the compensation period may be referred to as the potential Vp.

When the compensation period ends, the scanning line drive circuit 20 changes the control signal Gcmp (i) from the L level to the H level by switching the potential supplied to the control line 143 from the first potential V1 to the second potential V2. To do. As a result, the diode connection of the transistor 121 is released.
The scanning line drive circuit 20 controls the waveform when the control signal Gcmp (i) changes from the L level to the H level so as to be gentler than the waveform when the control signal Gcmp (i) changes from the H level to the L level. The potential supplied to the wire 143 is switched. That is, as shown in FIG. 7, the period in which the scanning line drive circuit 20 switches the potential supplied to the control line 143 from the second potential V2 to the first potential V1 is set as the third switching period T3, and from the first potential V1. The period for switching to the second potential V2 is defined as the fourth switching period T4. At this time, the scanning line drive circuit 20 changes the potential supplied to the control line 143 so that the time length of the fourth switching period T4 is sufficiently longer than the time length of the third switching period T3.

As described above, when viewed in a plan view, the control line 143 and the gate electrode G1 (gate of the transistor 121) intersect with each other. Therefore, there is a parasitic capacitance between the control line 143 and the gate electrode G1. Therefore, if the time length of the fourth switching period T4 is shortened to the same level as the time length of the third switching period T3 and the control signal Gcmp (i) is suddenly raised from the L level to the H level, control is performed. The potential of the gate electrode G1 changes due to the influence of the high frequency component of the control signal Gcmp (i) on the line 143.
Although details will be described later, at the end of the compensation period, the potential of the gate node g (potential of the gate electrode G1) is set to a potential that compensates for the variation in the threshold voltage of the transistor 121 for each pixel circuit 110. However, when the potential of the gate node g changes after the end of the compensation period, it becomes impossible to compensate for the variation in the threshold voltage for each pixel circuit 110, so that there is a problem that display unevenness that impairs the uniformity of the display screen occurs. Becomes noticeable.
On the other hand, in the present embodiment, when the time length of the fourth switching period T4 is sufficiently made longer than the time length of the third switching period T3 and the control signal Gcmp (i) changes from the L level to the H level. By making the waveform of No. 1 a gentle waveform, it is possible to prevent the potential fluctuation of the control line 143 from propagating to the gate node g (gate electrode G1). As a result, it is possible to compensate for the variation in the threshold voltage for each pixel circuit 110 and to perform high-quality display that guarantees the uniformity of display.

Actually, the time length of the third switching period T3 is sufficiently short enough to be regarded as "0". That is, the waveform when the control signal Gcmp (i) falls from the H level to the L level may be the same as the waveform when the control signal Gref falls from the H level to the L level, for example. However, in FIG. 7, for convenience of explanation, the falling waveform of the control signal Gcmp (i) is shown as a gentler waveform than the actual waveform in order to illustrate the third switching period T3.

Further, when the compensation period ends, the control circuit 3 changes the control signal Gref from the H level to the L level, so that the transistor 43 is turned off. Therefore, although the path from the data line 14 in the (3j-2) column to the gate node g in the pixel circuit 110 in the i-row (3j-2) column is in a floating state, the potential of the path is It is maintained at (Vel- | Vth |) by the holding capacities 50 and 132.

<Writing period>
After the initialization period, the writing period of (d) is reached as the third period. During the writing period of the i-th line, the scanning line drive circuit 20 supplies the first potential V1 to the scanning line 12 of the i-th line to bring the scanning signal Gwr (i) to the L level, as shown in FIG. The second potential V2 is supplied to the control line 144 on the i-th line to set the control signal Gel (i) to the H level, and the second potential V2 is supplied to the control line 143 on the i-th line to supply the control signal. Gcmp (i) is set to H level, the first potential V1 is supplied to the control line 145 on the i-th line, and the control signal Gorst (i) is set to L level. As a result, the diode connection of the transistor 121 is released.

Further, in the writing period of the i-th line, as shown in FIG. 7, the control circuit 3 sets the control signal / Gini to the H level, the control signal Gref to the L level, and the control signal Gcpl to the H level, respectively. Set. Therefore, since the transmission gate 42 is turned on, the data signal Vd (j) held in the holding capacity 41 is supplied to the other electrode of the holding capacity 44 via the node h1. As a result, the other electrode of the node h1 and the holding capacity 44 changes from the reference potential Vref during the compensation period. The amount of potential change of the node h1 at this time is expressed as ΔVh. Further, the potential (Vref + ΔVh) of the node h1 during the writing period may be expressed as the potential Vh.
When the potential of the node h1 changes from the reference potential Vref to the potential Vh by ΔVh, the potentials of the gate node g and the data line 14 also change from the potential Vp = (Vel− | Vth |) set in the compensation period. .. The amount of potential change of the gate node g at this time is expressed as ΔVg. Further, the potential (Vp + ΔVg) of the gate node g during the writing period may be expressed as the potential Vgate.

In the following, with reference to FIG. 9, changes in the potentials of the gate node g and the node h1 before and after the start of the writing period will be described in detail.
FIG. 9A is an explanatory diagram for explaining the potential changes of the node h1 and the gate node g before and after the start of the writing period. In this figure, (A-1) represents the potentials of the node h1 and the gate node g before the start of the writing period, and (A-2) shows the potential after the start of the writing period (that is, the transmission gate 42 is turned on). The potentials of the node h1 and the gate node g in (after) are shown. Since the holding capacity 50 and the holding capacity 132 are electrically connected in parallel during the compensation period and the writing period, the capacity value C0 of the combined capacity 501 of the holding capacity 50 and the holding capacity 132 is expressed by the following equation (1). ).
C0 = Cpix + Cdt …… (1)

Assuming that the charge accumulated in the combined capacity 501 before the start of the writing period is Q0a and the charge accumulated in the combined capacity 501 after the start of the writing period is Q0b, the charge is synthesized before and after the start of the writing period. The electric charge (Q0a-Q0b) flowing out of the capacitance 501 is represented by the following equation (2). Similarly, assuming that the charge stored in the holding capacity 44 is Q1a before the start of the writing period and the charge stored in the holding capacity 44 is Q1b after the start of the writing period, the writing period starts. The electric charge (Q1b-Q1a) flowing into the holding capacity 44 before and after is represented by the following equation (3). Before and after the start of the writing period, the electric charge flowing out from the combined capacitance 501 and the electric charge flowing into the holding capacitance 44 are equal, so the following equation (4) is established.
Q0a-Q0b = C0 * (Vp-Vgate) …… (2)
Q1b-Q1a = Crf1 * {(Vgate-Vh)-(Vp-Vref)} …… (3)
Q0a-Q0b = Q1b-Q1a …… (4)

From equations (2) to (4), the potential Vgate of the gate node g during the writing period can be calculated. Specifically, the potential Vgate is represented by the following equation (5).
Vgate = {Crf1 / (Crf1 + C0)} * {Vh-Vref} + Vp …… (5)

Here, the capacity ratio k1 represented by the following formula (6) is introduced. At this time, the potential Vgate of the gate node g in the writing period can be expressed by the following equation (7) using the capacitance ratio k1, and the potential change amount ΔVg of the gate node g before and after the start of the writing period is the capacitance ratio. It can be expressed by the following equation (8) using k1.
k1 = Crf1 / (Crf1 + Cdt + Cpix) …… (6)
Vgate = k1 * (Vh-Vref) + Vp
= K1 * ΔVh + Vp …… (7)
ΔVg = Vgate-Vp
= K1 * ΔVh …… (8)

As described above, in the writing period, the potential of the gate node g is a value (k1 * ΔVh) obtained by multiplying the potential change amount ΔVh of the node h1 by the capacitance ratio k1 from the potential Vp = (Vel− | Vth |) in the compensation period. The potential Vgate = (Vel− | Vth | + k1 · ΔVh) shifted in the upward direction by). At this time, the absolute value | Vgs | of the voltage Vgs of the transistor 121 is a value obtained by subtracting the potential increase of the gate node g from the threshold voltage | Vth | as shown in the following equation (9).
｜ Vgs ｜ ＝ ｜ Vth ｜ −k1 * ΔVh …… (9)

FIG. 9B is an explanatory diagram for explaining the potential changes of the nodes h1 and h2 before and after the start of the writing period. In this figure, (B-1) represents the potentials of the nodes h1 and h2 before the start of the writing period, and (B-2) shows the potentials of the nodes h1 and h2 after the start of the writing period (that is, the transmission gate 42 is turned on). It shows the potentials of node h1 and node h2 in (later). Since the combined capacity 501 of the holding capacity 50 and the holding capacity 132 and the holding capacity 41 are electrically connected in series during the compensation period and the writing period, the holding capacity 50, the holding capacity 132, and the holding capacity 44 The capacitance value C1 of the combined capacitance 502 is represented by the following equation (10).
C1 = (C0 * Crf1) / (C0 + Crf1) …… (10)

Assuming that the charge accumulated in the combined capacity 502 before the start of the writing period is Q1c and the charge accumulated in the combined capacity 502 after the start of the writing period is Q1d, the combined capacity is before and after the start of the writing period. The electric charge (Q1c−Q1d) flowing out from 502 is represented by the following equation (11). Similarly, assuming that the charge stored in the holding capacity 41 before the start of the writing period is Q2c and the charge stored in the holding capacity 41 after the start of the writing period is Q2d, before and after the start of the writing period. The electric charge (Q2d−Q2c) flowing into the holding capacity 41 is represented by the following equation (12). Before and after the start of the writing period, the electric charge flowing out from the combined capacity 502 and the electric charge flowing into the holding capacity 41 are equal, so the following equation (13) holds.
Q1c-Q1d = C1 * {Vref-Vh} …… (11)
Q2d-Q2c = Crf2 * {Vh-Vd (j)} …… (12)
Q1c-Q1d = Q2d-Q2c …… (13)

Therefore, the potential Vh of the node h1 during the writing period can be calculated from the equations (11) to (13). Specifically, the potential Vh is represented by the following equation (14). The potential change amount ΔVh at the node h1 is expressed by the following equation (15).
Vh = {C1 / (C1 + Crf2)} * (Vref)
+ {Crf2 / (C1 + Crf2)} * {Vd (j)} …… (14)
ΔVh = Vh-Vref
= {Crf2 / (C1 + Crf2)} * {Vd (j) -Vref} …… (15)

Here, when the capacitance ratio k2 represented by the following formula (16) is introduced, the potential change amount ΔVh can also be expressed by the following formula (17).
k2 = Crf2 / (C1 + Crf2) …… (16)
ΔVh = k2 * {Vd (j) −Vref} …… (17)

The potential Vgate of the gate node g during the writing period can be expressed by the following equation (18) by substituting the equation (17) for the equation (7). Therefore, the potential change amount ΔVg of the gate electrode G before and after the start of the writing period can be expressed by the following equation (19).
Vgate = k1 * k2 * {Vd (j) -Vref} + Vp …… (18)
ΔVg = k1 * k2 * {Vd (j) -Vref} …… (19)

In this way, the potential of the node h1 shifts the potential indicated by the data signal Vd (j) by the reference potential Vref, and changes this by the value ΔVh compressed by the capacitance ratio k2. As a result, the potential Vgate of the gate node g changes by the value obtained by further compressing the potential change amount ΔVh of the node h1 with the capacitance ratio k1. That is, as shown in the equation (18), the potential Vgate of the gate node g during the writing period shifts the data signal Vd (j) by the reference potential Vref, and has a capacitance value with respect to the shifted potential. A compressed potential is supplied by multiplying the capacitance ratio k3 = k1 * k2 determined based on Cdt, Crf1, Crf2, and Cpix.

FIG. 10 is a diagram showing the relationship between the potential of the data signal Vd (j) and the potential Vgate of the gate node g during the writing period. The data signal Vd (j) generated based on the image signal Vid supplied from the control circuit 3 can take a potential range from the minimum value Vmin to the maximum value Vmax according to the gradation level of the pixel as described above. .. Then, as described above, the potential Vgate in which the data signal Vd (j) is shifted by the reference potential Vref and compressed by the capacitance ratio k3 is written in the gate node g. At this time, the potential range ΔVgate of the gate node g is compressed to a value obtained by multiplying the potential range ΔVdata (= Vmax−Vmin) of the data signal by the capacitance ratio k3, as shown in the following equation (20).
ΔVgate = k3 * ΔVdata …… (20)

Further, as is clear from the equation (18), how much the potential range ΔVgate of the gate node g is shifted with respect to the potential range ΔVdata of the data signal is the potential Vp (= Vel− | Vth). It can be determined based on |) and the reference potential Vref.

After the writing period ends, the scanning line drive circuit 20 switches the potential supplied to the scanning line 12 from the first potential V1 to the second potential V2, thereby changing the scanning signal Gwr (i) from the L level to the H level. change. As a result, the transistor 122 is turned off, so that the potential of the gate node g is maintained at the potential Vgate = [{Vel- | Vth |} + k3 · {Vd (j) -Vref}].
In the scanning line drive circuit 20, the scanning line is set so that the waveform when the scanning signal Gwr (i) changes from the L level to the H level is gentler than the waveform when the scanning signal Gwr (i) changes from the H level to the L level. The potential supplied to 12 is switched. That is, as shown in FIG. 7, the period in which the scanning line drive circuit 20 switches the potential supplied to the scanning line 12 from the second potential V2 to the first potential V1 is set as the first switching period T1, and from the first potential V1. The period for switching to the second potential V2 is defined as the second switching period T2. At this time, the scanning line drive circuit 20 changes the potential supplied to the scanning line 12 so that the time length of the second switching period T2 is sufficiently longer than the time length of the first switching period T1.

As described above, the scanning line 12 and the gate electrode G1 (gate of the transistor 121) intersect with each other when viewed in a plan view. Therefore, there is a parasitic capacitance between the scanning line 12 and the gate electrode G1. Therefore, if the time length of the second switching period T2 is shortened to the same extent as the time length of the first switching period T1 and the scanning signal Gwr (i) is suddenly raised from the L level to the H level, scanning is performed. The potential of the gate electrode G1 changes due to the influence of the high frequency component of the scanning signal Gwr (i) on the line 12.
As described above, at the end of the writing period, the potential of the gate node g (potential of the gate electrode G1) is determined by the potential Vgate based on the data signal Vd (j) (image signal Vid) that defines the brightness of the OLED 130. .. However, when the potential of the gate node g changes after the end of the writing period, the potential of the gate node g becomes a potential different from the potential Vgate determined based on the data signal Vd (j). In this case, each pixel displays a gradation different from the gradation defined by the image signal Vid, and the display quality deteriorates.
On the other hand, in the present embodiment, when the time length of the second switching period T2 is sufficiently made longer than the time length of the first switching period T1 and the scanning signal Gwr (i) changes from the L level to the H level. By making the waveform of No. 1 a gentle waveform, it is possible to prevent the potential fluctuation of the scanning line 12 from propagating to the gate node g (gate electrode G1). As a result, each pixel can accurately display the gradation defined by the image signal Vid, and high-quality display becomes possible.

In reality, the time length of the first switching period T1 is sufficiently short enough to be regarded as "0". That is, the waveform when the scanning signal Gwr (i) falls from the H level to the L level may be the same as the waveform when the control signal Gref falls from the H level to the L level, for example. However, in FIG. 7, for convenience of explanation, in order to illustrate the first switching period T1, the falling waveform of the scanning signal Gwr (i) is described so as to be sufficiently gentler than the actual one. ..

<Light emission period>
After the writing period of the i-th line ends, the light emitting period starts. In the present embodiment, after the end of the writing period of the i-th row, the light emitting period is started after one horizontal scanning period. During the light emission period, the scanning line drive circuit 20 sets the scanning signal Gwr (i) to the H level as described above, so that the transistor 122 is turned off and the gate node g has the potential Vgate = [{Vel- | Vth. |} + K3 · {Vd (j) -Vref}] is maintained. Further, during the light emitting period, the scanning line drive circuit 20 sets the control signal Gel (i) to the L level, so that the transistor 124 is turned on in the pixel circuit 110 in the i-row (3j-2) column. Since the voltage Vgs between the gate and the source is [| Vth | −k3 · {Vd (j) −Vref}], the OLED 130 has a current corresponding to the gradation level as shown in FIG. Will be supplied in a state where the threshold voltage of the transistor 121 is compensated.
Such an operation is executed in parallel in time in the other pixel circuits 110 in the i-th row other than the pixel circuit 110 in the (3j-2) column during the scanning period in the i-th row. Further, such an operation of the i-th line is actually executed in the order of 1, 2, 3, ..., (M-1), m-th line in the period of one frame, and is repeated for each frame. Is done.

<Effect of embodiment>
According to this embodiment, the scanning line 12 and the control line 143 are provided at positions where they intersect the gate (gate electrode G1) of the transistor 121 when viewed in a plan view. Therefore, a plurality of control lines extending in the X direction (scanning lines 12, control lines 143, 144, 145) are compared with the case where the scanning lines 12 and the control lines 143 are provided so as not to intersect the gate of the transistor 121. Can be wired at high density, and the pitch of the control line can be narrowed. That is, according to the present embodiment, the pixel circuit 110 can be narrowed in pitch by wiring the control lines at a high density, whereby the electro-optical device 1 (display unit 100) can be miniaturized and the display can be made high-definition. It becomes possible to change.

According to the present embodiment, the scanning line drive circuit 20 makes the waveform when the scanning signal Gwr (i) changes from the L level to the H level gentler than the waveform when the scanning signal Gwr (i) changes from the H level to the L level. The potential supplied to the scanning line 12 is changed so as to be. As a result, even when the scanning line 12 and the gate of the transistor 121 intersect when viewed in a plan view, it is possible to prevent the potential fluctuation of the scanning signal Gwr (i) from propagating to the gate of the transistor 121. Therefore, each pixel can accurately display the gradation defined by the image signal Vid.

According to the present embodiment, the scanning line drive circuit 20 makes the waveform when the control signal Gcmp (i) changes from the L level to the H level gentler than the waveform when the control signal Gcmp (i) changes from the H level to the L level. The potential supplied to the control line 143 is changed so as to be. This makes it possible to prevent the potential fluctuation of the control signal Gcmp (i) from propagating to the gate of the transistor 121 even when the control line 143 and the gate of the transistor 121 intersect when viewed in a plan view. Therefore, high-quality display that guarantees the uniformity of display is possible.

According to the present embodiment, the potential range ΔVgate at the gate node g is narrowed with respect to the potential range ΔVdata of the data signal, so that the voltage reflecting the gradation level can be applied to the transistor 121 without carving the data signal with fine precision. Can be applied between the gate and source of. Therefore, even when the minute current flowing through the OLED 130 changes relatively significantly with respect to the change in the voltage Vgs between the gate and the source of the transistor 121 in the pixel circuit 110, the current supplied to the OLED 130 can be controlled with high accuracy. Becomes possible.

Further, as shown by the broken line in FIG. 4, the capacitance Cprs may be parasitic between the data line 14 and the gate node g in the pixel circuit 110. In this case, if the potential change width of the data line 14 is large, it propagates to the gate node g via the capacitance Cprs, so-called crosstalk and unevenness occur, and the display quality is deteriorated. The effect of the capacitance Cprs becomes remarkable when the pixel circuit 110 is miniaturized.
On the other hand, in the present embodiment, the potential change range of the data line 14 is also narrowed with respect to the potential range ΔVdata of the data signal, so that the influence via the capacitance Cprs can be suppressed.

Further, according to the present embodiment, the influence of the threshold voltage is offset by the current Ids supplied to the OLED 130 by the transistor 121. Therefore, according to the present embodiment, even if the threshold voltage of the transistor 121 varies from pixel circuit 110 to pixel circuit 110, the variation is compensated and a current corresponding to the gradation level is supplied to the OLED 130, so that the display screen can be displayed. As a result of suppressing the occurrence of display unevenness that impairs uniformity, high-quality display becomes possible.

This offset will be described with reference to FIG. As shown in this figure, the transistor 121 operates in a weakly inverted region (subthreshold region) in order to control a minute current supplied to the OLED 130.
In the figure, A shows the relationship between the gate potential of a transistor having a large threshold voltage | Vth | and the current supplied by the transistor, and B indicates the gate potential of a transistor having a small threshold voltage | Vth | and the current supplied by the transistor. The relationship is shown. In FIG. 11, the voltage Vgs between the gate and the source is the difference between the solid line and the potential Vel. Further, in FIG. 11, the vertical scale current is shown as a logarithm in which the direction from the source to the drain is negative (bottom).
During the compensation period, the gate node g changes from the initial potential Vini to the potential (Vel− | Vth |). Therefore, the operating point of the transistor having a large threshold voltage | Vth | represented by the solid line A moves from S to Aa, while the operating point of the transistor having a small threshold voltage | Vth | represented by the solid line B is S. Move from to Ba.
Next, when the potentials of the data signals to the pixel circuit 110 to which the two transistors belong are the same, that is, when the same gradation level is specified, the potential shift amount from the operating points Aa and Ba is the same during the writing period. , Both have the same k1 · ΔVh. Therefore, the operating point of the transistor represented by the solid line A moves from Aa to Ab, and the operating point of the transistor represented by the solid line B moves from Ba to Bb, but the current at the operating point after the potential shift Will be aligned with almost the same Ids for both of the two transistors.

According to the present embodiment, the operation of holding the data signal supplied from the control circuit 3 via the demultiplexer DM in the holding capacitance 41 is executed from the initialization period to the compensation period. That is, according to the present embodiment, the operation of initializing the potential of the anode 130a to the reset potential Vorst during the initialization period and the operation of holding the data signal in the holding capacitance 41 are executed in parallel and compensated. The operation of compensating for the variation in the threshold voltage of the transistor 121 during the period and the operation of holding the data signal in the holding capacitance 41 are executed in parallel. Therefore, the time constraint on the operation to be executed in one horizontal scanning period can be relaxed, and the data signal supply operation in the data signal supply circuit 70 can be slowed down.

<Modification example>
The present invention is not limited to the above-described embodiment, and various modifications such as those described below are possible. Further, in the following modification modes, one or a plurality of arbitrarily selected variants may be appropriately combined.

<Modification example 1>
In the above-described embodiment, each pixel circuit 110 has a configuration in which the scanning line 12 and the control line 143 intersect with the gate electrode G1 when viewed in a plan view, but in addition to the scanning line 12 and the control line 143, , The control line 144 may intersect with the gate electrode G1.
FIG. 12 is a plan view showing the configuration of the pixel circuit 110 according to the first modification. The pixel circuit 110 according to the first modification has a point where the control line 144 and the gate electrode G1 intersect when viewed in a plan view, and a point where the control line 144 has a branch portion 142a branched in the Y direction for each pixel circuit 110. Is configured in the same manner as the pixel circuit 110 according to the embodiment shown in FIG.
According to this configuration, a plurality of control lines (scanning lines 12, control lines 143, 144, 145) extending in the X direction are provided as compared with the case where the control lines 144 are provided so as not to intersect the gate of the transistor 121. Wiring can be performed at high density, and the pitch of control lines can be narrowed. This makes it possible to reduce the size of the electro-optical device (display unit) and to improve the definition of the display.

Further, when the control line 144 and the gate electrode G1 intersect, the scanning line drive circuit 20 changes the waveform when the control signal Gel (i) changes from H level to L level from L level to H level. The potential supplied to the control line 144 may be switched so as to be gentler than the waveform at the time.
FIG. 13 is a timing chart for explaining the operation of the electro-optical device according to the first modification. As shown in FIG. 13, in the scanning line drive circuit 20 according to the first modification, the time length of the fifth switching period T5 for switching the potential supplied to the control line 144 from the second potential V2 to the first potential V1 is the second. The potential supplied to the control line 144 is changed so as to be sufficiently longer than the time length of the sixth switching period T6 for switching from the first potential V1 to the second potential V2.
As described above, the potential of the gate electrode G1 (gate node g of the transistor 121) is set to the potential Vgate that defines the brightness of the OLED 130 in the writing period preceding the fifth switching period T5. Therefore, in the fifth switching period T5, when the potential of the control line 144 changes abruptly and the potential fluctuation propagates to the gate electrode G1, each pixel cannot accurately display the gradation defined by the image signal Vid.
On the other hand, in the scanning line drive circuit 20 according to the first modification, the time length of the fifth switching period T5 is sufficiently made longer than the time length of the sixth switching period T6, and the control signal Gel (i) is H. By making the waveform when changing from the level to the L level a gentle waveform, it is possible to prevent the potential fluctuation of the control line 144 from propagating to the gate node g (gate electrode G1). As a result, each pixel can accurately display the gradation defined by the image signal Vid, and high-quality display becomes possible.

<Modification 2>
In the above-described embodiment, each pixel circuit 110 has a configuration in which the scanning line 12 and the control line 143 intersect with the gate electrode G1 when viewed in a plan view, but in addition to the scanning line 12 and the control line 143, , The control line 145 may be configured to intersect the gate electrode G1.
FIG. 14 is a plan view showing the configuration of the pixel circuit 110 according to the second modification. The pixel circuit 110 according to the second modification has a point where the control line 145 and the gate electrode G1 intersect when viewed in a plan view, and a point where the control line 145 has a branch portion 145a branched in the Y direction for each pixel circuit 110. Is configured in the same manner as the pixel circuit 110 according to the embodiment shown in FIG.
According to this configuration, a plurality of control lines (scanning lines 12, control lines 143, 144, 145) extending in the X direction are provided as compared with the case where the control lines 145 are provided so as not to intersect the gate of the transistor 121. Wiring can be performed at high density, and the pitch of control lines can be narrowed. This makes it possible to reduce the size of the electro-optical device (display unit) and to improve the definition of the display.
Further, when the control line 145 and the gate electrode G1 intersect, in the scanning line drive circuit 20, as shown in FIG. 15, the waveform when the control signal Gorst (i) changes from the L level to the H level is H. The potential supplied to the control line 145 may be switched so as to be gentler than the waveform when changing from the level to the L level.
FIG. 15 is a timing chart for explaining the operation of the electro-optical device according to the second modification.
As shown in FIG. 15, in the scanning line drive circuit 20 according to the second modification, the time length of the eighth switching period T8 for switching the potential supplied to the control line 145 from the first potential V1 to the second potential V2 is the second. The potential supplied to the control line 145 is changed so as to be sufficiently longer than the time length of the seventh switching period T7 for switching from the two potential V2 to the first potential V1. In this case, after the potential of the gate node g (gate electrode G1) of the transistor 121 is determined to be the potential Vgate that defines the brightness of the OLED 130, the potential fluctuation is prevented from propagating to the gate electrode G1 on the control line 145. Each pixel makes it possible to accurately display the gradation defined by the image signal Vid.

<Modification example 3>
In the above-described embodiment and modification, each pixel circuit 110 includes transistors 121 to 125, OLED 130, and holding capacity 132, but the pixel circuit 110 has at least transistors 121, transistors 122, and Any one provided with an OLED 130 may be used. In this case, the display unit 100 is deformed from among a plurality of control lines (scanning lines 12, control lines 143, 144, 145) extending in the X direction provided in the display unit 100 in the above-described embodiment and modification. Only the control line corresponding to the transistor included in the pixel circuit 110 of Example 3 may be provided in each line. That is, the display unit 100 according to the modification 3 may be provided with one or more control lines including the scanning line 12 in each line. For example, when each pixel circuit 110 includes a transistor 121, a transistor 122, an OLED 130, and a holding capacity 132, only a scanning line 12 is provided as a control line corresponding to each line. Further, each pixel circuit 110 may include a transistor other than the transistors 121 to 125, and in this case, the display unit 100 may be provided with a control line corresponding to the transistor.
When one or more control lines including the scanning line 12 are provided in each line, at least one control line of the one or more control lines extending in the X direction provided in each line is the transistor 121 in a plan view. It is provided so as to intersect the gate node g (gate electrode G1) of the above. As a result, the control lines extending in the X direction can be wired at high density, and the electro-optic device (display unit) can be miniaturized and the display can be made high-definition.
Further, the scanning line drive circuit 20 measures the potential of at least one control line that intersects the gate electrode G1 in a plan view among the one or more control lines provided in each line from the end of the compensation period to the next scanning period. When the change is made before the start of, it is preferable to make the waveform of the potential change gentle. For example, when the gate electrode G1 and the scanning line 12 intersect, the scanning line driving circuit 20 switches the potential supplied to the scanning line 12 from the first potential V1 to the second potential V2 during the second switching period T2. The potential supplied to the scanning line 12 may be changed so that the length is sufficiently longer than the time length of the first switching period T1 for switching from the second potential V2 to the first potential V1. As a result, it is possible to prevent the potential change of the control line intersecting with the gate electrode G1 from propagating to the gate electrode G1, and each pixel can accurately display the gradation defined by the image signal Vid. It becomes.

The scanning line drive circuit 20 also changes the potential of the control line that does not intersect the gate electrode G1 in plan view from the end of the compensation period to the start of the next scanning period. The waveform of the potential change may be gentle. Even when the control line does not intersect the gate electrode G1, there may be a parasitic capacitance between the control line and the gate electrode G1. Therefore, by making the waveform when the potential of the control line changes gentle, it is possible to prevent the potential change of the control line from propagating to the gate electrode G1.

<Modification example 4>
In the above-described embodiment and modification, each level shift circuit LS includes a holding capacity 41, a holding capacity 44, a transistor 45, a transistor 43, and a transmission gate 42, but the level shift circuit LS is at least. , The holding capacity 44, the transistor 43, and the transistor 45 may be provided. In this case, the data signal supply circuit 70 and the demultiplexer DM may supply the data signal Vd (j) to the other electrode of the holding capacity 44 during the writing period.
Even when the level shift circuit LS does not have the holding capacity 41, the data signal Vd (j) supplied to the other electrode of the holding capacity 44 is compressed by the capacitance ratio k1 and then supplied to the gate node g. Will be done. This makes it possible to set the potential of the gate node of the drive transistor with fine precision without engraving the data signal with fine precision, so that the current can be supplied to the light emitting element with high precision. It is possible to display the quality.

<Modification 5>
In the above-described embodiment and modification, the data line drive circuit 10 includes a level shift circuit LS, a demultiplexer DM, and a data signal supply circuit 70, but the data line drive circuit 10 includes at least a data signal. Any one provided with a supply circuit 70 may be used. In this case, the data line drive circuit 10 directly supplies the data signal Vd (j) to the gate node g.
Further, in the above-described embodiments and modifications, the display panel 2 is provided with a holding capacity of 50 in each row, but may be configured without this.

<Modification 6>
Although the control circuit 3 and the display panel 2 are separated from each other in the above-described embodiments and modifications, the control circuit 3 and the display panel 2 may be formed on the same substrate. For example, the control circuit 3 may be integrated on a silicon substrate together with the display unit 100, the data line drive circuit 10, the scanning line drive circuit 20, and the like.

<Modification 7>
In the above-described embodiments and modifications, the electro-optical device 1 is integrated on a silicon substrate, but it may be integrated on another semiconductor substrate. For example, it may be an SOI substrate. Further, it may be formed on a glass substrate or the like by applying a polysilicon process. In any case, the present invention is effective in a configuration in which the pixel circuit 110 is miniaturized and the drain current of the transistor 121 changes exponentially with a change in the gate voltage Vgs.
Further, the present invention may be applied when miniaturization of the pixel circuit is not required.

<Modification 8>
In the above-described embodiment and modification, the data lines 14 are grouped into three columns, and the data lines 14 are sequentially selected in each group to supply the data signal. However, the data constituting the group is configured. The number of lines may be a predetermined number of "2" or more and "3n" or less. For example, the number of data lines constituting the group may be "2" or "4" or more.
Further, the data signals may be supplied to the data lines 14 in each column all at once without grouping, that is, without using the demultiplexer DM.

<Modification 9>
In the above-described embodiment and modification, the transistors 121 to 125 in the pixel circuit 110 are unified in the P channel type, but may be unified in the N channel type. Further, the P-channel type and the N-channel type may be appropriately combined.
For example, when the transistors 121 to 125 are unified in the N channel type, the positive and negative potentials of the data signal Vd (j) in the above-described embodiment and modification may be supplied to each pixel circuit 110. Further, in this case, the source and drain of the transistors 121 to 125 have a relationship opposite to that of the above-described embodiment and modification.
Further, in the above-described embodiments and modifications, the transistor 45 is a P-channel type and the transistor 43 is an N-channel type, but the P-channel type or the N-channel type may be unified. The transistor 45 may be an N-channel type, and the transistor 43 may be a P-channel type.
Further, in the above-described embodiment and modification, each transistor is a MOS type transistor, but it may be a thin film.

<Modification example 10>
In the above-described embodiment and modification, the OLED which is a light emitting element is exemplified as the electro-optical element, but for example, an inorganic light emitting diode or an LED (Light Emitting Diode) which emits light with a brightness corresponding to a current may be used.

<Application example>
Next, an electronic device to which the electro-optical device 1 according to the embodiment or the like and the application example is applied will be described. The electro-optical device 1 is suitable for high-definition display applications in which the pixels are small in size. Therefore, a head-mounted display will be described as an example of an electronic device.

FIG. 16 is a diagram showing the appearance of the head-mounted display, and FIG. 17 is a diagram showing the optical configuration thereof.
First, as shown in FIG. 16, the head-mounted display 300 has a temple 310, a bridge 320, lenses 301L, and 301R, similar to general eyeglasses, in appearance. Further, as shown in FIG. 17, the head-mounted display 300 has an electro-optic device 1L for the left eye and an electro-optic device 1L for the right eye on the back side (lower side in the drawing) of the lenses 301L and 301R in the vicinity of the bridge 320. An electro-optical device 1R for use is provided.
The image display surface of the electro-optical device 1L is arranged so as to be on the left side in FIG. As a result, the display image by the electro-optical device 1L is emitted in the direction of 9 o'clock in the figure through the optical lens 302L. The half mirror 303L reflects the image displayed by the electro-optical device 1L in the 6 o'clock direction, while transmitting the light incident from the 12 o'clock direction.
The image display surface of the electro-optical device 1R is arranged so as to be on the right side opposite to the electro-optical device 1L. As a result, the image displayed by the electro-optical device 1R is emitted in the direction of 3 o'clock in the figure via the optical lens 302R. The half mirror 303R reflects the image displayed by the electro-optical device 1R in the 6 o'clock direction, while transmitting the light incident from the 12 o'clock direction.

In this configuration, the wearer of the head-mounted display 300 can observe the display image by the electro-optical devices 1L and 1R in a see-through state superposed on the outside state.
Further, in the head mount display 300, when the image for the left eye is displayed on the electro-optical device 1L and the image for the right eye is displayed on the electro-optic device 1R among the binocular images with parallax, the wearer is notified. , The displayed image can be perceived as if it has depth and stereoscopic effect (3D display).

The electro-optical device 1 can be applied not only to the head-mounted display 300 but also to an electronic viewfinder in a video camera, an interchangeable lens digital camera, or the like.

1 ... Electro-optical device, 2 ... Display panel, 3 ... Control circuit, 10 ... Data line drive circuit, 12 ... Scan line, 14 ... Data line, 16 ... Power supply line, 20 ... Scan line drive circuit, 41, 44, 50 ... Retention capacity, 100 ... Display unit, 110 ... Pixel circuit, 121-125 ... Transistor, 130 ... OLED, 132 ... Retention capacity, 143, 144, 145 ... Control line, 150 ... Silicon substrate, LS ... Level shift circuit, DM … Demultiplexer.

Claims (4)

Scanning lines extending in the first direction,
A data line extending in the second direction intersecting the first direction,
Light emitting element and
A first transistor having a first gate electrode and supplying a current corresponding to the voltage between the first gate electrode and the source to the light emitting element.
With a second transistor having a second gate electrode electrically connected to the scanning line through the first contact hole and electrically connected to the first gate electrode and the data line. ,
With
The first contact hole is arranged so as to overlap the region sandwiched between the source of the second transistor and the drain of the second transistor in a plan view .
In a plan view, the scanning line is arranged so as to overlap the second gate electrode.
An electro-optical device characterized by this. A second contact hole arranged so as to overlap the source of the second transistor in a plan view,
A third contact hole arranged so as to overlap the drain of the second transistor in a plan view,
With
The first contact hole, the second contact hole, and the third contact hole are arranged along the second direction in a plan view.
The electro-optical device according to claim 1. Control line and
A third transistor having a third gate electrode that is electrically connected to the control line via a fourth contact hole.
With
The fourth contact hole is arranged so as to overlap the region sandwiched between the source of the third transistor and the drain of the third transistor in a plan view .
In a plan view, the control line is arranged so as to overlap the third gate electrode.
The electro-optical device according to any one of claims 1 or 2. A fifth contact hole arranged so as to overlap the source of the third transistor in a plan view,
A sixth contact hole arranged so as to overlap the drain of the third transistor in a plan view,
With
The fourth contact hole, the fifth contact hole, and the sixth contact hole are arranged along the second direction in a plan view.
The electro-optical device according to claim 3.

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