JP6583464B2 - Electro-optical device and electronic apparatus - Google Patents

Description

  The present invention relates to an electro-optical device and an electronic apparatus.

  In recent years, various electro-optical devices that display an image using a light emitting element such as an organic light emitting diode (OLED) element have been proposed. In this electro-optical device, a pixel circuit including a light emitting element, a transistor, and the like is provided corresponding to a pixel of an image to be displayed. Specifically, in general, a plurality of pixel circuits corresponding to pixels of an image to be displayed are provided in a matrix, and a control line such as a scanning line is provided in each row in order to drive the plurality of pixel circuits. Is. (For example, refer to Patent Document 1).

JP 2007-316462 A

By the way, in recent years, electro-optical devices are often required to have a smaller display size and higher display resolution. In this case, it is necessary to reduce the pitch of the control lines in order to arrange the pixel circuits with high density.
The present invention has been made in view of the above-described circumstances, and one of its purposes is to realize high-density wiring of a plurality of control lines including a plurality of scanning lines, and to increase the display resolution or display size. It is to realize the miniaturization of.

In order to achieve the above object, an electro-optical device according to the present invention includes a scanning line, a data line intersecting the scanning line, and a pixel circuit provided corresponding to the intersection of the scanning line and the data line. The pixel circuit corresponds to a drive transistor, a write transistor whose gate is electrically connected to the scan line, and a data signal supplied via the data line and the write transistor A first holding capacitor for holding electric charge; and a light emitting element that emits light with a luminance corresponding to a magnitude of current supplied through the driving transistor, and is perpendicular to a surface of the substrate on which the pixel circuit is formed. When viewed from various directions, the scanning line and the gate of the driving transistor overlap each other.
According to the present invention, since the scanning line is wired on the gate of the driving transistor, the space limitation when providing the scanning line is eased compared with the case where the scanning line is wired so as not to intersect the gate of the driving transistor. Is done. Thereby, it is possible to narrow the scanning line pitch and to increase the wiring density. That is, according to the present invention, it is possible to arrange a plurality of pixel circuits at a higher density, and it is possible to increase the display definition and reduce the display size. In the present invention, the write transistor may be electrically connected, for example, between the gate of the drive transistor and the data line.

The electro-optical device according to the invention includes one or more control lines including a scanning line, a data line intersecting with the scanning line, and a pixel provided corresponding to the intersection of the scanning line and the data line. The pixel circuit includes: a drive transistor; a write transistor whose gate is electrically connected to the scan line; and a data signal supplied via the data line and the write transistor. A first storage capacitor that holds a corresponding charge, and a light emitting element that emits light with a luminance corresponding to the magnitude of a current supplied through the driving transistor, and the one or more control lines include A control line that overlaps with the gate of the driving transistor when viewed from a direction perpendicular to the surface of the substrate on which the pixel circuit is formed is included.
According to the present invention, since the control line is wired on the gate of the driving transistor, the space restriction when providing the control line is relaxed compared to the case where the control line is not crossed with the gate of the driving transistor. Is done. Thereby, it is possible to reduce the pitch of the control lines and increase the density of the wiring. That is, according to the present invention, it is possible to arrange a plurality of pixel circuits at a higher density, and it is possible to increase the display definition and reduce the display size.

  In addition, the electro-optical device described above further includes a scanning line driving circuit that controls the operation of the pixel circuit, and the writing transistor is turned on when the scanning line driving circuit supplies a first potential to the scanning line. When the scanning line driving circuit supplies a second potential to the scanning line, the scanning line driving circuit is turned off, and when viewed from a direction perpendicular to the surface of the substrate on which the pixel circuit is formed, the scanning line and the driving transistor A period during which the scanning line driving circuit switches the potential supplied to the scanning line from the second potential to the first potential is defined as a first switching period, and the scanning line driving circuit includes the scanning line. When the period for switching the potential supplied to the line from the first potential to the second potential is the second switching period, the time length of the second switching period is longer than the time length of the first switching period. Preferably .

When the gate of the driving transistor and the scanning line intersect in plan view, a capacitance is parasitic between the gate of the driving transistor and the scanning line. When the potential of the scanning line changes rapidly, the influence of the potential change affects the gate of the driving transistor and the potential of the gate of the driving transistor changes.
The driving transistor supplies a current having a magnitude corresponding to the voltage between the gate and the source determined when the writing transistor is turned off to the light emitting element, and the light emitting element emits light with luminance corresponding to the magnitude of the current. To do. Therefore, when the writing transistor is turned off (that is, after being set to a voltage that defines the luminance of the light emitting element), when the gate potential of the driving transistor changes, the light emitting element has a luminance different from the prescribed luminance. Light is emitted, and the display quality of the electro-optical device is degraded.
On the other hand, the scanning line driving circuit according to the present invention changes the potential of the scanning line when the writing transistor is turned off more slowly than the potential change when the writing transistor is turned on. Thus, the potential variation of the scanning line when the writing transistor is turned off is prevented from propagating to the gate of the driving transistor, and the light emitting element can emit light with a prescribed luminance. That is, according to the electro-optical device according to the present invention, it is possible to reduce the pitch of the control lines without degrading the display quality.

The pixel circuit includes a first switching transistor electrically connected between a gate and a drain of the driving transistor, and the one or more control lines are electrically connected to a gate of the first switching transistor. The first control line may be included.
In this case, the first switching transistor is turned on when the scanning line driving circuit supplies a first potential to the first control line, and the scanning line driving circuit supplies a second potential to the first control line. And when viewed from a direction perpendicular to the surface of the substrate on which the pixel circuit is formed, the first control line and the gate of the driving transistor overlap, and the scanning line driving circuit A period for switching the potential supplied to one control line from the second potential to the first potential is a third switching period, and the potential supplied to the first control line by the scanning line driving circuit is the first potential. When the period for switching from the second potential to the second potential is the fourth switching period, it is preferable that the time length of the fourth switching period is longer than the time length of the third switching period.

When the gate of the driving transistor and the first switching transistor intersect in plan view, a capacitance is parasitic between the gate of the driving transistor and the first control line. When the potential of the first control line fluctuates rapidly, the influence of the potential fluctuation affects the gate of the drive transistor, and the potential of the gate of the drive transistor changes.
By the way, when the first switching transistor is turned on, the gate and the source of the driving transistor are electrically connected, and the voltage between the gate and the source of the driving transistor is set to a value that compensates for variations in threshold voltage for each pixel circuit. . Accordingly, when the gate potential of the driving transistor changes when the first switching transistor is turned off (that is, after the threshold compensation is performed), the variation in the threshold voltage of the driving transistor for each pixel circuit cannot be compensated, and the display Uniformity is impaired.
On the other hand, the scanning line driving circuit according to this aspect changes the potential change of the first control line when the first switching transistor is turned off more slowly than the change of the potential when the first switching transistor is turned on. As a result, the potential fluctuation of the first control line when the first switching transistor is turned off is prevented from propagating to the gate of the driving transistor, and the gate potential of the driving transistor changes from the threshold compensated potential. To prevent that. That is, according to the electro-optical device according to the present invention, even when the first control line is arranged on the gate of the driving transistor, the occurrence of display unevenness that impairs the display uniformity is prevented. Therefore, it is possible to achieve both miniaturization of the electro-optical device and high-definition display and high-quality display.

The pixel circuit includes a second switching transistor electrically connected between the driving transistor and the light emitting element, and the one or more control lines are electrically connected to a gate of the second switching transistor. A second control line to be connected may be included.
In this case, the second switching transistor is turned on when the scanning line driving circuit supplies a first potential to the second control line, and the scanning line driving circuit supplies a second potential to the second control line. And when viewed from a direction perpendicular to the surface of the substrate on which the pixel circuit is formed, the second control line and the gate of the driving transistor overlap, and the scanning line driving circuit A period for switching the potential supplied to the second control line from the second potential to the first potential is a fifth switching period, and the potential supplied to the second control line by the scanning line driving circuit is the first potential. When the period for switching from the second potential to the second potential is the sixth switching period, the time length of the fifth switching period is preferably longer than the time length of the sixth switching period.
According to this aspect, it is possible to prevent the potential fluctuation generated in the second control line when the second switching transistor is turned on from propagating to the gate of the driving transistor. Thereby, it is possible to reduce the pitch of the control lines without degrading the display quality.

The pixel circuit includes a third switching transistor electrically connected between the light emitting element and a power supply line to which a predetermined reset potential is supplied, and the one or more control lines are the third switching transistor. A third control line electrically connected to the gate of the transistor may be included.
In this case, the third switching transistor is turned on when the scanning line driving circuit supplies a first potential to the third control line, and the scanning line driving circuit supplies a second potential to the third control line. And when viewed from a direction perpendicular to the surface of the substrate on which the pixel circuit is formed, the third control line and the gate of the driving transistor overlap, and the scanning line driving circuit A period for switching the potential supplied to the three control lines from the second potential to the first potential is a seventh switching period, and the potential supplied to the third control line by the scanning line driving circuit is the first potential. When the period for switching from the second potential to the second potential is the eighth switching period, it is preferable that the time length of the eighth switching period is longer than the time length of the seventh switching period.
According to this aspect, it is possible to prevent the potential fluctuation generated in the third control line when the third switching transistor is turned off from propagating to the gate of the driving transistor. Thereby, it is possible to reduce the pitch of the control lines without degrading the display quality.

  The electro-optical device described above corresponds to a data line driving circuit electrically connected to the data line, a control circuit for controlling operations of the scanning line driving circuit and the data line driving circuit, and the data line. And a second storage capacitor that holds the potential of the data line. The data line driving circuit includes a first potential line to which a predetermined initial potential is supplied from the control circuit, and A second potential line to which a reference potential is supplied; and a level shift circuit provided corresponding to the data line. The level shift circuit has one electrode electrically connected to the data line. A third storage capacitor; a first transistor electrically connected between one electrode of the third storage capacitor and the first potential line; and another electrode of the third storage capacitor and the second potential line. Electrically connected between The control circuit maintains the first transistor in an on state in the first period, and drives the scanning line in the second period that starts after the first period ends. The circuit maintains the write transistor in an on state, and the control circuit maintains the first transistor in an off state and maintains the second transistor in an on state, starting after the second period ends. In the third period, the scanning line driving circuit maintains the writing transistor in the on state, and the control circuit maintains the first transistor and the second transistor in the off state, and performs the third holding. The other electrode of the capacitor is preferably supplied with a potential based on an image signal that defines the luminance of the light emitting element.

  According to the present invention, the data line is connected to the second storage capacitor and the third storage capacitor, and the other electrode of the third storage capacitor is supplied with a potential based on the image signal that defines the luminance of the light emitting element. Is done. Therefore, the fluctuation range of the potential of the data line is a width obtained by compressing the fluctuation range of the potential supplied to the other electrode of the third storage capacitor according to the capacitance ratio of the second storage capacitor and the third storage capacitor. That is, the variation range of the potential of the data line is narrower than the variation range of the potential based on the image signal. As a result, the potential of the gate of the driving transistor can be set with fine accuracy without engraving the image signal with fine accuracy. Therefore, current can be supplied to the light emitting element with high accuracy, and high-quality display can be achieved. In addition, since the potential change width of the data line can be suppressed to be small, it is possible to prevent occurrence of crosstalk, unevenness, and the like due to potential fluctuation of the data line.

In the electro-optical device according to the invention, the potential of the gate of the driving transistor is supplied by supplying charge from one electrode of the third storage capacitor to the first storage capacitor and the second storage capacitor via the data line. To decide. Specifically, the gate potential of the driving transistor is supplied from the capacitance value of the first storage capacitor, the capacitance value of the second storage capacitor, and the third storage capacitor to the first storage capacitor and the second storage capacitor. It is determined by the amount of charge. If the electro-optical device does not include the second storage capacitor, the gate potential of the driving transistor is determined by the capacitance value of the first storage capacitor and the charge supplied by the third storage capacitor. Therefore, when the capacitance value of the first storage capacitor has a relative variation for each pixel circuit due to an error in the semiconductor process, the gate potential of the driving transistor also varies for each pixel circuit. In this case, display unevenness occurs and the display quality deteriorates.
In contrast, the present invention includes a second storage capacitor that holds the potential of the data line. Since the second storage capacitor is provided corresponding to each of the data lines, the second storage capacitor can be configured to have a larger area electrode than the first storage capacitor provided in the pixel circuit. Accordingly, the second storage capacitor has a smaller relative variation in the capacitance value due to an error in the semiconductor process than the first storage capacitor. As a result, it is possible to prevent the gate potential of the driving transistor from varying for each pixel circuit, and display with high quality while preventing the occurrence of display unevenness.

  The level shift circuit includes a fourth storage capacitor, and the image is applied to one electrode of the fourth storage capacitor in at least a part of a period from the start of the first period to the start of the third period. It is preferable that a potential indicated by a signal is supplied and that one electrode of the fourth storage capacitor is electrically connected to the other electrode of the third storage capacitor in the third period.

According to the present invention, the image signal is supplied to one electrode of the fourth holding capacitor and temporarily held in the first period and the second period, and then temporarily passed through the third holding capacitor in the third period. And supplied to the gate of the driving transistor.
If the electro-optical device does not include the fourth storage capacitor, all the operations for supplying the potential indicated by the image signal to the gate of the driving transistor must be performed in the third period, and the third period is sufficiently long. Must be set.
On the other hand, in the present invention, since the image signal supply operation and the initialization operation of the data lines and the like are performed in parallel in the first period and the second period, the operation to be performed in one horizontal scanning period is described. Time constraints can be relaxed. As a result, the image signal supply operation can be slowed down, and a sufficient period for initializing the data lines and the like can be secured.
According to the invention, the magnitude of the potential fluctuation based on the image signal is compressed using the fourth holding capacitor in addition to the first holding capacitor, the second holding capacitor, and the third holding capacitor. Therefore, current can be supplied to the light emitting element with fine accuracy.

  The scanning line driving circuit maintains the first switching transistor in an on state in the second period, maintains the first switching transistor in an off state in a period other than the second period, and In the first period, the second period, and the third period, it is preferable that the third switching transistor is maintained in an on state and the second switching transistor is maintained in an off state.

According to the present invention, by turning on the first switching transistor in the second period, the gate potential of the driving transistor can be set to a potential corresponding to the threshold voltage of the driving transistor, and driving for each pixel circuit is performed. It becomes possible to compensate for variations in the threshold voltage of the transistor.
In addition, according to the present invention, the third switching transistor is turned on in the first period to the third period, so that the influence of the holding voltage of the capacitance parasitic on the light emitting element can be suppressed.

  In addition to the electro-optical device, the present invention can be conceptualized as an electronic apparatus having the electro-optical device. Typically, the electronic device includes a display device such as a head mounted display (HMD) or an electronic viewfinder.

1 is a perspective view illustrating a configuration of an electro-optical device according to an embodiment of the invention. It is a figure which shows the structure of the same electro-optical apparatus. It is a figure which shows the data line drive circuit in the same electro-optical apparatus. It is a figure which shows the pixel circuit in the same electro-optical apparatus. 2 is a plan view illustrating a configuration of a pixel circuit in the electro-optical device. FIG. 2 is a partial cross-sectional view illustrating a configuration of a pixel circuit in the same electro-optical device. FIG. 6 is a timing chart showing the operation of the electro-optical device. FIG. 6 is an operation explanatory diagram of the same electro-optical device. It is a figure explaining the potential change of the gate node of the same electro-optical device. It is explanatory drawing which shows the amplitude compression of the data signal in the same electro-optical apparatus. FIG. 6 is an explanatory diagram illustrating characteristics of a transistor in the electro-optical device. 10 is a plan view illustrating a configuration of a pixel circuit in an electro-optical device according to Modification 1. FIG. 6 is a timing chart showing the operation of the electro-optical device. 10 is a plan view illustrating a configuration of a pixel circuit in an electro-optical device according to Modification Example 2. FIG. 6 is a timing chart showing the operation of the electro-optical device. It is a perspective view which shows HMD using the electro-optical apparatus which concerns on embodiment etc. FIG. It is a figure which shows the optical structure of HMD.

  Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.

<Embodiment>
FIG. 1 is a perspective view showing a configuration of an electro-optical device 1 according to an embodiment of the present invention. The electro-optical device 1 is a micro display that displays an image on a head-mounted display, for example.
As shown in FIG. 1, the electro-optical device 1 includes a display panel 2 and a control circuit 3 that controls the operation of the display panel 2. The display panel 2 includes a plurality of pixel circuits and a drive circuit that drives the pixel circuits. In the present embodiment, a plurality of pixel circuits and drive circuits included in the display panel 2 are formed on a silicon substrate, and an OLED which is an example of a light emitting element is used for the pixel circuits. The display panel 2 is housed in, for example, a frame-shaped case 82 that opens at the display unit, and one end of an FPC (Flexible Printed Circuits) substrate 84 is connected.
On the FPC board 84, the control circuit 3 of the semiconductor chip is mounted by COF (Chip On Film) technology, and a plurality of terminals 86 are provided, and are connected to an upper circuit (not shown).

FIG. 2 is a block diagram illustrating a configuration of the electro-optical device 1 according to the embodiment. As described above, the electro-optical device 1 includes the display panel 2 and the control circuit 3.
Digital image data Video is supplied to the control circuit 3 from an upper circuit (not shown) in synchronization with a synchronization signal. Here, the image data Video is data that defines, for example, the 8-bit pixel gradation level of an image to be displayed on the display panel 2 (strictly speaking, the display unit 100 described later). The synchronization signal is a signal including a vertical synchronization signal, a horizontal synchronization signal, and a dot clock signal.
The control circuit 3 generates various control signals based on the synchronization signal and supplies them to the display panel 2. Specifically, the control circuit 3 controls the display panel 2 with a control signal Ctr, a negative logic control signal / Gini, a positive logic control signal Gref, a positive logic control signal Gcpl, The negative logic control signal / Gcpl in the inversion relationship and the control signals Sel (1), Sel (2), Sel (3), and the control signal / Sel (1) in the logic inversion relationship with respect to these signals ), / Sel (2), / Sel (3). Here, the control signal Ctr is a signal including a plurality of signals such as a pulse signal, a clock signal, and an enable signal. The control signals Sel (1), Sel (2), and Sel (3) are collectively referred to as the control signal Sel, and the control signals / Sel (1), / Sel (2), and / Sel (3) / Sel may be collectively called.
The control circuit 3 supplies various potentials to the display panel 2. Specifically, the control circuit 3 supplies the display panel 2 with a predetermined reset potential Vorst, a predetermined initial potential Vini, a predetermined reference potential Vref, and the like.
Further, the control circuit 3 generates an analog image signal Vid based on the image data Video.
Specifically, the control circuit 3 is provided with a lookup table that stores the potential indicated by the image signal Vid and the luminance of a light emitting element (an OLED 130 described later) included in the display panel 2 in association with each other. Then, the control circuit 3 refers to the lookup table to generate an image signal Vid indicating a potential corresponding to the luminance of the light emitting element specified in the image data Video, and supplies this to the display panel 2. To do.

As shown in FIG. 2, the display panel 2 includes a display unit 100 and drive circuits (the data line drive circuit 10 and the scan line drive circuit 20) that drive the display unit 100.
In the display unit 100, pixel circuits 110 corresponding to pixels of an image to be displayed are arranged in a matrix. More specifically, in the display unit 100, m rows of scanning lines 12 are provided extending in the horizontal direction (X direction) in the drawing, and (3n) columns of data lines 14 are grouped every three columns. Are extended in the vertical direction (Y direction) in the figure and are provided so as to be electrically insulated from each scanning line 12. A pixel circuit 110 is provided corresponding to the intersection of the m rows of scanning lines 12 and the (3n) columns of data lines 14. For this reason, in the present embodiment, the pixel circuits 110 are arranged in a matrix form of vertical m rows × horizontal (3n) columns.

Here, m and n are both natural numbers. In order to distinguish the rows in the matrix of the scanning lines 12 and the pixel circuits 110, they may be referred to as 1, 2, 3,... (M−1), m rows in order from the top in the drawing. Similarly, in order to distinguish the column of the matrix of the data line 14 and the pixel circuit 110, they may be called 1, 2, 3, ..., (3n-1), (3n) columns in order from the left in the figure. . Further, in order to generalize and describe the group of data lines 14, when an integer j of 1 to n is used, the j-th group counted from the left includes the (3j-2) th column, (3j-1). ) And (3j) th column data lines 14 belong.
Note that the three pixel circuits 110 corresponding to the intersection of the scanning lines 12 in the same row and the three columns of data lines 14 belonging to the same group respectively have R (red), G (green), and B (blue) pixels. Correspondingly, these three pixels represent one dot of a color image to be displayed. That is, in the present embodiment, one dot color is expressed by additive color mixing by light emission of an OLED corresponding to RGB.

Further, as shown in FIG. 2, in the display unit 100, (3n) columns of feeder lines 16 are provided so as to extend in the vertical direction and to be electrically insulated from each scanning line 12. A predetermined reset potential Vorst is commonly supplied to the power supply lines 16. Here, in order to distinguish the columns of the feeder lines 16, they may be called the feeder lines 16 in the first, second, third,..., (3n), (3n + 1) th columns in order from the left in the drawing. Each of the first to (3n) th column feeder lines 16 is provided corresponding to each of the first to (3n) th column data lines 14.
Further, the display panel 2 is provided with (3n) storage capacitors 50 corresponding to the first to (3n) th column data lines 14. The storage capacitor 50 has two electrodes. One electrode of the storage capacitor 50 is connected to the data line 14, and the other electrode is connected to the feeder line 16. That is, the storage capacitor 50 functions as a second storage capacitor that holds the potential of the data line 14. The storage capacitor 50 is preferably formed by sandwiching an insulator (dielectric) between the power supply line 16 and the data line 14 adjacent to each other. In this case, the distance between the power supply line 16 and the data line 14 adjacent to each other is determined so as to obtain a required capacity. Hereinafter, the capacitance value of the storage capacitor 50 is expressed as Cdt.
In FIG. 2, the storage capacitor 50 is provided outside the display unit 100, but this is only an equivalent circuit and may be provided inside the display unit 100. Further, the storage capacitor 50 may be provided from the inside to the outside of the display unit 100.

The scanning line driving circuit 20 generates a scanning signal Gwr for sequentially scanning the scanning lines 12 for each row over the period of the frame according to the control signal Ctr. Here, the scanning signals Gwr supplied to the scanning lines 12 in the 1, 2, 3,..., M-th rows are respectively Gwr (1), Gwr (2), Gwr (3),. ), Gwr (m).
In addition to the scanning signals Gwr (1) to Gwr (m), the scanning line driving circuit 20 generates various control signals synchronized with the scanning signal Gwr for each row and supplies them to the display unit 100. Illustration is omitted in FIG. The frame period is a period required for the electro-optical device 1 to display an image for one cut (frame). For example, if the frequency of the vertical synchronization signal included in the synchronization signal is 120 Hz, the first period is 1. This is a period of 8.3 milliseconds corresponding to the period.

The data line driving circuit 10 includes (3n) level shift circuits LS provided in a one-to-one correspondence with each of the (3n) columns of data lines 14 and each of the three columns of data lines 14 constituting each group. N demultiplexers DM and a data signal supply circuit 70 are provided.
The data signal supply circuit 70 generates data signals Vd (1), Vd (2),..., Vd (n) based on the image signal Vid and the control signal Ctr supplied from the control circuit 3. That is, the data signal supply circuit 70 uses the data signals Vd (1), Vd (2),..., Vd (n) based on the image signal Vid that is time-division multiplexed. ... Vd (n) is generated. The data signal supply circuit 70 applies the data signals Vd (1), Vd (2),..., Vd (n) to the demultiplexers DM corresponding to the first, second,. Supply. Further, the maximum potential that can be taken by the data signals Vd (1) to Vd (n) is Vmax, and the minimum value is Vmin.

  FIG. 3 is a circuit diagram for explaining the configuration of the demultiplexer DM and the level shift circuit LS. FIG. 3 representatively shows the demultiplexer DM belonging to the j-th group and the three level shift circuits LS connected to the demultiplexer DM. Hereinafter, the demultiplexer DM belonging to the j-th group may be referred to as DM (j).

Hereinafter, the configuration of the demultiplexer DM and the level shift circuit LS will be described with reference to FIG. 3 in addition to FIG.
As shown in FIG. 3, the demultiplexer DM is an aggregate of transmission gates 34 provided for each column, and sequentially supplies data signals to three columns constituting each group. Here, the input terminals of the transmission gates 34 corresponding to the (3j-2), (3j-1), and (3j) columns belonging to the jth group are commonly connected to each other, and the data signal Vd ( j) is supplied. The transmission gate 34 provided in the leftmost column (3j-2) in the j-th group has the control signal Sel (1) at the H level (when the control signal / Sel (1) is at the L level. ) Is turned on (conductive). Similarly, in the j-th group, the transmission gate 34 provided in the (3j−1) column which is the central column has the control signal Sel (2) at the H level (the control signal / Sel (2) is at the L level. The transmission gate 34 provided in the (3j) column which is the rightmost column in the j-th group when the control signal Sel (3) is at the H level (control signal / Sel (3) Is on).

The level shift circuit LS includes a set of a storage capacitor 41, a storage capacitor 44, a P-channel MOS transistor 45, an N-channel MOS transistor 43, and a transmission gate 42 for each column, and the transmission gate 34 of each column. The potential of the data signal output from the output terminal is shifted.
Here, the storage capacitor 44 has two electrodes. One electrode of the storage capacitor 44 is electrically connected to the data line 14 of the corresponding column and one of the source and the drain of the transistor 45. The other electrode of the storage capacitor 44 is electrically connected to the output terminal of the transmission gate 42 and one of the source and drain of the transistor 43 via the node h1. That is, the storage capacitor 44 functions as a third storage capacitor in which one electrode is electrically connected to the data line 14. Note that the capacitance value of the storage capacitor 44 is Crf1.

The other of the source or drain of the transistor 45 in each column is electrically connected to the power supply line 61 (first potential line). The control circuit 3 supplies the control signal / Gini in common to the gates of the transistors 45 in each column. Therefore, the transistor 45 electrically connects one electrode (and the data line 14) of the storage capacitor 44 and the power supply line 61 when the control signal / Gini is at L level, and the control signal / Gini is at H level. Sometimes electrically disconnected. A predetermined initial potential Vini is supplied from the control circuit 3 to the power supply line 61.
The other of the source and the drain of the transistor 43 in each column is electrically connected to the power supply line 62 (second potential line). The control circuit 3 supplies the control signal Gref in common to the gates of the transistors 43 in each column. For this reason, the transistor 43 electrically connects the other electrode of the storage capacitor 44 and the node h1 to the feeder line 62 when the control signal Gref is at the H level, and electrically connects when the control signal Gref is at the L level. Disconnected. The reference potential Vref is supplied from the control circuit 3 to the power supply line 62.

The storage capacitor 41 has two electrodes. One electrode of the storage capacitor 41 is electrically connected to the input terminal of the transmission gate 42 via the node h2. The output terminal of the transmission gate 42 is electrically connected to the other electrode of the storage capacitor 44 via the node h1.
The control circuit 3 supplies the control signal Gcpl and the control signal / Gcpl in common to the transmission gates 42 in each column. For this reason, the transmission gates 42 in each column are simultaneously turned on when the control signal Gcpl is at the H level (when the control signal / Gcpl is at the L level).
One electrode of the storage capacitor 41 in each column is electrically connected to the output end of the transmission gate 34 and the input end of the transmission gate 42 via the node h2. When the transmission gate 34 is turned on, the data signal Vd (j) is supplied to one electrode of the storage capacitor 41 via the output terminal of the transmission gate 34. That is, the storage capacitor 41 functions as a fourth storage capacitor in which the data signal Vd (j) is supplied to one electrode. The other electrode of the storage capacitor 41 in each column is connected in common to a power supply line 63 to which a potential Vss that is a fixed potential is supplied. Here, the potential Vss may correspond to an L level of a scanning signal or a control signal that is a logic signal. Note that the capacitance value of the storage capacitor 41 is Crf2.

  The pixel circuit 110 will be described with reference to FIG. Since each pixel circuit 110 has the same configuration when viewed electrically, i-th row is located in the i-th row and is located in the (3j-2) th column of the leftmost column in the j-th group. The pixel circuit 110 in the (3j-2) column will be described as an example. Note that i is a symbol for generally indicating a row in which the pixel circuits 110 are arranged, and is an integer of 1 to m.

As shown in FIG. 4, the pixel circuit 110 includes P-channel MOS transistors 121 to 125, an OLED 130, and a storage capacitor 132. The pixel circuit 110 is supplied with a scanning signal Gwr (i), control signals Gcmp (i), Gel (i), and Gorst (i). Here, the scanning signal Gwr (i), the control signals Gcmp (i), Gel (i), and Gorst (i) are respectively supplied by the scanning line driving circuit 20 corresponding to the i-th row.
Although not shown in FIG. 2, the display panel 2 (display unit 100) includes m rows of control lines 143 (first control lines) extending in the horizontal direction (X direction) in FIG. There are provided m rows of control lines 144 (second control lines) and m rows of control lines 145 (third control lines) extending in the lateral direction. The scanning line driving circuit 20 applies control signals Gcmp (1), Gcmp (2), Gcmp (3),..., Gcmp to the control lines 143 in the 1, 2, 3,. (m) is supplied, and control signals Gel (1), Gel (2), Gel (3),..., Gel (m ) And control signals Gorst (1), Gorst (2), Gorst (3),..., Gorst (m) to the control lines 145 in the 1, 2, 3,. Supply. That is, the scanning line driving circuit 20 sends the scanning signal Gwr (i), the control signals Gel (i), Gcmp (i), and Gorst (i) to the (3n) pixel circuits located in the i-th row. These are supplied in common through the scanning line 12 and the control lines 143, 144, and 145 of the i-th row, respectively. Hereinafter, the scanning line 12, the control line 143, the control line 144, and the control line 145 may be collectively referred to as “control lines”. That is, the display panel 2 according to the present embodiment is provided with four control lines including the scanning lines 12 in each row.

The transistor 122 has a gate electrically connected to the i-th scanning line 12 and a source or drain electrically connected to the data line 14 in the (3j-2) -th column. The storage capacitor 132 has two electrodes. The other of the source and the drain of the transistor 122 is electrically connected to the gate of the transistor 121, one electrode of the storage capacitor 132, and one of the source and the drain of the transistor 123. In other words, the transistor 122 is electrically connected between the gate of the transistor 121 and the data line 14 and functions as a writing transistor that controls the electrical connection between the gate of the transistor 121 and the data line 14. Note that a wiring that electrically connects the gate of the transistor 121, the other of the source and the drain of the transistor 122, one of the source and the drain of the transistor 123, and one electrode of the storage capacitor 132 is referred to as (the transistor 121 ) Sometimes referred to as a gate node g.
The transistor 121 has a source electrically connected to the power supply line 116 and a drain electrically connected to the source of the transistor 123 or the other of the drain and the source of the transistor 124. Here, the power supply line 116 is supplied with a potential Vel that is higher in the power supply in the pixel circuit 110. The transistor 121 functions as a driving transistor that passes a current corresponding to the voltage between the gate and the source of the transistor 121.
The transistor 123 has a gate electrically connected to the control line 143 and is supplied with a control signal Gcmp (i). The transistor 123 functions as a first switching transistor that controls electrical connection between the gate and drain of the transistor 121.
The transistor 124 has a gate electrically connected to the control line 144 and is supplied with a control signal Gel (i). The drain of the transistor 124 is electrically connected to the source of the transistor 125 and the anode 130a of the OLED 130, respectively. The transistor 124 functions as a second switching transistor that controls electrical connection between the drain of the transistor 121 and the anode of the OLED 130.
The transistor 125 has a gate electrically connected to the control line 145 and is supplied with a control signal Gorst (i). The drain of the transistor 125 is electrically connected to the power supply line 16 in the (3j-2) th column and is kept at the reset potential Vorst. The transistor 125 functions as a third switching transistor that controls electrical connection between the power supply line 16 and the anode 130 a of the OLED 130.
In this embodiment, since the display panel 2 is formed on a silicon substrate, the substrate potential of the transistors 121 to 125 is set to the potential Vel.
Note that the sources and drains of the transistors 121 to 125 in the above may be interchanged depending on the channel type and potential relationship of the transistors 121 to 125. The transistor may be a thin film transistor or a field effect transistor.

The storage capacitor 132 has one electrode electrically connected to the gate of the transistor 121 and the other electrode electrically connected to the power supply line 116. Therefore, the storage capacitor 132 functions as a first storage capacitor that holds the voltage between the gate and the source of the transistor 121. The capacitance value of the storage capacitor 132 is expressed as Cpix. At this time, the capacitance value Cdt of the storage capacitor 50, the capacitance value Crf1 of the storage capacitor 44, and the capacitance value Cpix of the storage capacitor 132 are:
Cdt >> Crf1 >> Cpix
Is set to be That is, Cdt is set to be larger than Crf1, and Cpix is set to be sufficiently smaller than Cdt and Crf1. Note that as the storage capacitor 132, a capacitor parasitic to the gate node g of the transistor 121 may be used, or a capacitor formed by sandwiching an insulating layer between different conductive layers in a silicon substrate may be used.

The anode 130 a of the OLED 130 is a pixel electrode provided individually for each pixel circuit 110. On the other hand, the cathode of the OLED 130 is a common electrode 118 provided in common throughout the pixel circuit 110, and is maintained at the potential Vct that is the lower side of the power supply in the pixel circuit 110. The OLED 130 is an element in which a white organic EL layer is sandwiched between an anode 130a and a light-transmitting cathode in the silicon substrate. A color filter corresponding to any of RGB is superimposed on the emission side (cathode side) of the OLED 130.
In such an OLED 130, when a current flows from the anode 130a to the cathode, holes injected from the anode 130a and electrons injected from the cathode are recombined in the organic EL layer to generate excitons, and white light is generated. appear. The white light generated at this time is transmitted through the cathode on the opposite side to the silicon substrate (anode 130a), and is colored by a color filter so as to be visually recognized by the viewer.

Next, the structure of the pixel circuit 110 will be described with reference to FIGS.
FIG. 5 is a plan view showing the configuration of the pixel circuit 110 in i row (3j-2) column. FIG. 5 shows a wiring structure when the pixel circuit 110 having the top emission structure is viewed in plan from the observation side, but for simplicity, a structure formed after the anode 130a of the OLED 130 is omitted. ing. 6 is a partial cross-sectional view taken along line Ee in FIG. In FIG. 6, only the anode 130a of the OLED 130 is shown, and the subsequent structures are omitted. In FIGS. 5 and 6, the scales may be different in order to make each layer, each member, each region, etc. recognizable.

As shown in FIG. 6, each element constituting the pixel circuit 110 is formed on a silicon substrate 150. In this embodiment, a P-type semiconductor substrate is used as the silicon substrate 150. In the silicon substrate 150, an N well 160 is formed over almost the entire surface. In FIG. 5, only the region of the N-well 160 where the transistors 121-125 are provided and the vicinity thereof are hatched so that the region where the transistors 121-125 are provided can be easily grasped when viewed in plan. Is shown.
The potential Vel is supplied to the N well 160 via an N-type diffusion layer (not shown). For this reason, the substrate potentials of the transistors 121 to 125 are the potential Vel.

  As shown in FIGS. 5 and 6, by doping ions on the surface of the N well 160, a plurality of P-type diffusion layers are formed. Specifically, nine P-type diffusion layers P <b> 1 to P <b> 9 are formed on the surface of the N well 160 for each pixel circuit 110. These P-type diffusion layers P1 to P9 function as sources or drains of the transistors 121 to 125. A gate insulating layer L0 is formed on the surface of the N well 160 and the P-type diffusion layers P1 to P9, and gate electrodes G1 to G5 are formed on the surface of the gate insulating layer L0 by patterning. These gate electrodes G1 to G5 function as gates of the transistors 121 to 125, respectively.

As shown in FIG. 5, the transistor 121 includes a gate electrode G1, a P-type diffusion layer P1, and a P-type diffusion layer P2. Among these, the P-type diffusion layer P <b> 1 functions as the source of the transistor 121, and the P-type diffusion layer P <b> 2 functions as the drain of the transistor 121.
The transistor 122 includes a gate electrode G2, a P-type diffusion layer P3, and a P-type diffusion layer P4. Among these, the P-type diffusion layer P3 functions as one of the source and the drain of the transistor 122, and the P-type diffusion layer P4 functions as the other of the source and the drain of the transistor 122.
The transistor 123 includes a gate electrode G3, a P-type diffusion layer P4, and a P-type diffusion layer P5. Among these, the P-type diffusion layer P4 functions as one of the source and the drain of the transistor 123, and the P-type diffusion layer P5 functions as the other of the source and the drain of the transistor 123. That is, the P-type diffusion layer P4 functions as the other of the source and the drain of the transistor 122 and also functions as one of the source and the drain of the transistor 123.
The transistor 124 includes a gate electrode G4, a P-type diffusion layer P6, and a P-type diffusion layer P7. Among these, the P-type diffusion layer P6 functions as the source of the transistor 124, and the P-type diffusion layer P7 functions as the drain of the transistor 124.
In this embodiment, the drain of the transistor 121, the source of the transistor 123 or the other of the drain, and the source of the transistor 124 are configured by individual P-type diffusion layers P2, P5, and P6, respectively. A single P-type diffusion layer may be used. In this case, the relay node N13 described later may not be provided.
The transistor 125 includes a gate electrode G5, a P-type diffusion layer P8, and a P-type diffusion layer P9. Among these, the P-type diffusion layer P8 functions as the source of the transistor 125, and the P-type diffusion layer P9 functions as the drain of the transistor 125.

As shown in FIG. 6, the first interlayer insulating layer L1 is formed so as to cover the gate electrodes G1 to G5 and the gate insulating layer L0.
By patterning a conductive wiring layer such as aluminum on the surface of the first interlayer insulating layer L1, the scanning line 12, the feed line 116, and the control lines 143 to 145 are formed for each row, respectively. For each pixel circuit 110, relay nodes N11 to N16 and a branch part 116a are formed. Note that the wiring layer formed on the surface of the first interlayer insulating layer L1 may be collectively referred to as a first wiring layer.

  As shown in FIG. 5, the power supply line 116 extends in the X direction intersecting with the Y-axis direction, and has a portion (branch portion 116 a) branched in the Y direction for each pixel circuit 110. When viewed in plan (ie, when the pixel circuit 110 is viewed from a direction perpendicular to the surface of the silicon substrate 150 where the pixel circuit 110 is disposed), the branch part 116a and a part of the branch part 116a and the P-type diffusion layer P1 Are provided so as to overlap each other. As shown in FIGS. 5 and 6, the branch portion 116a is electrically connected to the P-type diffusion layer P1 through a contact hole Ha1 penetrating the first interlayer insulating layer L1. In FIG. 5, the contact hole is shown as a portion where “□” marks are added to “□” marks where the different wiring layers overlap.

As shown in FIG. 5, the scanning line 12 extends in the X direction and is provided so as to intersect the gate electrode G1 and the gate electrode G2 when viewed in plan. That is, when viewed in plan, at least a part of the scanning line 12 and at least a part of the gate electrode G1 overlap. The scanning line 12 is electrically connected to the gate electrode G2 through the contact hole Ha5.
The control line 143 extends in the X direction and is provided so as to intersect the gate electrode G1 and the gate electrode G3 when viewed in plan. The control line 143 is electrically connected to the gate electrode G3 through the contact hole Ha7.
The control line 144 extends in the X direction, is provided so as to intersect with the gate electrode G4 when viewed in plan, and is electrically connected to the gate electrode G4 through the contact hole Ha10. The control line 145 extends in the X direction, is provided so as to intersect with the gate electrode G5 when viewed in plan, and is electrically connected to the gate electrode G5 via the contact hole Ha14.

As shown in FIGS. 5 and 6, the relay node N11 is electrically connected to the gate electrode G1 through the contact hole Ha2, and is also electrically connected to the P-type diffusion layer P4 through the contact hole Ha6. The That is, the relay node N11 corresponds to the gate node g that electrically connects the gate of the transistor 121, the other of the source and the drain of the transistor 122, and one of the source and the drain of the transistor 123.
The relay node N16 is provided so that the relay node N16 and a part of the gate electrode G1 overlap each other when viewed in plan. Then, the storage node 132 is formed by the relay node N16 and the gate electrode G1 sandwiching the first interlayer insulating layer L1. In other words, the gate electrode G1 corresponds to one electrode of the storage capacitor 132, and the relay node N16 corresponds to the other electrode of the storage capacitor 132.
Relay node N12 is electrically connected to P-type diffusion layer P3 through contact hole Ha4. The relay node N13 is electrically connected to the P-type diffusion layer P2 through the contact hole Ha3, and is electrically connected to the P-type diffusion layer P5 through the contact hole Ha8, and P It is electrically connected to the mold diffusion layer P6. Relay node N14 is electrically connected to P-type diffusion layer P7 through contact hole Ha11 and is also electrically connected to P-type diffusion layer P8 through contact hole Ha12. Relay node N15 is electrically connected to P-type diffusion layer P9 through contact hole Ha13.

As shown in FIG. 6, the second interlayer insulating layer L2 is formed so as to cover the first wiring layer and the first interlayer insulating layer L1.
By patterning a conductive wiring layer such as aluminum on the surface of the second interlayer insulating layer L2, a data line 14 and a power supply line 16 are formed for each column, and for each pixel circuit 110. , Relay nodes N21 and N22 are formed. The wiring layer formed on the surface of the second interlayer insulating layer L2 may be collectively referred to as a second wiring layer.
As shown in FIG. 5, the data line 14 is electrically connected to the relay node N12 through the contact hole Hb2. Thereby, the P type diffusion layer P3 is electrically connected to the data line 14 via the relay node N12. Feed line 16 is electrically connected to relay node N15 through contact hole Hb3. Thereby, the P-type diffusion layer P9 is electrically connected to the feeder line 16 via the relay node N15. The relay node N21 is electrically connected to the power supply line 116 through the contact hole Hb1, and is also electrically connected to the relay node N16 (the other electrode of the storage capacitor 132) through the contact hole Hb4. Thereby, the relay node N16 is electrically connected to the feeder line 116 via the relay node N21 and is kept at the potential Vel.
Further, as shown in FIG. 6, relay node N22 is electrically connected to relay node N14 through contact hole Hb5.

As shown in FIG. 6, a third interlayer insulating layer L3 is formed so as to cover the second wiring layer and the second interlayer insulating layer L2.
An anode 130a of the OLED 130 is formed on the surface of the third interlayer insulating layer L3 by patterning a conductive wiring layer such as aluminum or ITO (Indium Tin Oxide). The anode 130a of the OLED 130 is an individual pixel electrode for each pixel circuit 110, and is connected to the relay node N22 via a contact hole Hc1 penetrating the third interlayer insulating layer L3. That is, the anode 130a of the OLED 130 is electrically connected to the P-type diffusion layer P7 (that is, the drain of the transistor 124) and the P-type diffusion layer P8 (that is, the source of the transistor 125) via the relay node N22 and the relay node N14. Connected.
Although not shown, a light emitting layer made of an organic EL material is laminated on the anode 130a of the OLED 130 for each pixel circuit 110. On the light emitting layer, a cathode (common electrode 118) that is a transparent electrode common to all of the plurality of pixel circuits 110 is provided. That is, the OLED 130 sandwiches the light emitting layer between the anode and the cathode facing each other, and emits light with a luminance corresponding to the current flowing from the anode toward the common electrode 118. Of the light emitted from the OLED 130, the light directed in the opposite direction to the silicon substrate 150 (ie, upward in FIG. 6) is visually recognized as an image by the observer (top emission structure). In addition, a sealing material or the like for shielding the light emitting layer from the atmosphere is provided, but the description is omitted.

<Operation of Embodiment>
The operation of the electro-optical device 1 will be described with reference to FIG. FIG. 7 is a timing chart for explaining the operation of each part in the electro-optical device 1. As shown in this figure, the scanning line driving circuit 20 sequentially switches the scanning signals Gwr (1) to Gwr (m) to the L level, and sets the scanning lines 12 in the first to mth rows to 1 in the period of one frame. Scan in order for each horizontal scanning period (H). The operation in one horizontal scanning period (H) is common to the pixel circuits 110 in each row. Therefore, in the following, the operation will be described focusing on the pixel circuit 110 in the i-th row (3j-2) column in the scanning period in which the i-th row is horizontally scanned.

In the present embodiment, the scanning period of the i-th row is roughly divided into an initialization period indicated by (b), a compensation period indicated by (c), and a writing period indicated by (d) in FIG. It is done. Then, after the writing period of (d), the light emission period shown in (a) is reached, and the scanning period of the i-th row is reached again after the elapse of one frame period. Therefore, in the order of time, a cycle of (light emission period) → initialization period → compensation period → writing period → (light emission period) is repeated.
In FIG. 7, the scanning signal Gwr (i-1), control signals Gel (i-1), Gcmp (i-1), Gcmp (i-1), corresponding to the (i-1) th row before the ith row. For each of the Gorst (i-1), one horizontal scan is temporally performed in comparison with the scanning signal Gwr (i) and the control signals Gel (i), Gcmp (i), and Gorst (i) corresponding to the i-th row. The waveform is preceded in time by the period (H).

<Light emission period>
For convenience of explanation, the light emission period which is the premise of the initialization period will be described. In the light emission period of the i-th row, the scanning line driving circuit 20 supplies a predetermined second potential V2 to the i-th scanning line 12 and supplies a predetermined first potential V1 to the i-th control line 144. The second potential V2 is supplied to the i-th control line 143, and the second potential V2 is supplied to the i-th control line 145. In the present embodiment, the first potential V1 is set lower than the second potential V2. For example, the first potential V1 only needs to correspond to the L level of the control signal (control signal Gref or the like) supplied by the control circuit 3, and the second potential VH is the H of the control signal supplied by the control circuit 3. Anything corresponding to the level may be used. That is, as shown in FIG. 7, in the light emission period of the i-th row, the scanning signal Gwr (i) is set to H level, the control signal Gel (i) is set to L level, and the control signal Gcmp (i) Is set to H level, and the control signal Gorst (i) is set to H level.
For this reason, as shown in FIG. 8, in the pixel circuit 110 in the i row (3j-2) column, the transistor 124 is turned on, while the transistors 122, 123, and 125 are turned off. Therefore, the transistor 121 supplies a current Ids corresponding to the gate-source voltage Vgs to the OLED 130. As will be described later, in this embodiment, the voltage Vgs in the light emission period is a value obtained by level-shifting the potential of the data signal. Therefore, a current corresponding to the gradation level is supplied to the OLED 130 in a state where the threshold voltage of the transistor 121 is compensated.

  Note that since the light emission period of the i-th row is a period during which horizontal scanning is performed except for the i-th row, the potential of the data line 14 varies appropriately. However, in the pixel circuit 110 in the i-th row, since the transistor 122 is off, the potential fluctuation of the data line 14 is not considered here. Further, in FIG. 8, paths that are important in the description of the operation in the light emission period are indicated by bold lines.

<Initialization period>
Next, when the scanning period of the i-th row is reached, first, the initialization period (b) is started as the first period.
In the initialization period of the i-th row, as shown in FIG. 7, the scanning line driving circuit 20 supplies the second potential V2 to the i-th scanning line 12 and sets the scanning signal Gwr (i) to the H level. Then, the second potential V2 is supplied to the i-th control line 144 to set the control signal Gel (i) to H level, and the second potential V2 is supplied to the i-th control line 143 to control the signal. Gcmp (i) is set to the H level, the first potential V1 is supplied to the control line 145 in the i-th row, and the control signal Gorst (i) is set to the L level. Therefore, in the pixel circuit 110 in the i row (3j-2) column, the transistor 124 is turned off and the transistor 125 is turned on. As a result, the path of the current supplied to the OLED 130 is interrupted, and the anode 130a of the OLED 130 is set to the reset potential Vorst.
Since the OLED 130 has a configuration in which the organic EL layer is sandwiched between the anode 130a and the cathode as described above, a capacitance is parasitic between the anode and the cathode in parallel. When a current flows through the OLED 130 during the light emission period, the voltage across the anode and cathode of the OLED 130 is held by a parasitic capacitance in parallel between the anode and cathode. This holding voltage is controlled by turning on the transistor 125. Reset. For this reason, in the present embodiment, when a current flows again through the OLED 130 in a later light emission period, it is less susceptible to the voltage held by the capacitor parasitic in parallel between the anode and the cathode.

  Specifically, for example, when switching from a high-brightness display state to a low-brightness display state, if the configuration does not reset, the high voltage when the luminance is high (a large current flows) is retained. In addition, even if a small current is applied, an excessive current flows and the display state with low luminance cannot be achieved. On the other hand, in this embodiment, the potential of the anode 130a of the OLED 130 is reset when the transistor 125 is turned on, so that the reproducibility on the low luminance side is improved. In the present embodiment, the reset potential Vorst is set so that the difference between the reset potential Vorst and the potential Vct of the common electrode 118 is lower than the light emission threshold voltage of the OLED 130. For this reason, in the initialization period (a compensation period and a writing period described below), the OLED 130 is in an off (non-light emitting) state.

On the other hand, in the initialization period of the i-th row, as shown in FIG. 7, the control circuit 3 sets the control signal / Gini to the L level, the control signal Gref to the H level, and the control signal Gcpl to the L level. Set. For this reason, the transistor 43 and the transistor 45 are turned on. As a result, one electrode of the storage capacitor 44 and the power supply line 61 are electrically connected, and one electrode (and the data line 14) of the storage capacitor 44 is initialized to the initial potential Vini. In addition, the other electrode of the storage capacitor 44 and the power supply line 62 are electrically connected, and the other electrode (and the node h1) of the storage capacitor 44 is initialized to the reference potential Vref.
In this embodiment, the initial potential Vini is set such that (Vel−Vini) is larger than the threshold voltage | Vth | of the transistor 121. Note that since the transistor 121 is a P-channel transistor, the threshold voltage Vth with respect to the source potential is negative. Therefore, in order to prevent confusion in the description of the height relationship, the threshold voltage is expressed by the absolute value | Vth | and defined by the magnitude relationship.

As shown in FIG. 7, the data signal supply circuit 70 has the demultiplexers DM (1) and DM (2) in the period from the start of the scanning period of the i-th row to the start of the writing period. , ..., DM (n) are supplied with data signals Vd (1), Vd (2), ..., Vd (n), respectively. That is, in the j-th group, the data signal supply circuit 70 sequentially outputs the data signal Vd (j) in i row (3j-2) column, i row (3j-1) column, i row (3j). The potential is switched according to the gradation level of the pixels in the column.
On the other hand, the control circuit 3 exclusively sets the control signals Sel (1), Sel (2), and Sel (3) to the H level in order in accordance with the switching of the potential of the data signal. As a result, the three transmission gates 34 provided in each demultiplexer DM are turned on in the order of the left end column, the center column, and the right end column, respectively.
Here, in the initialization period, when the transmission gate 34 in the leftmost column belonging to the j-th group is turned on by the control signal Sel (1), the data signal Vd (j) is supplied to one electrode of the storage capacitor 41. Therefore, the data signal Vd (j) is held by the holding capacitor 41.

<Compensation period>
In the i-th scanning period, the second period is the compensation period (c). In the i-th compensation period, as shown in FIG. 7, the control circuit 3 sets the control signal / Gini to the H level, the control signal Gref to the H level, and the control signal Gcpl to the L level. For this reason, the transistor 43 is turned on, while the transistor 45 is turned off. As a result, the other electrode of the storage capacitor 44 and the power supply line 62 are electrically connected, and the node h1 is set to the reference potential Vref.

In the compensation period, when the transmission gate 34 in the leftmost column belonging to the jth group is turned on by the control signal Sel (1), the data signal Vd (j) is supplied to one electrode of the storage capacitor 41.
Note that when the transmission gate 34 in the leftmost column belonging to the jth group is already turned on by the control signal Sel (1) in the initialization period, the transmission gate 34 is not turned on in the compensation period. The data signal Vd (j) supplied when the leftmost row of transmission gates 34 is turned on is held by the holding capacitor 41.

Further, in the i-th compensation period, as shown in FIG. 7, the scanning line driving circuit 20 supplies the first potential V1 to the i-th scanning line 12 and sets the scanning signal Gwr (i) to the L level. And the second potential V2 is supplied to the i-th control line 144 to set the control signal Gel (i) to the H level, and the first potential V1 is supplied to the i-th control line 143 for control. The signal Gcmp (i) is set to the L level, the first potential V1 is supplied to the control line 145 in the i-th row, and the control signal Gorst (i) is set to the L level. For this reason, since the transistor 123 is turned on, the transistor 121 is diode-connected. As a result, a drain current flows through the transistor 121 and charges the gate node g and the data line 14. Specifically, the current flows through a path of the feeder line 116 → the transistor 121 → the transistor 123 → the transistor 122 → the data line 14 in the (3j-2) th column. Therefore, the data line 14 and the gate node g that are connected to each other when the transistor 121 is turned on rise from the initial potential Vini. However, since the current flowing through the path becomes difficult to flow as the gate node g approaches the potential (Vel− | Vth |), the data line 14 and the gate node g have the potential (Vel−) until the end of the compensation period. | Vth |).
Therefore, the storage capacitor 132 holds the threshold voltage | Vth | of the transistor 121 at the end of the compensation period. Hereinafter, the potential (Vel− | Vth |) of the gate node g at the end of the compensation period may be expressed as a potential Vp.

When the compensation period ends, the scanning line driving circuit 20 changes the control signal Gcmp (i) from the L level to the H level by switching the potential supplied to the control line 143 from the first potential V1 to the second potential V2. To do. As a result, the diode connection of the transistor 121 is released.
Note that the scanning line driving circuit 20 performs control so that the waveform when the control signal Gcmp (i) changes from the L level to the H level is gentler than the waveform when the control signal Gcmp (i) changes from the H level to the L level. The potential supplied to the line 143 is switched. That is, as shown in FIG. 7, the period during which the scanning line driving circuit 20 switches the potential supplied to the control line 143 from the second potential V2 to the first potential V1 is a third switching period T3, and the first potential V1 A period for switching to the second potential V2 is a fourth switching period T4. At this time, the scanning line driving circuit 20 changes the potential supplied to the control line 143 so that the time length of the fourth switching period T4 is sufficiently longer than the time length of the third switching period T3.

As described above, when viewed in plan, the control line 143 and the gate electrode G1 (the gate of the transistor 121) intersect each other. Therefore, there is a parasitic capacitance between the control line 143 and the gate electrode G1. Therefore, if the time length of the fourth switching period T4 is made as short as the time length of the third switching period T3 and the control signal Gcmp (i) is suddenly raised from the L level to the H level, the control is performed. Under the influence of the high frequency component of the control signal Gcmp (i) on the line 143, the potential of the gate electrode G1 changes.
Although details will be described later, at the end of the compensation period, the potential of the gate node g (the potential of the gate electrode G1) is determined to be a potential that compensates for variations in the threshold voltage of the transistor 121 for each pixel circuit 110. However, when the potential of the gate node g changes after the compensation period ends, variations in the threshold voltage for each pixel circuit 110 cannot be compensated, resulting in display unevenness that impairs the uniformity of the display screen. Becomes prominent.
On the other hand, in the present embodiment, when the time length of the fourth switching period T4 is sufficiently longer than the time length of the third switching period T3, the control signal Gcmp (i) changes from the L level to the H level. By making the waveform of a gentle waveform, the potential fluctuation of the control line 143 is prevented from propagating to the gate node g (gate electrode G1). As a result, it is possible to compensate for variations in the threshold voltage for each pixel circuit 110 and to display a high quality image with a uniform display.

  Actually, the time length of the third switching period T3 is short enough to be regarded as “0”. That is, the waveform when the control signal Gcmp (i) falls from the H level to the L level may be equal to, for example, the waveform when the control signal Gref falls from the H level to the L level. However, in FIG. 7, for convenience of explanation, the falling waveform of the control signal Gcmp (i) is shown as a gentler waveform than the actual waveform in order to illustrate the third switching period T3.

  Further, when the compensation period ends, the control circuit 3 changes the control signal Gref from the H level to the L level, so that the transistor 43 is turned off. Therefore, although the path from the data line 14 in the (3j-2) column to the gate node g in the pixel circuit 110 in the i row (3j-2) column is in a floating state, the potential of the path is It is maintained at (Vel− | Vth |) by the holding capacitors 50 and 132.

<Writing period>
After the initialization period, the writing period (d) is reached as the third period. In the writing period of the i-th row, the scanning line driving circuit 20 supplies the first potential V1 to the i-th scanning line 12 and sets the scanning signal Gwr (i) to the L level as shown in FIG. Then, the second potential V2 is supplied to the i-th control line 144 to set the control signal Gel (i) to H level, and the second potential V2 is supplied to the i-th control line 143 to control the signal. Gcmp (i) is set to the H level, the first potential V1 is supplied to the control line 145 in the i-th row, and the control signal Gorst (i) is set to the L level. As a result, the diode connection of the transistor 121 is released.

Further, in the writing period of the i-th row, as shown in FIG. 7, the control circuit 3 sets the control signal / Gini to the H level, the control signal Gref to the L level, and the control signal Gcpl to the H level. Set. For this reason, since the transmission gate 42 is turned on, the data signal Vd (j) held in the holding capacitor 41 is supplied to the other electrode of the holding capacitor 44 via the node h1. As a result, the node h1 and the other electrode of the storage capacitor 44 change from the reference potential Vref in the compensation period. The amount of potential change of the node h1 at this time is expressed as ΔVh. Further, the potential (Vref + ΔVh) of the node h1 in the writing period may be expressed as the potential Vh.
When the potential of the node h1 changes from the reference potential Vref to the potential Vh by ΔVh, the potential of the gate node g and the data line 14 also changes from the potential Vp = (Vel− | Vth |) set in the compensation period. . The potential change amount of the gate node g at this time is expressed as ΔVg. In addition, the potential (Vp + ΔVg) of the gate node g in the writing period may be expressed as a potential Vgate.

Hereinafter, with reference to FIG. 9, changes in the potentials of the gate node g and the node h1 before and after the start of the writing period will be described in detail.
FIG. 9A is an explanatory diagram for explaining potential changes of the node h1 and the gate node g before and after the start of the writing period. In this figure, (A-1) represents the potential of the node h1 and the gate node g before the start of the write period, and (A-2) is after the start of the write period (that is, the transmission gate 42 is turned on). The potentials of the node h1 and the gate node g in FIG. Note that since the storage capacitor 50 and the storage capacitor 132 are electrically connected in parallel in the compensation period and the writing period, the capacitance value C0 of the combined capacitor 501 of the storage capacitor 50 and the storage capacitor 132 is expressed by the following equation (1). ).
C0 = Cpix + Cdt (1)

If the charge accumulated in the combined capacitor 501 before the start of the writing period is Q0a and the charge accumulated in the combined capacitor 501 after the start of the write period is Q0b, the combined charge is generated before and after the start of the write period. The electric charge (Q0a-Q0b) flowing out from the capacitor 501 is expressed by the following equation (2). Similarly, if the charge accumulated in the holding capacitor 44 is Q1a before the start of the writing period and Q1b is the charge accumulated in the holding capacitor 44 after the start of the writing period, the writing period starts. The charge (Q1b-Q1a) flowing into the storage capacitor 44 before and after is expressed by the following equation (3). Since the charge flowing out from the combined capacitor 501 and the charge flowing into the storage capacitor 44 are equal before and after the start of the writing period, the following expression (4) is established.
Q0a-Q0b = C0 * (Vp-Vgate) (2)
Q1b-Q1a = Crf1 * {(Vgate-Vh)-(Vp-Vref)} (3)
Q0a-Q0b = Q1b-Q1a (4)

From the expressions (2) to (4), the potential Vgate of the gate node g in the writing period can be calculated. Specifically, the potential Vgate is expressed by the following formula (5).
Vgate = {Crf1 / (Crf1 + C0)} * {Vh−Vref} + Vp (5)

Here, the capacity ratio k1 shown in the following equation (6) is introduced. At this time, the potential Vgate of the gate node g in the writing period can be expressed by the following formula (7) using the capacitance ratio k1, and the potential change amount ΔVg of the gate node g before and after the start of the writing period is the capacitance ratio. It can be expressed by the following equation (8) using k1.
k1 = Crf1 / (Crf1 + Cdt + Cpix) (6)
Vgate = k1 * (Vh−Vref) + Vp
= K1 * ΔVh + Vp (7)
ΔVg = Vgate-Vp
= K1 * ΔVh (8)

Thus, in the writing period, the potential of the gate node g is obtained by multiplying the potential change amount ΔVh of the node h1 by the capacitance ratio k1 from the potential Vp = (Vel− | Vth |) in the compensation period (k1 * ΔVh). ), The potential Vgate = (Vel− | Vth | + k1 · ΔVh) shifted in the upward direction. At this time, the absolute value | Vgs | of the voltage Vgs of the transistor 121 is a value obtained by subtracting the potential increase of the gate node g from the threshold voltage | Vth | as shown in the following equation (9).
| Vgs | = | Vth | −k1 * ΔVh (9)

FIG. 9B is an explanatory diagram for explaining potential changes of the node h1 and the node h2 before and after the start of the writing period. In this figure, (B-1) represents the potentials of the nodes h1 and h2 before the start of the write period, and (B-2) is after the start of the write period (that is, the transmission gate 42 is turned on). The potentials of the node h1 and the node h2 in (after) are shown. Note that in the compensation period and the writing period, the combined capacitor 501 and the storage capacitor 41 of the storage capacitor 50 and the storage capacitor 132 are electrically connected in series, and thus the storage capacitor 50, the storage capacitor 132, and the storage capacitor 44 are connected. The capacitance value C1 of the composite capacitor 502 is expressed by the following equation (10).
C1 = (C0 * Crf1) / (C0 + Crf1) (10)

If the charge accumulated in the composite capacitor 502 before the start of the write period is Q1c and the charge stored in the composite capacitor 502 after the start of the write period is Q1d, the composite capacitor before and after the start of the write period. The electric charge (Q1c-Q1d) flowing out from 502 is expressed by the following equation (11). Similarly, if the charge accumulated in the storage capacitor 41 before the start of the write period is Q2c and the charge accumulated in the storage capacitor 41 after the start of the write period is Q2d, before and after the start of the write period The charge (Q2d−Q2c) flowing into the storage capacitor 41 is expressed by the following equation (12). Since the charge flowing out from the combined capacitor 502 and the charge flowing into the storage capacitor 41 are equal before and after the start of the writing period, the following equation (13) is established.
Q1c-Q1d = C1 * {Vref-Vh} (11)
Q2d-Q2c = Crf2 * {Vh-Vd (j)} (12)
Q1c-Q1d = Q2d-Q2c (13)

Therefore, the potential Vh of the node h1 in the writing period can be calculated from the equations (11) to (13). Specifically, the potential Vh is expressed by the following formula (14). The potential change amount ΔVh at the node h1 is expressed by the following equation (15).
Vh = {C1 / (C1 + Crf2)} * (Vref)
+ {Crf2 / (C1 + Crf2)} * {Vd (j)} (14)
ΔVh = Vh-Vref
= {Crf2 / (C1 + Crf2)} * {Vd (j) -Vref} (15)

Here, when the capacitance ratio k2 shown in the following equation (16) is introduced, the potential change amount ΔVh can also be expressed by the following equation (17).
k2 = Crf2 / (C1 + Crf2) (16)
ΔVh = k2 * {Vd (j) −Vref} (17)

The potential Vgate of the gate node g in the writing period can be expressed by the following formula (18) by substituting the formula (17) into the formula (7). Therefore, the potential change amount ΔVg of the gate electrode G before and after the start of the writing period can be expressed by the following equation (19).
Vgate = k1 * k2 * {Vd (j) -Vref} + Vp (18)
ΔVg = k1 * k2 * {Vd (j) −Vref} (19)

  Thus, the potential of the node h1 changes by a value ΔVh obtained by shifting the potential indicated by the data signal Vd (j) by the reference potential Vref and compressing it by the capacitance ratio k2. As a result, the potential Vgate of the gate node g changes by a value obtained by further compressing the potential change amount ΔVh of the node h1 with the capacitance ratio k1. That is, the potential Vgate of the gate node g in the writing period is obtained by shifting the data signal Vd (j) by the reference potential Vref and the capacitance value with respect to the shifted potential as shown in the equation (18). A compressed potential is supplied by multiplying the capacitance ratio k3 = k1 * k2 determined based on Cdt, Crf1, Crf2, and Cpix.

FIG. 10 is a diagram showing the relationship between the potential of the data signal Vd (j) and the potential Vgate of the gate node g in the writing period. As described above, the data signal Vd (j) generated based on the image signal Vid supplied from the control circuit 3 can take a potential range from the minimum value Vmin to the maximum value Vmax according to the gradation level of the pixel. . As described above, the potential Vgate obtained by shifting the data signal Vd (j) by the reference potential Vref and compressing it by the capacitance ratio k3 is written to the gate node g. At this time, the potential range ΔVgate of the gate node g is compressed to a value obtained by multiplying the potential range ΔVdata (= Vmax−Vmin) of the data signal by the capacitance ratio k3, as shown in the following equation (20).
ΔVgate = k3 * ΔVdata (20)

  Further, as to which direction and how much the potential range ΔVgate of the gate node g is shifted with respect to the potential range ΔVdata of the data signal, as apparent from the equation (18), the potential Vp (= Vel− | Vth. |) And the reference potential Vref.

After the writing period ends, the scanning line driving circuit 20 switches the potential supplied to the scanning line 12 from the first potential V1 to the second potential V2, thereby changing the scanning signal Gwr (i) from the L level to the H level. change. Accordingly, since the transistor 122 is turned off, the potential of the gate node g is maintained at the potential Vgate = [{Vel− | Vth |} + k3 · {Vd (j) −Vref}].
The scanning line driving circuit 20 scans the scanning line Gwr (i) so that the waveform when the scanning signal Gwr (i) changes from the L level to the H level is gentler than the waveform when the scanning signal Gwr (i) changes from the H level to the L level. The potential supplied to 12 is switched. That is, as shown in FIG. 7, a period during which the scanning line driving circuit 20 switches the potential supplied to the scanning line 12 from the second potential V2 to the first potential V1 is a first switching period T1, and the first potential V1 A period for switching to the second potential V2 is a second switching period T2. At this time, the scanning line driving circuit 20 changes the potential supplied to the scanning line 12 so that the time length of the second switching period T2 is sufficiently longer than the time length of the first switching period T1.

As described above, when viewed in plan, the scanning line 12 and the gate electrode G1 (the gate of the transistor 121) intersect each other. For this reason, a parasitic capacitance exists between the scanning line 12 and the gate electrode G1. Accordingly, if the time length of the second switching period T2 is made as short as the time length of the first switching period T1, and the scanning signal Gwr (i) is suddenly raised from the L level to the H level, scanning is performed. Under the influence of the high frequency component of the scanning signal Gwr (i) on the line 12, the potential of the gate electrode G1 changes.
As described above, at the end of the writing period, the potential of the gate node g (the potential of the gate electrode G1) is set to the potential Vgate based on the data signal Vd (j) (image signal Vid) that defines the luminance of the OLED 130. . However, when the potential of the gate node g changes after the end of the writing period, the potential of the gate node g is different from the potential Vgate determined based on the data signal Vd (j). In this case, each pixel displays a gradation different from the gradation specified by the image signal Vid, and the display quality deteriorates.
On the other hand, in the present embodiment, the time length of the second switching period T2 is made sufficiently longer than the time length of the first switching period T1, and the scanning signal Gwr (i) changes from the L level to the H level. By making the waveform of (2) a gentle waveform, the potential fluctuation of the scanning line 12 is prevented from propagating to the gate node g (gate electrode G1). As a result, each pixel can accurately display the gradation defined by the image signal Vid, and display with high quality is possible.

  Actually, the time length of the first switching period T1 is short enough to be regarded as “0”. That is, the waveform when the scanning signal Gwr (i) falls from the H level to the L level may be equal to the waveform when the control signal Gref falls from the H level to the L level, for example. However, in FIG. 7, for convenience of explanation, in order to illustrate the first switching period T <b> 1, the falling waveform of the scanning signal Gwr (i) is described so as to be sufficiently gradual compared to the actual. .

<Light emission period>
The light emission period is started after the writing period of the i-th row is completed. In the present embodiment, after the writing period of the i-th row ends, the light emission period starts after one horizontal scanning period. In the light emission period, the scanning line driving circuit 20 sets the scanning signal Gwr (i) to the H level as described above, so that the transistor 122 is turned off, and the gate node g has the potential Vgate = [{Vel− | Vth. |} + K3 · {Vd (j) −Vref}]. In the light emission period, the scanning line driving circuit 20 sets the control signal Gel (i) to the L level, so that the transistor 124 is turned on in the pixel circuit 110 in the i row (3j-2) column. Since the gate-source voltage Vgs is [| Vth | −k3 · {Vd (j) −Vref}], the OLED 130 has a current corresponding to the gradation level as shown in FIG. Is supplied in a state in which the threshold voltage of the transistor 121 is compensated.
Such an operation is also executed in parallel in time in other pixel circuits 110 in the i row other than the pixel circuit 110 in the (3j-2) th column in the scanning period of the i row. Further, such an operation on the i-th row is actually executed in the order of 1, 2, 3,..., (M−1), m-th row in the period of one frame, and is repeated for each frame. It is.

<Effect of embodiment>
According to the present embodiment, the scanning line 12 and the control line 143 are provided at a position intersecting with the gate (gate electrode G1) of the transistor 121 when viewed in plan. Therefore, a plurality of control lines extending in the X direction (scanning line 12, control lines 143, 144, and 145) are compared with the case where the scanning line 12 and the control line 143 are provided so as not to cross the gate of the transistor 121. Can be wired at high density, and the pitch of the control lines can be reduced. That is, according to the present embodiment, the control lines are arranged with high density, so that the pitch of the pixel circuits 110 can be reduced, thereby reducing the size of the electro-optical device 1 (display unit 100) and high definition of display. Can be realized.

  According to the present embodiment, the scanning line driving circuit 20 has a gentler waveform when the scanning signal Gwr (i) changes from the L level to the H level than the waveform when the scanning signal Gwr (i) changes from the H level to the L level. Thus, the potential supplied to the scanning line 12 is changed. Thereby, even when the scanning line 12 and the gate of the transistor 121 intersect when viewed in plan, it is possible to prevent the potential fluctuation of the scanning signal Gwr (i) from propagating to the gate of the transistor 121. Therefore, each pixel can accurately display the gradation specified by the image signal Vid.

  According to the present embodiment, the scanning line driving circuit 20 has a gentler waveform when the control signal Gcmp (i) changes from the L level to the H level than the waveform when the control signal Gcmp (i) changes from the H level to the L level. Thus, the potential supplied to the control line 143 is changed. Accordingly, even when the control line 143 and the gate of the transistor 121 intersect when viewed in plan, the potential fluctuation of the control signal Gcmp (i) can be prevented from propagating to the gate of the transistor 121. Therefore, high-quality display that ensures the uniformity of display is possible.

  According to the present embodiment, the potential range ΔVgate at the gate node g is narrowed with respect to the potential range ΔVdata of the data signal, so that the voltage reflecting the gradation level can be applied to the transistor 121 without engraving the data signal with fine accuracy. Can be applied between the gate and the source. Therefore, the current supplied to the OLED 130 is accurately controlled even when the minute current flowing through the OLED 130 changes relatively greatly with respect to the change in the gate-source voltage Vgs of the transistor 121 in the pixel circuit 110. Is possible.

Further, as indicated by a broken line in FIG. 4, there is a case where a capacitance Cprs is parasitic between the data line 14 and the gate node g in the pixel circuit 110. In this case, if the potential change width of the data line 14 is large, it is propagated to the gate node g via the capacitor Cprs, so-called crosstalk or unevenness occurs, and the display quality is deteriorated. The influence of the capacitance Cprs is noticeable when the pixel circuit 110 is miniaturized.
On the other hand, in the present embodiment, the potential change range of the data line 14 is also narrowed with respect to the potential range ΔVdata of the data signal, so that the influence via the capacitor Cprs can be suppressed.

  Further, according to this embodiment, the current Ids supplied to the OLED 130 by the transistor 121 cancels the influence of the threshold voltage. Therefore, according to the present embodiment, even if the threshold voltage of the transistor 121 varies from pixel circuit 110 to pixel circuit 110, the variation is compensated and a current corresponding to the gradation level is supplied to the OLED 130. As a result of suppressing the occurrence of display unevenness that impairs uniformity, high-quality display is possible.

This cancellation will be described with reference to FIG. As shown in this figure, the transistor 121 operates in a weak inversion region (subthreshold region) in order to control a minute current supplied to the OLED 130.
In the figure, A shows the relationship between the gate potential of a transistor having a large threshold voltage | Vth | and the current supplied by the transistor, and B shows the gate potential of a transistor having a small threshold voltage | Vth | and the current supplied by the transistor. Shows the relationship. In FIG. 11, the gate-source voltage Vgs is the difference between the solid line and the potential Vel. Further, in FIG. 11, the current on the vertical scale is indicated by a logarithm with the direction from the source to the drain being negative (down).
In the compensation period, the gate node g changes from the initial potential Vini to the potential (Vel− | Vth |). Therefore, a transistor having a large threshold voltage | Vth | represented by a solid line A moves from S to Aa, while a transistor having a small threshold voltage | Vth | represented by a solid line B has an operating point of S. Move from Ba to Ba.
Next, when the potential of the data signal to the pixel circuit 110 to which the two transistors belong is the same, that is, when the same gradation level is designated, the potential shift amount from the operating points Aa and Ba is Are the same k1 · ΔVh. Therefore, for the transistor represented by the solid line A, the operating point moves from Aa to Ab, and for the transistor represented by the solid line B, the operating point moves from Ba to Bb, but the current at the operating point after the potential shift is changed. The two transistors are aligned at substantially the same Ids.

  According to the present embodiment, the operation of holding the data signal supplied from the control circuit 3 via the demultiplexer DM in the holding capacitor 41 is executed from the initialization period to the compensation period. That is, according to the present embodiment, the operation of initializing the potential of the anode 130a to the reset potential Vorst and the operation of holding the data signal in the holding capacitor 41 are performed in parallel during the initialization period, and the compensation is performed. The operation for compensating for the variation in threshold voltage of the transistor 121 during the period and the operation for holding the data signal in the storage capacitor 41 are performed in parallel. For this reason, time restrictions can be relaxed for the operation to be executed in one horizontal scanning period, and the data signal supply operation in the data signal supply circuit 70 can be slowed down.

<Modification>
The present invention is not limited to the above-described embodiments, and various modifications as described below are possible, for example. Moreover, the aspect of the deformation | transformation described below can also combine suitably arbitrarily selected 1 or several.

<Modification 1>
In the above-described embodiment, each pixel circuit 110 has a configuration in which the scanning line 12 and the control line 143 intersect with the gate electrode G1 when viewed in plan, but in addition to the scanning line 12 and the control line 143, The control line 144 may intersect with the gate electrode G1.
FIG. 12 is a plan view illustrating a configuration of the pixel circuit 110 according to the first modification. The pixel circuit 110 according to the first modification includes a point where the control line 144 and the gate electrode G1 intersect when viewed in plan, and a point where the control line 144 has a branch portion 142a branched in the Y direction for each pixel circuit 110. The pixel circuit 110 is configured similarly to the pixel circuit 110 according to the embodiment shown in FIG.
According to this configuration, a plurality of control lines (scanning line 12, control lines 143, 144, and 145) extending in the X direction are compared with the case where the control line 144 is provided so as not to cross the gate of the transistor 121. Wiring can be performed with high density, and the pitch of the control lines can be reduced. As a result, it is possible to reduce the size of the electro-optical device (display unit) and increase the definition of the display.

When the control line 144 and the gate electrode G1 intersect, the scanning line driving circuit 20 changes the waveform when the control signal Gel (i) changes from the H level to the L level from the L level to the H level. The potential supplied to the control line 144 may be switched so as to be gentler than the waveform at that time.
FIG. 13 is a timing chart for explaining the operation of the electro-optical device according to the first modification. As illustrated in FIG. 13, the scanning line driving circuit 20 according to the first modification has a time length of a fifth switching period T5 in which the potential supplied to the control line 144 is switched from the second potential V2 to the first potential V1. The potential supplied to the control line 144 is changed so as to be sufficiently longer than the time length of the sixth switching period T6 for switching from the first potential V1 to the second potential V2.
As described above, the potential of the gate electrode G1 (the gate node g of the transistor 121) is set to the potential Vgate that defines the luminance of the OLED 130 in the writing period preceding the fifth switching period T5. Therefore, in the fifth switching period T5, when the potential of the control line 144 changes abruptly and the potential fluctuation propagates to the gate electrode G1, each pixel cannot accurately display the gradation defined by the image signal Vid.
On the other hand, in the scanning line driving circuit 20 according to the first modification, the time length of the fifth switching period T5 is sufficiently longer than the time length of the sixth switching period T6, and the control signal Gel (i) is H. By making the waveform at the time of changing from the level to the L level gentle, it is possible to prevent the potential fluctuation of the control line 144 from propagating to the gate node g (gate electrode G1). As a result, each pixel can accurately display the gradation defined by the image signal Vid, and display with high quality is possible.

<Modification 2>
In the above-described embodiment, each pixel circuit 110 has a configuration in which the scanning line 12 and the control line 143 intersect with the gate electrode G1 when viewed in plan, but in addition to the scanning line 12 and the control line 143, The control line 145 may cross the gate electrode G1.
FIG. 14 is a plan view illustrating a configuration of a pixel circuit 110 according to the second modification. The pixel circuit 110 according to the modified example 2 has a point where the control line 145 and the gate electrode G1 intersect when viewed in plan, and a point where the control line 145 has a branch portion 145a branched in the Y direction for each pixel circuit 110. The pixel circuit 110 is configured similarly to the pixel circuit 110 according to the embodiment shown in FIG.
According to this configuration, a plurality of control lines (scanning line 12, control lines 143, 144, and 145) extending in the X direction are compared with the case where the control line 145 is provided so as not to cross the gate of the transistor 121. Wiring can be performed with high density, and the pitch of the control lines can be reduced. As a result, it is possible to reduce the size of the electro-optical device (display unit) and increase the definition of the display.
When the control line 145 and the gate electrode G1 intersect, the scanning line driving circuit 20 has a waveform when the control signal Gorst (i) changes from L level to H level as shown in FIG. The potential supplied to the control line 145 may be switched so as to be gentler than the waveform when changing from the level to the L level.
FIG. 15 is a timing chart for explaining the operation of the electro-optical device according to the second modification.
As shown in FIG. 15, the scanning line driving circuit 20 according to the modified example 2 has a time length of an eighth switching period T8 for switching the potential supplied to the control line 145 from the first potential V1 to the second potential V2. The potential supplied to the control line 145 is changed so as to be sufficiently longer than the time length of the seventh switching period T7 for switching from the two potential V2 to the first potential V1. In this case, after the potential of the gate node g (gate electrode G1) of the transistor 121 is determined to be the potential Vgate that defines the luminance of the OLED 130, the potential fluctuation is prevented from propagating to the control electrode 145 to the gate electrode G1, Each pixel can accurately display the gradation defined by the image signal Vid.

<Modification 3>
In the embodiment and the modification described above, each pixel circuit 110 includes the transistors 121 to 125, the OLED 130, and the storage capacitor 132. However, the pixel circuit 110 includes at least the transistor 121, the transistor 122, and Any device including the OLED 130 may be used. In this case, the display unit 100 is modified from among a plurality of control lines (scanning line 12, control lines 143, 144, and 145) provided in the display unit 100 and extending in the X direction in the above-described embodiments and modifications. Only the control lines corresponding to the transistors included in the pixel circuit 110 of Example 3 may be provided in each row. In other words, the display unit 100 according to the modification 3 may be provided with one or more control lines including the scanning lines 12 in each row. For example, when each pixel circuit 110 includes the transistor 121, the transistor 122, the OLED 130, and the storage capacitor 132, only the scanning line 12 is provided as a control line corresponding to each row. Each pixel circuit 110 may include a transistor other than the transistors 121 to 125. In this case, the display unit 100 may be provided with a control line corresponding to the transistor.
When one or more control lines including the scanning lines 12 are provided in each row, at least one of the one or more control lines extending in the X direction provided in each row is the transistor 121 in plan view. And the gate node g (gate electrode G1). Thereby, the control lines extending in the X direction can be wired with high density, and the electro-optical device (display unit) can be downsized and the display can be made high definition.
Further, the scanning line driving circuit 20 applies the potential of at least one control line that intersects the gate electrode G1 in plan view among one or more control lines provided in each row from the end of the compensation period to the next scanning period. In the case of changing the time until the start of this, it is preferable to make the waveform of the potential change gentle. For example, when the gate electrode G1 and the scanning line 12 intersect, the scanning line driving circuit 20 is a time of the second switching period T2 for switching the potential supplied to the scanning line 12 from the first potential V1 to the second potential V2. What is necessary is just to change the electric potential supplied to the scanning line 12 so that length may become long enough compared with the time length of 1st switching period T1 which switches from 2nd electric potential V2 to 1st electric potential V1. Thereby, it is possible to prevent the potential change of the control line intersecting with the gate electrode G1 from propagating to the gate electrode G1, and each pixel can accurately display the gradation defined by the image signal Vid. It becomes.

  Note that the scanning line driving circuit 20 also changes the potential of the control line that does not intersect the gate electrode G1 in plan view between the end of the compensation period and the start of the next scanning period. The potential change waveform may be gentle. Even when the control line does not intersect the gate electrode G1, there may be a parasitic capacitance between the control line and the gate electrode G1. Therefore, by making the waveform when the potential of the control line changes gentle, it is possible to prevent the potential change of the control line from propagating to the gate electrode G1.

<Modification 4>
In the embodiment and the modification described above, each level shift circuit LS includes the storage capacitor 41, the storage capacitor 44, the transistor 45, the transistor 43, and the transmission gate 42. However, the level shift circuit LS includes at least the level shift circuit LS. Any storage capacitor 44, transistor 43, and transistor 45 may be used. In this case, the data signal supply circuit 70 and the demultiplexer DM may supply the data signal Vd (j) to the other electrode of the storage capacitor 44 in the writing period.
Even when the level shift circuit LS does not include the storage capacitor 41, the data signal Vd (j) supplied to the other electrode of the storage capacitor 44 is compressed by the capacitance ratio k1 and then supplied to the gate node g. Is done. As a result, the potential of the gate node of the driving transistor can be set with fine precision without having to carve the data signal with fine precision, so that current can be supplied to the light emitting element with high precision. Quality display is possible.

<Modification 5>
In the embodiment and the modification described above, the data line driving circuit 10 includes the level shift circuit LS, the demultiplexer DM, and the data signal supply circuit 70. However, the data line driving circuit 10 includes at least a data signal. Any device including the supply circuit 70 may be used. In this case, the data line driving circuit 10 supplies the data signal Vd (j) directly to the gate node g.
Furthermore, in the above-described embodiment and modification, the display panel 2 includes the storage capacitors 50 in each column, but may be configured without this.

<Modification 6>
In the embodiment and the modification described above, the control circuit 3 and the display panel 2 are separated from each other. However, the control circuit 3 and the display panel 2 may be formed on the same substrate. For example, the control circuit 3 may be integrated on the silicon substrate together with the display unit 100, the data line driving circuit 10, the scanning line driving circuit 20, and the like.

<Modification 7>
In the embodiment and the modification described above, the electro-optical device 1 is integrated on the silicon substrate. However, the electro-optical device 1 may be integrated on another semiconductor substrate. For example, an SOI substrate may be used. Further, it may be formed on a glass substrate or the like by applying a polysilicon process. In any case, the present invention is effective in a configuration in which the pixel circuit 110 is miniaturized and the drain current in the transistor 121 greatly changes exponentially with respect to the change in the gate voltage Vgs.
Further, the present invention may be applied when the pixel circuit does not need to be miniaturized.

<Modification 8>
In the embodiment and the modification described above, the data lines 14 are grouped every three columns, and the data lines 14 are sequentially selected in each group to supply the data signal. The number of lines may be a predetermined number of “2” or more and “3n” or less. For example, the number of data lines constituting the group may be “2”, or may be “4” or more.
Further, a configuration may be employed in which data signals are supplied to the data lines 14 of each column all at once without grouping, that is, without using the demultiplexer DM.

<Modification 9>
In the embodiment and the modification described above, the transistors 121 to 125 in the pixel circuit 110 are unified with the P-channel type, but may be unified with the N-channel type. Further, a P-channel type and an N-channel type may be appropriately combined.
For example, when the transistors 121 to 125 are unified with the N-channel type, the data signal Vd (j) in the above-described embodiments and modifications may be supplied to each pixel circuit 110 with a positive / negative reversed potential. In this case, the sources and drains of the transistors 121 to 125 are in a relation reversed from that of the above-described embodiment and modification.
In the embodiment and the modification described above, the transistor 45 is a P-channel type and the transistor 43 is an N-channel type. However, the transistor 45 may be unified as a P-channel type or an N-channel type. The transistor 45 may be an N-channel type and the transistor 43 may be a P-channel type.
In the embodiment and the modification described above, each transistor is a MOS transistor, but may be a thin film transistor.

<Modification 10>
In the above-described embodiment and modification, an OLED that is a light-emitting element is illustrated as an electro-optical element.

<Application example>
Next, an electronic apparatus to which the electro-optical device 1 according to the embodiment and the application example is applied will be described. The electro-optical device 1 is suitable for high-definition display with small pixels. Therefore, a head mounted display will be described as an example of an electronic device.

FIG. 16 is a diagram showing the external appearance of the head-mounted display, and FIG. 17 is a diagram showing its optical configuration.
First, as shown in FIG. 16, the head mounted display 300 has a temple 310, a bridge 320, and lenses 301L and 301R in the same manner as general glasses. As shown in FIG. 17, the head mounted display 300 is in the vicinity of the bridge 320 and on the back side (lower side in the drawing) of the lenses 301L and 301R, the electrooptic device 1L for the left eye and the right eye. Electro-optical device 1R.
The image display surface of the electro-optical device 1L is disposed on the left side in FIG. Accordingly, the display image by the electro-optical device 1L is emitted in the direction of 9 o'clock in the drawing through the optical lens 302L. The half mirror 303L reflects the display image by the electro-optical device 1L in the 6 o'clock direction, and transmits light incident from the 12 o'clock direction.
The image display surface of the electro-optical device 1R is disposed on the right side opposite to the electro-optical device 1L. As a result, the display image by the electro-optical device 1R is emitted in the direction of 3 o'clock in the drawing through the optical lens 302R. The half mirror 303R reflects the display image by the electro-optical device 1R in the 6 o'clock direction, and transmits light incident from the 12 o'clock direction.

In this configuration, the wearer of the head mounted display 300 can observe the display image by the electro-optical devices 1L and 1R in a see-through state superimposed on the outside.
In the head-mounted display 300, when a left-eye image is displayed on the electro-optical device 1L and a right-eye image is displayed on the electro-optical device 1R among binocular images with parallax, The displayed image can be perceived as if it had a depth or a stereoscopic effect (3D display).

  In addition to the head mounted display 300, the electro-optical device 1 can be applied to an electronic viewfinder in a video camera, an interchangeable lens digital camera, or the like.

DESCRIPTION OF SYMBOLS 1 ... Electro-optical device, 2 ... Display panel, 3 ... Control circuit, 10 ... Data line drive circuit, 12 ... Scan line, 14 ... Data line, 16 ... Feed line, 20 ... Scan line drive circuit, 41, 44, 50 DESCRIPTION OF SYMBOLS ... Holding capacity, 100 ... Display part, 110 ... Pixel circuit, 121-125 ... Transistor, 130 ... OLED, 132 ... Holding capacity, 143, 144, 145 ... Control line, 150 ... Silicon substrate, LS ... Level shift circuit, DM ... demultiplexer.

Claims (9)

A light emitting element;
A feeder line;
A driving transistor for electrically connecting the light emitting element and the feeder line;
A first transistor comprising a first gate electrode and electrically connecting the light emitting element and the driving transistor;
A first wiring arranged to intersect the first gate electrode in plan view;
An insulating layer disposed between the first wiring and the first gate electrode;
A first contact hole formed in the insulating layer and electrically connecting the first gate electrode and the first wiring;
Equipped with a,
The electro-optical device, wherein the first contact hole overlaps the first gate electrode in plan view . A light emitting element;
A feeder line;
A driving transistor for electrically connecting the light emitting element and the feeder line;
A first transistor comprising a first gate electrode and electrically connecting the light emitting element and the driving transistor;
A first wiring arranged to intersect the first gate electrode in plan view;
An insulating layer disposed between the first wiring and the first gate electrode;
A first contact hole formed in the insulating layer and electrically connecting the first gate electrode and the first wiring;
A second transistor comprising a second gate electrode;
With
The first wiring, in a plan view, an electro-optical device, characterized in that intersects with the second gate electrode. The electro-optical device according to claim 2 , wherein the first contact hole overlaps the first gate electrode in a plan view. The first transistor includes a drain and a source disposed along a first direction,
The electro-optical device according to claim 1, wherein the first wiring extends along a second direction different from the first direction. A third transistor comprising a third gate electrode and electrically connecting the first terminal of the driving transistor and the gate electrode of the driving transistor;
A second wiring arranged to intersect the third gate electrode in plan view;
A second contact hole formed in the insulating layer and electrically connecting the third gate electrode and the second wiring;
The electro-optical device according to claim 1, wherein the electro-optical device is provided. A pixel circuit having a first transistor including a first gate electrode, a light emitting element, and a driving transistor for supplying a current to the light emitting element;
A wiring arranged crossing the first gate electrode in plan view;
An insulating layer disposed between the wiring and the first gate electrode;
A contact hole formed in the insulating layer and electrically connecting the first gate electrode and the wiring;
Equipped with a,
The contact hole overlaps the first gate electrode in plan view;
An electro-optical device. The first transistor includes a drain and a source disposed along a first direction,
The wiring extends along a second direction different from the first direction;
The electro-optical device according to claim 6. The pixel circuit includes a second transistor having a second gate electrode,
The electro-optical device according to claim 6 , wherein the wiring intersects the second gate electrode in plan view. An electronic apparatus comprising the electro-optical device according to claim 1 .

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