JP5929121B2 - Electro-optical device and electronic apparatus - Google Patents

Description

The present invention relates to an electro-optical device and an electronic apparatus that are effective when a pixel circuit is miniaturized, for example.

In recent years, various electro-optical devices using light emitting elements such as organic light emitting diode (hereinafter referred to as “OLED”) elements have been proposed. In this electro-optical device, a configuration in which a pixel circuit including the light emitting element, the transistor, and the like is provided corresponding to the pixel of the image to be displayed corresponding to the intersection of the scanning line and the data line. In such a configuration, when a data signal having a potential corresponding to the gray level of the pixel is applied to the gate of the transistor, the transistor supplies a current corresponding to the voltage between the gate and the source to the light emitting element. Accordingly, the light emitting element emits light with luminance according to the gradation level. At this time, if the characteristics such as the threshold voltage of the transistor vary from pixel circuit to pixel circuit, display unevenness that impairs the uniformity of the display screen occurs. For this reason, a technique for compensating the characteristics of a transistor has been proposed (see, for example, Patent Document 1).
In many cases, electro-optical devices are required to have a smaller display size and higher display definition. In order to achieve both a reduction in display size and an increase in display definition, it is necessary to miniaturize the pixel circuit. Therefore, a technique for providing an electro-optical device in, for example, a silicon integrated circuit has been proposed (for example, Patent Documents). 2).

JP 2007-316462 A JP 2009-288435 A

By the way, in the pixel circuit, there are various transistors in addition to the transistor that supplies current to the light emitting element. When the pixel circuit is miniaturized, the transistors are close to each other, so that capacitive coupling is facilitated. For this reason, noise generated in a certain transistor affects other transistors, and as a result, the display quality can be reduced.
The present invention has been made in view of the above-described circumstances, and one of its purposes is an electro-optic that can prevent deterioration in display quality even when a pixel circuit is miniaturized and transistors are brought close to each other. It is to provide an apparatus and an electronic device.

In order to achieve the above object, the electro-optical device according to the present invention has a pixel circuit provided corresponding to the intersection of the plurality of scanning lines and the plurality of data lines, and the pixel circuit is A first transistor that supplies a current according to a voltage between a gate and a source; a two-terminal light emitting element that emits light with a luminance according to a current supplied by the first transistor; the data line; A second transistor that is turned on or off between the gate of the transistor, a third transistor that is turned on or off between the gate and the drain of the first transistor, and a current supplied to the light emitting element by the first transistor A fourth transistor that is turned on or off along a path; a terminal on the first transistor side of two terminals of the light emitting element; and a predetermined reset. A fifth transistor that is turned on or off with respect to a first power supply line that supplies power to the first potential, and the first transistor and the light emitting element are connected in series between a high-order power source and a low-order power source. The region where the pixel circuit is formed includes a first region and a second region, and the first region, the second transistor, and the third transistor are disposed in the first region, The fourth transistor and the fifth transistor are arranged in two regions. According to the present invention, the first region including the first transistor is separated from the second region including the fourth transistor and the fifth transistor. For this reason, since the noise accompanying the on / off operation of the fourth transistor and the fifth transistor is difficult to be superimposed on the gate of the first transistor, it is possible to prevent display quality from being deteriorated.
Note that the first region and the second region preferably have a configuration in which the region where the pixel circuit is formed is divided along the row direction, which is the extending direction of the scanning lines.

In the present invention, a first storage capacitor having one end connected to the data line, a second storage capacitor having one end connected to the data line and the other end connected to the first power supply line, and the pixel circuit A driving circuit for driving, wherein the driving circuit electrically connects the data line and a second feeding line for feeding an initial potential in a first period, and connects the other end of the first storage capacitor to a predetermined amount. Electrically connecting a third power supply line for supplying a potential, and electrically disconnecting the data line and the second power supply line in a second period following the first period; The second transistor and the third transistor are turned on while maintaining the connection between the other end of the first power supply line and the third power supply line, and the other end of the first storage capacitor and the second storage capacitor are turned on in a third period following the second period. 3 is electrically disconnected from the feeder line, and a signal having a potential corresponding to the luminance is 1 is supplied to the other end of the storage capacitor, the second transistor is turned off at the end of the third period, the fourth transistor is turned on in the fourth period following the third period, and the third transistor is It is preferable that the third transistor is turned off by the end of the third period, and the fifth transistor is turned on for a part or all of the period from the start of the first period to the start of the fourth period. According to this configuration, the data line, the first storage capacitor, and the second storage capacitor are initialized in the first period. In the second period, the second transistor and the third
When each transistor is turned on, the data line and the gate of the first transistor are at a potential corresponding to the threshold voltage of the first transistor. In the third period, when a signal having a potential corresponding to luminance is supplied to the other end of the first storage capacitor while the second transistor is turned on, the data line and the gate of the first transistor are in accordance with the threshold voltage. The potential variation at the other end of the first storage capacitor is shifted from the potential by the amount divided by the capacitance ratio. For this reason, the potential range at the gate of the first transistor is narrower than the potential range at the other end of the first storage capacitor. Therefore, according to this configuration, a current to be supplied to the light emitting element can be supplied with high accuracy while compensating for the characteristics of the transistor while not requiring a data signal with fine accuracy.

In the present invention, a shield wiring may be provided between the first region and the second region, and the potential of the shield wiring may be fixed when no current flows through the light emitting element. According to this, it can suppress more reliably that the noise etc. which generate | occur | produced by one side of the 1st area | region and the 2nd area | region are propagated to the other side.
Here, either one of the power supplies may be supplied to the shield wiring, or the reset potential may be supplied. In any aspect, since the potential supplied to the separate pixel circuit is used, the configuration can be prevented from becoming complicated.
In the present invention, the first transistor and the fourth transistor may be connected to each other through a conductive wiring. According to this configuration, the resistance of the current path to the light emitting element can be reduced. As the conductive wiring, for example, aluminum alone or an aluminum alloy is preferable.
In addition to the electro-optical device, the present invention can be conceptualized as an electronic apparatus having the electro-optical device. Typically, electronic devices include head-mounted displays (
Display devices such as HMD) and electronic viewfinders.

1 is a perspective view illustrating a configuration of an electro-optical device according to an embodiment of the invention. 2 is a diagram illustrating an electrical configuration of the electro-optical device. FIG. 2 is a diagram showing an equivalent circuit of a pixel circuit in the same electro-optical device. FIG. It is a top view which shows the structure of the pixel circuit. It is a top view which shows the structure of the pixel circuit. It is a figure which shows the connection state of the pixel circuit. 6 is a timing chart showing the operation of the electro-optical device. FIG. 6 is an operation explanatory diagram of the same electro-optical device. FIG. 6 is an operation explanatory diagram of the same electro-optical device. FIG. 6 is an operation explanatory diagram of the same electro-optical device. FIG. 6 is an operation explanatory diagram of the same electro-optical device. It is a figure which shows the amplitude compression of the data signal in the same electro-optical apparatus. It is a figure which shows the characteristic of the transistor in the same electro-optical apparatus. It is a top view which shows the structure of the pixel circuit which concerns on an application and a modification. It is a top view which shows the structure of the pixel circuit which concerns on an application and a modification. It is a perspective view which shows HMD using the electro-optical apparatus which concerns on embodiment etc. FIG. It is a figure which shows the optical structure of HMD.

  Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.

FIG. 1 is a perspective view showing a configuration of an electro-optical device 10 according to an embodiment of the present invention.
The electro-optical device 10 is a micro display that displays an image on a head-mounted display, for example. Although details of the electro-optic device 10 will be described later, a plurality of pixel circuits, a drive circuit for driving the pixel circuits, and the like are formed on, for example, a silicon substrate.
The L device is an OLED which is an example of a light emitting element.
The electro-optical device 10 is housed in a frame-shaped case 72 that opens at the display unit, and the FP
One end of a C (Flexible Printed Circuits) substrate 74 is connected. A semiconductor chip control circuit 5 is mounted on the FPC board 74 by a COF (Chip On Film) technique, and a plurality of terminals 76 are provided to be connected to a higher-level circuit (not shown). Image data is supplied from the upper circuit via a plurality of terminals 76 in synchronization with the synchronization signal. The synchronization signal includes a vertical synchronization signal, a horizontal synchronization signal, and a dot clock signal. Further, the image data defines the gradation level of the pixel of the image to be displayed by, for example, 8 bits.
The control circuit 5 combines the functions of the power supply circuit and the data signal output circuit of the electro-optical device 10. Specifically, the control circuit 5 supplies various control signals and various potentials generated according to the synchronization signal to the electro-optical device 10, and converts digital image data into an analog data signal so that the electro-optical device 10. To supply.

FIG. 2 is a diagram illustrating a configuration of the electro-optical device 10 according to the first embodiment. As shown in this figure, the electro-optical device 10 is roughly divided into a scanning line driving circuit 20, a demultiplexer 30, a level shift circuit 40, and a display unit 100.
Among these, in the display unit 100, pixel circuits 110 corresponding to pixels of an image to be displayed are arranged in a matrix. Specifically, in the display unit 100, m rows of scanning lines 12 are provided so as to extend in the horizontal direction in the figure, and (3n) columns of data lines 14 grouped every three columns are vertically arranged in the figure. The scanning lines 12 extend in the direction and are electrically insulated from each other. A pixel circuit 110 is provided corresponding to the intersection of the m rows of scanning lines 12 and the (3n) columns of data lines 14. Therefore, in the present embodiment, the pixel circuit 110
Are arranged in a matrix with vertical m rows × horizontal (3n) columns.

Here, m and n are both natural numbers. In order to distinguish rows in the matrix of the scanning lines 12 and the pixel circuits 110, 1, 2, 3,... (M
-1), sometimes called m rows. Similarly, in order to distinguish the column of the matrix of the data line 14 and the pixel circuit 110, 1, 2, 3, ..., (3n-1) in order from the left in the figure.
, (3n) columns. In order to generalize and describe the group of data lines 14, when an integer j of 1 to n is used, the j-th group counted from the left has (3j−
2) The data line 14 of the column, the (3j-1) th column, and the (3j) th column belongs.
Note that the three pixel circuits 110 corresponding to the intersection of the scanning lines 12 in the same row and the three columns of data lines 14 belonging to the same group respectively have R (red), G (green), and B (blue) pixels. Correspondingly, these three pixels represent one dot of a color image to be displayed. That is, in the present embodiment, one dot color is expressed by additive color mixing by light emission of an OLED corresponding to RGB.

In the present embodiment, the power supply line 16 is provided along the data line 14 for each column.
Since each of the power supply lines 16 is supplied with a potential Vorst as a reset potential, the power supply line 1
6 functions as a first feeder. Further, a holding capacitor 50 is provided for each column. Specifically, one end of the storage capacitor 50 is connected to the data line 14 and the other end is connected to the power supply line 16.
For this reason, the storage capacitor 50 functions as a second storage capacitor.
Note that the storage capacitor 50 is preferably formed by sandwiching an insulator (dielectric) between the wiring configuring the data line 14 and the wiring configuring the feeder line 16. Further, although the storage capacitor 50 is provided outside the display unit 100 in FIG. 2, this is only an equivalent circuit and may be provided inside the display unit 100 or from the inside to the outside. Of course. Although omitted in FIG. 2, the capacity of the storage capacitor 50 is Cdt.

The following control signals are supplied to the electro-optical device 10 by the control circuit 5.
Specifically, the electro-optical device 10 includes a control signal Ctr for controlling the scanning line driving circuit 20 and control signals Sel (1), / Sel (1), for controlling selection in the demultiplexer 30. Sel (2
), / Sel (2), Sel (3), / Sel (3) and control signals / Gini, Gref, Gcpl, / Gcpl for controlling the level shift circuit 40 are supplied.
Note that the control signal Ctr actually includes a plurality of signals such as a pulse signal, a clock signal, and an enable signal. The control signals Sel (1) and / Sel (1) are in a logically inverted relationship with each other. Similarly, control signals Sel (2) and / Sel (2) and control signals Sel (3) and / Sel (
3) and the control signals Gcpl and / Gcpl are also in a logically inverted relationship with each other.

In the electro-optical device 10, the data signals Vd (1), Vd (2),..., Vd (n) correspond to the first, second,. Control circuit 5
Supplied by The maximum potential of the data signals Vd (1) to Vd (n) can be expressed as Vmax.
And the minimum value is Vmin.

The scanning line driving circuit 20 generates a scanning signal for sequentially scanning the scanning lines 12 for each row over a frame period in accordance with the control signal Ctr. Where 1, 2,
3,..., (M−1), and the scanning signals supplied to the m-th scanning line 12 are Gwr (1),
Gwr (2), Gwr (3), ..., Gwr (m-1), Gwr (m) are written.
In addition to the scanning signals Gwr (1) to Gwr (m), the scanning line driving circuit 20 generates various control signals synchronized with the scanning signals for each row and supplies them to the display unit 100. Illustration is omitted in FIG. The frame period is a period required for the electro-optical device 10 to display an image for one cut (frame). For example, if the frequency of the vertical synchronization signal included in the synchronization signal is 120 Hz, the first period is 1. This is a period of 8.3 milliseconds corresponding to the period.

The demultiplexer 30 is an aggregate of transmission gates 34 provided for each column, and sequentially supplies data signals to three columns constituting each group.
Here, the input terminals of the transmission gates 34 corresponding to the (3j-2) column, the (3j-1) column, and the (3j) column belonging to the jth group are connected in common to each other, and the data signals are respectively connected to the common terminals. Vd (j) is supplied.
The transmission gate 34 provided in the leftmost column (3j-2) in the j-th group has the control signal Sel (1) at the H level (when the control signal / Sel (1) is at the L level. ) Is turned on (conductive). Similarly, in the jth group is the center column (3
j-1) The transmission gate 34 provided in the column is turned on when the control signal Sel (2) is at the H level (when the control signal / Sel (2) is at the L level). The transmission gates 34 provided in the rightmost column (3j) are turned on when the control signal Sel (3) is at the H level (when the control signal / Sel (3) is at the L level).

The level shift circuit 40 includes holding capacitors 41 and 44, a transmission gate 42,
N-channel MOS transistor 43 and P-channel MOS transistor 45
For each column, after temporarily holding the data signal output from the output terminal of the transmission gate 34 of each column, the potential is shifted and supplied to the data line 14.
In each column, one end of the storage capacitor 44 is connected to the data line 14 and the transistor 45 in the corresponding column.
The other end of the storage capacitor 44 is connected to the output end of the transmission gate 34 and the source node of the transistor 43. For this reason, the storage capacitor 44 functions as a first storage capacitor having one end connected to the data line 14.
On the other hand, in each column, the input end of the transmission gate 42 is connected to the output end of the transmission gate 34, and the output end of the transmission gate 42 is connected to the other end of the storage capacitor 44.

In each column, the source node of the transistor 45 is commonly connected across the columns to a power supply line 61 serving as a second power supply line that supplies the potential Vini as an initial potential, and the control signal / Gini is shared across the columns to the gate node. To be supplied. For this reason, the transistor 45
Is configured such that the data line 14 and the power supply line 61 are electrically connected when the control signal / Gini is at the L level and electrically disconnected when the control signal / Gini is at the H level. .
In each column, the drain node of the transistor 43 is connected in common across the columns to a power supply line 62 as a third power supply line that supplies the potential Vref, and a control signal G is connected to the gate node.
ref is supplied in common across each column. For this reason, the transistor 43 includes a storage capacitor 4
4 is electrically connected when the control signal Gref is at the H level and electrically disconnected when the control signal Gref is at the L level. Yes.
In each column, the transmission gates 42 are simultaneously turned on when the control signal Gcpl is at the H level (when the control signal / Gcpl is at the L level).

Although omitted in FIG. 2, the capacity of the storage capacitor 44 is Crf1.
The other end of the storage capacitor 41 is grounded in common to a fixed potential, for example, the potential Vss. Note that the potential Vss corresponds to an L level of a scanning signal or a control signal that is a logic signal.
Although omitted in FIG. 2, the capacity of the storage capacitor 41 is Crf2.

In the present embodiment, the scanning line driving circuit 20, the demultiplexer 30 and the level shift circuit 40 are divided for convenience, but these can be collectively considered as a driving circuit for driving the pixel circuit 110. .

The electrical configuration of the pixel circuit 110 will be described with reference to FIG. FIG. 3 shows the pixel circuit 1
10 is a diagram showing an equivalent circuit of FIG. Since each pixel circuit 110 has the same configuration when viewed electrically, here, it is the i-th row and the leftmost column (3j-2) in the j-th group.
A description will be given by taking the pixel circuit 110 in the i-th row (3j-2) column located in the column as an example.
Note that FIG. 3 only shows an equivalent circuit of the pixel circuit 110 and does not reflect an actual circuit layout. Further, i is a symbol for generally indicating a row in which the pixel circuits 110 are arranged, and is an integer of 1 to m.

As shown in FIG. 3, the pixel circuit 110 includes a P-channel MOS transistor 12.
1 to 125, a storage capacitor 140, and an OLED 150. The pixel circuit 110 is supplied with a scanning signal Gwr (i), control signals Gel (i), Gcmp (i), and Gorst (i). Here, the scanning signal Gwr (i), the control signals Gel (i), Gcmp (i), and Gorst (i) are respectively supplied by the scanning line driving circuit 20 corresponding to the i-th row. Among these, the control signal Gel (i) is supplied via the control line 134, and similarly, the control signals Gcmp (i) and Gorst (i) are supplied via the control lines 133 and 135, respectively.
Note that the scanning signal Gwr (i), the control signals Gel (i), Gcmp (i), and Gorst (i) are supplied corresponding to the i-th row. (3j-2) It is also supplied in common to the pixel circuits in other columns than the column.

Now, in the transistor 122 in the pixel circuit 110 in the i-th row (3j-2) column, the gate node is connected to the scanning line 12 in the i-th row, and either the drain or the source node is in the (3j-2) -th column. And the other is connected to the gate node of the transistor 121, one end of the storage capacitor 140, and the drain node of the transistor 123. Here, the gate node of the transistor 121 is denoted by g to distinguish it from other nodes.
In the transistor 121, the source node is connected to the power supply line 116, and the drain node is connected to the source node of the transistor 123 and the source node of the transistor 124. Here, the power supply line 116 is supplied with a potential Vel that is higher in the power supply in the pixel circuit 110.
In the transistor 123, the gate node is connected to the control line 133 of the i-th row and the control signal Gcmp (i) is supplied.
In the transistor 124, the gate node is connected to the i-th control line 134 and the control signal Gel (i) is supplied, and the drain node is connected to the source node of the transistor 125 and the anode Ad of the OLED 150. Yes.
In the transistor 125, the gate node is connected to the control line 135 of the i-th row, the control signal Gorst (i) corresponding to the i-th row is supplied, and the drain node corresponds to the (3j-2) -th column. It is connected to the feeder line 16 and is kept at the potential Vorst.

Here, the transistor 121 corresponds to the first transistor, and the transistor 122
Corresponds to the second transistor, and the transistor 123 corresponds to the third transistor. The transistor 124 corresponds to a fourth transistor, and the transistor 125 corresponds to a fifth transistor.

The other end of the storage capacitor 140 is connected to the power supply line 116. Therefore, the storage capacitor 140 is
The voltage between the source and drain of the transistor 121 is held. Here, when the capacity of the storage capacitor 140 is expressed as Cpix, the capacity Cdt of the storage capacitor 50, the capacity Crf1 of the storage capacitor 44, and the capacity Cpix of the storage capacitor 140 are:
Cdt >> Crf1 >> Cpix
Is set to be
That is, Cdt is set to be larger than Crf1, and Cpix is set to be sufficiently smaller than Cdt and Crf1. Note that Crf2 is about the same as Crf1 or slightly smaller than Crf1. As the storage capacitor 140, a capacitor parasitic to the gate node g of the transistor 121 may be used, or a capacitor formed by sandwiching an insulating layer between different conductive layers in a silicon substrate may be used.

The anode Ad of the OLED 150 is a pixel electrode provided individually for each pixel circuit 110. On the other hand, the cathode Ct of the OLED 150 is a common electrode 118 that is common to all the pixel circuits 110 and is kept at the potential Vct that is the lower side of the power supply in the pixel circuit 110.
The OLED 150 is a two-terminal element in which a white organic EL layer is sandwiched between an anode Ad and a light-transmitting cathode Ct on the silicon substrate. A color filter corresponding to any of RGB is superimposed on the emission side (cathode side) of the OLED 150.
In such an OLED 150, when a current flows from the anode Ad to the cathode Ct,
The holes injected from the anode Ad and the electrons injected from the cathode Ct are recombined in the organic EL layer to generate excitons, and white light is generated. The white light generated at this time is transmitted through the cathode opposite to the silicon substrate (anode), and is colored by a color filter so as to be visually recognized by the viewer (top emission structure).

In the present embodiment, since the electro-optical device 10 is formed on a silicon substrate, the substrate potential of the transistors 121 to 125 is set to the potential Vel.

Here, a manufacturing process of the pixel circuit 110 will be briefly described.
First, after an island-shaped N well (N−) serving as a base of the transistors 121 to 125 is formed in a region where the pixel circuit 110 is to be formed on a P-type silicon substrate, a polycrystalline structure is formed via a gate insulating film. A silicon wiring or the like is patterned to form a gate wiring. Thereafter, a P-type diffusion layer (P +) serving as a source node or a drain node is formed by ion implantation using the gate wiring as a mask.
Thereafter, a conductive wiring layer (first wiring layer) such as aluminum or copper via the first interlayer insulating film.
Are patterned, and various wirings to be described later are provided as the first wiring. At this time, the source node or the drain node and the first wiring are connected through a contact hole that opens the first interlayer insulating film.
Subsequently, a conductive wiring layer (second wiring layer) such as aluminum or copper is similarly patterned through the second interlayer insulating film, and various wirings are provided as second wirings. At this time, the first
The wiring and the second wiring are connected via a contact hole that opens the second interlayer insulating film.
The rectangular pixel electrode is connected to the OLED 15 via the third interlayer insulating film and the light shielding layer.
Formed as zero anode Ad. The subsequent steps are as described above.

FIG. 4 is a plan view showing the arrangement of the transistors 121 to 125 when the pixel circuit 110 having the top emission structure is viewed in plan from the observation side, and the wiring is shown up to the gate wiring. FIG. 5 is a plan view showing a structure when various wirings of the first wiring layer and the second wiring layer are further added to FIG. FIG. 6 is an explanatory diagram showing the structure in FIG. 5 replaced with a circuit, which is the same as FIG. 3 in terms of circuit.

As shown in FIGS. 4 and 5, the region where the pixel circuit 110 is formed has a lower first region 110a and an upper second region along the horizontal direction (extending direction of the scanning line 12) in the drawing. Region 11
It is separated into 0b. Among these, in the first region 110a, the transistors 121 to 1 are included.
23, and transistors 124 and 125 are provided in the second region 110b.

As shown in FIG. 4, the transistor 121 has a rectangular shape that is long in the column direction in plan view, and a gate wiring 121 g that is formed on an island-shaped N well via an insulating film,
And two P-type diffusion layers (regions indicated by hatching in the drawing) formed using the gate wiring 121g as a mask. Of the two diffusion layers in the transistor 121, the lower side in the figure is the source node and the upper side is the drain node.

The transistors 122 and 123 are arranged on the right side of the transistor 121 in the figure,
The common island-shaped N-well has a rectangular shape elongated in the column direction in plan view. In the common N well of the transistors 122 and 123, gate wirings 122g and 12 separated from each other are provided.
3g is formed, and three P-type diffusion layers are formed using this as a mask. Of these three diffusion layers, the lower side in the figure is one of the drain or source node in the transistor 122, and the center is the common node between the other drain or source node in the transistor 122 and the drain node in the transistor 123, The upper side is a source node in the transistor 123.

As shown in FIG. 4, the transistor 124 has a rectangular shape that is long in the column direction in plan view, and is located at a point aligned with the transistors 122 and 123 in the column direction. A gate wiring 124g is formed in an island-shaped N well in the transistor 124, and two P-type diffusion layers are formed using this as a mask. Of the two diffusion layers, the lower side in the figure is a source node in the transistor 124 and the upper side is a drain node.
The transistor 125 is located on the left side of the transistor 124 in the figure and at a point aligned with the transistor 121 in the column direction. A gate wiring 125g is formed in the island-shaped N well in the transistor 125, and this is used as a mask to form two P
A mold diffusion layer is formed. Of the two diffusion layers, the lower side is the transistor 12 in the figure.
5 is a drain node, and the upper side is a source node.

After the first interlayer insulating film is provided for the transistors 121 to 125 thus provided, the first wiring layer is patterned, and the scanning lines 12 and the wirings 8 as shown in FIG.
1 to 86, a power supply line 116, a wiring 116b, and control lines 133 to 135 are provided as the first wiring. Among these, the scanning line 12, the feeding line 116, and the control lines 133 to 135 are provided so as to extend in the row direction as described above.
The scanning line 12 passes through the upper surface side (the front side in the drawing) of the gate wiring 122g. The scanning line 12 is connected to the gate wiring 122g through a contact hole (□ in the figure) 12f that opens the first interlayer insulating film. The control line 133 passes through the upper surface side of the gate wiring 123g and is connected to the gate wiring 123g through the contact hole 133f.
The power supply line 116 is provided so as to include a boundary between the first region 110a and the second region 110b. The control lines 134 and 135 both pass through the upper surface side of the gate wirings 124g and 125g. Among these, the control line 134 is connected to the gate wiring 1 through the contact hole 134f.
The control line 135 is connected to the gate line 125 through the contact hole 135f.
connected to g.

The wiring 81 connects the data line 14 and one of the drain and source nodes in the transistor 122.
The wiring 82 connects the other node of the drain or source node in the transistor 122 and the common node of the drain node in the transistor 123 to the gate wiring 121g in the transistor 121 through the contact hole 82f. The wiring 82 is
It is wide on the upper surface side of the gate wiring 121 g and constitutes one of the pair of electrodes in the storage capacitor 140.
The wiring 83 connects the drain node in the transistor 121 and the source node in the transistor 123.
The wiring 84 is a relay electrode for connecting the source node in the transistor 124 to the wiring 91 of the second wiring layer described later. The wiring 85 connects the drain node in the transistor 125 and the power supply line 16. The wiring 86 connects the drain node in the transistor 124, the source node in the transistor 125, and the anode Ad in the OLED 150 (not shown in FIG. 5).
The wiring 116b is a relay wiring for connecting the source node in the transistor 121 to the power supply line 116 via the wiring 116a of the second wiring layer described later.

Subsequently, after the second interlayer insulating film is provided, the second wiring layer is patterned, and the data line 14, the feeder line 16, and the wirings 91 and 116a are provided as the second wiring as shown in FIG. .
The data line 14 and the power supply line 16 are provided so as to extend in the column direction. The data line 14 is located on the right side of the transistors 122, 123, and 124 in plan view, and is connected to the wiring 81 through a contact hole 14f that opens the second interlayer insulating film. As a result, the data line 14 is connected to one of the drain and source nodes of the transistor 122 via the wiring 81.
The feeder line 16 includes the transistors 122, 123, and 124 in the plan view and the transistor 1
21 and 125, and is connected to the wiring 85 through the contact hole 16f.
As a result, the feeder line 16 is connected to the drain node of the transistor 125 via the wiring 85.

On the other hand, the wiring 116a is provided on the left side of the transistor 121 in plan view, and the control line 13
3 and the scanning line 12, the power supply line 116 is connected to the contact hole 116e, and the wiring 116b is connected to the wiring line 116b. Wiring 116
a has a region overlapping the wiring 82 in plan view, and constitutes the other of the pair of electrodes in the storage capacitor 140. Thus, the storage capacitor 140 has a configuration in which the second interlayer insulating film is sandwiched between the wiring 82 and the wiring 116a. In addition, the power supply line 116 is connected to the source node in the transistor 121 through the wirings 116a and 116b.
The wiring 91 connects the wirings 83 and 84 in a state of straddling the power supply line 116.

As described above, in the pixel circuit 110, the first region 110a and the second region 110b are separated by the power supply line 116 having a fixed potential. A drain node in the transistor 121, a drain node in the transistor 123, and a source node in the transistor 124 are connected to each other by wirings 83, 84, and 91. On the other hand, the gate node g of the transistor 121 has a configuration in which the left side in the figure is shielded by the wiring 116 a and the right side is shielded by the feeder line 16.

<Operation of First Embodiment>
The operation of the electro-optical device 10 will be described with reference to FIG. FIG. 7 shows the electro-optical device 10.
6 is a timing chart for explaining the operation of each part in FIG.
As shown in this figure, the scanning signals Gwr (1) to Gwr (m) are sequentially switched to the L level, and the scanning lines 12 in the 1st to m-th rows in one frame period are in one horizontal scanning period (H). Scanned sequentially.
The operation in one horizontal scanning period (H) is common to the pixel circuits 110 in each row. Therefore, in the following, the operation will be described focusing on the pixel circuit 110 in the i-th row (3j-2) column in the scanning period in which the i-th row is horizontally scanned.

In this embodiment, the scanning period of the i-th row is roughly classified into an initialization period shown in FIG. 7B, a compensation period shown in FIG. 7C, and a writing period shown in FIG. Divided. Then, after the writing period of (d), the light emission period shown in (a) is reached, and the scanning period of the i-th row is reached again after the elapse of one frame period. Therefore, in the order of time, a cycle of (light emission period) → initialization period → compensation period → writing period → (light emission period) is repeated.
In FIG. 7, the scanning signal Gwr (i) corresponding to the (i−1) th row before the i-th row.
-1), the control signals Gel (i-1), Gcmp (i-1), and Gorst (i-1), the scanning signal Gwr (i) and the control signal Gel (i) corresponding to the i-th row. , Gcmp (i) and Gorst (i) are temporally preceded by one horizontal scanning period (H).

<Light emission period>
For convenience of explanation, the light emission period which is the premise of the initialization period will be described. As shown in FIG. 7, in the light emission period of the i-th row, the scanning signal Gwr (i) is at the H level, and the control signals Gel (i), Gcmp (i), and Gorst (i) that are logic signals. Among them, the control signal Gel (i) is at the L level, and the control signals Gcmp (i) and Gorst (i) are at the H level.
For this reason, as shown in FIG. 8, in the pixel circuit 110 in the i row (3j-2) column, the transistor 124 is turned on, while the transistors 122, 123, and 125 are turned off. Therefore, the transistor 121 has a current Ids corresponding to the gate-source voltage Vgs.
Is supplied to the OLED 150. As will be described later, in this embodiment, the voltage V during the light emission period
gs is a value obtained by level shifting from the threshold voltage of the transistor 121 according to the potential of the data signal. Therefore, a current corresponding to the gradation level is supplied to the OLED 150 in a state where the threshold voltage of the transistor 121 is compensated.

Note that since the light emission period of the i-th row is a period during which horizontal scanning is performed except for the i-th row, the data line 1
The potential of 4 varies as appropriate. However, in the pixel circuit 110 in the i-th row, since the transistor 122 is off, the potential fluctuation of the data line 14 is not considered here. Further, in FIG. 8, paths that are important in the explanation of the operation are indicated by bold lines (the following FIGS. 9 to 11).
The same applies to the above).

<Initialization period>
Next, when the scanning period of the i-th row is reached, first, the initialization period (b) is started as the first period. In the initialization period, the control signal Gel (i) is at the H level compared to the light emission period, and the control signal Gors
t (i) changes to L level.
Therefore, as shown in FIG. 9, in the pixel circuit 110 in the i row (3j-2) column, the transistor 124 is turned off and the transistor 125 is turned on. OLED
The path of the current supplied to 150 is interrupted, and the anode Ad of the OLED 150 is reset to the potential Vorst.
Since the OLED 150 has a configuration in which the organic EL layer is sandwiched between the anode Ad and the cathode Ct as described above, the capacitance Coled is parasitic between the anode Ad and the cathode Ct in parallel as shown by a broken line in the drawing. . When a current flows through the OLED 150 during the light emission period, the voltage between the anode and the cathode of the OLED 150 is held by the capacitor Coled. This holding voltage is reset by turning on the transistor 125.
For this reason, in this embodiment, when a current flows again through the OLED 150 in a later light emission period, it is less likely to be affected by the voltage held by the capacitor Coled.

Specifically, for example, when switching from a high-brightness display state to a low-brightness display state, if the configuration does not reset, the high voltage when the luminance is high (a large current flows) is retained. In addition, even if a small current is applied, an excessive current flows and the display state with low luminance cannot be achieved. On the other hand, in this embodiment, the potential of the anode Ad of the OLED 150 is reset by turning on the transistor 125, so that the reproducibility on the low luminance side is improved.
In the present embodiment, the potential Vorst and the common electrode 118 are the same as the potential Vorst.
Is set so that the difference from the potential Vct is lower than the light emission threshold voltage of the OLED 150. Therefore, in the initialization period (compensation period and writing period described below), the OLED 150 is in an off (non-light emitting) state.

On the other hand, in the initialization period, the control signal / Gini becomes L level, the control signal Gref becomes H level, and the control signal Gcpl becomes L level. For this reason, in the level shift circuit 40, as shown in FIG. 9, the transistors 45 and 43 are turned on, and the transmission gate 42 is turned off. Therefore, the data line 14 that is one end of the storage capacitor 44 is initialized to the potential Vini, and the node h that is the other end of the storage capacitor 44 is initialized to the potential Vref.
Here, for the potential Vini, (Vel−Vini) is the threshold voltage of the transistor 121 |
It is set to be larger than Vth |. Note that since the transistor 121 is a P-channel type, the threshold voltage Vth with respect to the potential of the source node is negative. Therefore, in order to avoid confusion in the description of the height relationship, the threshold voltage is expressed by the absolute value | Vth | and defined by the magnitude relationship.
Further, the potential Vref is set to such a value that the potential of the node h rises and changes in the subsequent writing period with respect to the potential that the data signals Vd (1) to Vd (n) can take, for example, from the minimum value Vmin. Is set to be low.

The control circuit 5 supplies a data signal over the initialization period and the compensation period. That is, in the j-th group, the control circuit 5 sequentially outputs the data signal Vd (j) in i rows (3
While switching to the potential corresponding to the gradation level of the pixels in the j-2) column, i row (3j-1) column, i row (3j) column, the control signal Sel (1) , Sel (2), Sel
Set (3) to the H level exclusively in order. As a result, in the demultiplexer 30, the transmission gates 34 are turned on in the order of the left end column, the center column, and the right end column in each group.
When the transmission gate 34 in the leftmost column belonging to the jth group is turned on by the control signal Sel (1) in the initialization period, the data signal Vd (j) is stored in the storage capacitor 41 as shown in FIG. Therefore, the data signal is held by the holding capacitor 41.

<Compensation period>
In the i-th scanning period, the second period is the compensation period (c). In the compensation period, the scanning signal Gwr (i) and the control signal Gcmp (i) are at the L level as compared with the initialization period. On the other hand, in the compensation period, the control signal / Gini becomes H level while the control signal Gref is maintained at H level.
Therefore, as shown in FIG. 10, in the pixel circuit 110 in the i row (3j−2) column, the transistor 122 is turned on, and the gate node g is electrically connected to the data line 14.
When the transistor 123 is turned on, the transistor 121 is diode-connected.
Therefore, the current is fed from the power supply line 116 → the transistor 121 → the transistor 123 →
Since the transistor 122 → (3j−2) -th column data line 14 flows, the gate node g rises from the potential Vini. However, since the current flowing through the path becomes difficult to flow as the gate node g approaches the potential (Vel− | Vth |), the data line 14 and the gate node g have the potential (Vel−) until the end of the compensation period. | Vth |).
Therefore, the storage capacitor 140 holds the threshold voltage | Vth | of the transistor 121 until the end of the compensation period.

On the other hand, in the level shift circuit 40, the control signal / Gini becomes the H level while the control signal Gref is maintained at the H level. Therefore, in the level shift circuit 40, the node h is fixed at the potential Vref.
In the compensation period, when the transmission gate 34 in the leftmost column belonging to the j-th group is turned on by the control signal Sel (1), the data signal Vd (j) is held by the holding capacitor 41 as shown in FIG. Is done.

If the transmission gate 34 in the leftmost column belonging to the j-th group is already turned on by the control signal Sel (1) in the initialization period, the transmission gate 34 is not turned on in the compensation period. There is no change in that the data signal Vd (j) is held at 41.
When the compensation period ends, the control signal Gcmp (i) becomes H level, so that the diode connection of the transistor 121 is released.

The control signal Gre is between the end of the compensation period and the start of the next writing period.
Since f becomes L level, the transistor 43 is turned off. Therefore, although the path from the data line 14 in the (3j-2) column to the gate node g in the pixel circuit 110 in the i row (3j-2) column is in a floating state, the potential of the path is Holding capacity 50,
140 maintains (Vel− | Vth |).

<Writing period>
In the i-th scanning period, the third period is the writing period (c) after the compensation period. In the writing period, the control signal Gcmp (i) is at the H level, while in the compensation period, the control signal / Gini is at the H level (the control signal / Gcpl is at the L level) while the control signal Gref is at the L level. ).
Therefore, as shown in FIG. 11, in the level shift circuit 40, the transmission gate 42 is turned on, so that the data signal held in the holding capacitor 41 is supplied to the node h that is the other end of the holding capacitor 44. That is, a signal having a potential corresponding to the luminance of the OLED 150 is supplied to the node h. For this reason, the node h shifts from the potential Vref in the compensation period. At this time, the potential change of the node h is ΔV, and the potential after the change is (Vref +
It will be expressed as ΔV).

On the other hand, since the gate node g is connected to one end of the storage capacitor 44 via the data line 14, the capacitance ratio k2 is changed from the potential (Vel− | Vth |) in the compensation period to the potential change ΔV of the node h. The value is shifted in the direction of increasing by the multiplied value. That is, the potential of the gate node g is a value (Vel− | Vth) shifted upward from the potential (Vel− | Vth |) in the compensation period by a value obtained by multiplying the potential change ΔV of the node h by the capacitance ratio k2. | + K 2 · ΔV). When this is expressed as an absolute value by the voltage Vgs of the transistor 121, it becomes a value (| Vth | −k 2 · ΔV) obtained by subtracting the threshold voltage | Vth |
The capacity ratio k2 is a capacity ratio of Cdt, Crf1, and Crf2. Strictly speaking, the capacitance Cpix of the storage capacitor 140 must be taken into consideration, but the capacitance Cpix is determined by the capacitances Cdt, Crf1, Crf2.
Since it is set to be sufficiently small compared to, it is ignored.

FIG. 12 is a diagram showing the relationship between the potential of the data signal and the potential of the gate node g in the writing period. As described above, the data signal supplied from the control circuit 5 can take a potential range from the minimum value Vmin to the maximum value Vmax according to the gradation level of the pixel. In this embodiment, the data signal is not directly written to the gate node g, but is level-shifted and written to the gate notebook g as shown in the figure.
At this time, the potential range ΔVgate of the gate node g is equal to the potential range ΔVdata (=
Vmax−Vmin) is multiplied by a capacity ratio k2.
In addition, the potential Vp (= Vel− | Vth |) and Vref can determine how much the potential range ΔVgate of the gate node g is shifted with respect to the potential range ΔVdata of the data signal. This is because the potential range ΔVdata of the data signal is compressed with the capacitance ratio k2 with respect to the potential Vref, and the compression range shifted with reference to the potential Vp becomes the potential range ΔVgate of the gate node g. Because.

Thus, in the writing period of the i-th row, the gate node g of the pixel circuit 110 in the i-th row has a capacitance ratio k from the potential (Vel− | Vth |) in the compensation period to the potential change ΔV of the node h.
A potential (Vel− | Vth | + k 2 · ΔV) shifted by an amount corresponding to 2 is written.
Eventually, the scanning signal Gwr (i) becomes H level, and the transistor 122 is turned off. Thus, the writing period ends, and the potential of the gate node g is fixed to the shifted value.

<Light emission period>
In the present embodiment, after the end of the writing period of the i-th row, the light emission period is reached as the fourth period after one horizontal scanning period (H) has elapsed. In this light emission period, the control signal Gel (i) is L as described above.
Therefore, in the pixel circuit 110 in the i row (3j-2) column, the transistor 1
24 turns on. Since the voltage Vgs between the gate and the source is (| Vth | −k 2 · ΔV), the current corresponding to the gray level in the OLED 150 is the threshold voltage of the transistor 121 as shown in FIG. It will be supplied in a compensated state.
Such an operation is also executed in parallel in time in other pixel circuits 110 in the i row other than the pixel circuit 110 in the (3j-2) th column in the scanning period of the i row. Further, such an operation of the i-th row is actually performed in the period of one frame, 1, 2, 3,.
), Executed in the order of the m-th row, and repeated for each frame.

According to the present embodiment, the potential range ΔVgate at the gate node g is narrowed with respect to the potential range ΔVdata of the data signal, so that the voltage reflecting the gradation level can be applied to the transistor 121 without engraving the data signal with fine accuracy. Can be applied between the gate and the source. For this reason, even in the case where the minute current flowing through the OLED 150 changes relatively greatly with respect to the change in the gate-source voltage Vgs of the transistor 121 in the fine pixel circuit 110, the current supplied to the OLED 150 is accurately controlled. It becomes possible to do.

Further, as indicated by a broken line in FIG. 3, a capacitance Cprs is actually parasitic between the data line 14 and the gate node g in the pixel circuit 110. For this reason, if the potential change width of the data line 14 is large, it propagates to the gate node g through the capacitor Cprs, and so-called crosstalk or unevenness occurs, thereby degrading the display quality. The influence of the capacitance Cprs is noticeable when the pixel circuit 110 is miniaturized.
On the other hand, in the present embodiment, the potential change range of the data line 14 is also narrowed with respect to the potential range ΔVdata of the data signal, so that the influence via the capacitor Cprs can be suppressed.

According to this embodiment, the period during which the transistor 125 is turned on, that is, the OLED 15
Since a period longer than the scanning period, for example, two horizontal scanning periods can be secured as the reset period of 0, the voltage held in the parasitic capacitance of the OLED 150 in the light emitting period can be sufficiently initialized.

Further, according to the present embodiment, the current Ids supplied to the OLED 150 by the transistor 121 cancels the influence of the threshold voltage. For this reason, according to the present embodiment, even if the threshold voltage of the transistor 121 varies from pixel circuit 110 to pixel circuit 110, the variation is compensated and a current corresponding to the gradation level is supplied to the OLED 150. As a result of suppressing the occurrence of display unevenness that impairs uniformity, high-quality display is possible.

This cancellation will be described with reference to FIG. As shown in this figure, the transistor 121 operates in a weak inversion region (subthreshold region) in order to control a minute current supplied to the OLED 150.
In the figure, A is a transistor having a large threshold voltage | Vth |, and B is a threshold voltage | Vth |.
Each shows a transistor with a small. In FIG. 13, the gate-source voltage Vgs is the difference between the characteristic indicated by the solid line and the potential Vel. In FIG. 13, the current on the vertical scale is shown as a logarithm with the direction from the source to the drain being positive (upper).
In the compensation period, the gate node g changes from the potential Vini to the potential (Vel− | Vth |).
Therefore, the transistor A having a large threshold voltage | Vth | moves from S to Aa while the transistor B having a small threshold voltage | Vth | moves from S to Ba.
Next, when the potential of the data signal to the pixel circuit 110 to which the two transistors belong is the same, that is, when the same gradation level is designated, the potential shift amount from the operating points Aa and Ba is Are the same k 2 · ΔV. Therefore, for transistor A, the operating point moves from Aa to Ab, and for transistor B, the operating point changes from Ba to Bb.
However, the currents at the operating point after the potential shift are aligned at substantially the same Ids in both the transistors A and B.
Thus, according to the present embodiment, the threshold voltage of the transistor 121 is set to the pixel circuit 110.
Even if there is variation every time, the variation is compensated.

Further, according to the present embodiment, the data signal supplied from the control circuit 5 is once held in the holding capacitor 41 from the initialization period to the compensation period, and then the holding potential is level-shifted in the writing period. Supply to the data line 14 above. For this reason, from the viewpoint of the control circuit 5, the data signal may be supplied over a relatively long period from the initialization period to the compensation period, not the writing period. it can.

By the way, the drain node in the transistor 121, the drain node in the transistor 123, and the source node in the transistor 124 are electrically connected to each other. For this reason, the transistors 121, 124, and 125 may have a configuration in which the N-well region and the P-type diffusion layer are partially used like the transistors 122 and 123.
However, in this embodiment, as shown in FIG. 4 or FIG. 5, the pixel circuit 110 is divided into a first region 110a and a second region 110b, and transistors 121 to 123 are provided in the first region 110a. Transistors 124 and 125 in two regions 110b
Is provided. For this reason, the transistor 121 and the transistors 124 and 125 are separated in regions. This is due to the following reason.

That is, in the i-th row, when the light emission period (a) is reached, the control signal Gel (i) changes to L level, the transistor 124 is turned on, and the control signal Gorst (i) becomes H level. The transistor 125 is turned off. When noise associated with this on / off operation (change in the potential of the control signal) is superimposed on the gate node g in the transistor 121, it will fluctuate from the potential during the writing period of (d), and the display quality will deteriorate. Resulting in.
In the present embodiment, the first region 110a including the transistor 121 is the transistor 1
It is separated from the second region 110 b including 24 and 125. For this reason, transistor 1
The noise accompanying the on / off operation of 24 and 125 is not easily superimposed on the gate node g in the transistor 121.

On the other hand, in the writing period (d), the writing path from the data line 14 to the gate node g is limited to the range of the first region 110a. Therefore, when viewed from the transistors 124 and 125, the influence of the electric field fluctuation in the first region 110a in the writing period is reduced.
The anode Ad (the source node of the transistor 125 and the drain node of the transistor 124) has a potential Vorst from the initialization period (b) to the writing period (d).
However, if the potential Vorst varies due to noise or the like, threshold compensation and data writing to the gate node g cannot be performed accurately.
According to the present embodiment, since the transistors 124 and 125 including the anode Ad are separated from the first region 110a including the transistor 121, the transistors 124 and 125 are not easily affected by noise or the like generated in the first region 110a. For this reason, threshold compensation and data writing can be executed more accurately as compared with a configuration in which separation is not performed.

Further, in the present embodiment, a fixed potential feeder 116 is disposed between the first region 110a and the second region 110b. For this reason, the effect that the influence of the noise and electric field fluctuation from one side to the other of the first region 110a and the second region 110b can be expected.

From the drain node of the transistor 121 to the source node of the transistor 124 is a part of the current path to the OLED 150. Here, the transistors 121 and 124
When a part of the structure is used, the resistance loss particularly in the diffusion layer portion increases. Therefore, in the present embodiment, from the drain node of the transistor 121 provided in the first region 110a to the source node of the transistor 124 provided in the second region 110b,
The wirings 83 and 84 as the first wiring that is the conductive wiring layer and the wiring 91 as the second wiring that is also the conductive wiring layer are connected. In the configuration in which the wirings 83, 84, and 91 are connected, the transistor 121,
Compared with the configuration in which 124 is partially used, the resistance from the drain node of the transistor 121 to the source node of the transistor 124 can be reduced.
In the embodiment, the transistor 124 is arranged on the right side and the transistor 125 is arranged on the left side in the second region 110b. However, even if the transistor 124 is arranged on the same left side as the transistor 121, the current path is made almost straight. good.

<Application and modification>
The present invention is not limited to the above-described embodiments and application examples, and various modifications as described below are possible. Moreover, the aspect of the deformation | transformation described below can also combine suitably arbitrarily selected 1 or several.

<Boundary between first area and second area>
In the embodiment, the power supply line 116 as the shield wiring is arranged at the boundary between the first region 110a and the second region 110b. However, if a wiring for supplying some fixed potential is provided, the shield It can function as wiring. For this reason, as shown in FIG. 14, for example, the wiring 16a may be provided so as to include the boundary, and the wiring 16a may function as a shield wiring as a configuration for supplying the potential Vorst.
Here, the wiring 16a is formed so as to extend in the row direction, and is connected to the power supply line 16 through a contact hole 16e that opens the second interlayer insulating film. For this reason, the electric potential Vorst is supplied by a mesh-like wiring of the power supply line 16 extending in the column direction and the wiring 16a extending in the row direction. The wiring 16a may have a strip shape.
The feeder line 116 is located below the first region 110 a in the drawing, and a portion branched from the feeder line 116 is connected to the source node of the transistor 121. Also, the wiring 11
Reference numeral 6c denotes a pattern of the second wiring layer. One end of the second wiring layer is connected to the source node of the transistor 121, and the other end straddles the scanning line 12 and overlaps the wiring 82 in plan view. That is, in the example of FIG. 14, the storage capacitor 140 includes the wiring 82 and the wiring 116c as the second
In this configuration, an interlayer insulating film is sandwiched.

In addition, there is a considerable parasitic capacitance between the gate and drain of the transistor 121. Therefore, in the i-th row, even when the control signal Gel (i) is at the H level and the transistor 124 is turned off (when no current flows through the OLED 150),
The drain node of the transistor 121 is maintained by the parasitic capacitance at a potential when a current flows during the light emission period.
Therefore, as shown in FIG. 15, the wiring 83 connected to the drain node of the transistor 121 can be provided without providing the power supply line 116 and the wiring 16 a at the boundary between the first region 110 a and the second region 110 b. It can function as shield wiring.

For the storage capacitor 140, the wiring 82 of the first wiring layer and the wiring 116 of the second wiring layer are used.
The first interlayer insulation is not limited to the configuration in which the second interlayer insulating film is sandwiched between a (116c) and the diffusion layer serving as the source node of the transistor 121 is enlarged and the diffusion layer and the wiring composed of the first wiring layer are used. It is good also as a structure which clamps a film | membrane.

<Control circuit>
In the embodiment, the control circuit 5 that supplies the data signal is separated from the electro-optical device 10. However, the control circuit 5 also includes a silicon substrate along with the scanning line driving circuit 20, the demultiplexer 30, and the level shift circuit 40. It may be integrated in.

<Board>
In the embodiment, the electro-optical device 10 is integrated on the silicon substrate. However, the electro-optical device 10 may be integrated on another semiconductor substrate. Further, it may be formed on a glass substrate or the like by applying a polysilicon process. In any case, it is effective for a configuration in which the pixel circuit 110 is miniaturized.

<Control signal Gcmp (i)>
In the embodiment and the like, in the i-th row, the control signal Gcmp (i) is set to the H level in the writing period, but may be set to the L level. That is, the threshold compensation by turning on the transistor 123 and the writing to the node gate g may be executed in parallel.

<Demultiplexer>
In the embodiment and the like, the data lines 14 are grouped every three columns, and the data lines 14 are sequentially selected in each group to supply data signals. However, the number of data lines constituting the group is as follows. "2" may be sufficient and "4" or more may be sufficient.
Further, a configuration may be adopted in which data signals are supplied to the data lines 14 of each column all at once without grouping, that is, without using the demultiplexer 30.

<Transistor channel type>
In the above-described embodiment, the transistors 121 to 125 in the pixel circuit 110 are connected to P.
The channel type is unified, but the N channel type may be unified. Also, P channel type and N
The channel types may be combined as appropriate.

<Others>
In the embodiments and the like, an OLED that is a light emitting element is illustrated as an electro-optical element, but any light emitting element may be used as long as it emits light with a luminance according to current, such as an inorganic light emitting diode or LED (Light Emitting Diode).

<Electronic equipment>
Next, an electronic apparatus to which the electro-optical device 10 according to the embodiment and the application example is applied will be described. The electro-optical device 10 is suitable for high-definition display with small pixels. there,
As an electronic apparatus, a head mounted display will be described as an example.

FIG. 16 is a diagram showing the external appearance of the head-mounted display, and FIG. 17 is a diagram showing its optical configuration.
First, as shown in FIG. 16, the head mounted display 300 is similar in appearance to general glasses, such as a temple 310, a bridge 320, lenses 301 </ b> L and 301 </ b> R.
Have Further, as shown in FIG. 17, the head mounted display 300 is in the vicinity of the bridge 320 and on the back side (lower side in the drawing) of the lenses 301L and 301R, the electro-optical device 10L for the left eye and the right eye. Electro-optical device 10R.
The image display surface of the electro-optical device 10L is arranged on the left side in FIG.
Accordingly, the display image by the electro-optical device 10L is emitted in the direction of 9 o'clock in the drawing through the optical lens 302L. The half mirror 303L reflects the display image from the electro-optical device 10L in the 6 o'clock direction, and transmits light incident from the 12 o'clock direction.
The image display surface of the electro-optical device 10R is disposed on the right side opposite to the electro-optical device 10L. As a result, a display image by the electro-optical device 10R is displayed on the optical lens 302R.
Through 3 o'clock in the figure. The half mirror 303R is the electro-optical device 10
While the display image by R is reflected in the 6 o'clock direction, light incident from the 12 o'clock direction is transmitted.

In this configuration, the wearer of the head mounted display 300 is able to perform the electro-optical device 1.
Display images by 0L and 10R can be observed in a see-through state superimposed on the outside.
In the head-mounted display 300, when a left-eye image is displayed on the electro-optical device 10L and a right-eye image is displayed on the electro-optical device 10R among binocular images with parallax, The displayed image can be perceived as if it had a depth or a stereoscopic effect (3D display).

The electro-optical device 10 can be applied to an electronic viewfinder in a video camera, an interchangeable lens digital camera, etc. in addition to the head mounted display 300.

DESCRIPTION OF SYMBOLS 10 ... Electro-optical apparatus, 12 ... Scanning line, 14 ... Data line, 16 ... Feeding line, 20 ... Scanning line drive circuit, 30 ... Demultiplexer, 40 ... Level shift circuit, 41, 44, 50 ... Retention capacity, 100 ... Display unit 110... Pixel circuit 110 a first region 110 b second region 11
6 ... feeder line, 118 ... common electrode, 121-125 ... transistor, 140 ... holding capacity,
150 ... OLED, 300 ... head-mounted display.

Claims (5)

And a pixel circuits provided corresponding to intersections of a plurality of scanning lines and a plurality of data lines,
The pixel circuit includes:
A first transistor for supplying a current according to a voltage between the gate and the source;
A two-terminal type light emitting element that emits light at a luminance corresponding to the current supplied by the first transistor;
A second transistor that is turned on or off between the data line and the gate of the first transistor;
A third transistor that is turned on or off between a gate and a drain of the first transistor;
A fourth transistor which is turned on or off in the path of current supplied to the light emitting element by the first transistor,
Of the two terminals of the light emitting element, a fifth transistor that is turned on or off between a terminal on the first transistor side and a first feeder that feeds a predetermined reset potential;
Including
The first transistor and the light emitting element are connected in series between a high-order power supply and a low-order power supply,
The region where the pixel circuit is formed includes a first region and a second region,
In the first region, the first transistor, the second transistor, and the third transistor are disposed,
The fourth transistor and the fifth transistor are disposed in the second region ,
A shield wiring is provided between the first region and the second region;
When no current flows through the light emitting element, the potential of the shield wiring is fixed,
The electro-optical device , wherein the shield wiring is supplied with the reset potential . A first storage capacitor having one end connected to the data line;
A second storage capacitor having one end connected to the data line and the other end connected to the first power feed line;
A driving circuit for driving the pixel circuit;
The drive circuit is
In the first period,
Electrically connecting the data line and a second power supply line for supplying an initial potential; electrically connecting the other end of the first storage capacitor and a third power supply line for supplying a predetermined potential;
In a second period following the first period,
The data line and the second power supply line are electrically disconnected, and the second transistor and the third transistor are connected in a state where the other end of the first storage capacitor and the third power supply line are electrically connected. Turn on
In a third period following the second period,
Electrically connecting the other end of the first storage capacitor and the third feeder to the other end of the first storage capacitor with a signal having a potential corresponding to the luminance;
Turning off the second transistor at the end of the third period;
Turning on the fourth transistor in a fourth period following the third period;
Turning off the third transistor by the end of the third period;
2. The electro-optical device according to claim 1, wherein the fifth transistor is turned on during a part or all of a period from the start of the first period to the start of the fourth period. Wherein the first transistor and the fourth transistor, the electro-optical device according to claim 1 or claim 2 through a conductive wire, characterized in that connected to each other. And a pixel circuits provided corresponding to intersections of a plurality of scanning lines and a plurality of data lines,
The pixel circuit includes:
A first transistor for supplying a current according to a voltage between the gate and the source;
A two-terminal type light emitting element that emits light at a luminance corresponding to the current supplied by the first transistor;
A second transistor that is turned on or off between the data line and the gate of the first transistor;
A third transistor that is turned on or off between a terminal on the first transistor side of the two terminals of the light emitting element and a first feeder that feeds a predetermined reset potential;
Have
The first transistor and the light emitting element are connected in series between a high-order power supply and a low-order power supply,
The region where the pixel circuit is formed includes a first region and a second region,
In the first region, the first transistor and the second transistor are disposed,
The third transistor is disposed in the second region,
A shield wiring is provided between the first region and the second region;
When no current flows through the light emitting element, the potential of the shield wiring is fixed,
The electro-optical device , wherein the shield wiring is supplied with the reset potential . An electronic apparatus comprising the electro-optical device according to any one of claims 1 to 4.

Images