JP2007316510A - Active matrix type display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an active matrix type display device in which the deviation between the amount of current of a video signal and the amount of current flowing in a self-light emitting element can be reduced and a gradation reproducibility in a low gradation region is high. <P>SOLUTION: The active matrix type display device is equipped with a plurality of pixel sections PX disposed in matrix on a substrate, a plurality of video signal lines X connected for every column of the pixel sections, and a plurality of control signal lines SG, BG connected for every row of the pixel sections. Each pixel section has a display element 16 which is connected between a low potential power source line, and a high potential power source line, and emits light according to the supply current, a driving transistor DRT which is connected between the high potential power source line and the display element and controls the amount of current supplied to the display element, an output switch BCT which is connected between the drain of the driving transistor and the display element and is on-off controlled by the control signal from a control signal line, and a holding capacitor Cs which is connected between the gate and the source of the driving transistor. The source electrode S of the driving transistor is formed by being partly overlapped with at least the gate electrode G of the driving transistor. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an active matrix display device in which a display screen is configured by arranging display pixels including self-luminous elements such as organic electroluminescence (hereinafter referred to as EL) elements in a matrix.

  2. Description of the Related Art Planar active matrix display devices are widely used as display devices for personal computers, portable information terminals, and televisions. In recent years, as such a flat-type active matrix display device, an organic EL display device using a self-luminous element such as an organic EL element has attracted attention and has been actively researched and developed. This organic EL display device does not require a backlight that obstructs the reduction in thickness and weight, is suitable for moving image reproduction because of its high-speed response, and further has a feature that it can be used even in cold regions because the luminance does not decrease at low temperatures. .

  In general, an organic EL display device includes a plurality of display pixels arranged in a plurality of rows and a plurality of columns and constituting a display screen, a plurality of scanning lines extending along each row of display pixels, and a column of display pixels. A plurality of extended signal lines, a scanning line driving circuit for driving each scanning line, a signal line driving circuit for driving each signal line, and the like are provided. Each display pixel includes an organic EL element that is a self-light-emitting element and a pixel circuit that supplies a drive current to the organic EL element.

  For example, as disclosed in Patent Document 1, each pixel circuit includes an output switch that performs on / off control of a current flowing through the organic EL element, and a drive that controls the amount of current flowing through the organic EL element based on a video signal. A transistor, a storage capacitor for holding the gate control voltage of the driving transistor, a pixel switch for taking in the video signal current into the pixel circuit, and a switch for short-circuiting the gate and drain of the driving transistor when writing the video signal are provided. These switches and drive transistors are constituted by thin film transistors (hereinafter referred to as TFTs).

When writing the video signal current, the control signal line potential for controlling the pixel circuit is set to the on level, the pixel switch and the switch are turned on, and the control signal line potential for controlling the EL light emission is set to the off level. Turn off. As a result, the video signal current flows through the drive transistor, and the gate potential of the drive transistor is set to a potential corresponding to the current amount of the video signal current. Thereafter, the pixel switch and the switch are turned off, and the pixel circuit is disconnected from the video signal wiring. This video signal is written as a gate control voltage in the holding capacitor and held for a predetermined period. Subsequently, when the output switch is turned on, a current corresponding to the video signal is supplied to the organic EL element via the drive transistor and the output switch, and the organic EL element emits light at a desired luminance level.
JP 2003-280576 A

  By the way, in the pixel circuit as described above, a pixel switch composed of a TFT usually has a parasitic capacitance Cgd formed between a source and a gate. Due to the presence of the parasitic capacitance Cgd, the gate potential of the driving transistor is also displaced when the control signal line for controlling the EL emission is switched from the off potential to the on potential. As a result, a current different from the video signal current amount flows to the EL, resulting in poor gradation reproducibility in the low gradation region.

  The present invention has been made in view of the above points, and an object of the present invention is to provide an active matrix that can reduce the deviation between the amount of video signal current and the amount of current flowing through the self-light-emitting element and has high gradation reproducibility in a low gradation region. To provide a mold display device.

  In order to achieve the above object, an active matrix display device according to an aspect of the present invention includes a plurality of pixel portions arranged in a matrix on a substrate, and a plurality of video signals connected to each column of the pixel portions. And a plurality of first control signal lines and second control signal lines connected to each row of the pixel portion, and each pixel portion includes a low potential first voltage power line and a high potential first line. A display element connected between two voltage power supply lines and emitting light according to a supply current; and connected between the second voltage power supply line and the display element and supplied to the display element according to a gate control voltage. A drive transistor that controls the amount of current to be output; an output switch that is connected between the drain of the drive transistor and the display element and that is on / off controlled by a control signal from the first control signal line; Drive A gate of Njisuta, a storage capacitor connected between the source, the source electrode of the driving transistor is over at least a portion of the gate electrode of the driving transistor.

  According to the present invention, it is possible to provide an active matrix display device that can reduce the deviation between the amount of video signal current and the amount of current flowing through the self-light-emitting element and has high gradation reproducibility in a low gradation region.

Hereinafter, an active matrix display device according to an embodiment of the present invention will be described in detail with reference to the drawings. Hereinafter, an organic EL display device using an organic EL as a self-luminous element will be described as an example.
As shown in FIG. 1, the organic EL display device includes an organic EL panel 10 and a controller 12 that controls the organic EL panel 10.

  The organic EL panel 10 is arranged in a matrix on a light-transmitting insulating substrate 8 such as a glass plate, and is connected to each row of display pixels, each of which is connected to each row of display pixels mx that constitutes a display region 11. The n write control lines SG (1 to n) and the light emission control lines BG (1 to n), which are provided independently by n, and the m signal lines X (1 to 1) connected to the respective columns of display pixels, respectively. m), a scanning line driving circuit 14 for sequentially driving the write control lines SG (1 to n) and the light emission control lines BG (1 to n) for each row of display pixels, and a plurality of signal lines X ( 1 to m) is provided.

  The controller 12 shown in FIG. 1 is formed on a printed circuit board disposed outside the organic EL panel 10 and controls the scanning line driving circuit 14 and the signal line driving circuit 15. The controller 12 receives a digital video signal and a synchronization signal supplied from the outside, and generates a vertical scanning control signal for controlling the vertical scanning timing and a horizontal scanning control signal for controlling the horizontal scanning timing based on the synchronizing signal. The scanning control signal and the horizontal scanning control signal are supplied to the scanning line driving circuit 14 and the signal line driving circuit 15, respectively, and the digital video signal is supplied to the signal line driving circuit 15 in synchronization with the horizontal and vertical scanning timings.

  The signal line driving circuit 15 converts the video signals Data1 to Data sequentially obtained in each horizontal scanning period under the control of the horizontal scanning control signal into an analog format and supplies them in parallel to the plurality of signal lines X (1 to m) as current signals. To do. The scanning line driving circuit 14 includes a shift register, an output buffer, etc., sequentially transfers a horizontal scanning start pulse supplied from the outside to the next stage, and outputs two types of control signals to the display pixels PX in each row via the output buffer. That is, the control signal Sa and the control signal Sb are supplied. Thus, the control signal Sa and the control signal Sb are supplied to the write control lines SG (1 to n) and the light emission control lines BG (1 to n), respectively, and SST, TCT, and BCT are driven.

On the other hand, each display pixel PX includes an organic EL element 16 that is a self-luminous element and a pixel circuit 18 that supplies a drive current to the organic EL element as display elements.
FIG. 2 shows an equivalent circuit of the display pixel PX. A pixel circuit 18 shown in FIG. 2 is a current signal type pixel circuit that controls light emission of the organic EL element 16 in accordance with a video signal composed of a current signal. Hereinafter, it includes a DRT), a switch TCT (hereinafter referred to as TCT), an output switch BCT (hereinafter referred to as BCT), and a storage capacitor Cs.
SST, DRT, TCT, and BCT are composed of thin film transistors of the same conductivity type, for example, P-channel type.

  The DRT, BCT, and organic EL element 16 are connected in series between the high potential power supply line Vdd and the low potential power supply line Vss. The source of the DRT is connected to the high potential power supply line Vdd. The organic EL element 16 has one electrode, here the cathode, connected to the low potential power line Vss. In the BCT, the source is connected to the drain of the DRT, the drain is connected to the anode of the organic EL element 16, and the gate is connected to the light emission control line BG. The high potential power supply line Vdd and the low potential power supply line Vss are set to potentials of + 6V and −9V, for example.

  The DRT outputs a signal current corresponding to the video signal to the organic EL element 16. The BCT is ON (conductive state) and OFF (non-conductive state) controlled by a control signal from the light emission control line BG, and controls connection / disconnection between the DRT and the organic EL element 16.

  The holding capacitor Cs is connected between the source and gate of the DRT and holds the gate control potential of the DRT determined by the video signal. The storage capacitor Cs has a pair of flat electrodes opposed in parallel to each other. Here, the storage capacitor Cs is formed as a parallel plate capacitor by a DRT gate electrode film and a polysilicon layer.

  SST is connected between the corresponding signal line X and the drain of the DRT, and its gate is connected to the write control line SG. SST is turned on (conducting state) and off (non-conducting state) in response to a control signal supplied from the write control line SG, and takes in a video signal from the corresponding signal line X.

  TCT is connected between the drain and gate of the DRT, and the gate is connected to the write control line SG. TCT is controlled to be on (conductive state) and off (non-conductive state) in accordance with a control signal from the write control line SG, and controls connection / disconnection between the gate and drain of the DRT.

  In this embodiment, all the thin film transistors constituting the pixel circuit 18 are formed in the same process and the same layer structure, and are top gate thin film transistors using polysilicon as a semiconductor layer. By constituting all the thin film transistors with the same conductivity type, an increase in the number of manufacturing steps can be suppressed.

Next, the operation of the pixel circuit 18 will be described.
At the time of writing the video signal current, the scanning line drive circuit 14 sets the OFF potential to the light emission control line BG to turn off the BCT, sets the ON potential to the write control line SG, and sets SST and TCT. Is made conductive. Then, the signal line driving circuit 15 causes a video signal current to flow from the video signal line X and writes it to the holding capacitor Cs that can hold the gate-source voltage of the DRT. Thereby, the gate potential of the DRT is set to a potential corresponding to the amount of current.
At the time of video display, the scanning line drive circuit 14 disconnects the pixel circuit 18 from the video signal line X by setting an off potential to the write control line SG and making SST and TCT non-conductive. The gate potential of the DRT corresponding to the written video current is held by the holding capacitor Cs.
Next, the scanning line driving circuit 14 sets an ON potential to the light emission control line BG to make the BCT conductive. Then, a light emission current corresponding to the gate-source voltage of the DRT flows to the organic EL element 16, and the organic EL element 16 emits light with a luminance corresponding to the light emission current.

FIG. 3 is a plan view schematically showing a structure that can be employed in the display pixel, and FIG. 4 is a cross-sectional view showing the structure of the DRT. The present invention is characterized by the structure of the DRT.
The configuration of the DRT will be described in detail with reference to FIGS.

A P-channel type thin film transistor that constitutes a DRT includes a semiconductor layer 50 made of polysilicon formed on an insulating substrate 8, and this semiconductor layer is located between a source region 50a, a drain region 50b, and between the source and drain regions. A channel region 50c is provided. A gate insulating film 52 is formed over the semiconductor layer 50, and a gate electrode G is provided on the gate insulating film so as to face the channel region 50c. An interlayer insulating film 54 is formed over the gate electrode G, and a source electrode S and a drain electrode D are provided on the interlayer insulating film. Here, the source electrode S is connected to the high potential power supply line Vdd to have the same potential, and the source electrode S further includes a shield electrode SH extending so as to substantially cover the gate electrode G of the DRT.
The source electrode S and the drain electrode D are respectively connected to the source region 50a and the drain region 50b of the semiconductor layer 50 through contacts formed through the interlayer insulating film 54 and the gate insulating film 52, respectively. The drain electrode D of the DRT is connected to the BCT via a wiring formed on the interlayer insulating film 54.

A plurality of wirings including the video signal wiring X and the high potential power supply line Vdd are provided on the interlayer insulating film 54. A protective insulating film 56 is formed on the interlayer insulating film 54 so as to cover the source electrode S, the shield electrode SH, the drain electrode D, and the wiring. On the protective insulating film 56, a planarization layer 58 and a color separation layer 60 are sequentially laminated, and a common electrode 66 that constitutes a cathode of the organic EL element 16 is further provided.
Each thin film transistor constituting the SST, TCT, and BCT is also formed in the same structure as described above except that the shield electrode is not provided.

FIG. 5 is a plan view schematically showing a conventional structure that can be employed in a display pixel, and FIG. 6 is a cross-sectional view showing the structure of a conventional DRT. A mechanism that causes a problem in the conventional structure will be described with reference to FIGS.
In the conventional structure, the source electrode S does not include the shield electrode SH that covers the gate electrode G, as shown in FIGS.
As shown in FIG. 6, since the gate electrode G and the drain 50b of the DRT are arranged in close proximity to each other, a parasitic capacitance Cgd between parallel patterns exists between them.
During video display, the BCT is turned on as described above. At this time, the potential of the drain electrode D of the DRT is shifted from the potential at the end of writing to a potential corresponding to a diode voltage for allowing a predetermined light emission current to flow through the organic EL element 16. Since the parasitic capacitance Cgd transmits the displacement of the potential to the gate electrode G of the DRT, the potential of the gate electrode G is also displaced. As a result, a current different from the video signal current amount flows through the organic EL element 16.
When both TCT and DRT are formed of P-channel TFTs, the potential of the drain electrode D is displaced in the minus direction, and the potential of the gate electrode G is also displaced in the minus direction. As a result, since the current flowing through the DRT changes in the increasing direction, the light emission current increases and causes an increase in black luminance.

On the other hand, as shown in FIGS. 3 and 4, the source electrode S of the DRT connected to the high potential power supply line Vdd and having the same potential is extended so as to almost cover the gate electrode G of the DRT. By forming a simple shield electrode SH, the influence of the parasitic capacitance Cgd can be reduced.
That is, by adopting such a structure, most of the lines of electric force generated from the gate electrode G of the DRT are terminated at the shield electrode SH of the DRT disposed above the DRT gate electrode G. The parasitic capacitance Cgd is reduced.

  Such a structure increases the parasitic capacitance between the gate 50c and the source 50a of the DRT, but the high potential power supply line Vdd connected to the source electrode S has a DC potential. There is no potential variation.

  Here, the case where the anode of the organic EL element 16 is connected to the high potential power supply line Vdd via the BCT and the P channel type DRT and the cathode is connected to the low potential power supply line Vss has been described. The anode may be connected to the low potential power line Vss via the drain of the DRT. In any case, it is necessary to form the light emitting surface side with a transparent conductive material. For example, when the cathode is disposed on the light emitting surface side, the alkaline earth metal and the rare earth metal are formed thin enough to have optical transparency. This can be achieved.

  In this embodiment, the shield electrode SH substantially covers the gate electrode of the DRT. However, the shield electrode SH may cover a part of the gate electrode G. This is because it is possible to reduce the influence of the parasitic capacitance Cgd even if a portion is covered.

Note that the present invention is not limited to the active matrix display device using the current as a video signal, and can also be applied to an active matrix display device using a voltage as a video signal.
FIG. 7 is an equivalent circuit diagram of a pixel circuit of an active matrix display device according to another embodiment of the present invention. FIG. 8 is a plan configuration diagram of a pixel circuit of an active matrix display device according to another embodiment of the present invention. In addition, the same code | symbol is attached | subjected to the site | part same as 1st Embodiment. Since the pixel circuit using this voltage as a video signal is a well-known circuit, its detailed configuration and operation will not be described.
As shown in FIG. 8, the source electrode S of the DRT connected to the high potential power supply line Vdd extends so as to substantially cover the gate electrode G of the DRT, thereby forming the shield electrode SH. With this configuration, the influence of the parasitic capacitance Cgd can be reduced as in the first embodiment.

  In the active matrix display device of each of the embodiments described above, the shield structure is realized by extending the source electrode pattern of the DRT so as to substantially overlap the gate electrode G of the DRT, and the BCT is switched from on to off. The parasitic capacitance Cgd, which is a cause of fluctuations in the DRT gate potential, is reduced.

  In this embodiment, the shield electrode SH substantially covers the gate electrode of the DRT. However, the shield electrode SH may cover a part of the gate electrode G. This is because it is possible to reduce the influence of the parasitic capacitance Cgd even if a portion is covered.

  In addition, the present invention is not limited to the above-described embodiments as they are, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

  In the above-described embodiment, the case where all the thin film transistors constituting the pixel circuit are formed of the same conductivity type, here, the P channel type is described. However, the present invention is not limited to this, and all the thin film transistors are formed of N channel type thin film transistors. Is also possible. It is also possible to form pixel circuits in a mixture of thin film transistors of different conductivity types, such as pixel switches and switches composed of N-channel thin film transistors, and drive transistors and output switches composed of P-channel thin film transistors.

  Furthermore, the semiconductor layer of the thin film transistor is not limited to polysilicon, but may be composed of amorphous silicon. The self-light-emitting elements constituting the display pixel are not limited to organic EL elements, and various light-emitting elements capable of self-light emission are applicable.

1 is a circuit diagram showing a configuration of an active matrix display device according to an embodiment of the present invention. FIG. 6 is a diagram showing an equivalent circuit of display pixels in the active matrix display device. The top view which shows roughly the structure employable as a display pixel. Sectional drawing which shows the structure of DRT. The top view which shows schematically the conventional structure employable as a display pixel. Sectional drawing which shows the structure of the conventional DRT. FIG. 10 is an equivalent circuit diagram of a pixel circuit of an active matrix display device according to another embodiment. FIG. 10 is a plan configuration diagram of a pixel circuit of an active matrix display device according to another embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 12 ... Controller, 14 ... Scan line drive circuit, 15 ... Signal line drive circuit, 16 ... Organic EL element, 18 ... Pixel circuit, 50a ... Source, 50b ... Drain, 50c ... Gate, SST ... Pixel switch, DRT ... Drive transistor , TCT ... switch, BCT ... output switch, X ... video signal line, BG ... light emission control line, SG ... write control line, CG ... cancel control line, S ... source electrode, G ... gate electrode, D ... drain electrode, SH: shield electrode, PX: display pixel, Cs: holding capacitor, Cgd: parasitic capacitance, Vdd: high potential power line, Vss: low potential power line, X: video signal line.

Claims (4)

A plurality of pixel portions arranged in a matrix on the substrate;
A plurality of video signal lines connected to each column of the pixel portion;
A plurality of first control signal lines and second control signal lines connected to each row of the pixel portion,
Each pixel unit is connected between a low potential first voltage power supply line and a high potential second voltage power supply line, and emits light in response to a supply current; the second voltage power supply line and the display element A drive transistor for controlling the amount of current supplied to the display element in accordance with a gate control voltage, a drain of the drive transistor and the display element, and the first transistor An output switch that is turned on and off by a control signal from a control signal line, and a storage capacitor connected between the gate and source of the drive transistor,
An active matrix display device, wherein a source electrode of the driving transistor covers at least a part of a gate electrode of the driving transistor.   2. The active matrix display device according to claim 1, wherein a source electrode of the driving transistor covers a gate electrode of the driving transistor.   Each pixel portion is formed by a transistor and connected between the drain of the driving transistor and the video signal line, and is controlled to be turned on and off by a control signal from the second control signal line. And a switch that is connected between the gate and drain of the drive transistor and that is on / off controlled by a control signal from the second control signal line. The active matrix display device according to claim 1, wherein the display device is an active matrix display device. A plurality of third control signal lines connected to each row of the pixel portion,
Each pixel portion has one electrode connected between the write capacitor connected to the gate of the drive transistor and the other electrode of the write capacitor formed by the transistor and the video signal line. A pixel switch that is on / off controlled by a control signal from the second control signal line and that takes in a video signal from the video signal line to the pixel unit, and is connected between the gate and drain of the driving transistor, and The active matrix display device according to claim 1, further comprising a switch that is on / off controlled by a control signal from a third control signal line.

Images