JP2009053524A - Active matrix display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an active matrix display device which can be improved in display quality, lessened in electric power consumption and reduced in size. <P>SOLUTION: The active matrix display device comprises: a plurality of pixel parts Px which include display elements 16 and pixel circuits 18 for supplying driving currents to the display elements and are arranged on a substrate; and a signal line driving circuit which supplies a first signal current to pixel circuits through an image signal line X1 and then supplies a second signal current to the pixel circuits through the image signal line. Each pixel circuit comprises: a pixel switch SST1 which controls selection and non-selection; a first storage part 32a which stores a first driving electric current in accordance with the first signal current and thereafter supplies the stored first driving electric current and furthermore, stores a second driving electric current in accordance with the second signal current; a second storage part 32b which stores the first driving electric current supplied from the first storage part; and a third storage part 32c which, when not selecting the pixel part, stores a differential electric current between the second driving electric current stored in the first storage part and the first driving electric current stored in the second storage part, and outputs the stored differential electric current to the display element. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an active matrix display device, and more particularly to an active matrix display device that performs signal writing using a current signal.

  In recent years, the demand for flat display devices typified by liquid crystal display devices has been rapidly increased by taking advantage of the features of thinness, light weight, and low power consumption. In particular, an active matrix display device in which a pixel switch having a function of electrically separating an on pixel and an off pixel and holding a video signal to the on pixel is provided in each pixel has crosstalk between adjacent pixels. Since a good display quality without any problem can be obtained, it has come to be used for various displays including portable information devices.

  As such a flat-type active matrix display device, an organic electroluminescence (EL) display device using a self-luminous element has attracted attention, and research and development has been actively conducted. The organic EL display device does not require a backlight that obstructs the reduction in thickness and weight, is suitable for moving image reproduction because of high-speed response, and further has a feature that it can be used even in a cold region because the luminance does not decrease at low temperatures.

  The organic EL display device includes an organic EL element as a display element for each pixel and a pixel circuit that supplies a drive current to the display element, and performs a display operation by controlling the light emission luminance of the display element. The pixel circuit includes, for example, a drive transistor and an output switch connected in series to the organic EL element, a diode connection switch connected between the gate and drain of the drive transistor, and holding a gate potential corresponding to a video signal. These drive transistors, output switches, and diode connection switches are composed of thin film transistors, for example. As such an organic EL display device, a method of supplying image information to a pixel circuit by a current signal is known.

  In the case of a display device that supplies a signal using a current signal, there is a risk that sufficient signal supply may not be possible due to the wiring capacity of the wiring that supplies the signal. In particular, there is a problem that a display failure due to insufficient writing occurs when the current value to be written is small. Further, when performing multi-grayscale display, writing becomes difficult on the low-grayscale side where the set current amount is small, resulting in display problems.

  In order to prevent such a shortage of writing due to the wiring capacity, an organic EL display device is provided that supplies two systems of current signals from a video signal driver and writes the difference current to a pixel as a video signal (for example, Patent Document 1). This display device writes a base current from a constant current circuit to a pixel circuit via a video signal line, and also writes a gray scale current from a source IC to the pixel circuit via a video signal line. A difference current from the current is written into the pixel circuit. Then, the display element is driven by the differential current.

According to such a configuration, the current value supplied to the video signal line can be freely set, and the base current and the gradation current can be set to a current value sufficiently larger than the wiring capacity. As a result, it is possible to write a small current that is the difference current with a large write current that is not affected by the wiring capacitance.
JP 2004-341023 A

  However, in the display device configured as described above, it is necessary to provide a constant current circuit for each video signal line, and the peripheral portion of the display device, that is, the frame portion increases. In addition, display unevenness in the signal line direction may occur due to variations in a plurality of constant current circuits. Further, since the differential current is taken when the video signal is written, the power consumption is likely to increase.

  The present invention has been made in view of the above problems, and an object thereof is to provide an active matrix display device capable of improving display quality and reducing power consumption.

To achieve the above object, an active matrix display device according to an aspect of the present invention includes a display element and a plurality of pixel circuits arranged in a matrix on a substrate, the pixel circuit supplying a driving current to the display element. A first signal current is supplied to the pixel circuit via the video signal line, and the video signal line is connected to the pixel unit via the video signal line. A signal line driving circuit for supplying a second signal current to the pixel circuit,
Each of the pixel circuits stores a first switch that stores a pixel switch that controls selection and non-selection of the pixel unit and a first drive current corresponding to the first signal current when the pixel unit is selected. A first storage unit for supplying a current and storing a second drive current corresponding to the second signal current; and a first drive current supplied from the first storage unit when the pixel unit is not selected. Storing a differential current between a second storage unit to be stored, a second drive current stored in the first storage unit when the pixel unit is not selected, and a first drive current stored in the second storage unit; A third storage unit that outputs the stored difference current as a drive current to the display element.

  According to the present invention, it is possible to perform a good display operation without being affected by the wiring capacity, reduce the constant current circuit, reduce the frame area, and reduce display unevenness caused by the constant current circuit. A possible active matrix display device can be provided. In addition, an active matrix display device capable of reducing power consumption can be provided.

Hereinafter, an organic EL display device will be described in detail as a first embodiment of the present invention with reference to the drawings.
FIG. 1 is a plan view schematically showing an organic EL display device. As shown in FIG. 1, the organic EL display device is configured as, for example, a large active matrix display device of 10 type or more, and includes an organic EL panel 10 and a controller 12 that controls the organic EL panel 10.

  The organic EL panel 10 includes a light-transmitting insulating substrate 8 such as a glass plate, m × n display pixels PX arranged in a matrix on the insulating substrate and constituting a display region 11, and each display pixel row. The first scanning line Sga (1 to m), the second scanning line Sgb (1 to m), the third scanning line Sgc (1 to m), and the fourth scanning line Sga (1 to m), which are connected and provided independently by m. The scanning line Sgd (1 to m), the fifth scanning line Sge (1 to m), and n video signal lines X (1 to n) connected to each column of the display pixels PX are provided. The organic EL panel 10 includes first, second, third, fourth, and fifth scanning lines Sga (1 to m), Sgb (1 to m), Sgc (1 to m), and Sgd (1 to m). , Sge (1 to m) are sequentially provided for each row of the display pixels PX, and scanning line driving circuits 14a and 14b and a signal line driving circuit 15 for driving the plurality of video signal lines X (1 to n) are provided. . The scanning line driving circuits 14 a and 14 b and the signal line driving circuit 15 are integrally formed on the insulating substrate 8 outside the display area 11.

  Each display pixel PX that functions as a pixel portion includes a display element having a photoactive layer between opposing electrodes, and a pixel circuit 18 that supplies a drive current to the display element. The display element is, for example, a self-luminous element. In this embodiment, the organic EL element 16 including at least an organic light-emitting layer is used as a photoactive layer.

  FIG. 2 shows an equivalent circuit of the display pixel PX. The pixel circuit 18 is a current signal type pixel circuit that controls light emission of the organic EL element 16 in accordance with a video signal composed of a current signal. The pixel switch SST1, the first switch SST2, the second switch SST3, the output switch BCT, the first switch 1 memory | storage part 32a, the 2nd memory | storage part 32b, and the 3rd memory | storage part 32c are provided.

  The first storage unit 32a includes a first drive transistor DRT1, a first holding switch TCT1, and a first holding capacitor C1 as a capacitor. The second storage unit 32b includes a second drive transistor DRT2, a second holding switch TCT2, and a second holding capacitor C2 as a capacitor. The third storage unit 32c includes a third drive transistor DRT3, a third holding switch TCT3, and a third holding capacitor C3 as a capacitor.

  Except for the second drive transistor DRT2, the pixel switch SST1, the first switch SST2, the second switch SST3, the first drive transistor DRT1, the third drive transistor DRT3, the first holding switch TCT1, the second holding switch TCT2, and the third holding Here, the switch TCT3 and the output switch BCT are composed of thin film transistors of the same conductivity type, for example, a P-channel type. The second drive transistor DRT2 is composed of an N-channel thin film transistor.

  In the present embodiment, the thin film transistors each including the other drive transistors and the switches except for the second drive transistor DRT2 are formed in the same process and the same layer structure, and a top gate thin film transistor using polysilicon as a semiconductor layer. It is. The second drive transistor DRT2 is a thin film transistor having a top gate structure using polysilicon as a semiconductor layer, and is formed in the same process and the same layer structure as the pixel switch SST1 and the like. The first and third drive transistors DRT3 -Differently formed by implanting impurities of different conductivity types into the drain region. Pixel switch SST1, first driving transistor DRT1, second driving transistor DRT2, third driving transistor DRT3, first holding switch TCT1, second holding switch TCT2, third holding switch TCT3, first switch SST2, second switch SST3, Each of the output switches BCT has a first terminal, a second terminal, and a control terminal. In this embodiment, the first terminal, the second terminal, and the control terminal are a source, a drain, and a gate, respectively.

  In the first storage unit 32a, the first drive transistor DRT1 is connected in series with the organic EL element 16 between the high-potential voltage power supply line Vdd and the low-potential reference voltage power supply line Vss, and a current corresponding to the video signal. The amount is output to the organic EL element. Here, the source of the first drive transistor DRT1 is connected to the power supply voltage line Vdd, and the drain is connected to the anode of the organic EL element 16. The reference voltage power supply line Vss and the voltage power supply line Vdd are set to potentials of −9 V and +6 V, for example.

  The first storage capacitor C1 is connected between the source and gate of the first drive transistor DRT1, and holds the gate control potential of the first drive transistor DRT1 determined by the video signal. The pixel switch SST1 is connected between the corresponding video signal line X (1-n) and the drain of the first driving transistor DRT1, and its gate is connected to the corresponding second scanning line Sgb (1-m). . The pixel switch SST1 captures a video signal from the corresponding video signal line X (1-n) in response to the control signal SG2 (1-m) supplied from the second scanning line Sgb (1-m).

  The first holding switch TCT1 is connected between the drain and gate of the first drive transistor DRT1, and the gate thereof is connected to the second scanning line Sgb (1 to m). The first holding switch TCT1 is turned on (conductive state) and turned off (non-conductive state) in response to the control signal SG2 (1-m) from the second scanning line Sgb (1-m), and the first drive transistor DRT1 Controls the connection and disconnection between the gate and drain, and regulates current leakage from the first storage capacitor C1.

  In the second storage unit 32b, the second drive transistor DRT2 is connected in series with the organic EL element 16 between the two reference voltage power supply lines Vss, and outputs a current amount corresponding to the video signal. Here, the source of the second drive transistor DRT2 is connected to the reference voltage power supply line Vss, and the drain is connected to the organic EL element 16. The second storage capacitor C2 is connected between the source and gate of the second drive transistor DRT2, and holds the gate control potential of the second drive transistor DRT2 determined by the video signal.

  The second holding switch TCT2 is connected between the drain and gate of the second drive transistor DRT2, and the gate thereof is connected to the first scanning line Sga (1 to m). The second holding switch TCT2 is turned on (conductive state) and turned off (non-conductive state) in response to the control signal SG1 (1-m) from the first scanning line Sga (1-m), and the second drive transistor DRT2 Controls connection and disconnection between the gate and drain, and regulates current leakage from the second storage capacitor C2.

  The first switch SST2 is connected between the source of the second holding switch TCT2, the drain of the second driving transistor DRT2, and the drain of the first driving transistor DRT1, and the gate thereof is connected to the fourth scanning line Sgd (1 to m )It is connected to the. The first switch SST2 is turned on (conductive state) and turned off (non-conductive state) in response to the control signal SG4 (1-m) from the fourth scanning line Sgd (1-m), and the second drive transistor DRT2 Controls connection and disconnection with the first drive transistor DRT1. That is, the first switch SST2 controls connection / disconnection of the current path between the first storage unit 32a and the second storage unit 32b.

  In the third storage unit 32c, the third drive transistor DRT3 is connected in series with the organic EL element 16 between the voltage power supply line Vdd and the reference voltage power supply line Vss, and a current amount corresponding to the video signal is supplied to the organic EL element. Output. Here, the source of the third drive transistor DRT3 is connected to the voltage power supply line Vdd, and the drain is connected to the organic EL element 16.

  The third storage capacitor C3 is connected between the source and gate of the third drive transistor DRT3 and holds the gate control potential of the third drive transistor DRT3 determined by the video signal.

  The third holding switch TCT3 is connected between the drain and gate of the third drive transistor DRT3, and the gate thereof is connected to the third scanning line Sgc (1 to m). The third holding switch TCT3 is turned on (conductive state) and turned off (non-conductive state) in response to the control signal SG3 (1-m) from the third scanning line Sgc (1-m), and the third drive transistor DRT3 Controls the connection and disconnection between the gate and drain, and regulates current leakage from the third storage capacitor C1.

  The output switch BCT is connected between the drain of the third drive transistor DRT3 and one electrode of the organic EL element 16, here the anode, and the gate thereof is connected to the fifth scanning line Sge (1 to m). Yes. The output switch BCT is ON / OFF controlled by a control signal BG (1-m) from the fifth scanning line Sge (1-m), and controls connection / disconnection between the third drive transistor DRT3 and the organic EL element 16. To do.

  The second switch SST3 is connected between the source of the first holding switch TCT1, the drain of the first driving transistor DRT1, and the drain of the third driving transistor DRT3, and the gate thereof is connected to the third scanning line Sgc (1 to m )It is connected to the. The second switch SST3 is turned on (conductive state) and turned off (non-conductive state) in response to the control signal SG3 (1-m) from the third scanning line Sgc (1-m), and the first drive transistor DRT1. Controls connection / disconnection between the third drive transistor DRT3 and the output switch BCT. That is, the first switch SST2 controls connection / disconnection between the first storage unit 32a and the third storage unit 32c.

Next, the configuration of the third drive transistor DRT3 and the organic EL element 16 will be described in detail with reference to FIG. FIG. 3 shows a cross section of the display pixel Px including the organic EL element 16.
The P-channel type thin film transistor constituting the third drive transistor DRT3 includes a semiconductor layer 50 made of polysilicon formed on the insulating substrate 8, and this semiconductor layer includes a source region 50a, a drain region 50b, and a source / drain region. It has a channel region 50c located between them. A gate insulating film 52 is formed over the semiconductor layer 50, and a gate electrode G is provided on the gate insulating film so as to face the channel region 50c. An interlayer insulating film 54 is formed over the gate electrode G, and a source electrode (source) S and a drain electrode (drain) D are provided on the interlayer insulating film. The source electrode S and the drain electrode D are respectively connected to the source region 50a and the drain region 50b of the semiconductor layer 50 through contacts formed through the interlayer insulating film 54 and the gate insulating film 52, respectively. The drain electrode D of the third drive transistor DRT3 is connected to the output switch BCT via a wiring formed on the interlayer insulating film 54.

  The thin film transistors constituting the first drive transistor DRT1, the pixel switch SST1, the first holding switch TCT1, the second holding switch TCT2, the third holding switch TCT3, the first switch SST2, the second switch SST3, and the output switch BCT are also described above. Are formed in the same structure. The second drive transistor DRT2 is also formed in the same structure as described above, but an LDD region may be further added.

  A plurality of wirings including the video signal lines X (1 to n) are provided on the interlayer insulating film 54. A protective film 56 is formed on the interlayer insulating film 54 so as to cover the source electrode S, the drain electrode D, and the wiring. On the protective film 56, a hydrophilic film 58 and a partition film 60 are laminated in this order.

  The organic EL element 16 has a structure in which an organic light emitting layer 64 containing a luminescent organic compound is sandwiched between an anode 62 and a cathode 66. The anode 62 is made of a transparent electrode material such as ITO (indium tin oxide) and is provided on the protective film 56. Of the hydrophilic film 58 and the partition wall film 60, the part facing the anode 62 is removed by etching. An anode buffer layer 63 and an organic light emitting layer 64 are formed on the anode 62, and a cathode 66 made of silver / aluminum alloy is laminated on the organic light emitting layer 64 and the partition wall film 60.

  In the organic EL element 16 having such a structure, when the holes injected from the anode 62 and the electrons injected from the cathode 66 recombine inside the organic light emitting layer 64, organic molecules constituting the organic light emitting layer are formed. Is excited to generate excitons. The excitons emit light in the process of radiation deactivation, and the light is emitted from the organic light emitting layer 64 to the outside through the transparent anode 62 and the insulating substrate 8.

  Here, the cathode 66 may be light transmissive, and light may be extracted from the surface opposite to the insulating substrate 8. Further, a reverse lamination type in which the anode 62 is disposed on the insulating substrate 8 side with respect to the cathode 66 may be employed. In either case, it is necessary to form the light emitting surface side with a transparent conductive material. For example, when the cathode 66 is disposed on the light emitting surface side, the alkaline earth metal and the rare earth metal are thin enough to have light transmittance. This can be achieved by forming.

  On the other hand, the controller 12 shown in FIG. 1 is formed on a printed circuit board disposed outside the organic EL panel 10 and controls the scanning line driving circuits 14 a and 14 b and the signal line driving circuit 15. The controller 12 receives a digital video signal and a synchronization signal supplied from the outside, and generates a vertical scanning control signal for controlling the vertical scanning timing and a horizontal scanning control signal for controlling the horizontal scanning timing based on the synchronizing signal. The controller 12 supplies the vertical scanning control signal and the horizontal scanning control signal to the scanning line driving circuits 14a and 14b and the signal line driving circuit 15, respectively, and outputs a digital video signal in synchronization with the horizontal and vertical scanning timings. This is supplied to the line drive circuit 15.

  The scanning line driving circuits 14a and 14b include a shift register, an output buffer, and the like, and sequentially transfer a horizontal scanning start pulse supplied from the outside to the next stage, as shown in FIGS. 1 and 2, via the output buffer. Four types of control signals, that is, control signals SG1 (1 to m), SG2 (1 to m), SG3 (1 to m), SG4 (1 to m), and BG (1 to m) are applied to the display pixels PX in each row. Supply. Thereby, each 1st, 2nd, 3rd, 4th, 5th scanning line Sga (1-m), Sgb (1-m), Sgc (1-m), Sgd (1-m), Sge ( 1 to m) are control signals SG1 (1 to m), control signals SG2 (1 to m), SG3 (1 to m), control signals SG4 (1 to m) and control in one horizontal scanning period different from each other. It is driven by a signal BG (1 to m).

  The signal line driving circuit 15 converts the video signal sequentially obtained in each horizontal scanning period into the analog format under the control of the horizontal scanning control signal to obtain the first signal current Io and the second signal current Io-Isig. A signal current is supplied in parallel to the plurality of video signal lines X (1 to n). As shown in FIG. 2, the signal line driving circuit 15 includes a plurality of source ICs 30 connected to the video signal lines X (1 to n). Each source IC 30 is formed of a variable N-channel IC and functions as a current supply unit. The source IC 30 supplies the first signal current Io as the base current and the second signal current Io-Isig as the gradation current to the pixel circuit 18 through the video signal lines X (1 to n). The first signal current Io and the second signal current Io-Isig are each time-divisionally supplied to the plurality of display pixels PX using the same video signal wiring X (1 to n).

  The current amount of the first signal current Io and the second signal current Io-Isig is set to a current amount that does not cause insufficient writing. That is, the current amount of the first signal current Io and the second signal current Io-Isig is from the highest gradation display to the lowest gradation display in the wiring capacity (Cp) of the video signal line X in one horizontal scanning period (t). Is set to a value larger than the amount of charge corresponding to a value multiplied by the potential change amount (maximum voltage change ΔV) (Io (Io−Isig)> Cp × ΔV / t). For example, the first signal current Io and the second signal current Io-Isig are set to the same magnitude as the drive current for performing the highest gradation display of the organic EL display device. As an example, the first signal current Io is set to 0.1 to 1.0 μA, for example.

  Also, one of the first signal current Io and the second signal current Io-Isig, for example, the first signal current Io is a constant current, and the second signal current Io-Isig is a signal current that varies according to the gradation. Yes. The second signal current Io-Isig may be a constant signal current, and the first signal current Io may be a signal current that varies according to the gradation. Alternatively, both the first signal current Io and the second signal current Io-Isig can be variable signal currents.

  In the organic EL display device configured as described above, the pixel circuit 18 operates in a first signal current (constant current P channel) writing operation, a first signal current (constant current N channel) writing operation, and a second signal current. It is divided into a (provisional signal) writing operation, a differential signal (main signal) writing operation, and a light emitting operation.

  FIG. 4 is a table showing on / off (high, Low) timings of the control signals Sa1, Sb1, Sc1, and Sd1, and FIG. 5 shows each element associated with the on / off of the control signals Sa1, Sb1, Sc1, and Sd1. It is a figure which shows the on / off timing of. FIG. 6 schematically shows the operation of the pixel circuit 18 in the display pixel PX in the first row.

  As shown in FIGS. 4, 5, and 6, in the first signal current (constant current P channel) writing operation, for example, the first holding is performed from the first scanning line driving circuit 14 a to the display pixel PX in the first row. A level (ON potential) at which the switch TCT1 and the pixel switch SST1 are turned on, here, a low level control signal SG1 is output. At the same time, the second holding switch TCT2, the first switch SST2, the third holding switch TCT3, the second switch SST3, and the output switch BCT are turned off from the first scanning line driving circuit 14a and the second scanning line driving circuit 14b. Control signals SG2, SG3, SG4, and BG at a level (off potential), here, high level are output. Accordingly, the first holding switch TCT1 and the pixel switch SST1 are turned on (conductive state), and the second holding switch TCT2, the first switch SST2, the third holding switch TCT3, the second switch SST3, and the output switch BCT are turned off ( The first signal current writing operation is started.

  In the first signal current (P channel) writing period, for example, the first signal current Io set to a predetermined constant current is supplied from the corresponding source IC 30 of the signal line driving circuit 15 to the video signal line X1, and the pixel switch The pixel is supplied to the display pixel PX selected by SST1.

  In the display pixel PX, the pixel switch SST1 and the first holding switch TCT1 are in the ON state, and the captured first signal current Io is supplied to the first drive transistor DRT1 of the first storage unit 32a and the first drive transistor DRT1 is written. State. As a result, a write current flows from the voltage power supply line Vdd to the video signal line X1 through the first drive transistor DRT1, and the potential between the gate and source of the first drive transistor DRT1 corresponding to the amount of the first signal current Io is held first. It is written in the capacity C1.

  Next, the control signal SG1 is turned off (high level), and the first holding switch TCT1 and the pixel switch SST1 are turned off. Thereby, the first signal current writing operation is completed. Subsequently, as shown in FIGS. 4, 5, and 7, the control signals SG2 and SG4 are turned on (low level), and the second holding switch TCT2 and the first switch SST2 are turned on. Second switch SST3 and output switch BCT are kept off (non-conducting state). As a result, the first signal current (N-channel) write operation starts.

  In the first signal current (N channel) writing period, the first drive transistor DRT1 outputs a first drive current having a current amount corresponding to the first signal current Io by the gate control voltage written in the first storage capacitor C1. To do. As a result, the first signal current is supplied from the first storage unit 32a to the second storage unit 32b via the first switch SST2.

  In the second storage unit 32b, the second holding switch TCT2 is in the ON state, and the captured first signal current Io is supplied to the second driving transistor DRT2 to put the second driving transistor DRT2 in the writing state. Thus, a write current flows from the voltage power supply line Vdd to the reference voltage power supply line Vss through the first drive transistor DRT1 and the second drive transistor DRT2, and the gate of the second drive transistor DRT2 corresponding to the current amount of the first signal current Io, The source-to-source potential is written into the second storage capacitor C2.

  Next, the control signals SG2 and SG4 are turned off (high level), and the second holding switch TCT2 and the first switch SST2 are turned off. Thereby, the first signal current (N-channel) write operation is completed.

  Subsequently, as shown in FIGS. 4, 5, and 8, the control signal SG1 is turned on (low level), and the first holding switch TCT1 and the pixel switch SST1 are turned on. The output switch BCT is kept off (non-conducting state). Thereby, the second signal current (provisional signal) write operation is started.

  In the second signal current (provisional signal) writing period, the second signal current Io-Isig corresponding to the desired gradation is supplied from the corresponding source IC 30 of the signal line driving circuit 15 to the video signal line X1, and the pixel switch SST1. Is supplied to the selected display pixel PX.

  In the display pixel PX, the pixel switch SST1 and the first holding switch TCT1 are in the on state, and the captured second signal current Io-Isig is supplied to the first drive transistor DRT1 of the first storage unit 32a. DRT1 is set to the write state. As a result, a write current flows from the voltage power supply line Vdd to the video signal line X1 through the first drive transistor DRT1, and the gate-source potential of the first drive transistor DRT1 corresponding to the amount of the second signal current Io-Isig is the first. 1 is written in the storage capacitor C1.

  Next, the control signal SG1 is turned off (high level), and the first holding switch TCT1 and the pixel switch SST1 are turned off. As a result, the second signal current (provisional signal) writing operation is completed.

  Subsequently, as shown in FIGS. 4, 5, and 9, the control signals SG3 and SG4 are turned on (low level), and the first switch SST2, the second switch SST3, and the third holding switch TCT3 are turned on. Become. The first holding switch TCT1, the second holding switch TCT2, and the output switch BCT are kept off (non-conducting state). Thereby, this signal current (difference signal) writing operation is started.

  In the signal current writing period, the first driving transistor DRT1 outputs a second driving current having a current amount corresponding to the second signal current Io-Isig by the gate control voltage written in the first holding capacitor C1. Thus, the second drive current (Io-Isig) is supplied from the first storage unit 32a to the second storage unit 32b via the first switch SST2.

  In addition, the second drive transistor DRT2 of the second storage unit 32b uses the gate control voltage written in the second storage capacitor C2 to generate the first drive current (Io) having a current amount corresponding to the first signal current Io as a reference voltage. Output to the power line Vss. Of the first drive current (Io), a current (Io-Isig) corresponding to the second drive current is second from the voltage power supply line Vdd through the first drive transistor DRT1 and the first switch SST2 of the first storage unit 32a. The remaining drive current, that is, the differential current (Io− (Io−Isig)) = Isig is supplied from the voltage power supply line Vdd to the third drive of the third storage unit 32c, which is supplied to the second drive transistor DRT2 of the storage unit 32b. The transistor DRT3 and the second switch SST3 are supplied to the second drive transistor DTR2 through the first switch SST2.

  At this time, the third holding switch TCT2 is in an on state, and the third drive transistor DRT3 is in a writing state. Therefore, when the differential current Isig flows through the third drive transistor DRT3, the potential between the gate and the source of the third drive transistor DRT3 corresponding to the amount of the differential current Isig is written into the third storage capacitor C3.

  Next, the control signals SG3 and SG4 are turned off (high level), and the first and second switches SST1 and SST2 and the third holding switch TCT3 are turned off. Thereby, the write operation of the main signal current to the third storage unit 32c, that is, the differential current Isig is completed.

  Subsequently, as shown in FIGS. 4, 5, and 10, the control signal BG is turned on (low level), and the output switch BCT is turned on. The other switches are kept off. Thereby, the light emission operation is started.

  In the light emission period, the third drive transistor DRT3 outputs a drive current Isig having a current amount corresponding to the differential current Isig by the gate control voltage written in the third storage capacitor C3. This drive current Isig is supplied to the organic EL element 16 through the output switch BCT. Thereby, the organic EL element 16 emits light, and the light emission operation is started. The organic EL element 16 maintains the light emitting state until the control signal BG becomes the off potential again after one frame period.

  According to the organic EL display device configured as described above, in the writing of the video signal current, the first signal current is supplied to the first storage unit 32a of the pixel circuit 18 through the video signal line and then written. The first signal current stored in the first storage unit is supplied to the second storage unit 32b by the first drive transistor and written, and further, the second signal current is supplied to the pixel circuit 18 through the video signal line. 1 Write to the storage unit 32a. At the time of light emission, the differential current between the second signal current stored in the first storage unit and the first signal current stored in the second storage unit is written and stored in the third storage unit, and the stored differential current is stored in the drive current Isig. Is output to the display element 16. Therefore, even when low gradation light emission is performed, it is possible to freely set the current values of the first and second signal currents supplied to the video signal line, which are sufficiently larger than the wiring capacity of the video signal line. Can be set to Therefore, even when displaying at low brightness, the signal current can be written in a short time without being affected by the wiring capacity, and the display failure at low brightness, unevenness, and the feeling of roughness are eliminated. High-quality image display can be realized.

  Even when a low current write is performed after a high current write to the video signal line, a shortage of a low current video signal can be solved. For example, conventionally, when writing a video signal with the highest gradation display (white display) and then writing with the lowest gradation display (black display), the latter lack of video signal writing causes the higher gradation display (white display) to be written. There is a possibility that the image is in a writing state and the white display has a tail on display. According to the present embodiment, it is possible to eliminate such display defects caused by insufficient writing.

  In each pixel circuit, at the time of writing a signal current, the signal current or the drive current flowing through the other transistors except the output switch BCT may be increased several times to several tens of times the drive current supplied to the organic EL element 16. it can. The variation in the current increase rate due to the Early effect and the kink effect of the first, second, and third drive transistors DRT3, DRT2, DTR3, and other thin film transistors constituting the switches is smaller as the current flowing through the transistors is larger. Therefore, as in this embodiment, by increasing the current flowing through the transistor to several times to several tens of times the light emission current supplied to the organic EL element 16, variation in the current increase rate of the transistor is suppressed, and the organic EL A driving current without variation can be supplied to the element. As a result, it is possible to suppress the luminance variation between the display pixels PX and to display a good image with improved display quality.

  Further, according to the organic EL display device, in writing the video signal current, the first signal current is written and stored in the second drive transistor of the second storage unit by the first drive transistor of the first storage unit. Has been. Therefore, the constant current circuit used conventionally can be reduced, and the supply unit can be configured by the source IC 30. Therefore, it is possible to reduce the width of the frame portion of the display device and to increase the size of the display area or the size of the entire device. At the same time, the manufacturing cost can be reduced. Further, display unevenness in the video signal line direction due to the constant current circuit can be eliminated, and display quality can be improved.

  Furthermore, only the differential current for causing the organic EL element 16 to emit light during the light emission period is supplied to the organic EL element, and it is not necessary to pass a drive current to the first storage unit and the second storage unit. Therefore, it is possible to greatly reduce the power consumption associated with image display.

  In the first embodiment described above, the first switch SST2, the second holding switch TCT2, and the output switch BCT of the pixel circuit 18 are not limited to P-channel TFTs but may be N-channel TFTs. Good. Further, the pixel switch SST1 and the first holding switch TCT1 can be either a P-channel type or an N-channel type as long as the carriers are the same.

Next, an organic EL display device according to a second embodiment of the present invention will be described with reference to FIG.
According to the second embodiment, in the third storage unit 32c of the pixel circuit 18, the third drive transistor DRT3 is configured by an N-channel thin film transistor. The third drive transistor DRT3 is connected in series with the organic EL element 16 between the low-potential reference voltage power supply line Vss and the high-potential voltage power supply line Vdd. Here, the source of the third drive transistor DRT3 is connected to the low-potential reference voltage power supply line Vss, and the drain is connected to the organic EL element 16 via the output switch BCT.

The output switch BCT is connected between the drain of the third drive transistor DRT3 and one electrode of the organic EL element 16, here the anode, and the gate thereof is connected to the fifth scanning line Sge (1 to m). Yes. The cathode of the organic EL element 16 is connected to the power supply voltage line Vdd.
In the second embodiment, other configurations of the organic EL display device are the same as those of the first embodiment described above, and the same reference numerals are given to the same portions, and the detailed description thereof is omitted.

  In the organic EL display device according to the second embodiment configured as described above, the pixel circuit 18 operates in a first signal current (constant current P channel) write operation and a first signal current (constant current N channel). The operation is divided into a writing operation, a second signal current (provisional signal) writing operation, a differential signal (main signal) writing operation, and a light emitting operation.

  FIG. 12 is a table showing on / off (high, Low) timings of the control signals Sa1, Sb1, Sc1, and Sd1, and FIG. 13 shows each element associated with the on / off of the control signals Sa1, Sb1, Sc1, and Sd1. It is a figure which shows the on / off timing of. FIG. 14 schematically shows the operation of the pixel circuit 18 in the display pixel PX in the first row.

  As shown in FIGS. 12, 13, and 14, in the first signal current (constant current P-channel) write operation, the first holding switch TCT1 and the pixel switch SST1 are turned on (as in the first embodiment described above). The second holding switch TCT2, the first switch SST2, the third holding switch TCT3, the second switch SST3, and the output switch BCT are turned off (non-conducting state), and the first signal current writing operation is performed. Be started.

  For example, the first signal current Io set to a predetermined constant current is supplied from the corresponding source IC 30 of the signal line driving circuit 15 to the video signal line X1 and supplied to the display pixel PX selected by the pixel switch SST1. . As a result, a write current flows from the voltage power supply line Vdd to the video signal line X1 through the first drive transistor DRT1, and the potential between the gate and source of the first drive transistor DRT1 corresponding to the amount of the first signal current Io is held first. It is written in the capacity C1.

  Next, the first holding switch TCT1 and the pixel switch SST1 are turned off, and the first signal current writing operation is completed. Subsequently, as shown in FIGS. 12, 13, and 15, the second holding switch TCT2 and the first switch SST2 are turned on. Second switch SST3 and output switch BCT are kept off (non-conducting state). As a result, the first signal current (N-channel) write operation starts.

  In the first signal current (N channel) writing period, as in the first embodiment, the first drive transistor DRT1 corresponds to the first signal current Io by the gate control voltage written to the first storage capacitor C1. A first drive current having a current amount is output. As a result, the first signal current is supplied from the first storage unit 32a to the second storage unit 32b via the first switch SST2. In the second storage unit 32b, the second holding switch TCT2 is in an ON state, and the captured first signal current Io flows to the reference voltage power supply line Vss through the second drive transistor DRT2. Accordingly, the gate-source potential of the second drive transistor DRT2 corresponding to the amount of the first signal current Io is written into the second storage capacitor C2.

  Next, the second holding switch TCT2 and the first switch SST2 are turned off, and the first signal current (N channel) writing operation is completed.

  Subsequently, as shown in FIGS. 12, 13, and 16, the first holding switch TCT1 and the pixel switch SST1 are turned on, and the output switch BCT is kept off (non-conducting state). Thereby, the second signal current (provisional signal) write operation is started.

  In the second signal current (provisional signal) writing period, the second signal current Io + Isig corresponding to the desired gradation is supplied from the corresponding source IC 30 of the signal line driving circuit 15 to the video signal line X1, and is selected by the pixel switch SST1. Is supplied to the display pixel PX. As a result, a write current flows from the voltage power supply line Vdd to the video signal line X1 through the first drive transistor DRT1, and the gate-source potential of the first drive transistor DRT1 corresponding to the current amount of the second signal current Io + Isig is held first. It is written in the capacity C1. Next, the first holding switch TCT1 and the pixel switch SST1 are turned off, and the second signal current (provisional signal) writing operation is completed.

  Subsequently, as shown in FIGS. 12, 13, and 17, the control signals SG3 and SG4 are turned on (low level), and the first switch SST2, the second switch SST3, and the third holding switch TCT3 are turned on. Become. The first holding switch TCT1, the second holding switch TCT2, and the output switch BCT are kept off (non-conducting state). As a result, the first storage unit 32a is connected to the second storage unit 32b and the third storage unit 32c, and this signal current (difference signal) write operation starts.

  In the signal current writing period, the first driving transistor DRT1 outputs a second driving current Io + Isig having a current amount corresponding to the second signal current by the gate control voltage written in the first holding capacitor C1. At this time, the second drive transistor DRT2 of the second storage unit 32b uses the gate control voltage written in the second storage capacitor C2 as a reference for the first drive current (Io) having a current amount corresponding to the first signal current Io. Output to the voltage power supply line Vss is possible. Therefore, of the second drive current Io + Isig supplied from the first drive transistor DRT1, the current Io corresponding to the first drive current is supplied from the first storage unit 32a through the first switch SST1 and the second drive transistor DRT2. It flows to the power supply line Vss.

  Of the second drive current Io + Isig, the remaining drive current, that is, the differential current ((Io + Isig) −Io) = Isig passes through the second switch SST3 to the third drive transistor DRT3 of the third storage unit 32c. Supplied. At this time, the third holding switch TCT2 is in an on state, and the third drive transistor DRT3 is in a writing state. Therefore, when the differential current Isig flows through the third drive transistor DRT3, the gate-source potential of the third drive transistor DRT3 corresponding to the current amount of the differential current Isig is written and stored in the third storage capacitor C3. .

  Next, the control signals SG3 and SG4 are turned off (high level), and the first and second switches SST1 and SST2 and the third holding switch TCT3 are turned off. Thereby, the write operation of the main signal current to the third storage unit 32c, that is, the differential current Isig is completed.

  Subsequently, as shown in FIGS. 12, 13, and 18, the control signal BG is turned on (low level), and the output switch BCT is turned on. The other switches are kept off. Thereby, the light emission operation is started.

  In the light emission period, the third drive transistor DRT3 outputs a drive current Isig having a current amount corresponding to the differential current Isig by the gate control voltage written in the third storage capacitor C3. The drive current Isig flows from the voltage power supply line Vdd through the organic EL element 16, the output switch BCT, and the third drive transistor DRT3. Thereby, the organic EL element 16 emits light. The organic EL element 16 maintains the light emitting state until the control signal BG becomes the off potential again after one frame period.

  According to the organic EL display device configured as described above, it is possible to obtain the same functions and effects as those of the first embodiment described above. In other words, an active matrix capable of performing a good display operation without being affected by the wiring capacity, reducing the constant current circuit, reducing the frame area, and reducing the display unevenness caused by the constant current circuit. A mold display device is obtained. Further, during the light emission period, only the differential current for causing the organic EL element 16 to emit light is supplied to the organic EL element, and there is no need to flow a drive current to the first storage unit and the second storage unit. Therefore, it is possible to greatly reduce the power consumption associated with image display.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

  In the above-described embodiments, the semiconductor layer of the thin film transistor is not limited to polysilicon, but can be composed of amorphous silicon. The self-luminous elements constituting the display pixels are not limited to organic EL elements, and various display elements capable of self-luminance are applicable.

FIG. 1 is a plan view schematically showing an organic EL display device according to the first embodiment of the present invention. FIG. 2 is a plan view showing an equivalent circuit of display pixels in the organic EL display device. FIG. 3 is a cross-sectional view showing a driving transistor and an organic EL element of the organic EL display device. FIG. 4 is a diagram showing ON / OFF (high, Low) timings of control signals in the organic EL display device. FIG. 5 is a diagram showing the on / off timing of each switch in the organic EL display device. FIG. 6 is a plan view showing an equivalent circuit of the display pixel when writing the first signal current (P channel) in the organic EL display device. FIG. 7 is a plan view showing an equivalent circuit of a display pixel when writing the first signal current (N channel) in the organic EL display device. FIG. 8 is a plan view showing an equivalent circuit of the display pixel when writing the second signal current (provisional signal) in the organic EL display device. FIG. 9 is a plan view showing an equivalent circuit of the display pixel when the main signal (differential current) is written in the organic EL display device. FIG. 10 is a plan view showing an equivalent circuit of the display pixel during the light emitting operation of the organic EL display device. FIG. 11 is a plan view showing an equivalent circuit of a display pixel in the organic EL display device according to the second embodiment of the present invention. FIG. 12 is a diagram showing ON / OFF (high, Low) timings of control signals in the organic EL display device. FIG. 13 is a diagram showing the on / off timing of each switch in the organic EL display device. FIG. 14 is a plan view showing an equivalent circuit of the display pixel at the time of writing the first signal current (P channel) in the organic EL display device according to the second embodiment. FIG. 15 is a plan view showing an equivalent circuit of the display pixel at the time of writing the first signal current (N channel) in the organic EL display device according to the second embodiment. FIG. 16 is a plan view showing an equivalent circuit of the display pixel when writing the second signal current (provisional signal) in the organic EL display device according to the second embodiment. FIG. 17 is a plan view showing an equivalent circuit of a display pixel when writing the main signal (differential current) of the organic EL display device according to the second embodiment. FIG. 18 is a plan view showing an equivalent circuit of the display pixel during the light emitting operation of the organic EL display device according to the second embodiment.

Explanation of symbols

8 ... Insulating substrate, 10 ... Organic EL panel, 12 ... Controller,
14a, 14b ... scanning line drive circuit, 15 ... signal line drive circuit, 16 ... organic EL element,
18 ... Pixel circuit, SST1 ... Pixel switch, SST2 ... First switch,
SST3 ... second switch, DRT1 ... first drive transistor,
DRT2 ... second drive transistor, DRT3 ... third drive transistor,
TCT1 ... first holding switch, TCT2 ... second holding switch,
TCT3 ... third holding switch, BCT ... output switch, 30 ... source IC

Claims (7)

A plurality of pixel portions including a display element and a pixel circuit for supplying a driving current to the display element, the pixel parts being arranged in a matrix on the substrate;
A plurality of video signal lines connected to each column of the pixel portion;
A signal line driving circuit that supplies a first signal current to the pixel circuit via the video signal line and then supplies a second signal current to the pixel circuit via the video signal line;
Each of the pixel circuits stores a first switch that stores a pixel switch that controls selection and non-selection of the pixel unit and a first drive current corresponding to the first signal current when the pixel unit is selected. A first storage unit for supplying a current and storing a second drive current corresponding to the second signal current; and a first drive current supplied from the first storage unit when the pixel unit is not selected. Storing a differential current between a second storage unit to be stored, a second drive current stored in the first storage unit when the pixel unit is not selected, and a first drive current stored in the second storage unit; And a third storage unit that outputs the stored difference current as a drive current to the display element.   The first storage unit includes a first drive transistor that is formed of a P-channel thin film transistor and is connected between voltage power supplies and outputs a first drive current and a second drive current, and the second storage unit includes And a second drive transistor that is formed of an N-channel thin film transistor and is connected between voltage power supplies and outputs a first drive current written by the first drive transistor, and the third storage unit includes P 2. The active device according to claim 1, further comprising a third driving transistor that is formed of a channel-type thin film transistor and that is connected between voltage power supplies and outputs the differential current written by the first and second driving transistors. Matrix type display device.   The first storage unit includes a first drive transistor that is formed of a P-channel thin film transistor and is connected between voltage power supplies and outputs a first drive current and a second drive current, and the second storage unit includes And a second driving transistor that is formed of an N-channel thin film transistor and is connected between voltage power supplies and outputs a first driving current written by the first driving transistor, and the third storage unit includes N 2. The active device according to claim 1, further comprising a third driving transistor that is formed of a channel-type thin film transistor and that is connected between voltage power supplies and outputs the differential current written by the first and second driving transistors. Matrix type display device.   4. The signal line driving circuit includes an N-channel IC that supplies a first signal current and a second signal current to the first storage unit of each pixel unit through the video signal line. The active matrix display device according to item. Each of the pixel circuits has an output switch connected in series with the display element and a third drive transistor between voltage power sources,
The first storage unit is formed of a transistor and a first storage capacitor that holds a potential between the source and gate of the first drive transistor, and is connected to the gate and drain of the first drive transistor. A first holding switch for controlling conduction and non-conduction of the driving transistor,
The pixel switch is connected between the drain of the first driving transistor and the drain of the first holding switch and the signal line,
The second memory unit is formed of a transistor and a second storage capacitor that holds a potential between the source and gate of the second drive transistor, and is connected to the gate and drain of the second drive transistor. A second holding switch for controlling conduction and non-conduction of the driving transistor; and a first switch formed by a transistor and connected to the drain of the first driving transistor and the drain of the second driving transistor;
The third storage unit is formed of a transistor and a third storage capacitor that holds a potential between the source and gate of the third drive transistor, and is connected to the gate and drain of the third drive transistor. A third holding switch for controlling conduction and non-conduction of the driving transistor, and a second switch formed by a transistor and connected between the drain of the third driving transistor and the first switch. Item 5. The active matrix display device according to any one of Items 1 to 4.   6. The active matrix display device according to claim 5, wherein the transistor, the first driving transistor, the second driving transistor, and the second driving transistor are configured by thin film transistors using polysilicon as a semiconductor layer.   The active matrix display device according to claim 1, wherein the display element is a self-light-emitting element having an organic light-emitting layer between opposed electrodes.

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