JP2007025226A - Active matrix type display device and driving method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an active matrix type display device capable of reducing difference in an amount of displacement at termination of writing and at the start of writing of a video signal and with high gradation reproducibility in a low gradation area. <P>SOLUTION: The active matrix type display has a plurality of display pixels PX arranged like a matrix. When threshold voltage of a display element 16 is considered as Vth, e(V), potential of a first voltage power line is considered as Vss(V), parasitic capacitance added to a drain of a drive transistor 22 is considered as Cx(F), video signal current for obtaining black gradation is considered as Ib(A) and drain potential of the drive transistor at a point of time when writing of black gradation signal current is terminated is considered as Vp(V), an interval between off timing of an output switch of n lines when writing of the signal current is terminated and on timing of a pixel switch of n lines when writing of the signal current is started is set approximately to Cx×äVp-(Vss+Vth, e)}/Ib. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an active matrix display device in which display pixels including display elements such as organic electroluminescence (hereinafter referred to as EL) elements are arranged in a matrix form and a driving method thereof.

  2. Description of the Related Art Planar active matrix display devices are widely used as display devices for personal computers, portable information terminals, and televisions. In recent years, as such a flat-type active matrix display device, an organic EL display device using a self-luminous element such as an organic EL element has attracted attention and has been actively researched and developed. This organic EL display device does not require a backlight that obstructs the reduction in thickness and weight, is suitable for moving image reproduction because of its high-speed response, and further has a feature that it can be used even in cold regions because the luminance does not decrease at low temperatures. .

  In general, an organic EL display device includes a plurality of display pixels arranged in a plurality of rows and a plurality of columns and constituting a display screen, a plurality of scanning lines extending along each row of display pixels, and a column of display pixels. A plurality of extended signal lines, a scanning line driving circuit for driving each scanning line, a signal line driving circuit for driving each signal line, and the like are provided. Each display pixel includes an organic EL element that is a self-light-emitting element and a pixel circuit that supplies a drive current to the organic EL element.

  For example, as disclosed in Patent Document 1, each pixel circuit includes an output switch that performs on / off control of a current flowing through the organic EL element, and a drive that controls the amount of current flowing through the organic EL element based on a video signal. A transistor, a storage capacitor for holding the gate control voltage of the driving transistor, a pixel switch for taking in the video signal current into the pixel circuit, and a switch for short-circuiting the gate and drain of the driving transistor when writing the video signal are provided. These switches and drive transistors are constituted by thin film transistors (hereinafter referred to as TFTs).

When writing the video signal current, the control signal line potential for controlling the pixel circuit is set to the on level, the pixel switch and the switch are turned on, and the control signal line potential for controlling the EL light emission is set to the off level. Turn off. As a result, the video signal current flows through the drive transistor, and the gate potential of the drive transistor is set to a potential corresponding to the current amount of the video signal current. Thereafter, the pixel switch and the switch are turned off, and the pixel circuit is disconnected from the video signal wiring. This video signal is written as a gate control voltage in the holding capacitor and held for a predetermined period. Subsequently, when the output switch is turned on, a current corresponding to the video signal is supplied to the organic EL element via the drive transistor and the output switch, and the organic EL element emits light at a desired luminance level.
JP 2003-280576 A

  In the pixel circuit as described above, a pixel switch composed of a TFT usually has a parasitic capacitance Cgs formed between a source and a gate. Due to the presence of the parasitic capacitance Cgs, the potential of the video signal line is displaced when the control signal line for controlling the pixel circuit is switched. There is no problem as long as the absolute value of the displacement amount is the same when the control signal line changes from on to off (when writing ends) and when the control signal line changes from off to on (when writing starts). However, when the potential at the node between the drive transistor and the output switch is different at the end of writing and at the start of writing, the amount of displacement of the video signal line potential is not the same, and the following problems may occur. .

  The difference in the amount of displacement of the video signal line potential between the end of writing and the start of writing is filled with the signal current supplied from the driver IC. However, when the video signal current is low, that is, the displacement is within the writing period. Can't fill the difference. In this case, a signal current that is smaller or larger than the original video signal current is written, and this causes a problem in gradation reproducibility in the low gradation region.

  The present invention has been made in view of the above points, and an object of the present invention is to reduce the difference in displacement of the video signal line potential between the end of writing of the video signal and the start of writing. An object of the present invention is to provide an active matrix display device with high reproducibility and a driving method thereof.

In order to achieve the above object, an active matrix display device according to an aspect of the present invention includes a plurality of pixel portions arranged in a matrix on a substrate, and a plurality of video signals connected to each column of the pixel portions. A plurality of first control signal lines and second control signal lines respectively connected to each row of the pixel portion,
Each pixel portion is connected between a low potential first voltage power supply line and a high potential second voltage power supply line, and emits light in response to a supply current; the second voltage power supply line and the display element A drive transistor for controlling the amount of current supplied to the display element according to a gate control voltage, a drain of the drive transistor and the display element, and the second transistor An output switch that is controlled to be turned on and off by a control signal from a control signal line, a transistor formed between a drain of the driving transistor and the video signal line, and an output switch from the first control signal line Connected between a pixel switch that is on / off controlled by a control signal and takes in a video signal from the video signal line to the pixel portion, and a gate and a drain of the driving transistor. And a switch that is turned on and off by a control signal from the first control signal line, and a storage capacitor that is connected between the gate and source of the drive transistor and holds a gate control voltage corresponding to the video signal. ,have.
The threshold voltage of the display element is Vth, e (V), the potential of the first voltage power supply line is Vss (V), the parasitic capacitance added to the drain of the driving transistor is Cx (F), and black gradation display is performed. When the video signal current to be obtained is Ib (A) and the drain potential of the driving transistor at the time when the writing of the black gradation signal current is finished is Vp (V), the nth row at the end of the writing of the signal current. The interval between the turn-off timing of the output switch and the turn-on timing of the pixel switch in the n-th row at the start of signal current writing
Cx × {Vp− (Vss + Vth, e)} / Ib.

An active matrix display device driving method according to another aspect of the present invention includes a plurality of video signal lines and a plurality of control signal lines, a current source for outputting a video signal to the video signal line, and the video signal line. And a pixel circuit that outputs a signal current corresponding to the video signal, and a plurality of pixels each having a resolution of 100 (ppi) or more, each including a display element that performs a display operation according to the signal current. A driving method for an active matrix display device comprising:
In the writing period in which the control signal lines are sequentially selected, each pixel in the selected row connects the current source and the pixel circuit via the video signal line, writes the video signal to the pixel circuit, and does not select Each pixel in a row connects the pixel circuit and the display element, outputs the signal current to the display element, disconnects the pixel circuit and the display element, and then selects an interval Is characterized by being 5 to 160 μsec.

A driving method of an active matrix display device according to another aspect of the present invention includes a plurality of video signal lines and a plurality of control signal lines, a current source for outputting a video signal to the video signal line, and the video signal line. And a plurality of pixels each having a resolution of 100 (ppi) or less, each including a display circuit that outputs a signal current corresponding to the video signal, and a display element that performs a display operation according to the signal current. A driving method for an active matrix display device comprising:
In the writing period in which the control signal lines are sequentially selected, each pixel in the selected row connects the current source and the pixel circuit via the video signal line, writes the video signal to the pixel circuit, and does not select Each pixel in a row connects the pixel circuit and the display element, outputs the signal current to the display element, disconnects the pixel circuit and the display element, and then selects an interval Is characterized by being 1 to 36 μsec. According to the active matrix display device configured as described above and its driving method, in each pixel unit, the potential of a node (point P) located between the drain of the driving transistor and the output switch is determined by the output switch. During the light emission period that is on, the value corresponds to the voltage applied to the display element in accordance with the light emission luminance. At the time of black gradation display, the potential at the point P is a potential obtained by adding the threshold voltage (Vth, e) of the display element to the potential (Vss) of the first voltage power supply line.

  If the output switch is turned off before the writing of the signal current is started, the current is supplied through the driving transistor thereafter, so that the potential at the point P gradually shifts to the potential of the second voltage power supply line. Since the gate control potential of the driving transistor is held by the holding capacitor, the displacement of the P-point potential proceeds by a constant current (Ib) corresponding to black gradation display. The state of the same potential as the P point potential at the time of writing the signal current exists in the middle of this displacement. Therefore, by appropriately setting the pixel switch ON timing based on the output switch OFF timing, video signal writing can be started at substantially the same potential as that at the end of writing.

  According to the present invention, it is possible to reduce a difference in displacement of the video signal line potential between the end of video signal writing and the start of writing, and an active matrix display device having high gradation reproducibility in a low gradation region and its A driving method can be provided.

Hereinafter, an active matrix organic EL display device according to an embodiment of the present invention will be described in detail with reference to the drawings.
As shown in FIG. 1, the organic EL display device includes an organic EL panel 10 and a controller 12 that controls the organic EL panel 10.

  The organic EL panel 10 is arranged in a matrix on a light-transmitting insulating substrate 8 such as a glass plate, and is connected to each row of display pixels, each of which is connected to each row of display pixels mx that constitutes a display region 11. A first control signal line Y (1 to n) and a second control signal line Bg (1 to n) provided independently for each n lines, and m signal lines X respectively connected to each column of display pixels. (1 to m), the first and second control signal lines Y (1 to n), Bg (1 to n) are sequentially driven for each row of display pixels, and a plurality of signal lines X ( 1 to m) is provided.

  Each display pixel PX includes, as a display element, an organic EL element 16 that is a self-luminous element, and a pixel circuit 18 that supplies a drive current to the organic EL element. FIG. 2 shows an equivalent circuit of the display pixel PX. The pixel circuit 18 is a current signal type pixel circuit that controls light emission of the organic EL element 16 in accordance with a video signal composed of a current signal, and includes a pixel switch 20, a drive transistor 22, a switch 24, an output switch 26, and a storage capacitor Cs. It has. The pixel switch 20, the drive transistor 22, the switch 24, and the output switch 26 are composed of thin film transistors of the same conductivity type, for example, a P channel type.

  The drive transistor 22, the output switch 26, and the organic EL element 16 are connected in series between the low-potential first voltage power supply line Vss and the high-potential second voltage power supply line Vdd. The source of the drive transistor 22 is connected to the second voltage power supply line Vdd. The organic EL element 16 has one electrode, here the cathode, connected to the first voltage power supply line Vss. The output switch 26 has a source connected to the drain of the drive transistor 22, a drain connected to the anode of the organic EL element 16, and a gate connected to the second control signal line Bg. The first and second voltage power supply lines Vss and Vdd are set to potentials of −9 V and +6 V, for example.

  The drive transistor 22 outputs a signal current corresponding to the video signal to the organic EL element 16. The output switch 26 is ON (conductive state) and OFF (non-conductive state) controlled by the control signal Sb from the second control signal line Bg, and controls connection / disconnection between the drive transistor 22 and the organic EL element 16.

  A node between the drain of the driving transistor 22 and the source of the output switch 26 is a point P, and a parasitic capacitance generated at the drain of the driving transistor 22 is Cx. In the present embodiment, the parasitic capacitance Cx indicates the sum of the parasitic capacitances of the pixel switch 20, the switch 24, the driving transistor 22, and the output transistor 26.

  The holding capacitor Cs is connected between the source and gate of the driving transistor 22 and holds the gate control potential of the driving transistor 22 determined by the video signal. The storage capacitor Cs has a pair of plate-like electrodes opposed in parallel to each other. Here, the holding capacitor Cs is formed as a parallel plate capacitor by a gate electrode film of a driving transistor and a polysilicon layer.

  The pixel switch 20 is connected between the corresponding signal line X and the drain of the drive transistor 22, and its gate is connected to the first control signal line Y. The pixel switch 20 is controlled to be on (conductive state) and off (non-conductive state) in response to the control signal Sa supplied from the first control signal line Y, and takes in the video signal from the corresponding signal line X.

  The switch 24 is connected between the drain and gate of the drive transistor 22, and the gate is connected to the first control signal line Y. The switch 24 is turned on (conducting state) and off (nonconducting state) in accordance with a control signal Sa from the first control signal line Y, and controls connection and disconnection between the gate and drain of the drive transistor 22.

  In this embodiment, all the thin film transistors constituting the pixel circuit 18 are formed in the same process and the same layer structure, and are top gate thin film transistors using polysilicon as a semiconductor layer. By constituting all the thin film transistors with the same conductivity type, an increase in the number of manufacturing steps can be suppressed.

Next, the configuration of the drive transistor 22 and the organic EL element 16 will be described in detail with reference to FIG.
The P-channel type thin film transistor that constitutes the drive transistor 22 includes a semiconductor layer 50 made of polysilicon formed on the insulating substrate 8, and this semiconductor layer is formed between the source region 50a, the drain region 50b, and the source and drain regions. It has a channel region 50c located. A gate insulating film 52 is formed over the semiconductor layer 50, and a gate electrode G is provided on the gate insulating film so as to face the channel region 50c. An interlayer insulating film 54 is formed over the gate electrode G, and a source electrode (source) S and a drain electrode (drain) D are provided on the interlayer insulating film. The source electrode S and the drain electrode D are respectively connected to the source region 50a and the drain region 50b of the semiconductor layer 50 through contacts formed through the interlayer insulating film 54 and the gate insulating film 52, respectively. The drain electrode D of the drive transistor 22 is connected to the output switch 26 via a wiring formed on the interlayer insulating film 54. The thin film transistors constituting the pixel switch 20, the switch 24, and the output switch 26 are also formed in the same structure as described above.

  A plurality of wirings including the video signal wiring X are provided on the interlayer insulating film 54. A protective film 56 is formed on the interlayer insulating film 54 so as to cover the source electrode S, the drain electrode D, and the wiring. On the protective film 56, a hydrophilic film 58 and a partition film 60 are laminated in this order.

  The organic EL element 16 has a structure in which an organic light emitting layer 64 containing a luminescent organic compound is sandwiched between an anode 62 and a cathode 66. The anode 62 is made of a transparent electrode material such as ITO (indium tin oxide) and is provided on the protective film 56. Of the hydrophilic film 58 and the partition film 60, a portion corresponding to the anode 62 is removed by etching. An anode buffer layer 63 and an organic light emitting layer 64 are formed on the anode 62, and a cathode 66 made of barium / aluminum alloy is laminated on the organic light emitting layer 64 and the partition wall film 60.

  In the organic EL element 16 having such a structure, when the holes injected from the anode 62 and the electrons injected from the cathode 66 recombine inside the organic light emitting layer 64, organic molecules constituting the organic light emitting layer are formed. Is excited to generate excitons. The excitons emit light in the process of radiation deactivation, and the light is emitted from the organic light emitting layer 64 to the outside through the transparent anode 62 and the insulating substrate 8.

  Here, the case where the anode 62 is connected to the second voltage power supply line Vdd via the output switch 26 and the P-channel type drive transistor 22 and the cathode 66 is connected to the first voltage power supply Vss has been described. The anode 62 may be connected to the first voltage power supply Vss via the drain of the output switch 26 to the drain of the driving transistor 22. In either case, it is necessary to form the light emitting surface side with a transparent conductive material. For example, when the cathode 66 is disposed on the light emitting surface side, the alkaline earth metal and the rare earth metal are thin enough to have light transmittance. This can be achieved by forming.

  On the other hand, the controller 12 shown in FIG. 1 is formed on a printed circuit board disposed outside the organic EL panel 10 and controls the scanning line driving circuit 14 and the signal line driving circuit 15. The controller 12 receives a digital video signal and a synchronization signal supplied from the outside, and generates a vertical scanning control signal for controlling the vertical scanning timing and a horizontal scanning control signal for controlling the horizontal scanning timing based on the synchronizing signal. The scanning control signal and the horizontal scanning control signal are supplied to the scanning line driving circuit 14 and the signal line driving circuit 15, respectively, and the digital video signal is supplied to the signal line driving circuit 15 in synchronization with the horizontal and vertical scanning timings.

  The signal line driving circuit 15 converts the video signals Data1 to Data sequentially obtained in each horizontal scanning period under the control of the horizontal scanning control signal into an analog format and supplies them in parallel to the plurality of signal lines X (1 to m) as current signals. To do. The scanning line driving circuit 14 includes a shift register, an output buffer, etc., sequentially transfers a horizontal scanning start pulse supplied from the outside to the next stage, and outputs two types of control signals to the display pixels PX in each row via the output buffer. That is, the control signal Sa and the control signal Sb are supplied. As a result, the control signal Sa and the control signal Sb are supplied to the first control signal line Y (1 to n) and the second control signal line Bg (1 to n), respectively, and the pixel switch 20, the switch 24, and the output The switch 26 is driven.

The operation of the pixel circuit 18 based on the output signals of the scanning line driving circuit 14 and the signal line driving circuit 15 will be described with reference to the timing chart shown in FIG.
For example, the scanning line driving circuit 14 generates a pulse having a width corresponding to the signal writing period in each horizontal scanning period from the start signal a (Starta), the clock a (Clka), and the enable signal a (Enva). The pulse is sequentially output as a control signal Sa for each pixel row. The scanning line driving circuit 14 generates a pulse having a predetermined width corresponding to the light emission period from the start signal b (Startb), the clock b (Clkb), and the enable signal b (Envb), and uses the pulse as the control signal Sb. Output sequentially for each pixel row.

  The operation of the pixel circuit 18 is divided into a video signal writing operation and a light emission operation. For example, when writing the display pixel Px in the nth row, the output switch 26 is turned off in preparation for entering the writing operation. In this case, the output switch 26 is turned off through the second control signal line Bg. Here, the high-level control signal Sb is output, and the output switch 26 is turned off. Subsequently, as described later, a control signal Sa that turns on (conductive state) the pixel switch 20 and the switch 24 at a predetermined timing, here, a low level is output, and the video signal writing operation is started. .

In the video signal writing period, the driving transistor 22 is in a diode connection state, and the video signal current (Data (n)) supplied from the signal line driving circuit 15 to the corresponding video signal wiring X (1 to n) is a pixel. It is supplied to the selected display pixel PX via the switch 20. In the display pixel PX, the pixel switch 20 and the switch 24 are in the on state, and the captured video signal current is supplied to the driving transistor 22 to put the driving transistor 22 in the writing state. As a result, a write current flows from the first voltage power supply line Vdd to the video signal wiring X through the drive transistor 22, and the gate-source potential of the drive transistor 22 corresponding to the amount of the video signal current is written to the storage capacitor Cs.
Next, the control signal Sa becomes high level (off potential), and the pixel switch 20 and the switch 24 are turned off. Thereby, the video signal writing operation is completed.

  Subsequently, the control signal Sb becomes low level (on potential), and the output switch 26 is turned on. Thereby, the light emission operation is started. As shown in FIG. 4, in the light emission period, the drive transistor 22 is controlled by the gate control voltage written in the storage capacitor Cs, and outputs a light emission current having a current amount corresponding to the video signal current from the first voltage power supply line Vdd. Supply to the switch 26 side. This light emission current is supplied to the organic EL element 16 via the output switch 26. Thereby, the organic EL element 16 emits light, and the light emission operation is started. The organic EL element 16 maintains the light emission state until the control signal Sa is supplied again after one vertical period.

  As an example, the threshold voltage Vth, e = 5.0 (V) of the organic EL element 16, the first voltage power supply line potential Vss = −9 (V), the second voltage power supply line potential Vdd = 6 (V), the drive transistor The parasitic capacitance Cx added to the drain of 22 = 0.01 (pF), the signal current Ib = 3 (nA) for obtaining the black gradation display, and the drain of the driving transistor when the writing of the black gradation current is finished Description will be made assuming that the potential (P-point potential) is Vp = 4.5 (V).

  As shown in the timing chart of FIG. 4, in the display pixel Px, the P-point potential in the light emission period during black gradation display is (Vss + Vth, e) = − 4 (V). Next, when the output switch 26 is turned off in preparation for entering the write operation, the potential at the point P approaches Vdd = 6 (V) by the current supply from the second voltage power supply line Vdd via the drive transistor 22. At this time, the gate control voltage of the driving transistor 22 is held by the holding capacitor Cs. For this reason, the potential of the point P increases with a constant current of Ib = 3 (nA) which is a black gradation current. That is, the black gradation current Ib charges or discharges the parasitic capacitance Cx = 0.01 (pF) at the drain of the driving transistor 22. Therefore, the potential at the point P changes (rises) at dVp / dt = Ib / Cx = 0.3 (V / μsec).

The point P potential becomes the potential Vp = 4.5 (V) at the end of writing of the black gradation current, based on the point when the output switch 26 is turned off.
{Vp− (Vss + Vth, e)} / (Ib / Cx) = 8.5 / 0.3≈28 (μsec)
Later.

  Then, after the output switch 26 is turned off, the pixel switch 20 and the switch 24 are turned on at the above timing to start writing video signals. As a result, the P point potential can be made substantially the same at the end of writing and at the start of writing. Therefore, the difference in the amount of displacement of the video signal line potential can be reduced when the first control signal Sa for controlling the pixel switch 20 changes from on to off and when the first control signal Sa changes from off to on.

  For example, in an organic EL display device that is used as a display of a cellular phone and has a pixel portion resolution of 100 (ppi) or higher and a black gradation display luminance of 1 (cd / m2) or lower, The interval between the off timing of the output switch 26 of the display pixel Px and the on timing of the pixel switch 20 in the n-th row is set in the range of 5 to 160 (μsec). Further, in an organic EL display device that is used as a TV display and has a pixel portion resolution of 100 (ppi) or less and a black gradation display luminance of 1 (cd / m 2) or less, the display pixel in the n-th row The interval between the off timing of the Px output switch 26 and the on timing of the pixel switch 20 in the n-th row is set in the range of 1 to 36 (μsec).

As described above, according to the organic EL display device according to the present embodiment, the interval between the output switch OFF timing and the pixel switch ON timing in the display pixel is substantially the same.
It is set to be Cx × {Vp− (Vss + Vth, e)} / Ib.
As a result, the drain potential of the drive transistor at the start of writing becomes substantially the same as the potential at the end of writing, and the displacement amount of the video signal line potential when the first control signal line is switched from on to off, and the first control signal line The difference between the amount of displacement of the video signal line potential when switching from OFF to ON can be reduced. Therefore, even in low gradation display, it is possible to provide an active matrix type organic EL display device that prevents displacement of the video signal current and has high gradation reproducibility.

  In the above-described embodiment, the capacitance added to the drain of the driving transistor is described as the parasitic capacitance. However, the same applies to the case where an intentional capacitance is added to provide a margin for the on-timing setting of the pixel switch. Can be expected. In the above-described embodiment, the potential at the time of black gradation display is set. However, the present invention is not limited to this, and the same effect can be expected even when the potential is set at the time of low gradation display of 1 to 2 gradations.

  In addition, the present invention is not limited to the above-described embodiments as they are, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

  In the above-described embodiment, the case where all the thin film transistors constituting the pixel circuit are formed of the same conductivity type, here, the P channel type is described. However, the present invention is not limited to this, and all the thin film transistors are formed of N channel type thin film transistors. Is also possible. It is also possible to form pixel circuits in a mixture of thin film transistors of different conductivity types, such as pixel switches and switches composed of N-channel thin film transistors, and drive transistors and output switches composed of P-channel thin film transistors.

  Furthermore, the semiconductor layer of the thin film transistor is not limited to polysilicon, but may be composed of amorphous silicon. The self-light-emitting elements constituting the display pixel are not limited to organic EL elements, and various light-emitting elements capable of self-light emission are applicable.

1 is a circuit diagram showing a configuration of an organic EL display device according to an embodiment of the present invention. The figure which shows the equivalent circuit of the display pixel in the said organic EL display apparatus. Sectional drawing which shows a part of said organic electroluminescence display. 4 is a timing chart for explaining the operation of the display pixel.

Explanation of symbols

12 ... Controller, 14 ... Scan line drive circuit,
15 ... signal line drive circuit, 16 ... organic EL element, 18 ... pixel circuit,
20 ... Pixel switch, 22 ... Drive transistor,
24 ... switch, 26 ... output switch,
62 ... anode, 64 ... organic light emitting layer, 66 ... cathode,
PX ... display pixel, Vdd ... first voltage power line, Vss ... second voltage power line,
Y: first control signal line, X: video signal line, Bg: second control signal line,
Cs: holding capacity, Cx: parasitic capacity.

Claims (7)

A plurality of pixel portions arranged in a matrix on the substrate;
A plurality of video signal lines connected to each column of the pixel portion;
A plurality of first control signal lines and second control signal lines connected to each row of the pixel portion,
Each pixel portion is connected between a low potential first voltage power supply line and a high potential second voltage power supply line, and emits light in response to a supply current; the second voltage power supply line and the display element A drive transistor for controlling the amount of current supplied to the display element according to a gate control voltage, a drain of the drive transistor and the display element, and the second transistor An output switch that is controlled to be turned on and off by a control signal from a control signal line, a transistor formed between a drain of the driving transistor and the video signal line, and an output switch from the first control signal line Connected between a pixel switch that is on / off controlled by a control signal and takes in a video signal from the video signal line to the pixel portion, and a gate and a drain of the driving transistor. And a switch that is turned on and off by a control signal from the first control signal line, and a storage capacitor that is connected between the gate and source of the drive transistor and holds a gate control voltage corresponding to the video signal. Have
The threshold voltage of the display element is Vth, e (V), the potential of the first voltage power supply line is Vss (V), the parasitic capacitance added to the drain of the driving transistor is Cx (F), and black gradation display is performed. When the video signal current to obtain is Ib (A) and the drain potential of the driving transistor at the time when the writing of the black gradation signal current is finished is Vp (V),
The interval between the turn-off timing of the output switch of the n-th row at the end of the signal current write and the turn-on timing of the pixel switch of the n-th row at the start of the write of the signal current is approximately
An active matrix display device set to Cx × {Vp− (Vss + Vth, e)} / Ib.   The resolution of the pixel portion is 100 (ppi) or more, the display luminance of black gradation is 1 (cd / m 2) or less, the off-timing of the n-th row output switch and the on-timing of the n-th row pixel switch The active matrix display device according to claim 1, wherein an interval between the active matrix display device and the display device is in a range of 5 to 160 (μsec).   The resolution of the pixel portion is 100 (ppi) or less, the display luminance of black gradation is 1 (cd / m 2) or less, the off timing of the output switch of the nth row, and the on timing of the pixel switch of the nth row The active matrix display device according to claim 1, wherein an interval between the active matrix display device and the display device is in a range of 1 to 36 (μsec).   4. The active matrix display device according to claim 1, wherein the display element is a self-light-emitting element having an organic light-emitting layer between opposed electrodes.   5. The active matrix display device according to claim 1, wherein each of the driving transistor, the switch, the output switch, and the pixel switch includes a thin film transistor that uses polysilicon as a semiconductor layer. 6. A plurality of video signal lines and a plurality of control signal lines;
A current source for outputting a video signal to the video signal line;
A plurality of resolutions each including a pixel circuit arranged along the video signal line and outputting a signal current corresponding to the video signal and a display element that performs a display operation according to the signal current is 100 (ppi) or more A driving method of an active matrix display device comprising:
In a writing period for sequentially selecting the control signal lines,
Each pixel in the selected row connects the current source and the pixel circuit via the video signal line, and writes the video signal to the pixel circuit,
Each pixel in the non-selected row connects the pixel circuit and the display element, and outputs the signal current to the display element,
A method for driving an active matrix display device, characterized in that an interval between disconnection of the pixel circuit and the display element and subsequent selection is 5 to 160 μsec. A plurality of video signal lines and a plurality of control signal lines;
A current source for outputting a video signal to the video signal line;
A plurality of resolutions each including a pixel circuit arranged along the video signal line and outputting a signal current according to the video signal and a display element that performs a display operation according to the signal current is 100 (ppi) or less A driving method of an active matrix display device comprising:
In a writing period for sequentially selecting the control signal lines,
Each pixel in the selected row connects the current source and the pixel circuit via the video signal line, and writes the video signal to the pixel circuit,
Each pixel in the non-selected row connects the pixel circuit and the display element, and outputs the signal current to the display element,
A method for driving an active matrix display device, characterized in that an interval between disconnection of the pixel circuit and the display element and selection of the pixel circuit is 1 to 36 μsec.

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