JP6702492B2 - Electro-optical device and electronic equipment - Google Patents

Description

The present invention relates to an electro-optical device and electronic equipment.

In recent years, various electro-optical devices that display images using light emitting elements such as organic light emitting diode (hereinafter referred to as “OLED”) elements have been proposed. In this electro-optical device, a pixel circuit including a light emitting element, a transistor and the like is provided corresponding to the pixel of the image to be displayed. Specifically, a plurality of pixel circuits corresponding to pixels of an image to be displayed are provided in a matrix, and a control line such as a scanning line is provided in each row to drive the plurality of pixel circuits. Target. (For example, refer to Patent Document 1).

JP, 2007-316462, A

By the way, in recent years, electro-optical devices are often required to have a smaller display size and a higher definition display. In this case, it is necessary to narrow the pitch of the control lines in order to arrange the pixel circuits with high density.
The present invention has been made in view of the above-mentioned circumstances, and one of the objects thereof is to realize a high-density wiring of a plurality of control lines including a plurality of scanning lines, thereby achieving a high-definition display or a display size. It is to realize the miniaturization of.

In order to achieve the above object, the electro-optical device according to the present invention includes a scanning line, a data line intersecting with the scanning line, and a pixel circuit provided corresponding to the intersection of the scanning line and the data line. And the pixel circuit is responsive to a data signal supplied via a driving transistor, a writing transistor whose gate is electrically connected to the scanning line, and a data signal supplied through the data line and the writing transistor. A first storage capacitor that holds an electric charge and a light emitting element that emits light with a brightness according to a magnitude of a current supplied through the driving transistor, and are perpendicular to a surface of a substrate on which the pixel circuit is formed. When viewed from another direction, the scanning line and the gate of the drive transistor overlap each other.
According to the present invention, since the scanning line is wired on the gate of the driving transistor, the space constraint when providing the scanning line is relaxed as compared with the case where the scanning line does not cross the gate of the driving transistor. To be done. As a result, it becomes possible to narrow the scanning line pitch and increase the wiring density. That is, according to the present invention, a plurality of pixel circuits can be arranged at a higher density, and high definition display and downsizing of the display size can be achieved. In the present invention, the write transistor may be electrically connected between the gate of the drive transistor and the data line, for example.

Further, in the electro-optical device according to the present invention, one or more control lines including a scanning line, a data line intersecting with the scanning line, and a pixel provided corresponding to the intersection of the scanning line and the data line. The pixel circuit includes a drive transistor, a write transistor whose gate is electrically connected to the scan line, and a data signal supplied via the data line and the write transistor. A first storage capacitor that holds a corresponding electric charge; and a light emitting element that emits light with a brightness according to the magnitude of the current supplied through the drive transistor, and the one or more control lines include the above A control line that overlaps with the gate of the drive transistor when viewed from a direction perpendicular to the surface of the substrate on which the pixel circuit is formed is included.
According to the present invention, since the control line is wired on the gate of the driving transistor, the space constraint when providing the control line is relaxed as compared with the case where the control line does not cross the gate of the driving transistor. To be done. As a result, the pitch of control lines can be narrowed and the density of wiring can be increased. That is, according to the present invention, a plurality of pixel circuits can be arranged at a higher density, and high definition display and downsizing of the display size can be achieved.

The electro-optical device further includes a scanning line driving circuit that controls the operation of the pixel circuit, and the writing transistor is turned on when the scanning line driving circuit supplies a first potential to the scanning line. When the scanning line driving circuit supplies a second potential to the scanning line, the scanning line driving circuit is turned off. When viewed from a direction perpendicular to the surface of the substrate on which the pixel circuit is formed, the scanning line and the driving transistor And a scanning line driving circuit switches the potential supplied to the scanning line from the second potential to the first potential as a first switching period, and the scanning line driving circuit scans the scanning line. When the period for switching the potential supplied to the line from the first potential to the second potential is the second switching period, the time length of the second switching period is longer than the time length of the first switching period, Preferably.

When the gate of the driving transistor and the scanning line intersect in a plan view, capacitance is parasitic between the gate of the driving transistor and the scanning line. Then, when the potential of the scanning line fluctuates rapidly, the influence of the fluctuation of the potential reaches the gate of the drive transistor, and the potential of the gate of the drive transistor changes.
The drive transistor supplies a current having a magnitude corresponding to the gate-source voltage determined when the writing transistor is turned off to the light emitting element, and the light emitting element emits light with a luminance according to the magnitude of the current. To do. Therefore, when the potential of the gate of the driving transistor changes when the writing transistor is turned off (that is, after the voltage that defines the brightness of the light emitting element is set), the light emitting element has a brightness different from the specified brightness. Light is emitted, and the display quality of the electro-optical device deteriorates.
On the other hand, the scanning line driving circuit according to the present invention changes the potential of the scanning line when the writing transistor is turned off more gently than the potential when the writing transistor is turned on. This prevents potential fluctuations of the scanning line when the writing transistor is turned off from propagating to the gate of the driving transistor, and enables the light emitting element to emit light with a prescribed brightness. That is, according to the electro-optical device of the present invention, it is possible to realize a narrower pitch of the control lines without deteriorating the display quality.

Also, the pixel circuit includes a first switching transistor electrically connected between a gate and a drain of the driving transistor, and the one or more control lines are electrically connected to a gate of the first switching transistor. The first control line may be included.
In this case, the first switching transistor is turned on when the scanning line driving circuit supplies a first potential to the first control line, and the scanning line driving circuit supplies a second potential to the first control line. When turned on, the first control line and the gate of the driving transistor overlap each other when viewed from a direction perpendicular to a surface of the substrate on which the pixel circuit is formed, and the scanning line driving circuit A period in which the potential supplied to one control line is switched from the second potential to the first potential is referred to as a third switching period, and the potential supplied to the first control line by the scanning line drive circuit is set to the first potential. When the period for switching from to the second potential is the fourth switching period, the time length of the fourth switching period is preferably longer than the time length of the third switching period.

When the gate of the driving transistor and the first switching transistor intersect in a plan view, a capacitance is parasitic between the gate of the driving transistor and the first control line. Then, when the potential of the first control line suddenly changes, the influence of the potential change reaches the gate of the drive transistor, and the potential of the gate of the drive transistor changes.
By the way, when the first switching transistor is turned on, the gate and the source of the drive transistor are electrically connected, and the gate-source voltage of the drive transistor is set to a value that compensates for the variation in the threshold voltage of each pixel circuit. . Therefore, when the potential of the gate of the driving transistor changes when the first switching transistor is turned off (that is, after the threshold compensation is performed), it becomes impossible to compensate the variation in the threshold voltage of the driving transistor for each pixel circuit, and The uniformity is lost.
On the other hand, the scanning line drive circuit according to this aspect causes the change in the potential of the first control line when the first switching transistor is turned off to change more gently than the change in the potential when the first switching transistor is turned on. This prevents the potential fluctuation of the first control line when the first switching transistor is turned off from propagating to the gate of the driving transistor, and the potential of the gate of the driving transistor changes from the threshold-compensated potential. Prevent that. That is, according to the electro-optical device of the present invention, even when the first control line is arranged on the gate of the driving transistor, the occurrence of display unevenness that impairs display uniformity is prevented. Therefore, it is possible to achieve both miniaturization of the electro-optical device, high definition display, and high-quality display.

Further, the pixel circuit includes a second switching transistor electrically connected between the driving transistor and the light emitting element, and the one or more control lines are electrically connected to a gate of the second switching transistor. It may include a second control line connected.
In this case, the second switching transistor is turned on when the scanning line driving circuit supplies the first potential to the second control line, and the scanning line driving circuit supplies the second potential to the second control line. When turned on, the second control line and the gate of the driving transistor overlap each other when viewed from a direction perpendicular to the surface of the substrate on which the pixel circuit is formed, and the scanning line driving circuit A period in which the potential supplied to the second control line is switched from the second potential to the first potential is a fifth switching period, and the potential supplied to the second control line by the scanning line drive circuit is the first potential. It is preferable that the time length of the fifth switching period is longer than the time length of the sixth switching period, when the period for switching from to the second potential is the sixth switching period.
According to this aspect, it is possible to prevent the potential fluctuation generated in the second control line when the second switching transistor is turned on from propagating to the gate of the drive transistor. As a result, the pitch of the control lines can be narrowed without deteriorating the display quality.

The pixel circuit includes a third switching transistor electrically connected between a power supply line to which a predetermined reset potential is supplied and the light emitting element, and the one or more control lines include the third switching transistor. A third control line electrically connected to the gate of the transistor may be included.
In this case, the third switching transistor is turned on when the scanning line driving circuit supplies the first potential to the third control line, and the scanning line driving circuit supplies the second potential to the third control line. When turned on, the third control line and the gate of the driving transistor overlap each other when viewed from a direction perpendicular to the surface of the substrate on which the pixel circuit is formed, and the scanning line driving circuit A period in which the potential supplied to the third control line is switched from the second potential to the first potential is a seventh switching period, and the potential supplied to the third control line by the scanning line drive circuit is the first potential. When the period for switching from to the second potential is the eighth switching period, the time length of the eighth switching period is preferably longer than the time length of the seventh switching period.
According to this aspect, it is possible to prevent the potential fluctuation generated in the third control line when the third switching transistor is turned off from propagating to the gate of the drive transistor. As a result, the pitch of the control lines can be narrowed without deteriorating the display quality.

The electro-optical device described above corresponds to the data line, a data line drive circuit electrically connected to the data line, a control circuit for controlling operations of the scanning line drive circuit and the data line drive circuit, and the data line. And a second storage capacitor which holds the potential of the data line, the data line driving circuit includes a first potential line to which a predetermined initial potential is supplied from the control circuit, and a second storage capacitor from the control circuit. The level shift circuit includes a second potential line to which a reference potential is supplied and a level shift circuit provided corresponding to the data line. One electrode of the level shift circuit is electrically connected to the data line. A third storage capacitor, a first transistor electrically connected between one electrode of the third storage capacitor and the first potential line, and the other electrode of the third storage capacitor and the second potential line. And a second transistor electrically connected between the first transistor and the second transistor, the control circuit maintaining the first transistor in an on state in a first period, and the second circuit started after the first period ends. In the period, the scanning line driving circuit maintains the write transistor in an ON state, the control circuit maintains the first transistor in an OFF state, and the second transistor in an ON state, In a third period started after the second period ends, the scan line driving circuit maintains the write transistor in an on state, and the control circuit turns the first transistor and the second transistor in an off state. It is preferable that the other electrode of the third storage capacitor is supplied with a potential based on an image signal that defines the brightness of the light emitting element.

According to the present invention, the data line is connected to the second storage capacitor and the third storage capacitor, and the other electrode of the third storage capacitor is supplied with a potential based on the image signal that defines the luminance of the light emitting element. To be done. Therefore, the fluctuation range of the potential of the data line is a width obtained by compressing the fluctuation range of the potential supplied to the other electrode of the third storage capacitor according to the capacitance ratio of the second storage capacitor and the third storage capacitor. That is, the variation range of the potential of the data line is narrower than the variation range of the potential based on the image signal. As a result, the potential of the gate of the drive transistor can be set with fine precision without carving the image signal with fine precision. Therefore, the current can be accurately supplied to the light emitting element, and high quality display can be performed. Further, since the potential change width of the data line can be suppressed to be small, it is possible to prevent the occurrence of crosstalk or unevenness due to the potential change of the data line.

In the electro-optical device according to the aspect of the invention, the potential of the gate of the drive transistor is changed by supplying the charge from the one electrode of the third storage capacitor to the first storage capacitor and the second storage capacitor via the data line. To decide. Specifically, the potential of the gate of the drive transistor is supplied from the capacitance value of the first storage capacitor, the capacitance value of the second storage capacitor, and the third storage capacitor to the first storage capacitor and the second storage capacitor. It is determined by the amount of charge. If the electro-optical device does not include the second storage capacitor, the potential of the gate of the drive transistor is determined by the capacitance value of the first storage capacitor and the charge supplied by the third storage capacitor. Therefore, when the capacitance value of the first storage capacitor has a relative variation in each pixel circuit due to an error in the semiconductor process, the potential of the gate of the driving transistor also varies in each pixel circuit. In this case, display unevenness occurs and display quality deteriorates.
On the other hand, the present invention includes the second storage capacitor that holds the potential of the data line. Since the second storage capacitor is provided corresponding to each of the data lines, it can be configured to have an electrode having a larger area than that of the first storage capacitor provided in the pixel circuit. Therefore, the second storage capacitor has a smaller relative variation in the capacitance value due to the error in the semiconductor process than the first storage capacitor. As a result, it is possible to prevent the gate potential of the drive transistor from varying for each pixel circuit, and it is possible to perform high-quality display in which uneven display is prevented.

The level shift circuit includes a fourth storage capacitor, and the image is displayed on one electrode of the fourth storage capacitor in at least a part of a period from the start of the first period to the start of the third period. It is preferable that the potential indicated by the signal be supplied and that one electrode of the fourth storage capacitor be electrically connected to the other electrode of the third storage capacitor in the third period.

According to the present invention, in the first period and the second period, the image signal is supplied to one electrode of the fourth storage capacitor and is temporarily stored, and then in the third period, via the third storage capacitor. Is supplied to the gate of the drive transistor.
If the electro-optical device does not include the fourth storage capacitor, all the operations of supplying the potential indicated by the image signal to the gate of the driving transistor must be performed in the third period, and the third period is sufficiently long. Must be set.
On the other hand, according to the present invention, in the first period and the second period, the operation of supplying the image signal and the operation of initializing the data lines and the like are performed in parallel. Time constraints can be relaxed. As a result, it is possible to reduce the speed of the image signal supply operation, and it is possible to secure a sufficient period for initializing the data lines and the like.
Further, according to the present invention, the magnitude of the potential change based on the image signal is compressed using the fourth holding capacitor in addition to the first holding capacitor, the second holding capacitor, and the third holding capacitor. Therefore, the current can be supplied to the light emitting element with fine accuracy.

Further, the scan line driving circuit maintains the first switching transistor in an ON state in the second period, maintains the first switching transistor in an OFF state in a period other than the second period, and It is preferable to maintain the third switching transistor in an ON state and maintain the second switching transistor in an OFF state during one period, the second period, and the third period.

According to the present invention, by turning on the first switching transistor in the second period, the potential of the gate of the drive transistor can be set to a potential corresponding to the threshold voltage of the drive transistor, and the drive for each pixel circuit can be performed. It is possible to compensate for variations in the threshold voltage of the transistor.
Further, according to the present invention, by turning on the third switching transistor in the first period to the third period, it is possible to suppress the influence of the holding voltage of the capacitance parasitic on the light emitting element.

Note that the present invention can be conceptualized as an electronic device including the electro-optical device, in addition to the electro-optical device. The electronic device typically includes a display device such as a head mounted display (HMD) or an electronic viewfinder.

It is a perspective view showing the composition of the electro-optical device concerning the embodiment of the present invention. It is a figure which shows the structure of the same electro-optical device. It is a figure which shows the data line drive circuit in the same electro-optical device. It is a figure which shows the pixel circuit in the same electro-optical device. FIG. 3 is a plan view showing a configuration of a pixel circuit in the same electro-optical device. FIG. 3 is a partial cross-sectional view showing the configuration of a pixel circuit in the same electro-optical device. 3 is a timing chart showing the operation of the same electro-optical device. FIG. 3 is an operation explanatory diagram of the same electro-optical device. It is a figure explaining the electric potential change of the gate node of the same electro-optical device. It is explanatory drawing which shows the amplitude compression of the data signal in the same electro-optical device. It is explanatory drawing which shows the characteristic of the transistor in the same electro-optical device. 9 is a plan view showing a configuration of a pixel circuit in an electro-optical device according to Modification Example 1. FIG. 3 is a timing chart showing the operation of the same electro-optical device. 11 is a plan view showing the configuration of a pixel circuit in an electro-optical device according to Modification 2. FIG. 3 is a timing chart showing the operation of the same electro-optical device. FIG. 6 is a perspective view showing an HMD using the electro-optical device according to the embodiment and the like. It is a figure which shows the optical structure of HMD.

Embodiments for carrying out the present invention will be described below with reference to the drawings.

<Embodiment>
FIG. 1 is a perspective view showing the configuration of an electro-optical device 1 according to an embodiment of the present invention. The electro-optical device 1 is, for example, a micro display that displays an image on a head mounted display.
As shown in FIG. 1, the electro-optical device 1 includes a display panel 2 and a control circuit 3 that controls the operation of the display panel 2. The display panel 2 includes a plurality of pixel circuits and a drive circuit that drives the pixel circuits. In the present embodiment, the plurality of pixel circuits and drive circuits included in the display panel 2 are formed on a silicon substrate, and an OLED that is an example of a light emitting element is used for the pixel circuits. The display panel 2 is housed in, for example, a frame-shaped case 82 that opens in the display section, and one end of an FPC (Flexible Printed Circuits) substrate 84 is connected to the display panel 2.
The control circuit 3 of the semiconductor chip is mounted on the FPC board 84 by COF (Chip On Film) technology, and a plurality of terminals 86 are provided to be connected to an upper circuit (not shown).

FIG. 2 is a block diagram showing the configuration of the electro-optical device 1 according to the embodiment. As described above, the electro-optical device 1 includes the display panel 2 and the control circuit 3.
Digital image data Video is supplied to the control circuit 3 from a higher-order circuit (not shown) in synchronization with the synchronization signal. Here, the image data Video is data that defines the gradation level of the pixel of the image to be displayed on the display panel 2 (strictly speaking, the display unit 100 described later) with, for example, 8 bits. The sync signal is a signal including a vertical sync signal, a horizontal sync signal, and a dot clock signal.
The control circuit 3 generates various control signals based on the synchronization signal and supplies the control signals to the display panel 2. Specifically, the control circuit 3 controls the display panel 2 with a control signal Ctr, a negative logic control signal /Gini, a positive logic control signal Gref, and a positive logic control signal Gcpl. Negative logic control signal /Gcpl, which has an inversion relationship, control signals Sel(1), Sel(2), Sel(3), and a control signal /Sel(1 that has a logic inversion relationship with respect to these signals. ), /Sel(2), /Sel(3). Here, the control signal Ctr is a signal including a plurality of signals such as a pulse signal, a clock signal, and an enable signal. The control signals Sel(1), Sel(2), and Sel(3) are collectively referred to as the control signal Sel, and the control signals /Sel(1), /Sel(2), and /Sel(3) are referred to as control signals. /Sel may be collectively referred to.
Further, the control circuit 3 supplies various potentials to the display panel 2. Specifically, the control circuit 3 supplies the display panel 2 with a predetermined reset potential Vorst, a predetermined initial potential Vini, a predetermined reference potential Vref, and the like.
Further, the control circuit 3 generates an analog image signal Vid based on the image data Video.
Specifically, the control circuit 3 is provided with a look-up table in which the potential indicated by the image signal Vid and the brightness of a light emitting element (OLED 130 described later) included in the display panel 2 are stored in association with each other. Then, the control circuit 3 refers to the lookup table to generate an image signal Vid indicating a potential corresponding to the luminance of the light emitting element defined by the image data Video, and supplies the image signal Vid to the display panel 2. To do.

As shown in FIG. 2, the display panel 2 includes a display unit 100 and a drive circuit (data line drive circuit 10 and scan line drive circuit 20) that drives the display unit 100.
In the display unit 100, pixel circuits 110 corresponding to the pixels of the image to be displayed are arranged in a matrix. Specifically, in the display unit 100, m rows of scanning lines 12 are provided extending in the horizontal direction (X direction) in the drawing, and data lines 14 of (3n) columns are grouped every three columns. Are extended in the vertical direction (Y direction) in the figure and are provided so as to be electrically insulated from each scanning line 12. A pixel circuit 110 is provided at the intersection of the m rows of scanning lines 12 and the (3n)th column of data lines 14. Therefore, in the present embodiment, the pixel circuits 110 are arranged in a matrix with m rows vertically and (3n) columns horizontally.

Here, both m and n are natural numbers. In order to distinguish rows in the matrix of the scanning lines 12 and the pixel circuits 110, the rows may be referred to as 1, 2, 3,..., (m−1), m rows in this order from the top. Similarly, in order to distinguish the columns (columns) of the data line 14 and the matrix of the pixel circuits 110, the columns may be referred to as 1, 2, 3,..., (3n−1), (3n) columns in order from the left in the figure. . Further, in order to generalize the group of the data lines 14 and use an integer j of 1 or more and n or less, the (3j-2)th column and (3j-1) are included in the jth group counted from the left. It means that the data lines 14 of the (3)th column and the (3j)th column belong.
The three pixel circuits 110 corresponding to the intersections of the scanning lines 12 in the same row and the data lines 14 in the three columns belonging to the same group are R (red), G (green), and B (blue) pixels, respectively. Correspondingly, these three pixels represent one dot of the color image to be displayed. That is, in the present embodiment, the color of one dot is expressed by the additive color mixture by the light emission of the OLED corresponding to RGB.

Further, as shown in FIG. 2, in the display unit 100, the (3n)-th row power supply lines 16 extend in the vertical direction and are provided so as to be electrically insulated from each scanning line 12. A predetermined reset potential Vorst is commonly supplied to each power supply line 16. Here, in order to distinguish the columns of the feeder line 16, the feeder line 16 may be referred to as the 1st, 2nd, 3rd,... (3n), (3n+1)th column in order from the left in the figure. Each of the power supply lines 16 in the first column to the (3n)th column is provided corresponding to each of the data lines 14 in the first column to the (3n)th column.
Further, the display panel 2 is provided with (3n) storage capacitors 50 corresponding to the data lines 14 in the first to (3n)th columns. The storage capacitor 50 has two electrodes. One electrode of the storage capacitor 50 is connected to the data line 14, and the other electrode is connected to the power supply line 16. That is, the storage capacitor 50 functions as a second storage capacitor that holds the potential of the data line 14. The storage capacitor 50 is preferably formed by sandwiching an insulator (dielectric) between the power supply line 16 and the data line 14 which are adjacent to each other. In this case, the distance between the power supply line 16 and the data line 14 which are adjacent to each other is determined so that the required capacity can be obtained. In the following, the capacitance value of the storage capacitor 50 will be referred to as Cdt.
In FIG. 2, the storage capacitor 50 is provided outside the display unit 100, but this is merely an equivalent circuit and may be provided inside the display unit 100. Further, the storage capacitor 50 may be provided from the inside to the outside of the display unit 100.

The scanning line drive circuit 20 generates a scanning signal Gwr for sequentially scanning the scanning lines 12 row by row over a frame period in accordance with the control signal Ctr. Here, the scanning signals Gwr supplied to the scanning lines 12 of the first, second, third,..., Mth rows are respectively Gwr(1), Gwr(2), Gwr(3),. ), Gwr(m).
In addition to the scanning signals Gwr(1) to Gwr(m), the scanning line driving circuit 20 generates various control signals synchronized with the scanning signal Gwr for each row and supplies them to the display unit 100. Illustration is omitted in FIG. The frame period is a period required for the electro-optical device 1 to display an image for one cut (frame). For example, if the frequency of the vertical synchronizing signal included in the synchronizing signal is 120 Hz, the The period is 8.3 milliseconds.

The data line driving circuit 10 includes (3n) level shift circuits LS provided in a one-to-one correspondence with each of the (3n) column data lines 14, and each of the three column data lines 14 forming each group. It is provided with n demultiplexers DM and a data signal supply circuit 70.
The data signal supply circuit 70 generates data signals Vd(1), Vd(2),..., Vd(n) based on the image signal Vid and the control signal Ctr supplied from the control circuit 3. That is, the data signal supply circuit 70 uses the data signals Vd(1), Vd(2),..., Vd(n) based on the time-division multiplexed image signal Vid to generate the data signals Vd(1), Vd(2). ,..., Vd(n) is generated. Then, the data signal supply circuit 70 supplies the data signals Vd(1), Vd(2),..., Vd(n) to the demultiplexers DM corresponding to the 1, 2,. Supply. In addition, the maximum value of potentials that the data signals Vd(1) to Vd(n) can take is Vmax, and the minimum value thereof is Vmin.

FIG. 3 is a circuit diagram for explaining the configurations of the demultiplexer DM and the level shift circuit LS. 3 representatively shows the demultiplexer DM belonging to the j-th group and the three level shift circuits LS connected to the demultiplexer DM. In the following, the demultiplexer DM belonging to the j-th group may be referred to as DM(j).

The configurations of the demultiplexer DM and the level shift circuit LS will be described below with reference to FIG. 3 in addition to FIG.
As shown in FIG. 3, the demultiplexer DM is an assembly of transmission gates 34 provided for each column, and sequentially supplies a data signal to the three columns forming each group. Here, the input ends of the transmission gates 34 corresponding to columns (3j-2), (3j-1), and (3j) belonging to the j-th group are commonly connected to each other, and the data signal Vd( j) is supplied. When the control signal Sel(1) is at the H level (when the control signal /Sel(1) is at the L level), the transmission gate 34 provided in the leftmost column (3j-2) in the jth group is ) On (conducting). Similarly, the transmission gate 34 provided in the (3j−1)th column which is the central column in the j-th group has the control signal Sel(2) at the H level (the control signal /Sel(2) is at the L level). When the control signal Sel(3) is at the H level (control signal /Sel(3)), the transmission gate 34 provided in the rightmost column (3j) in the j-th group is turned on (control signal /Sel(3)). Is at the L level).

The level shift circuit LS includes a set of a storage capacitor 41, a storage capacitor 44, a P-channel MOS type transistor 45 (first transistor), an N-channel MOS type transistor 43 (second transistor), and a transmission gate 42 for each column. , And shifts the potential of the data signal output from the output end of the transmission gate 34 of each column.
Here, the storage capacitor 44 has two electrodes. One electrode of the storage capacitor 44 is electrically connected to the data line 14 in the corresponding column and one of the source and the drain of the transistor 45. The other electrode of the storage capacitor 44 is electrically connected to the output end of the transmission gate 42 and one of the source and the drain of the transistor 43 via the node h1. That is, the storage capacitor 44 functions as a third storage capacitor whose one electrode is electrically connected to the data line 14. The capacity value of the storage capacitor 44 is Crf1.

The other of the source and the drain of the transistor 45 in each column is electrically connected to the power supply line 61 (first potential line). Further, the control circuit 3 commonly supplies the control signal /Gini to the gates of the transistors 45 in each column. Therefore, the transistor 45 electrically connects one electrode (and the data line 14) of the storage capacitor 44 and the power supply line 61 when the control signal /Gini is at L level, and the control signal /Gini is at H level. Sometimes electrically disconnected. The control circuit 3 supplies a predetermined initial potential Vini to the power supply line 61.
The other of the source and the drain of the transistor 43 in each column is electrically connected to the power supply line 62 (second potential line). Further, the control circuit 3 commonly supplies the control signal Gref to the gates of the transistors 43 in each column. Therefore, the transistor 43 electrically connects the other electrode of the storage capacitor 44 and the node h1 to the power supply line 62 when the control signal Gref is at the H level and when the control signal Gref is at the L level. To be disconnected. The control circuit 3 supplies the reference potential Vref to the power supply line 62.

The storage capacitor 41 has two electrodes. One electrode of the storage capacitor 41 is electrically connected to the input end of the transmission gate 42 via the node h2. The output end of the transmission gate 42 is electrically connected to the other electrode of the storage capacitor 44 via the node h1.
The control circuit 3 commonly supplies the control signal Gcpl and the control signal /Gcpl to the transmission gates 42 in each column. Therefore, the transmission gates 42 in each column are turned on all at once when the control signal Gcpl is at the H level (when the control signal /Gcpl is at the L level).
One electrode of the storage capacitor 41 in each column is electrically connected to the output end of the transmission gate 34 and the input end of the transmission gate 42 via the node h2. When the transmission gate 34 is turned on, the data signal Vd(j) is supplied to one electrode of the storage capacitor 41 via the output terminal of the transmission gate 34. That is, the storage capacitor 41 functions as a fourth storage capacitor whose one electrode is supplied with the data signal Vd(j). The other electrode of the storage capacitor 41 in each column is commonly connected to the power supply line 63 to which the potential Vss which is a fixed potential is supplied. Here, the potential Vss may correspond to the L level of the scanning signal or the control signal which is a logical signal. The capacity value of the storage capacitor 41 is Crf2.

The pixel circuit 110 will be described with reference to FIG. Since the pixel circuits 110 are electrically identical in configuration to each other, here, the i-th row is located in the i-th row and is located in the (3j−2)-th column in the leftmost column of the j-th group. The pixel circuit 110 of the (3j-2) column will be described as an example. It should be noted that i is a symbol for generally indicating a row in which the pixel circuits 110 are arranged, and is an integer of 1 or more and m or less.

As shown in FIG. 4, the pixel circuit 110 includes P-channel MOS type transistors 121 to 125, an OLED 130, and a storage capacitor 132. A scanning signal Gwr(i), control signals Gcmp(i), Gel(i), and Gorst(i) are supplied to the pixel circuit 110. Here, the scanning signal Gwr(i), the control signals Gcmp(i), Gel(i), and Gorst(i) are each supplied by the scanning line drive circuit 20 corresponding to the i-th row.
Although not shown in FIG. 2, on the display panel 2 (display unit 100), m rows of control lines 143 (first control lines) extending in the horizontal direction (X direction) in FIG. A control line 144 (second control line) extending in m rows and a control line 145 (third control line) extending in m in the horizontal direction are provided. Then, the scanning line drive circuit 20 controls signals Gcmp(1), Gcmp(2), Gcmp(3),..., Gcmp for the control lines 143 of the first, second, third,. , (m) are supplied to the control lines 144 of the first, second, third,..., Mth rows to control signals Gel(1), Gel(2), Gel(3),. ) Is supplied to the control lines 145 of the first, second, third,..., Mth rows, and control signals Gorst(1), Gorst(2), Gorst(3),. Supply. That is, the scanning line drive circuit 20 outputs the scanning signal Gwr(i), the control signals Gel(i), Gcmp(i), and Gorst(i) to the (3n) pixel circuits located in the i-th row. , Are commonly supplied via the scanning line 12 of the i-th row and the control lines 143, 144, and 145, respectively. Hereinafter, the scanning line 12, the control line 143, the control line 144, and the control line 145 may be collectively referred to as a “control line”. That is, the display panel 2 according to the present embodiment is provided with four control lines including the scanning line 12 in each row.

In the transistor 122, a gate is electrically connected to the i-th scanning line 12 and one of a source and a drain is electrically connected to the (3j−2)-th column data line 14. Further, the storage capacitor 132 has two electrodes. The other of the source and the drain of the transistor 122 is electrically connected to the gate of the transistor 121, one electrode of the storage capacitor 132, and one of the source and the drain of the transistor 123, respectively. That is, the transistor 122 is electrically connected between the gate of the transistor 121 and the data line 14, and functions as a write transistor that controls the electrical connection between the gate of the transistor 121 and the data line 14. Note that in the following, a wiring that electrically connects the gate of the transistor 121, the other of the source and the drain of the transistor 122, the one of the source and the drain of the transistor 123, and the one electrode of the storage capacitor 132 is described as follows. ) Sometimes called a gate node g.
The source of the transistor 121 is electrically connected to the power supply line 116, and the drain of the transistor 121 is electrically connected to the other of the source and the drain of the transistor 123 and the source of the transistor 124. Here, the power supply line 116 is supplied with the potential Vel which is the higher side of the power supply in the pixel circuit 110. The transistor 121 functions as a drive transistor that allows a current according to the voltage between the gate and the source of the transistor 121 to flow.
The gate of the transistor 123 is electrically connected to the control line 143 and the control signal Gcmp(i) is supplied. The transistor 123 functions as a first switching transistor that controls an electrical connection between the gate and the drain of the transistor 121.
The gate of the transistor 124 is electrically connected to the control line 144 and the control signal Gel(i) is supplied. The drain of the transistor 124 is electrically connected to the source of the transistor 125 and the anode 130a of the OLED 130, respectively. The transistor 124 functions as a second switching transistor that controls the electrical connection between the drain of the transistor 121 and the anode of the OLED 130.
The gate of the transistor 125 is electrically connected to the control line 145, and the control signal Gorst(i) is supplied. The drain of the transistor 125 is electrically connected to the power supply line 16 of the (3j−2)th column and is kept at the reset potential Vorst. The transistor 125 functions as a third switching transistor that controls the electrical connection between the power supply line 16 and the anode 130a of the OLED 130.
Since the display panel 2 is formed on the silicon substrate in the present embodiment, the substrate potential of the transistors 121 to 125 is set to the potential Vel.
Note that the sources and drains of the transistors 121 to 125 in the above may be interchanged depending on the channel types of the transistors 121 to 125 and potential relationships. The transistor may be a thin film transistor or a field effect transistor.

The storage capacitor 132 has one electrode electrically connected to the gate of the transistor 121 and the other electrode electrically connected to the power supply line 116. Therefore, the storage capacitor 132 functions as a first storage capacitor that holds the gate-source voltage of the transistor 121. The capacity value of the storage capacitor 132 is expressed as Cpix. At this time, the capacitance value Cdt of the storage capacitor 50, the capacitance value Crf1 of the storage capacitor 44, and the capacitance value Cpix of the storage capacitor 132 are
Cdt>Crf1>>Cpix
Is set. That is, Cdt is set to be larger than Crf1 and Cpix is set to be sufficiently smaller than Cdt and Crf1. Note that as the storage capacitor 132, a capacitor parasitic on the gate node g of the transistor 121 may be used, or a capacitor formed by sandwiching an insulating layer between different conductive layers in a silicon substrate may be used.

The anode 130 a of the OLED 130 is a pixel electrode provided individually for each pixel circuit 110. On the other hand, the cathode of the OLED 130 is the common electrode 118 that is commonly provided over the entire pixel circuit 110, and is maintained at the potential Vct on the lower side of the power source in the pixel circuit 110. The OLED 130 is an element in which a white organic EL layer is sandwiched between an anode 130a and a light-transmitting cathode on the silicon substrate. Then, on the emission side (cathode side) of the OLED 130, a color filter corresponding to any of RGB is overlaid.
In such an OLED 130, when a current flows from the anode 130a to the cathode, holes injected from the anode 130a and electrons injected from the cathode are recombined in the organic EL layer to generate excitons, and white light is emitted. Occur. The white light generated at this time passes through the cathode on the side opposite to the silicon substrate (anode 130a), is colored by the color filter, and is visually recognized by the observer.

Next, the structure of the pixel circuit 110 will be described with reference to FIGS.
FIG. 5 is a plan view showing the configuration of the pixel circuit 110 in the i-th row (3j−2) column. FIG. 5 shows a wiring structure when the pixel circuit 110 having the top emission structure is viewed in plan from the observation side. However, for simplification, the structure formed after the anode 130a of the OLED 130 is omitted. ing. Further, FIG. 6 is a partial cross-sectional view taken along the line Ee in FIG. In FIG. 6, only the anode 130a of the OLED 130 is shown, and the subsequent structure is omitted. Note that in FIGS. 5 and 6, the scales may be different in order to make each layer, each member, each region, and the like recognizable.

As shown in FIG. 6, each element forming the pixel circuit 110 is formed on the silicon substrate 150. In this embodiment, a P-type semiconductor substrate is used as the silicon substrate 150. An N well 160 is formed on almost the entire surface of the silicon substrate 150. Note that, in FIG. 5, in the plan view, only the region where the transistors 121 to 125 are provided and the vicinity thereof are hatched in the N well 160 so that the region where the transistors 121 to 125 are provided can be easily grasped. Is attached.
The potential Vel is supplied to the N well 160 via an N type diffusion layer (not shown). Therefore, the substrate potentials of the transistors 121 to 125 are the potential Vel.

As shown in FIGS. 5 and 6, a plurality of P-type diffusion layers are formed by doping the surface of the N well 160 with ions. Specifically, nine P-type diffusion layers P1 to P9 are formed on the surface of the N well 160 for each pixel circuit 110. These P-type diffusion layers P1 to P9 function as sources or drains of the transistors 121 to 125. Further, the gate insulating layer L0 is formed on the surfaces of the N well 160 and the P-type diffusion layers P1 to P9, and the gate electrodes G1 to G5 are formed on the surface of the gate insulating layer L0 by patterning. These gate electrodes G1 to G5 function as the gates of the transistors 121 to 125, respectively.

As shown in FIG. 5, the transistor 121 has a gate electrode G1, a P-type diffusion layer P1, and a P-type diffusion layer P2. Of these, the P-type diffusion layer P1 functions as the source of the transistor 121, and the P-type diffusion layer P2 functions as the drain of the transistor 121.
The transistor 122 also has a gate electrode G2, a P-type diffusion layer P3, and a P-type diffusion layer P4. Of these, the P-type diffusion layer P3 functions as one of the source and the drain of the transistor 122, and the P-type diffusion layer P4 functions as the other of the source and the drain of the transistor 122.
The transistor 123 has a gate electrode G3, a P-type diffusion layer P4, and a P-type diffusion layer P5. Of these, the P-type diffusion layer P4 functions as one of the source and the drain of the transistor 123, and the P-type diffusion layer P5 functions as the other of the source and the drain of the transistor 123. That is, the P-type diffusion layer P4 functions as the other of the source and the drain of the transistor 122, and also functions as one of the source and the drain of the transistor 123.
The transistor 124 has a gate electrode G4, a P-type diffusion layer P6, and a P-type diffusion layer P7. Of these, the P-type diffusion layer P6 functions as the source of the transistor 124, and the P-type diffusion layer P7 functions as the drain of the transistor 124.
In addition, in the present embodiment, the drain of the transistor 121, the other of the source and the drain of the transistor 123, and the source of the transistor 124 are configured by the individual P-type diffusion layers P2, P5, and P6, respectively. You may comprise by one P type diffusion layer. In this case, the relay node N13 described later may not be provided.
The transistor 125 has a gate electrode G5, a P-type diffusion layer P8, and a P-type diffusion layer P9. Of these, the P-type diffusion layer P8 functions as the source of the transistor 125, and the P-type diffusion layer P9 functions as the drain of the transistor 125.

As shown in FIG. 6, the first interlayer insulating layer L1 is formed so as to cover the gate electrodes G1 to G5 and the gate insulating layer L0.
By patterning a conductive wiring layer of aluminum or the like on the surface of the first interlayer insulating layer L1, the scanning line 12, the power supply line 116, and the control lines 143 to 145 are formed for each row. The relay nodes N11 to N16 and the branch portion 116a are formed for each pixel circuit 110. The wiring layer formed on the surface of the first interlayer insulating layer L1 may be collectively referred to as a first wiring layer.

As shown in FIG. 5, the power supply line 116 extends in the X direction intersecting with the Y axis direction and has a portion (branching portion 116a) branched in the Y direction for each pixel circuit 110. The branch part 116a has a part of the branch part 116a and the P-type diffusion layer P1 when viewed in a plan view (that is, when the pixel circuit 110 is viewed from a direction perpendicular to a surface of the silicon substrate 150 on which the pixel circuit 110 is arranged). And are provided so as to overlap each other. Further, as shown in FIGS. 5 and 6, the branch portion 116a is electrically connected to the P-type diffusion layer P1 via the contact hole Ha1 penetrating the first interlayer insulating layer L1. Note that, in FIG. 5, the contact hole is shown as a portion in which different wiring layers are overlapped with each other, and a “□” mark is attached to a “□” mark.

As shown in FIG. 5, the scanning line 12 extends in the X direction and is provided so as to intersect the gate electrode G1 and the gate electrode G2 when seen in a plan view. That is, when viewed in a plan view, at least part of the scanning line 12 and at least part of the gate electrode G1 overlap. The scanning line 12 is electrically connected to the gate electrode G2 via the contact hole Ha5.
The control line 143 is provided so as to extend in the X direction and intersect the gate electrode G1 and the gate electrode G3 when seen in a plan view. The control line 143 is electrically connected to the gate electrode G3 via the contact hole Ha7.
The control line 144 extends in the X direction, is provided so as to intersect with the gate electrode G4 when seen in a plan view, and is electrically connected to the gate electrode G4 via the contact hole Ha10. The control line 145 extends in the X direction, is provided so as to intersect the gate electrode G5 when seen in a plan view, and is electrically connected to the gate electrode G5 through the contact hole Ha14.

As shown in FIGS. 5 and 6, the relay node N11 is electrically connected to the gate electrode G1 through the contact hole Ha2 and electrically connected to the P-type diffusion layer P4 through the contact hole Ha6. It That is, the relay node N11 corresponds to the gate node g that electrically connects the gate of the transistor 121, the other of the source and the drain of the transistor 122, and one of the source and the drain of the transistor 123.
The relay node N16 is provided such that the relay node N16 and a part of the gate electrode G1 overlap each other when seen in a plan view. The storage node 132 is formed by the relay node N16 and the gate electrode G1 sandwiching the first interlayer insulating layer L1. That is, the gate electrode G1 corresponds to one electrode of the storage capacitor 132, and the relay node N16 corresponds to the other electrode of the storage capacitor 132.
The relay node N12 is electrically connected to the P-type diffusion layer P3 via the contact hole Ha4. The relay node N13 is electrically connected to the P-type diffusion layer P2 via the contact hole Ha3, electrically connected to the P-type diffusion layer P5 via the contact hole Ha8, and P via the contact hole Ha9. It is electrically connected to the mold diffusion layer P6. The relay node N14 is electrically connected to the P-type diffusion layer P7 through the contact hole Ha11 and electrically connected to the P-type diffusion layer P8 through the contact hole Ha12. The relay node N15 is electrically connected to the P-type diffusion layer P9 via the contact hole Ha13.

As shown in FIG. 6, a second interlayer insulating layer L2 is formed so as to cover the first wiring layer and the first interlayer insulating layer L1.
By patterning a conductive wiring layer of aluminum or the like on the surface of the second interlayer insulating layer L2, the data line 14 and the power supply line 16 are formed for each column, and each pixel circuit 110 is formed. , Relay nodes N21 and N22 are respectively formed. The wiring layer formed on the surface of the second interlayer insulating layer L2 may be collectively referred to as the second wiring layer.
As shown in FIG. 5, the data line 14 is electrically connected to the relay node N12 via the contact hole Hb2. As a result, the P-type diffusion layer P3 is electrically connected to the data line 14 via the relay node N12. The power supply line 16 is electrically connected to the relay node N15 via the contact hole Hb3. As a result, the P-type diffusion layer P9 is electrically connected to the power supply line 16 via the relay node N15. The relay node N21 is electrically connected to the power supply line 116 through the contact hole Hb1 and also electrically connected to the relay node N16 (the other electrode of the storage capacitor 132) through the contact hole Hb4. As a result, the relay node N16 is electrically connected to the power supply line 116 via the relay node N21 and kept at the potential Vel.
Further, as shown in FIG. 6, the relay node N22 is electrically connected to the relay node N14 through the contact hole Hb5.

As shown in FIG. 6, a third interlayer insulating layer L3 is formed so as to cover the second wiring layer and the second interlayer insulating layer L2.
The anode 130a of the OLED 130 is formed on the surface of the third interlayer insulating layer L3 by patterning a conductive wiring layer such as aluminum or ITO (Indium Tin Oxide). The anode 130a of the OLED 130 is an individual pixel electrode for each pixel circuit 110, and is connected to the relay node N22 via a contact hole Hc1 penetrating the third interlayer insulating layer L3. That is, the anode 130a of the OLED 130 is electrically connected to the P-type diffusion layer P7 (that is, the drain of the transistor 124) and the P-type diffusion layer P8 (that is, the source of the transistor 125) via the relay node N22 and the relay node N14. Connected.
Although not shown, a light emitting layer made of an organic EL material is laminated on the anode 130a of the OLED 130 for each pixel circuit 110. Then, on the light emitting layer, a cathode (common electrode 118) that is a transparent electrode common to all of the plurality of pixel circuits 110 is provided. That is, the OLED 130 sandwiches the light emitting layer between the anode and the cathode that face each other, and emits light with the brightness according to the current flowing from the anode toward the common electrode 118. Of the light emitted from the OLED 130, the light traveling in the direction opposite to the silicon substrate 150 (that is, the upward direction in FIG. 6) is visually recognized as an image by a viewer (top emission structure). In addition to this, a sealing material or the like for shielding the light emitting layer from the atmosphere is provided, but the description thereof is omitted.

<Operation of Embodiment>
The operation of the electro-optical device 1 will be described with reference to FIG. 7. FIG. 7 is a timing chart for explaining the operation of each unit in the electro-optical device 1. As shown in this figure, the scanning line driving circuit 20 sequentially switches the scanning signals Gwr(1) to Gwr(m) to the L level, and sets the scanning lines 12 of the 1st to mth rows to 1 in the period of one frame. Scanning is performed in sequence for each horizontal scanning period (H). The operation in one horizontal scanning period (H) is common to the pixel circuits 110 in each row. Therefore, in the following, the operation will be described with particular attention paid to the pixel circuit 110 in the i-th row (3j−2) column in the scanning period in which the i-th row is horizontally scanned.

In the present embodiment, the scanning period of the i-th row is roughly divided into an initialization period shown in FIG. 7B, a compensation period shown in FIG. 7C, and a writing period shown in FIG. Be done. Then, after the writing period of (d), the light emitting period shown in (a) starts, and after the elapse of one frame period, the scanning period of the i-th row is reached again. Therefore, in the order of time, the cycle of (light emitting period)→initializing period→compensation period→writing period→(light emitting period) is repeated.
In FIG. 7, the scanning signal Gwr(i-1), control signal Gel(i-1), Gcmp(i-1), which corresponds to the (i-1)th row that is one row before the ith row, For each of Gorst(i-1), one horizontal scan is performed in time from the scanning signal Gwr(i), control signals Gel(i), Gcmp(i), and Gorst(i) corresponding to the i-th row. The waveform is temporally preceded by the period (H).

<Light emitting period>
For convenience of description, the light emitting period, which is a prerequisite for the initialization period, will be described. In the light emission period of the i-th row, the scanning line drive circuit 20 supplies the predetermined second potential V2 to the i-th scanning line 12 and supplies the predetermined first potential V1 to the i-th control line 144. , The second potential V2 is supplied to the i-th control line 143, and the second potential V2 is supplied to the i-th control line 145. In this embodiment, the first potential V1 is set lower than the second potential V2. For example, the first potential V1 has only to correspond to the L level of the control signal (control signal Gref or the like) supplied by the control circuit 3, and the second potential VH is the H level of the control signal supplied by the control circuit 3. Anything that corresponds to the level will do. That is, as shown in FIG. 7, in the light emission period of the i-th row, the scanning signal Gwr(i) is set to the H level, the control signal Gel(i) is set to the L level, and the control signal Gcmp(i) is set. Is set to the H level, and the control signal Gorst(i) is set to the H level.
Therefore, in the pixel circuit 110 in the i-th row (3j−2)-th column as shown in FIG. 8, the transistor 124 is turned on, while the transistors 122, 123, and 125 are turned off. Therefore, the transistor 121 supplies the OLED 130 with the current Ids corresponding to the gate-source voltage Vgs. As will be described later, in the present embodiment, the voltage Vgs in the light emitting period is a value obtained by level-shifting the potential of the data signal. Therefore, the OLED 130 is supplied with a current according to the gradation level in a state where the threshold voltage of the transistor 121 is compensated.

Note that the light emission period of the i-th row is a period in which the rows other than the i-th row are horizontally scanned, and therefore the potential of the data line 14 changes appropriately. However, in the pixel circuit 110 of the i-th row, since the transistor 122 is off, the potential fluctuation of the data line 14 is not taken into consideration here. Further, in FIG. 8, paths that are important in the description of the operation during the light emission period are indicated by thick lines.

<Initialization period>
Next, when the scanning period of the i-th row is reached, first, the initialization period of (b) starts as the first period.
In the initialization period of the i-th row, the scanning line driving circuit 20 supplies the second potential V2 to the scanning line 12 of the i-th row to set the scanning signal Gwr(i) to the H level, as shown in FIG. The control signal Gel(i) is set to the H level by supplying the second potential V2 to the control line 144 of the i-th row, and the second potential V2 is supplied to the control line 143 of the i-th row to control the signal. Gcmp(i) is set to H level, the first potential V1 is supplied to the control line 145 of the i-th row, and the control signal Gorst(i) is set to L level. Therefore, in the pixel circuit 110 in the i-th row (3j−2) column, the transistor 124 is turned off and the transistor 125 is turned on. This cuts off the path of the current supplied to the OLED 130 and sets the anode 130a of the OLED 130 to the reset potential Vorst.
Since the OLED 130 has a structure in which the organic EL layer is sandwiched between the anode 130a and the cathode as described above, the capacitance is parasitic in parallel between the anode and the cathode. When a current is flowing through the OLED 130 during the light emission period, the voltage between the anode and the cathode of the OLED 130 is held by the parasitic parasitic capacitance in parallel between the anode and the cathode. Will be reset. Therefore, in the present embodiment, when the current again flows in the OLED 130 in the later light emitting period, it is less likely to be affected by the voltage held by the capacitance parasitic in parallel between the anode and the cathode.

In detail, for example, when the display is changed from the high-brightness display state to the low-brightness display state, if the configuration is not reset, the high voltage when the brightness is high (a large current flows) is retained. Moreover, even if a small current is tried to flow, an excessive current will flow, and it will not be possible to achieve a low-brightness display state. On the other hand, in the present embodiment, the potential of the anode 130a of the OLED 130 is reset by turning on the transistor 125, so that the reproducibility on the low luminance side is improved. In this embodiment, the reset potential Vorst is set so that the difference between the reset potential Vorst and the potential Vct of the common electrode 118 is lower than the light emission threshold voltage of the OLED 130. Therefore, during the initialization period (the compensation period and the writing period described below), the OLED 130 is in the off (non-light emitting) state.

On the other hand, in the initialization period of the i-th row, the control circuit 3 sets the control signal /Gini to the L level, the control signal Gref to the H level, and the control signal Gcpl to the L level, as shown in FIG. Set. Therefore, the transistors 43 and 45 are turned on. As a result, one electrode of the storage capacitor 44 and the power supply line 61 are electrically connected, and one electrode of the storage capacitor 44 (and the data line 14) is initialized to the initial potential Vini. Further, the other electrode of the storage capacitor 44 and the power supply line 62 are electrically connected, and the other electrode of the storage capacitor 44 (and the node h1) is initialized to the reference potential Vref.
In the present embodiment, the initial potential Vini is set so that (Vel-Vini) is higher than the threshold voltage |Vth| of the transistor 121. Since the transistor 121 is a P-channel type, the threshold voltage Vth based on the potential of the source is negative. Therefore, in order to prevent confusion in the explanation of the relationship between high and low, the threshold voltage is represented by absolute value |Vth|, and is defined in terms of magnitude.

As shown in FIG. 7, the data signal supply circuit 70 has the demultiplexers DM(1), DM(2) in the period from the start of the scanning period of the i-th row to the start of the writing period. ,..., DM(n) are supplied with data signals Vd(1), Vd(2),..., Vd(n), respectively. That is, in the j-th group, the data signal supply circuit 70 sequentially outputs the data signal Vd(j) in the i-th row (3j−2) column, the i-th row (3j−1)th column, and the i-th row (3j). Switching to a potential according to the gradation level of the pixels in the column.
On the other hand, the control circuit 3 sets the control signals Sel(1), Sel(2), and Sel(3) to the H level in sequence in synchronization with the switching of the potential of the data signal. As a result, the three transmission gates 34 provided in each demultiplexer DM are turned on in the order of the left end column, the center column, and the right end column.
Here, in the initialization period, when the transmission gate 34 in the leftmost column belonging to the jth group is turned on by the control signal Sel(1), the data signal Vd(j) is supplied to one electrode of the storage capacitor 41. Therefore, the data signal Vd(j) is held by the holding capacitor 41.

<Compensation period>
In the scanning period of the i-th row, the second period is the compensation period of (c). In the compensation period of the i-th row, the control circuit 3 sets the control signal /Gini to the H level, the control signal Gref to the H level, and the control signal Gcpl to the L level, as shown in FIG. Therefore, the transistor 43 is turned on, while the transistor 45 is turned off. As a result, the other electrode of the storage capacitor 44 and the power supply line 62 are electrically connected, and the node h1 is set to the reference potential Vref.

Further, during the compensation period, when the transmission gate 34 in the leftmost column belonging to the j-th group is turned on by the control signal Sel(1), the data signal Vd(j) is supplied to one electrode of the storage capacitor 41.
If the leftmost column transmission gate 34 belonging to the j-th group is already turned on by the control signal Sel(1) in the initialization period, the transmission gate 34 is not turned on in the compensation period. The data signal Vd(j) supplied when the leftmost column transmission gate 34 is turned on is held by the holding capacitor 41.

Further, in the compensation period of the i-th row, the scanning line driving circuit 20 supplies the first potential V1 to the scanning line 12 of the i-th row to set the scanning signal Gwr(i) to the L level, as shown in FIG. , The second potential V2 is supplied to the control line 144 of the i-th row to set the control signal Gel(i) to the H level, and the first potential V1 is supplied to the control line 143 of the i-th row for control. The signal Gcmp(i) is set to the L level, the first potential V1 is supplied to the i-th row control line 145, and the control signal Gorst(i) is set to the L level. Therefore, since the transistor 123 is turned on, the transistor 121 is diode-connected. As a result, the drain current flows through the transistor 121, and the gate node g and the data line 14 are charged. Specifically, the current flows through the path of the power supply line 116→transistor 121→transistor 123→transistor 122→data line 14 in the (3j−2)th column. Therefore, when the transistor 121 is turned on, the data line 14 and the gate node g which are connected to each other rise from the initial potential Vini. However, the current flowing through the above path becomes less likely to flow as the gate node g approaches the potential (Vel−|Vth|), and therefore the data line 14 and the gate node g have the potential (Vel−) by the end of the compensation period. Saturates at |Vth|).
Therefore, the storage capacitor 132 holds the threshold voltage |Vth| of the transistor 121 at the end of the compensation period. In the following, the potential (Vel−|Vth|) of the gate node g at the end of the compensation period may be referred to as the potential Vp.

When the compensation period ends, the scanning line driving circuit 20 changes the control signal Gcmp(i) from the L level to the H level by switching the potential supplied to the control line 143 from the first potential V1 to the second potential V2. To do. As a result, the diode connection of the transistor 121 is released.
The scanning line driving circuit 20 controls the waveform when the control signal Gcmp(i) changes from the L level to the H level to be gentler than the waveform when the control signal Gcmp(i) changes from the H level to the L level. The potential supplied to the line 143 is switched. That is, as shown in FIG. 7, the scanning line drive circuit 20 switches the potential supplied to the control line 143 from the second potential V2 to the first potential V1 to the third switching period T3, and from the first potential V1. A period for switching to the second potential V2 is referred to as a fourth switching period T4. At this time, the scanning line driving circuit 20 changes the potential supplied to the control line 143 so that the time length of the fourth switching period T4 is sufficiently longer than the time length of the third switching period T3.

As described above, the control line 143 and the gate electrode G1 (the gate of the transistor 121) intersect each other when seen in a plan view. Therefore, there is a parasitic capacitance between the control line 143 and the gate electrode G1. Therefore, if the time length of the fourth switching period T4 is shortened to the same extent as the time length of the third switching period T3 and the control signal Gcmp(i) is suddenly raised from the L level to the H level, the control is performed. The potential of the gate electrode G1 changes under the influence of the high frequency component of the control signal Gcmp(i) on the line 143.
As will be described later in detail, at the end of the compensation period, the potential of the gate node g (potential of the gate electrode G1) is set to a potential that compensates for variations in the threshold voltage of the transistor 121 for each pixel circuit 110. However, when the potential of the gate node g changes after the end of the compensation period, it becomes impossible to compensate for the variation in the threshold voltage of each pixel circuit 110, which causes display unevenness that impairs the uniformity of the display screen. Becomes noticeable.
On the other hand, in the present embodiment, when the time length of the fourth switching period T4 is set sufficiently longer than the time length of the third switching period T3, when the control signal Gcmp(i) changes from the L level to the H level. A gentle waveform is used to prevent the potential fluctuation of the control line 143 from propagating to the gate node g (gate electrode G1). As a result, it is possible to compensate for variations in the threshold voltage of each pixel circuit 110, and to perform high-quality display that ensures display uniformity.

In addition, actually, the time length of the third switching period T3 is sufficiently short that it can be regarded as “0”. That is, the waveform when the control signal Gcmp(i) falls from the H level to the L level may be equal to the waveform when the control signal Gref falls from the H level to the L level. However, in FIG. 7, for the sake of convenience of description, the falling waveform of the control signal Gcmp(i) is described as a gentler waveform than the actual waveform in order to illustrate the third switching period T3.

Further, when the compensation period ends, the control circuit 3 changes the control signal Gref from the H level to the L level, so that the transistor 43 is turned off. Therefore, although the path from the data line 14 in the (3j−2)th column to the gate node g in the pixel circuit 110 in the i-th row (3j−2)th column is in a floating state, the potential of the path is It is maintained at (Vel−|Vth|) by the storage capacitors 50 and 132.

<Writing period>
After the initialization period, the writing period of (d) is reached as the third period. In the writing period of the i-th row, as shown in FIG. 7, the scanning line driving circuit 20 supplies the first potential V1 to the scanning line 12 of the i-th row to set the scanning signal Gwr(i) to the L level. The control signal Gel(i) is set to the H level by supplying the second potential V2 to the control line 144 of the i-th row, and the second potential V2 is supplied to the control line 143 of the i-th row to control the signal. Gcmp(i) is set to the H level, the first potential V1 is supplied to the i-th row control line 145, and the control signal Gorst(i) is set to the L level. As a result, the diode connection of the transistor 121 is released.

In the writing period of the i-th row, the control circuit 3 sets the control signal /Gini to the H level, the control signal Gref to the L level, and the control signal Gcpl to the H level, as shown in FIG. Set. Therefore, since the transmission gate 42 is turned on, the data signal Vd(j) held in the holding capacitor 41 is supplied to the other electrode of the holding capacitor 44 via the node h1. As a result, the other electrode of the node h1 and the storage capacitor 44 changes from the reference potential Vref during the compensation period. The potential change amount of the node h1 at this time is represented by ΔVh. Further, the potential (Vref+ΔVh) of the node h1 during the writing period may be represented as the potential Vh.
When the potential of the node h1 changes from the reference potential Vref to the potential Vh by ΔVh, the potentials of the gate node g and the data line 14 also change from the potential Vp=(Vel−|Vth|) set in the compensation period. . The potential change amount of the gate node g at this time is represented by ΔVg. In addition, the potential (Vp+ΔVg) of the gate node g in the writing period may be represented as the potential Vgate.

Hereinafter, changes in the potentials of the gate node g and the node h1 before and after the start of the writing period will be described in detail with reference to FIG.
FIG. 9A is an explanatory diagram for explaining potential changes of the node h1 and the gate node g before and after the start of the writing period. In this figure, (A-1) shows the potentials of the node h1 and the gate node g before the start of the write period, and (A-2) shows the potential after the start of the write period (that is, the transmission gate 42 is turned on). The potentials of the node h1 and the gate node g are shown in FIG. Note that since the storage capacitor 50 and the storage capacitor 132 are electrically connected in parallel in the compensation period and the writing period, the capacitance value C0 of the combined capacitance 501 of the storage capacitor 50 and the storage capacitor 132 is expressed by the following equation (1). ).
C0=Cpix+Cdt (1)

If the charge accumulated in the combined capacitor 501 before the start of the write period is Q0a and the charge accumulated in the combined capacitor 501 after the start of the write period is Q0b, the charges are combined before and after the start of the write period. The charges (Q0a-Q0b) flowing out from the capacitor 501 are represented by the following equation (2). Similarly, if the charge accumulated in the storage capacitor 44 before the start of the write period is Q1a and the charge accumulated in the storage capacitor 44 after the start of the write period is Q1b, the start of the write period is started. The charge (Q1b-Q1a) flowing into the storage capacitor 44 before and after is expressed by the following equation (3). Before and after the start of the writing period, the charge flowing out of the combined capacitor 501 and the charge flowing into the holding capacitor 44 are equal, and therefore the following expression (4) is established.
Q0a-Q0b = C0*(Vp-Vgate) (2)
Q1b-Q1a = Crf1*{(Vgate-Vh)-(Vp-Vref)} (3)
Q0a-Q0b = Q1b-Q1a (4)

From the equations (2) to (4), the potential Vgate of the gate node g in the writing period can be calculated. Specifically, the potential Vgate is represented by the following equation (5).
Vgate={Crf1/(Crf1+C0)}*{Vh-Vref}+Vp (5)

Here, the capacity ratio k1 shown in the following equation (6) is introduced. At this time, the potential Vgate of the gate node g in the writing period can be expressed by the following equation (7) using the capacitance ratio k1, and the potential change amount ΔVg of the gate node g before and after the start of the writing period is It can be expressed by the following equation (8) using k1.
k1 = Crf1/(Crf1+Cdt+Cpix) (6)
Vgate=k1*(Vh-Vref)+Vp
= K1*ΔVh+Vp (7)
ΔVg = Vgate-Vp
= K1*ΔVh (8)

Thus, in the writing period, the potential of the gate node g is a value (k1*ΔVh) obtained by multiplying the potential change amount ΔVh of the node h1 by the capacitance ratio k1 from the potential Vp=(Vel−|Vth|) in the compensation period. ), the potential is shifted upward by Vgate=(Vel−|Vth|+k1·ΔVh). At this time, the absolute value |Vgs| of the voltage Vgs of the transistor 121 is a value obtained by subtracting the amount of increase in the potential of the gate node g from the threshold voltage |Vth|, as shown in the following equation (9).
|Vgs| = |Vth|-k1*ΔVh (9)

FIG. 9B is an explanatory diagram for explaining potential changes of the nodes h1 and h2 before and after the start of the writing period. In this figure, (B-1) shows the potentials of the nodes h1 and h2 before the start of the write period, and (B-2) shows after the start of the write period (that is, the transmission gate 42 is turned on). The latter shows the potentials of the nodes h1 and h2. Note that, in the compensation period and the writing period, the combined capacitance 501 of the holding capacitors 50 and 132 and the holding capacitor 41 are electrically connected in series, so that the holding capacitor 50, the holding capacitor 132, and the holding capacitor 44 are connected. The capacity value C1 of the combined capacity 502 is expressed by the following equation (10).
C1 = (C0*Crf1)/(C0+Crf1) (10)

When the charge accumulated in the combined capacitance 502 before the start of the writing period is Q1c and the charge accumulated in the combined capacitance 502 after the start of the writing period is Q1d, the combined capacitance before and after the start of the write period is shown. The charge (Q1c-Q1d) flowing out from 502 is expressed by the following equation (11). Similarly, if the charge stored in the storage capacitor 41 before the start of the writing period is Q2c and the charge stored in the storage capacitor 41 after the start of the writing period is Q2d, then before and after the start of the writing period. The electric charge (Q2d-Q2c) flowing into the storage capacitor 41 at is expressed by the following equation (12). Before and after the start of the writing period, the charge flowing out of the combined capacitance 502 and the charge flowing into the storage capacitance 41 are equal, and therefore the following expression (13) is established.
Q1c-Q1d = C1*{Vref-Vh} (11)
Q2d-Q2c = Crf2*{Vh-Vd(j)} (12)
Q1c-Q1d = Q2d-Q2c (13)

Therefore, the potential Vh of the node h1 during the writing period can be calculated from the equations (11) to (13). Specifically, the potential Vh is represented by the following equation (14). Further, the potential change amount ΔVh at the node h1 is expressed by the following equation (15).
Vh = {C1/(C1+Crf2)}*(Vref)
+ {Crf2/(C1+Crf2)}*{Vd(j)} (14)
ΔVh = Vh-Vref
= {Crf2/(C1+Crf2)}*{Vd(j)-Vref} (15)

Here, when the capacitance ratio k2 shown in the following equation (16) is introduced, the potential change amount ΔVh can also be expressed by the following equation (17).
k2 = Crf2/(C1+Crf2) (16)
ΔVh = k2*{Vd(j)-Vref} (17)

The potential Vgate of the gate node g in the writing period can be expressed by the following expression (18) by substituting the expression (17) into the expression (7). Therefore, the potential change amount ΔVg of the gate electrode G before and after the start of the writing period can be expressed by the following equation (19).
Vgate=k1*k2*{Vd(j)-Vref}+Vp (18)
ΔVg = k1*k2*{Vd(j)-Vref} (19)

In this way, the potential of the node h1 changes by the value ΔVh obtained by shifting the potential indicated by the data signal Vd(j) by the reference potential Vref and compressing it by the capacitance ratio k2. As a result, the potential Vgate of the gate node g changes by a value obtained by further compressing the potential change amount ΔVh of the node h1 by the capacitance ratio k1. That is, the potential Vgate of the gate node g in the writing period shifts the data signal Vd(j) by the reference potential Vref as shown in Expression (18), and the capacitance value with respect to the shifted potential. The compressed potential is supplied by multiplying the capacitance ratio k3=k1*k2 determined based on Cdt, Crf1, Crf2, and Cpix.

FIG. 10 is a diagram showing the relationship between the potential of the data signal Vd(j) and the potential Vgate of the gate node g in the writing period. The data signal Vd(j) generated based on the image signal Vid supplied from the control circuit 3 can take a potential range from the minimum value Vmin to the maximum value Vmax according to the gradation level of the pixel as described above. .. Then, as described above, the potential Vgate obtained by shifting the data signal Vd(j) by the reference potential Vref and compressing it by the capacitance ratio k3 is written to the gate node g. At this time, the potential range ΔVgate of the gate node g is compressed to a value obtained by multiplying the potential range ΔVdata (=Vmax−Vmin) of the data signal by the capacitance ratio k3 as shown in the following equation (20).
ΔVgate = k3*ΔVdata (20)

As to how much the potential range ΔVgate of the gate node g is shifted with respect to the potential range ΔVdata of the data signal, as is apparent from the equation (18), the potential Vp (=Vel−|Vth |) and the reference potential Vref.

After the writing period ends, the scanning line drive circuit 20 switches the potential supplied to the scanning line 12 from the first potential V1 to the second potential V2, thereby changing the scanning signal Gwr(i) from the L level to the H level. change. As a result, the transistor 122 is turned off, so that the potential of the gate node g is maintained at the potential Vgate=[{Vel-|Vth|}+k3·{Vd(j)-Vref}].
The scanning line driving circuit 20 scans the scanning line Gwr(i) so that the waveform when the scanning signal Gwr(i) changes from the L level to the H level is gentler than the waveform when the scanning signal Gwr(i) changes from the H level to the L level. The electric potential supplied to 12 is switched. That is, as shown in FIG. 7, the scanning line driving circuit 20 switches the potential supplied to the scanning line 12 from the second potential V2 to the first potential V1 to the first switching period T1, and from the first potential V1. A period for switching to the second potential V2 is referred to as a second switching period T2. At this time, the scanning line driving circuit 20 changes the potential supplied to the scanning line 12 so that the time length of the second switching period T2 is sufficiently longer than the time length of the first switching period T1.

As described above, the scanning line 12 intersects with the gate electrode G1 (the gate of the transistor 121) when seen in a plan view. Therefore, parasitic capacitance exists between the scanning line 12 and the gate electrode G1. Therefore, if the time length of the second switching period T2 is shortened to the same extent as the time length of the first switching period T1 and the scanning signal Gwr(i) is suddenly raised from the L level to the H level, the scanning is performed. The potential of the gate electrode G1 changes under the influence of the high frequency component of the scanning signal Gwr(i) on the line 12.
As described above, at the end of the writing period, the potential of the gate node g (the potential of the gate electrode G1) is set to the potential Vgate based on the data signal Vd(j) (image signal Vid) that defines the brightness of the OLED 130. . However, when the potential of the gate node g changes after the end of the writing period, the potential of the gate node g becomes a potential different from the potential Vgate determined based on the data signal Vd(j). In this case, each pixel displays a gradation different from the gradation defined by the image signal Vid, and the display quality deteriorates.
On the other hand, in the present embodiment, when the time length of the second switching period T2 is made sufficiently longer than the time length of the first switching period T1, when the scanning signal Gwr(i) changes from the L level to the H level. A gentle waveform is used to prevent the potential variation of the scanning line 12 from propagating to the gate node g (gate electrode G1). As a result, each pixel can accurately display the gradation defined by the image signal Vid, and high-quality display is possible.

In addition, in reality, the time length of the first switching period T1 is sufficiently short that it can be regarded as “0”. That is, the waveform when the scanning signal Gwr(i) falls from the H level to the L level may be equal to the waveform when the control signal Gref falls from the H level to the L level. However, in FIG. 7, for convenience of explanation, in order to illustrate the first switching period T1, it is described that the falling waveform of the scanning signal Gwr(i) is sufficiently gentle as compared with the actual waveform. ..

<Light emitting period>
After the writing period of the i-th row ends, the light emitting period starts. In the present embodiment, after the writing period of the i-th row ends, the light emitting period starts with one horizontal scanning period. In the light emission period, the scanning line driving circuit 20 sets the scanning signal Gwr(i) to the H level as described above, so that the transistor 122 is turned off and the gate node g has the potential Vgate=[{Vel−|Vth. .Vertline.}+k3.{Vd(j)-Vref}]. Further, in the light emission period, the scanning line drive circuit 20 sets the control signal Gel(i) to the L level, so that the transistor 124 in the pixel circuit 110 in the i-th row (3j−2) column is turned on. Since the gate-source voltage Vgs is [|Vth|-k3.{Vd(j)-Vref}], the OLED 130 has a current corresponding to the gradation level, as shown in FIG. Will be supplied with the threshold voltage of the transistor 121 compensated.
Such an operation is temporally performed in parallel in the pixel circuit 110 of the i-th row other than the pixel circuit 110 of the (3j−2)th column in the scanning period of the i-th row. Further, such an operation of the i-th row is actually executed in the order of 1, 2, 3,..., (m−1), m-th row in the period of one frame, and is repeated for each frame. Be done.

<Effects of the embodiment>
According to the present embodiment, the scanning line 12 and the control line 143 are provided at positions intersecting the gate (gate electrode G1) of the transistor 121 when seen in a plan view. Therefore, compared with the case where the scanning line 12 and the control line 143 are provided so as not to intersect the gate of the transistor 121, a plurality of control lines (scanning line 12, control lines 143, 144, and 145) extending in the X direction are provided. Can be wired at high density, and the pitch of control lines can be narrowed. That is, according to the present embodiment, by arranging the control lines at a high density, it is possible to narrow the pitch of the pixel circuits 110, and thereby downsize the electro-optical device 1 (display unit 100) and achieve high-definition display. Can be realized.

According to the present embodiment, the scanning line drive circuit 20 makes the waveform when the scanning signal Gwr(i) changes from the L level to the H level gentler than the waveform when the scanning signal Gwr(i) changes from the H level to the L level. The potential supplied to the scanning line 12 is changed so that Accordingly, even when the scanning line 12 and the gate of the transistor 121 intersect in a plan view, the potential fluctuation of the scanning signal Gwr(i) can be prevented from propagating to the gate of the transistor 121. Therefore, each pixel can accurately display the gradation defined by the image signal Vid.

According to the present embodiment, the scanning line drive circuit 20 makes the waveform when the control signal Gcmp(i) changes from the L level to the H level gentler than the waveform when the control signal Gcmp(i) changes from the H level to the L level. The potential supplied to the control line 143 is changed so that Thereby, even when the control line 143 and the gate of the transistor 121 intersect in a plan view, the potential fluctuation of the control signal Gcmp(i) can be prevented from propagating to the gate of the transistor 121. Therefore, it is possible to perform high-quality display while ensuring display uniformity.

According to the present embodiment, the potential range ΔVgate at the gate node g is narrowed with respect to the potential range ΔVdata of the data signal. Therefore, even if the data signal is not finely divided, the voltage that reflects the gradation level can be applied to the transistor 121. Can be applied between the gate and the source. Therefore, in the pixel circuit 110, the current supplied to the OLED 130 can be accurately controlled even when the minute current flowing in the OLED 130 changes relatively greatly with respect to the change in the gate-source voltage Vgs of the transistor 121. Will be possible.

Further, as shown by a broken line in FIG. 4, a capacitance Cprs may be parasitic between the data line 14 and the gate node g in the pixel circuit 110. In this case, if the potential change width of the data line 14 is large, it propagates to the gate node g through the capacitance Cprs, so-called crosstalk or unevenness occurs, and the display quality is degraded. The influence of the capacitance Cprs becomes remarkable when the pixel circuit 110 is miniaturized.
On the other hand, in the present embodiment, the potential change range of the data line 14 is narrowed with respect to the potential range ΔVdata of the data signal, so that the influence via the capacitance Cprs can be suppressed.

Further, according to the present embodiment, the influence of the threshold voltage is offset in the current Ids supplied to the OLED 130 by the transistor 121. Therefore, according to the present embodiment, even if the threshold voltage of the transistor 121 varies for each pixel circuit 110, the variation is compensated and the current according to the gradation level is supplied to the OLED 130. As a result of suppressing occurrence of display unevenness that impairs uniformity, high-quality display is possible.

This offset will be described with reference to FIG. As shown in this figure, the transistor 121 operates in the weak inversion region (subthreshold region) in order to control the minute current supplied to the OLED 130.
In the figure, A shows the relationship between the gate potential in a transistor having a large threshold voltage |Vth| and the current supplied by the transistor, and B shows the gate potential in a transistor having a small threshold voltage |Vth| and the current supplied by the transistor. The relationship is shown. In FIG. 11, the gate-source voltage Vgs is the difference between the solid line and the potential Vel. Further, in FIG. 11, the vertical scale current is shown by a logarithm in which the direction from the source to the drain is negative (down).
During the compensation period, the gate node g changes from the initial potential Vini to the potential (Vel−|Vth|). Therefore, the operating point of the transistor with a large threshold voltage |Vth| represented by the solid line A moves from S to Aa, while the operating point of the transistor with a small threshold voltage |Vth| represented by the solid line B is S. To Ba.
Next, when the potentials of the data signals to the pixel circuits 110 to which the two transistors belong are the same, that is, when the same gradation level is designated, the potential shift amount from the operating points Aa and Ba is in the writing period. , Both are the same k1·ΔVh. Therefore, the operating point of the transistor represented by the solid line A moves from Aa to Ab, and the operating point of the transistor represented by the solid line B moves from Ba to Bb, but the current at the operating point after the potential shift is changed. Will have the same Ids for both the two transistors.

According to the present embodiment, the operation of holding the data signal supplied from the control circuit 3 via the demultiplexer DM in the holding capacitor 41 is executed from the initialization period to the compensation period. That is, according to the present embodiment, the operation of initializing the potential of the anode 130a to the reset potential Vorst and the operation of holding the data signal in the holding capacitor 41 are performed in parallel during the initialization period and the compensation is performed. During the period, the operation of compensating for the variation in the threshold voltage of the transistor 121 and the operation of holding the data signal in the holding capacitor 41 are performed in parallel. Therefore, it is possible to relax the time constraint on the operation to be executed in one horizontal scanning period, and it is possible to reduce the speed of the data signal supply operation in the data signal supply circuit 70.

<Modification>
The present invention is not limited to the above-described embodiments, and various modifications such as those described below are possible. In addition, one or more arbitrarily selected aspects of the modifications described below can be appropriately combined.

<Modification 1>
In the above-described embodiment, each pixel circuit 110 has a configuration in which the scanning line 12 and the control line 143 intersect with the gate electrode G1 when seen in a plan view. The control line 144 may intersect with the gate electrode G1.
FIG. 12 is a plan view showing the configuration of the pixel circuit 110 according to the first modification. In the pixel circuit 110 according to the first modification, the control line 144 and the gate electrode G1 intersect each other when viewed in a plan view, and the control line 144 has a branch portion 142a branched in the Y direction for each pixel circuit 110. Except the above, the pixel circuit 110 has the same configuration as the pixel circuit 110 according to the embodiment shown in FIG.
According to this configuration, a plurality of control lines (scan lines 12, control lines 143, 144, 145) extending in the X direction are provided as compared with the case where the control line 144 is provided so as not to cross the gate of the transistor 121. Wiring can be performed at high density, and the pitch of control lines can be narrowed. As a result, the electro-optical device (display unit) can be downsized and the display can be made finer.

When the control line 144 and the gate electrode G1 intersect, the scanning line drive circuit 20 changes the waveform of the control signal Gel(i) from the H level to the L level from the L level to the H level. The potential supplied to the control line 144 may be switched so that it becomes gentler than the waveform at that time.
FIG. 13 is a timing chart for explaining the operation of the electro-optical device according to the first modification. As illustrated in FIG. 13, in the scanning line drive circuit 20 according to the first modification, the time length of the fifth switching period T5 that switches the potential supplied to the control line 144 from the second potential V2 to the first potential V1 is The potential supplied to the control line 144 is changed so as to be sufficiently longer than the time length of the sixth switching period T6 for switching from the first potential V1 to the second potential V2.
As described above, the potential of the gate electrode G1 (gate node g of the transistor 121) is set to the potential Vgate that defines the brightness of the OLED 130 in the writing period preceding the fifth switching period T5. Therefore, in the fifth switching period T5, when the potential of the control line 144 abruptly changes and the potential variation propagates to the gate electrode G1, each pixel cannot accurately display the gradation defined by the image signal Vid.
On the other hand, in the scanning line driving circuit 20 according to the first modification, the time length of the fifth switching period T5 is set sufficiently longer than the time length of the sixth switching period T6, and the control signal Gel(i) becomes H. By making the waveform at the time of changing from the level to the L level a gentle waveform, it is possible to prevent the potential fluctuation of the control line 144 from propagating to the gate node g (gate electrode G1). As a result, each pixel can accurately display the gradation defined by the image signal Vid, and high-quality display is possible.

<Modification 2>
In the above-described embodiment, each pixel circuit 110 has a configuration in which the scanning line 12 and the control line 143 intersect with the gate electrode G1 when seen in a plan view. However, in addition to the scanning line 12 and the control line 143, The control line 145 may cross the gate electrode G1.
FIG. 14 is a plan view showing the configuration of the pixel circuit 110 according to the second modification. The pixel circuit 110 according to Modification 2 has a point where the control line 145 intersects with the gate electrode G1 when seen in a plan view, and a point where the control line 145 has a branch portion 145a branched in the Y direction for each pixel circuit 110. Except the above, the pixel circuit 110 has the same configuration as the pixel circuit 110 according to the embodiment shown in FIG.
According to this configuration, compared with the case where the control line 145 is provided so as not to cross the gate of the transistor 121, the plurality of control lines (scan lines 12, control lines 143, 144, 145) extending in the X direction are provided. Wiring can be performed at high density, and the pitch of control lines can be narrowed. As a result, the electro-optical device (display unit) can be downsized and the display can be made finer.
Further, when the control line 145 and the gate electrode G1 intersect, the scanning line driving circuit 20 causes the waveform when the control signal Gorst(i) changes from the L level to the H level to be H level, as shown in FIG. The potential supplied to the control line 145 may be switched so that the waveform becomes gentler than the waveform when changing from the level to the L level.
FIG. 15 is a timing chart for explaining the operation of the electro-optical device according to Modification 2.
As shown in FIG. 15, in the scanning line drive circuit 20 according to the second modification, the time length of the eighth switching period T8 for switching the potential supplied to the control line 145 from the first potential V1 to the second potential V2 is The potential supplied to the control line 145 is changed so as to be sufficiently longer than the time length of the seventh switching period T7 for switching from the second potential V2 to the first potential V1. In this case, after the potential of the gate node g (gate electrode G1) of the transistor 121 is settled at the potential Vgate that defines the brightness of the OLED 130, the potential fluctuation is prevented from propagating to the control line 145 to the gate electrode G1. Each pixel can accurately display the gradation defined by the image signal Vid.

<Modification 3>
In the above-described embodiment and modification, each pixel circuit 110 includes the transistors 121 to 125, the OLED 130, and the storage capacitor 132, but the pixel circuit 110 includes at least the transistor 121, the transistor 122, and the Anything that includes the OLED 130 may be used. In this case, the display unit 100 is a modified one of the plurality of control lines (scanning lines 12, control lines 143, 144, 145) provided in the display unit 100 and extending in the X direction in the above-described embodiment and modification. It suffices that only the control lines corresponding to the transistors included in the pixel circuit 110 of Example 3 be provided in each row. That is, the display unit 100 according to the modified example 3 may be one in which one or more control lines including the scanning lines 12 are provided in each row. For example, when each pixel circuit 110 includes the transistor 121, the transistor 122, the OLED 130, and the storage capacitor 132, only the scanning line 12 is provided as the control line corresponding to each row. In addition, each pixel circuit 110 may include transistors other than the transistors 121 to 125, and in this case, the display unit 100 may be provided with a control line corresponding to the transistor.
When one or more control lines including the scanning lines 12 are provided in each row, at least one control line of the one or more control lines extending in the X direction provided in each row has the transistor 121 in plan view. Is provided so as to intersect the gate node g (gate electrode G1). As a result, the control lines extending in the X direction can be arranged with high density, and the electro-optical device (display unit) can be downsized and the display can be made finer.
Further, the scanning line driving circuit 20 sets the potential of at least one control line, which crosses the gate electrode G1 in plan view, among the one or more control lines provided in each row, from the end of the compensation period to the next scanning period. In the case of changing the potential before the start of, the waveform of the potential change is preferably gentle. For example, when the gate electrode G1 and the scanning line 12 intersect with each other, the scanning line driving circuit 20 switches the potential supplied to the scanning line 12 from the first potential V1 to the second potential V2 during the second switching period T2. The potential supplied to the scanning line 12 may be changed so that the length is sufficiently longer than the time length of the first switching period T1 for switching the second potential V2 to the first potential V1. This can prevent the potential change of the control line intersecting with the gate electrode G1 from propagating to the gate electrode G1, and each pixel can accurately display the gradation defined by the image signal Vid. Becomes

The scanning line driving circuit 20 changes the potential of the control line that does not intersect the gate electrode G1 in plan view from the end of the compensation period to the start of the next scanning period. The waveform of the potential change may be gentle. Even if the control line does not cross the gate electrode G1, parasitic capacitance may exist between the control line and the gate electrode G1. Therefore, by making the waveform when the potential of the control line changes to be gentle, it is possible to prevent the potential change of the control line from propagating to the gate electrode G1.

<Modification 4>
In the above-described embodiments and modified examples, each level shift circuit LS includes the storage capacitor 41, the storage capacitor 44, the transistor 45, the transistor 43, and the transmission gate 42, but the level shift circuit LS is at least The storage capacitor 44, the transistor 43, and the transistor 45 may be included. In this case, the data signal supply circuit 70 and the demultiplexer DM may supply the data signal Vd(j) to the other electrode of the storage capacitor 44 during the writing period.
Even if the level shift circuit LS does not include the storage capacitor 41, the data signal Vd(j) supplied to the other electrode of the storage capacitor 44 is supplied to the gate node g after being compressed by the capacity ratio k1. To be done. Thus, the potential of the gate node of the driving transistor can be set with fine accuracy without carving the data signal with high accuracy, so that current can be supplied to the light emitting element with high accuracy. It is possible to display the quality.

<Modification 5>
In the above-described embodiment and modification, the data line driving circuit 10 includes the level shift circuit LS, the demultiplexer DM, and the data signal supply circuit 70. However, the data line driving circuit 10 includes at least the data signal. It is sufficient that it includes the supply circuit 70. In this case, the data line drive circuit 10 directly supplies the data signal Vd(j) to the gate node g.
Furthermore, in the above-described embodiment and modification, the display panel 2 includes the storage capacitors 50 in each column, but may be configured without the storage capacitors 50.

<Modification 6>
Although the control circuit 3 and the display panel 2 are separate bodies in the above-described embodiments and modifications, the control circuit 3 and the display panel 2 may be formed on the same substrate. For example, the control circuit 3 may be integrated on the silicon substrate together with the display unit 100, the data line driving circuit 10, the scanning line driving circuit 20, and the like.

<Modification 7>
Although the electro-optical device 1 is integrated on the silicon substrate in the above-described embodiment and modification, it may be integrated on another semiconductor substrate. For example, it may be an SOI substrate. Alternatively, a polysilicon process may be applied to form it on a glass substrate or the like. In any case, the present invention is effective in a configuration in which the pixel circuit 110 is miniaturized and the drain current in the transistor 121 changes exponentially with respect to the change in the gate voltage Vgs.
Further, the present invention may be applied to the case where miniaturization of the pixel circuit is not required.

<Modification 8>
In the above-described embodiment and modification, the data lines 14 are grouped in every three columns, and the data lines 14 are sequentially selected in each group to supply the data signal. The number of lines may be a predetermined number of "2" or more and "3n" or less. For example, the number of data lines forming a group may be "2" or may be "4" or more.
Further, a configuration may be adopted in which the data signals are supplied to the data lines 14 of each column all at once without grouping, that is, without using the demultiplexer DM.

<Modification 9>
In the above-described embodiment and modification, the transistors 121 to 125 in the pixel circuit 110 are unified as P-channel type, but may be unified as N-channel type. Further, the P-channel type and the N-channel type may be appropriately combined.
For example, when unifying the transistors 121 to 125 of the N-channel type, it is sufficient to supply the pixel circuit 110 with a potential whose polarity is opposite to that of the data signal Vd(j) in the above-described embodiment and modification. Further, in this case, the sources and the drains of the transistors 121 to 125 have a relationship opposite to that of the above-described embodiment and modification.
In addition, in the above-described embodiment and modification, the transistor 45 is a P-channel type and the transistor 43 is an N-channel type, but they may be unified into a P-channel type or an N-channel type. The transistor 45 may be an N-channel type and the transistor 43 may be a P-channel type.
Further, in the above-described embodiments and modifications, each transistor is a MOS type transistor, but it may be a thin film transistor.

<Modification 10>
Although the OLED which is a light emitting element is illustrated as the electro-optical element in the above-described embodiments and modified examples, it may be any one that emits light with a brightness according to a current, such as an inorganic light emitting diode or an LED (Light Emitting Diode).

<Application example>
Next, electronic devices to which the electro-optical device 1 according to the embodiments and the application examples are applied will be described. The electro-optical device 1 is suitable for a high-definition display application with a small pixel size. Therefore, as an electronic device, a head mounted display will be described as an example.

FIG. 16 is a diagram showing the external appearance of the head mounted display, and FIG. 17 is a diagram showing its optical configuration.
First, as shown in FIG. 16, the head mounted display 300 externally has a temple 310, a bridge 320, and lenses 301L and 301R, similar to general glasses. In addition, as shown in FIG. 17, the head mounted display 300 includes the electro-optical device 1L for the left eye and the right eye on the back side (lower side in the drawing) of the lenses 301L and 301R near the bridge 320. And an electro-optical device 1R for use.
The image display surface of the electro-optical device 1L is arranged on the left side in FIG. As a result, the display image by the electro-optical device 1L is emitted in the 9 o'clock direction in the figure via the optical lens 302L. The half mirror 303L reflects the display image by the electro-optical device 1L in the 6 o'clock direction, while transmitting the light incident from the 12:00 o'clock direction.
The image display surface of the electro-optical device 1R is arranged on the right side opposite to the electro-optical device 1L. As a result, the display image by the electro-optical device 1R is emitted through the optical lens 302R in the 3 o'clock direction in the figure. The half mirror 303R reflects the display image by the electro-optical device 1R in the 6 o'clock direction, while transmitting the light incident from the 12 o'clock direction.

With this configuration, the wearer of the head-mounted display 300 can observe the display images of the electro-optical devices 1L and 1R in a see-through state in which they are superposed on the outside.
Further, in the head mounted display 300, of the binocular images with parallax, the image for the left eye is displayed on the electro-optical device 1L and the image for the right eye is displayed on the electro-optical device 1R. , The displayed image can be perceived as if it has a depth and a stereoscopic effect (3D display).

The electro-optical device 1 can be applied not only to the head-mounted display 300 but also to an electronic viewfinder in a video camera, a lens-interchangeable digital camera, or the like.

DESCRIPTION OF SYMBOLS 1... Electro-optical device, 2... Display panel, 3... Control circuit, 10... Data line drive circuit, 12... Scan line, 14... Data line, 16... Feed line, 20... Scan line drive circuit, 41, 44, 50 ... storage capacitor, 100... display unit, 110... pixel circuit, 121-125... transistor, 130... OLED, 132... storage capacitor, 143, 144, 145... control line, 150... silicon substrate, LS... level shift circuit, DM … Demultiplexer.

Claims (7)

Scan line,
Data line,
A pixel circuit provided corresponding to the intersection of the scanning line and the data line,
Equipped with
The pixel circuit is
A light emitting element,
A first power supply line,
A drive transistor electrically connecting the light emitting element to the first power supply line, and a first transistor having a first gate electrode, the first gate electrode electrically connected to the scan line. When,
An insulating layer disposed between the scanning line and the first gate electrode in a cross-sectional view,
A first contact hole formed in the insulating layer to electrically connect the first gate electrode and the scanning line;
Control lines,
A second power supply line,
A second transistor having a second gate electrode formed in the same layer as the first gate electrode, wherein the second gate electrode is electrically connected to the control line;
A second contact hole formed in the insulating layer for electrically connecting the second gate electrode and the control line;
Equipped with
The first transistor electrically connects the gate of the driving transistor and the data line,
The scan line is arranged in a layer different from the first gate electrode in a cross-sectional view,
The scan line overlaps the first contact hole and the first gate electrode in plan view,
The second transistor electrically connects the second power supply line and the light emitting element, and the control line is arranged in a layer different from the second gate electrode in a cross-sectional view,
The electro-optical device , wherein the control line overlaps the second contact hole and the second gate electrode in a plan view . The electro-optical device according to claim 1, wherein the scanning line overlaps two transistors included in the pixel circuit in a plan view. The control lines, in a plan view, an electro-optical device according to claim 1 or 2 any one characterized by overlapping the two transistors included in the pixel circuit has. The pixel circuit is
Further comprising a storage capacitor having a first electrode and a second electrode,
The first electrode is arranged to have the same potential as the gate of the drive transistor,
The storage capacitor in a plan view, an electro-optical device according to any one of claims 1-3, characterized in that overlaps with the gate of the driving transistor. Scan line,
Data line,
A pixel circuit provided corresponding to the intersection of the scanning line and the data line,
Equipped with
The pixel circuit is
A light emitting element,
A first power supply line,
A drive transistor electrically connecting the light emitting element to the first power supply line, and a first transistor having a first gate electrode, the first gate electrode electrically connected to the scan line. When,
An insulating layer disposed between the scanning line and the first gate electrode in a cross-sectional view,
A first contact hole formed in the insulating layer to electrically connect the first gate electrode and the scanning line;
Control lines,
A second transistor having a second gate electrode formed in the same layer as the first gate electrode, wherein the second gate electrode is electrically connected to the control line;
Equipped with
The first transistor electrically connects the gate of the driving transistor and the data line,
The scan line is arranged in a layer different from the first gate electrode in a cross-sectional view,
The scan line overlaps the first contact hole and the first gate electrode in plan view,
The electro-optical device , wherein the control line overlaps two transistors included in the pixel circuit in a plan view . The scanning line overlaps two transistors included in the pixel circuit in a plan view.
The electro-optical device according to claim 5, wherein. The pixel circuit is
Further comprising a storage capacitor having a first electrode and a second electrode,
The first electrode is arranged to have the same potential as the gate of the drive transistor,
The storage capacitor overlaps with the gate of the drive transistor in plan view.
7. The electro-optical device according to claim 5, characterized in that

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