JP6052365B2 - Electro-optical device and electronic apparatus - Google Patents

Description

  The present invention relates to an electro-optical device and an electronic apparatus.

  In recent years, various electro-optical devices using light emitting elements such as organic light emitting diode (hereinafter referred to as “OLED”) elements have been proposed. In this electro-optical device, a configuration in which a pixel circuit including the light emitting element, the transistor, and the like is provided corresponding to the pixel of the image to be displayed corresponding to the intersection of the scanning line and the data line. (For example, refer to Patent Document 1). In such a configuration, when a data signal having a potential corresponding to the gray level of the pixel is applied to the gate of the transistor, the transistor supplies a current corresponding to the voltage between the gate and the source to the light emitting element. Accordingly, the light emitting element emits light with luminance according to the gradation level.

JP 2007-316462 A

By the way, a circuit that outputs a data signal is required to have high driving capability in order to charge the data line in a short time. On the other hand, in order to perform high-quality display, it is required to control the potential of the data signal with fine accuracy and to express fine gradation changes. However, it has been difficult to control the potential of the data signal with fine accuracy in a circuit having a high driving capability.
The present invention has been made in view of the above-described circumstances, and one of its purposes is to provide an electro-optical device capable of high-quality display while not requiring a fine-precision data signal. is there.

  In order to achieve the above object, an electro-optical device according to the present invention includes a plurality of scanning lines, a plurality of data lines, and a plurality of scanning lines provided corresponding to the intersections of the plurality of scanning lines and the plurality of data lines. Electrically connected to the plurality of data lines, a display portion including the pixel circuit, a first storage capacitor provided corresponding to each of the plurality of data lines and holding the potential of each of the data lines. A data line driving circuit, a drive control circuit for controlling the operation of the data line driving circuit, and a display for supplying brightness information indicating the brightness of the entire screen to be displayed on the display unit to the driving control circuit Each of the plurality of pixel circuits is electrically connected between a light emitting element, a driving transistor for supplying a current to the light emitting element, a gate of the driving transistor, and the data line. Write transition And a second storage capacitor, one end of which is electrically connected to the gate of the drive transistor and holds a voltage between the gate and source of the drive transistor, and the display control circuit includes: An image signal defining brightness is supplied to the data line driving circuit, and the data line driving circuit includes a potential control line to which a potential control signal is supplied from the driving control circuit, and each of the plurality of data lines. And each of the plurality of level shift circuits is connected to the data line at one end and supplied with a potential based on the image signal at the other end. A third storage capacitor, and a first transistor electrically connected between the other end of the third storage capacitor and the potential control line, and the drive control circuit includes the brightness control circuit. Based on the information, controlling the potential of the potential control signals, characterized in that.

  According to the present invention, the data line is connected to the first storage capacitor and one end of the third storage capacitor, and the other end of the third storage capacitor has a potential based on the image signal that defines the luminance of the light emitting element. Is supplied. Therefore, the magnitude of the potential fluctuation of the data line is a value obtained by compressing the magnitude of the potential fluctuation based on the image signal in accordance with the capacity ratio of the first storage capacitor and the third storage capacitor. That is, the variation range of the potential of the data line is narrower than the variation range of the potential based on the image signal. As a result, the potential of the gate node of the driving transistor can be set with a fine accuracy without engraving the data signal with a fine accuracy, and the current can be supplied to the light emitting element with a high accuracy. Display is possible. In addition, since the potential change width of the data line can be suppressed to be small, it is possible to prevent the occurrence of crosstalk, unevenness, and the like due to the potential fluctuation of the data line.

  Note that, when the fluctuation range of the potential based on the image signal is compressed in accordance with the capacity ratio of the first storage capacitor and the third storage capacitor, the luminance of the light emitting element is lower than that in the case where the compression is not performed. However, according to the present embodiment, by controlling the potential of the potential control signal based on the brightness information, the voltage between the gate and the source of the driving transistor can be increased, so that a large current is supplied to the light emitting element. It becomes possible to do. That is, according to the present invention, it is possible to both control the magnitude of the current supplied to the light emitting element with high accuracy and supply a large current to the light emitting element. As a result, the electro-optical device according to the present invention can display a high-quality image and a bright image.

  Note that the electro-optical device according to the invention supplies the potential of the gate node of the driving transistor by supplying electric charge from one end of the third storage capacitor to the first storage capacitor and the second storage capacitor via the data line. decide. Specifically, the potential of the gate node of the drive transistor is supplied from the capacitance value of the first storage capacitor, the capacitance value of the second storage capacitor, and the third storage capacitor to the first storage capacitor and the second storage capacitor. It is determined by the amount of charge to be performed. If the electro-optical device does not include the first storage capacitor, the potential of the gate node of the driving transistor is determined by the capacitance value of the second storage capacitor and the charge supplied by the third storage capacitor. Therefore, when the capacitance value of the second storage capacitor has a relative variation for each pixel circuit due to an error in the semiconductor process, the potential of the gate node of the driving transistor also varies for each pixel circuit. In this case, display unevenness occurs and the display quality deteriorates. In contrast, the present invention includes a first storage capacitor that holds the potential of the data line. Since the first storage capacitor is provided corresponding to each of the data lines, the first storage capacitor can be configured to have a larger area electrode than the second storage capacitor provided in the pixel circuit. Therefore, the plurality of first storage capacitors provided in each column can suppress the relative variation in the capacitance value caused by the error in the semiconductor process, as compared with the second storage capacitor. As a result, variation in the potential of the gate node of the driving transistor for each pixel circuit can be prevented, and high-quality display can be achieved while preventing display unevenness.

In the electro-optical device described above, the display control circuit includes a storage unit that stores the brightness of the light emitting element, the potential indicated by the image signal, and the brightness information in association with each other. Preferably, the image signal defining the luminance of the light emitting element is generated based on the image signal.
When the brightness of the entire screen to be displayed on the display unit is changed by changing the potential of the potential control signal based on the brightness information, the luminance of the light emitting element and the potential indicated by the image signal supplied to the light emitting element The relationship with will also change. In this case, even if gamma correction is performed without considering the potential change of the potential control signal, the light emitting element may emit light with a luminance different from the luminance specified by the image signal.
On the other hand, the electro-optical device according to the invention includes a storage unit that stores brightness information in association with the luminance of the light emitting element and the potential indicated by the image signal. Therefore, even when the brightness of the entire screen to be displayed on the display unit is changed based on the brightness information, the light emitting element can emit light with the correct luminance specified by the image signal.

In the electro-optical device described above, the electro-optical device includes a scanning line driving circuit that controls operations of the plurality of pixel circuits, and the data line driving circuit includes a first power supply line that supplies an initial potential. The level shift circuit includes a second transistor electrically connected between one end of the third storage capacitor and the first power supply line. In the first period, the drive control circuit includes the second transistor. In the second period that starts after the first period ends, the scanning line driving circuit maintains the writing transistor in the on state, and the driving control circuit includes the first transistor. In the third period starting after the second period ends, the scanning line driving circuit is configured to maintain the second transistor in the off state. The writing transistor is maintained in an on state, the drive control circuit maintains the first transistor and the second transistor in an off state, and the other end of the third storage capacitor has a potential based on the image signal. Is preferably supplied.
According to the present invention, in the first period and the second period, the potential of the data line is initialized, and in the third period, a signal having a potential defining the luminance of the light emitting element is provided at the other end of the third storage capacitor. Supplied. For this reason, since the potential of the gate node of the driving transistor is accurately set to a value corresponding to a potential signal that defines the luminance of the light emitting element, high-quality display is possible.
In addition, the potential based on the image signal supplied to the other end of the third storage capacitor in the third period is compressed based on the capacitance ratio of the third storage capacitor and the first storage capacitor, and then the gate node of the driving transistor. To be supplied. For this reason, the electro-optical device according to the present invention can accurately supply the magnitude of the current supplied to the light emitting element, and display with high quality is possible.

In the electro-optical device described above, the level shift circuit includes a fourth storage capacitor, and the fourth storage capacitor is at least part of a period from the start of the first period to the start of the third period. In the above, it is preferable that one end is supplied with a potential indicated by the image signal output from the display control circuit, and one end is electrically connected to the other end of the third storage capacitor in the third period. .
According to the present invention, in the first period and the second period, the data signal is supplied to one end of the fourth holding capacitor, temporarily held, and then supplied to the gate node of the driving transistor in the third period. The
If the electro-optical device does not include the fourth storage capacitor, all the operations for supplying the data signal to the gate node of the driving transistor must be performed in the third period, and the time length of the third period is sufficient. Must be set to length.
On the other hand, in the present invention, since the data signal supply operation and the initialization operation of the data lines and the like are performed in parallel in the first period and the second period, the operation to be performed in one horizontal scanning period is described. Time constraints can be relaxed. As a result, the speed of the data signal supply operation can be reduced, and a sufficient period for initializing the data lines and the like can be secured.
According to the invention, the magnitude of the potential fluctuation based on the image signal is compressed using the fourth holding capacitor in addition to the first holding capacitor, the second holding capacitor, and the third holding capacitor. Therefore, current can be supplied to the light emitting element with fine accuracy.

  In the electro-optical device described above, the data line driving circuit includes a plurality of sets of first switches and second switches provided corresponding to the fourth holding capacitors, and an output terminal of the first switch is , Electrically connected to the other end of the third holding capacitor, and an input end of the first switch is electrically connected to one end of the fourth holding capacitor and an output end of the second switch, In a period from the start of one period to the start of the third period, the drive control circuit turns on the second switch with the first switch turned off, and the display control circuit The potential indicated by the image signal may be supplied to the input terminal of the switch, and in the third period, the drive control circuit may turn on the first switch while the second switch is turned off. .

In the electro-optical device described above, the fourth storage capacitor includes a plurality of fourth capacitors that are electrically connected in parallel between the second power supply line to which a fixed potential is supplied and the output terminal of the second switch. Each of the plurality of fourth individual circuits includes a fourth individual capacitor and a fourth individual electrically connected in series between the second feeder and the output end of the second switch. It is preferable that the drive control circuit selectively turns on a part or all of the plurality of fourth individual switches based on the brightness information.
According to the present invention, the capacitance value of the fourth storage capacitor can be changed based on the brightness information. As a result, for example, when the brightness of the entire screen to be displayed on the display unit is bright and the possibility of unevenness due to the potential fluctuation of the data line is low, the fluctuation range of the potential based on the image signal is reduced. It is possible to display a clear image with a large contrast ratio by reducing the compression rate.

  In the electro-optical device described above, the plurality of data lines are grouped by a predetermined number, and the input terminals of the predetermined number of the second switches corresponding to the predetermined number of data lines belonging to one group are common. The drive control circuit may be connected so that a predetermined number of second switches belonging to the one group are turned on in a predetermined order in synchronization with the supply of the image signal.

In the electro-optical device described above, the pixel circuit includes a threshold compensation transistor electrically connected between a gate and a drain of the driving transistor, and the scanning line driving circuit includes the threshold voltage compensation transistor in the second period. Preferably, the threshold compensation transistor is maintained in an on state, and the threshold compensation transistor is maintained in an off state in a period other than the second period.
According to the present invention, the potential of the gate of the driving transistor can be set to a potential corresponding to the threshold voltage of the driving transistor, and variations in the threshold voltage for each driving transistor can be compensated.

The electro-optical device includes a plurality of third power supply lines that are provided corresponding to the plurality of data lines and supply a predetermined reset potential, and the pixel circuit includes the third power supply line and the third power supply line. The scan line driver circuit includes an initialization transistor electrically connected to the light emitting element, and the scan line driver circuit includes at least a part of the first period, the second period, and the third period. It is preferable to maintain the initialization transistor in an on state.
According to the present invention, the influence of the holding voltage of the capacitance parasitic on the light emitting element can be suppressed.

In the electro-optical device described above, each of the plurality of third feeder lines is provided along each of the plurality of data lines, and the first storage capacitor includes the plurality of data lines and the plurality of first lines. It is preferable that the three power supply lines are formed by the data line and the third power supply line adjacent to each other.
According to the present invention, since the third storage capacitor can be made sufficiently large (that is, larger than the first storage capacitor and the second storage capacitor), the variation range of the potential of the data line is the light emitting element. Compared to the fluctuation range of the potential of the potential signal that defines the brightness of the signal, the potential of the gate node of the driving transistor can be set with a fine accuracy without engraving the data signal with a fine accuracy. It becomes possible. In addition, when the third storage capacitor is sufficiently large, it is possible to prevent the potential of the gate node of the driving transistor from varying for each pixel circuit, and it is possible to perform a high-quality display that prevents the occurrence of display unevenness. . The third storage capacitor may be formed by providing the data line and the second power supply line adjacent to each other in the same layer. The third storage capacitor may be formed by arranging the data line and the second power supply line adjacent to each other so as to overlap when viewed in plan.

In the electro-optical device described above, the first storage capacitor is electrically connected between the data line and the third feed line that are adjacent to each other among the plurality of data lines and the plurality of third feed lines. A plurality of first individual circuits connected in parallel, wherein each of the plurality of first individual circuits is electrically connected in series between the data line and the third feeder line adjacent to each other; The driving control circuit may include an individual capacitor and a first individual switch, and the drive control circuit may selectively turn on a part or all of the plurality of first individual switches based on the brightness information.
In the electro-optical device described above, the third storage capacitor includes a plurality of third individual circuits electrically connected in parallel, and each of the plurality of third individual circuits is electrically connected to the data line. A third individual capacitor and a third individual switch connected in series to each other, and the drive control circuit selectively selects a part or all of the plurality of third individual switches based on the brightness information. It is good also as an aspect which turns on.
According to the present invention, for example, when the brightness of the entire screen to be displayed on the display unit is bright and there is a low possibility that unevenness due to the potential fluctuation of the data line is visually recognized, the potential based on the image signal is reduced. It is possible to display a clear image with a large contrast ratio by reducing the compression ratio with respect to the fluctuation range.

  In the electro-optical device described above, the pixel circuit includes a light emission control transistor electrically connected between the drive transistor and the light emitting element, and the scanning line drive circuit includes at least the first period. In the period from the start to the end of the third period, it is preferable to maintain the light emission control transistor in an off state.

  In addition to the electro-optical device, the present invention can be conceptualized as an electronic apparatus having the electro-optical device. Typically, the electronic device includes a display device such as a head mounted display (HMD) or an electronic viewfinder.

1 is a perspective view illustrating a configuration of an electro-optical device according to a first embodiment of the invention. It is a figure which shows the structure of the same electro-optical apparatus. It is a figure which shows the drive control circuit in the same electro-optical apparatus. It is a figure which shows the pixel circuit in the same electro-optical apparatus. 6 is a timing chart showing the operation of the electro-optical device. FIG. 6 is an operation explanatory diagram of the same electro-optical device. FIG. 6 is an operation explanatory diagram of the same electro-optical device. FIG. 6 is an operation explanatory diagram of the same electro-optical device. FIG. 6 is an operation explanatory diagram of the same electro-optical device. FIG. 10 is an explanatory diagram illustrating a potential change of a gate node in the same electro-optical device. It is explanatory drawing which shows the amplitude compression of the data signal in the same electro-optical apparatus. FIG. 6 is an explanatory diagram illustrating characteristics of a transistor in the electro-optical device. It is a figure which shows the structure of the electro-optical apparatus concerning 2nd Embodiment. It is a figure which shows the drive control circuit in the same electro-optical apparatus. 6 is a timing chart showing the operation of the electro-optical device. FIG. 6 is an operation explanatory diagram of the same electro-optical device. FIG. 6 is an operation explanatory diagram of the same electro-optical device. FIG. 6 is an operation explanatory diagram of the same electro-optical device. FIG. 6 is an operation explanatory diagram of the same electro-optical device. 6 is an explanatory diagram illustrating compression of a potential width of a data signal in the electro-optical device. FIG. 10 is a diagram showing a configuration of a storage capacitor according to Modification Example 5. FIG. FIG. 10 is a diagram illustrating a configuration of a storage capacitor according to Modification Example 6. 10 is a diagram showing a configuration of a storage capacitor according to Modification Example 7. FIG. FIG. 10 is a diagram illustrating a pixel circuit according to Modification 4. It is a perspective view which shows HMD using the electro-optical apparatus which concerns on embodiment etc. FIG. It is a figure which shows the optical structure of HMD.

  Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.

<First Embodiment>
FIG. 1 is a perspective view showing a configuration of an electro-optical device 1 according to an embodiment of the present invention. The electro-optical device 1 is a micro display that displays an image on a head-mounted display, for example.
As shown in FIG. 1, the electro-optical device 1 includes a display panel 2 and a control unit 3 that controls the operation of the display panel 2. The display panel 2 includes a plurality of pixel circuits and a drive circuit that drives the pixel circuits. In the present embodiment, a plurality of pixel circuits and drive circuits included in the display panel 2 are formed on a silicon substrate, and an OLED which is an example of a light emitting element is used for the pixel circuits. The display panel 2 is housed in, for example, a frame-shaped case 82 that opens at the display unit, and one end of an FPC (Flexible Printed Circuits) substrate 84 is connected.
On the FPC board 84, the control unit 3 of the semiconductor chip is mounted by a COF (Chip On Film) technique, and a plurality of terminals 86 are provided, and are connected to an upper circuit (not shown).

FIG. 2 is a block diagram illustrating a configuration of the electro-optical device 1 according to the first embodiment. As described above, the electro-optical device 1 includes the display panel 2 and the control unit 3. Among these, the control unit 3 includes a display control circuit 4 and a drive control circuit 5.
Digital image data Video is supplied to the display control circuit 4 in synchronization with a synchronization signal from an upper circuit (not shown). Here, the image data Video is data that defines, for example, the 8-bit pixel gradation level of an image to be displayed on the display panel 2 (strictly speaking, the display unit 100 described later). The synchronization signal is a signal including a vertical synchronization signal, a horizontal synchronization signal, and a dot clock signal.
The display control circuit 4 generates a control signal Ctr based on the synchronization signal and supplies it to the display panel 2 and the drive control circuit 5. The control signal Ctr is a signal including a pulse signal, a clock signal, an enable signal, and the like.
The display control circuit 4 generates brightness information Br based on brightness designation information input from an input unit (not shown) by the user of the electro-optical device 1 and supplies the brightness information Br to the drive control circuit 5. . Here, the lightness designation information is data that defines the brightness of the entire screen when the display panel 2 (strictly speaking, the display unit 100 described later) displays an image. The brightness information Br is data that defines the brightness of the entire screen when the display unit 100 displays an image, and can take Rbr different values. Here, Rbr is a natural number of 1 or more. The brightness information Br may be set to a value equal to the brightness designation information.
In the present embodiment, the display control circuit 4 generates the brightness information Br based on the brightness designation information input by the user. However, the display control circuit 4 may generate the brightness information Br based on the image data Video. . For example, it may be calculated based on the average value of the luminance of the light emitting elements defined by the image data Video.
Next, the display control circuit 4 generates an analog image signal Vid as follows based on the brightness information Br and the image data Video. That is, the display control circuit 4 includes a storage unit 6 that stores the potential indicated by the image signal Vid, the luminance of a light emitting element (OLED 130 described later) included in the display panel 2, and brightness information Br in association with each other. The storage unit 6 is provided with Rbr look-up tables LUT corresponding to each possible value of the brightness information Br. In each look-up table LUT, the potential indicated by the image signal Vid and the luminance of the light emitting element when the screen to be displayed on the display unit 100 has a brightness corresponding to the value indicated by the brightness information Br. Correspondingly stored. The display control circuit 4 refers to the look-up table LUT corresponding to the brightness information Br, and outputs a potential corresponding to the luminance defined in the image data Video to generate the image signal Vid. Then, the display control circuit 4 supplies the generated image signal Vid to the display panel 2.

The drive control circuit 5 generates various control signals and various potentials based on the control signal Ctr and brightness information Br supplied from the display control circuit 4 and supplies them to the display panel 2.
Specifically, the drive control circuit 5 controls the control signal Sel (1), Sel (2), Sel (3) for the display panel 2 and a control signal having a logical inversion relationship with respect to these signals. / Sel (1), / Sel (2), / Sel (3), a negative logic control signal / Gini, a positive logic control signal Gref, a predetermined reset potential, Vorst, and a potential control signal Supply. Here, the potential Vref of the potential control signal is determined based on the brightness information Br. Hereinafter, the control signals Sel (1), Sel (2), and Sel (3) are collectively referred to as the control signal Sel, and the control signals / Sel (1), / Sel (2), and / Sel (3) are represented. , And may be collectively referred to as control signal / Sel.

As shown in FIG. 2, the display panel 2 includes a display unit 100 and drive circuits (the data line drive circuit 10 and the scan line drive circuit 20) that drive the display unit 100.
In the display unit 100, pixel circuits 110 corresponding to pixels of an image to be displayed are arranged in a matrix. Specifically, in the display unit 100, m rows of scanning lines 12 are provided extending in the horizontal direction (X direction) in the drawing, and (3n) columns of data lines 14 are grouped every three columns. Are extended in the vertical direction (Y direction) in the figure and are provided so as to be electrically insulated from each scanning line 12. A pixel circuit 110 is provided corresponding to the intersection of the m rows of scanning lines 12 and the (3n) columns of data lines 14. For this reason, in the present embodiment, the pixel circuits 110 are arranged in a matrix form of vertical m rows × horizontal (3n) columns.

Here, m and n are both natural numbers. In order to distinguish rows (rows) in the matrix of the scanning lines 12 and the pixel circuits 110, they may be referred to as 1, 2, 3,..., (M−1), m rows in order from the top in the drawing. Similarly, in order to distinguish the columns of the data line 14 and the matrix of the pixel circuit 110, they may be referred to as 1, 2, 3, ..., (3n-1), (3n) columns in order from the left in the figure. . Further, in order to generalize and describe the group of data lines 14, when an integer j of 1 to n is used, the j-th group counted from the left includes the (3j-2) th column, (3j-1). ) And (3j) th column data lines 14 belong.
Note that the three pixel circuits 110 corresponding to the intersection of the scanning lines 12 in the same row and the three columns of data lines 14 belonging to the same group respectively have R (red), G (green), and B (blue) pixels. Correspondingly, these three pixels represent one dot of a color image to be displayed. That is, in the present embodiment, one dot color is expressed by additive color mixing by light emission of an OLED corresponding to RGB.

Further, as shown in FIG. 2, in the display unit 100, (3n) rows of feed lines 16 (third feed lines) extend in the vertical direction and are electrically insulated from each scanning line 12. Provided. The power supply lines 16 are commonly supplied with the potential Vorst. Here, in order to distinguish the columns of the feeder lines 16, they may be called the feeder lines 16 in the first, second, third,..., (3n), (3n + 1) th columns in order from the left in the drawing. Each of the first to (3n) th column feeder lines 16 is provided along each of the first to (3n) th column data lines 14. That is, when an integer of 1 or more and (3n) or less is p, the p-th power supply line 16 and the p-th data line 14 are provided adjacent to each other.
Further, the display panel 2 is provided with (3n) storage capacitors 50 corresponding to the first to (3n) th column data lines 14. One end of the storage capacitor 50 is connected to the data line 14, and the other end is connected to the power supply line 16. That is, the storage capacitor 50 functions as a first storage capacitor that holds the potential of the data line 14. The storage capacitor 50 is preferably formed by sandwiching an insulator (dielectric) between the power supply line 16 and the data line 14 adjacent to each other. In this case, the distance between the power supply line 16 and the data line 14 adjacent to each other is determined so as to obtain a required capacity. Hereinafter, the capacitance value of the storage capacitor 50 is expressed as Cdt.
In FIG. 2, the storage capacitor 50 is provided outside the display unit 100, but this is only an equivalent circuit and may be provided inside the display unit 100. Further, the storage capacitor 50 may be provided from the inside to the outside of the display unit 100.

The scanning line driving circuit 20 generates a scanning signal Gwr for sequentially scanning the scanning lines 12 for each row over the period of the frame in accordance with the control signal Ctr. Here, the scanning signals Gwr supplied to the scanning lines 12 of 1, 2, 3,..., (M−1), and the m-th row are Gwr (1), Gwr (2), Gwr (3),. , Gwr (m-1), Gwr (m).
In addition to the scanning signals Gwr (1) to Gwr (m), the scanning line driving circuit 20 generates various control signals synchronized with the scanning signal Gwr for each row and supplies them to the display unit 100. In FIG. 2, the illustration is omitted. The frame period is a period required for the electro-optical device 1 to display an image for one cut (frame). For example, if the frequency of the vertical synchronization signal included in the synchronization signal is 120 Hz, the first period is 1. This is a period of 8.3 milliseconds corresponding to the period.

The data line driving circuit 10 includes (3n) level shift circuits LS provided in a one-to-one correspondence with each of the (3n) columns of data lines 14 and each of the three columns of data lines 14 constituting each group. N demultiplexers DM and a data signal supply circuit 70 are provided.
The data signal supply circuit 70 generates data signals Vd (1), Vd (2),..., Vd (n) based on the image signal Vid and the control signal Ctr supplied from the control unit 3. Specifically, the data signal supply circuit 70 includes, for example, a shift register, and data signals Vd (1), Vd (2),..., Vd obtained by time-dividing the image signal Vid based on the control signal Ctr. Generate (n). The data signal supply circuit 70 applies the data signals Vd (1), Vd (2),..., Vd (n) to the demultiplexers DM corresponding to the first, second,. Supply. Note that the maximum potential of the data signals Vd (1) to Vd (n) is Vmax, and the minimum value is Vmin.

  FIG. 3 is a circuit diagram for explaining the configuration of the demultiplexer DM and the level shift circuit LS. FIG. 3 representatively shows the demultiplexer DM belonging to the j-th group and the three level shift circuits LS connected to the demultiplexer DM. Hereinafter, the demultiplexer DM belonging to the j-th group may be referred to as DM (j).

Hereinafter, the configuration of the demultiplexer DM and the level shift circuit LS will be described with reference to FIG. 3 in addition to FIG.
As shown in FIG. 3, the demultiplexer DM is an aggregate of transmission gates 34 (second switches) provided for each column, and sequentially supplies data signals to three columns constituting each group. is there. Here, the input terminals of the transmission gates 34 corresponding to the (3j-2), (3j-1), and (3j) columns belonging to the jth group are commonly connected to each other, and the data signal Vd ( j) is supplied. The transmission gate 34 provided in the leftmost column (3j-2) in the j-th group has the control signal Sel (1) at the H level (when the control signal / Sel (1) is at the L level. ) Is turned on (conductive). Similarly, in the j-th group, the transmission gate 34 provided in the (3j−1) column which is the central column has the control signal Sel (2) at the H level (the control signal / Sel (2) is at the L level. The transmission gate 34 provided in the (3j) column which is the rightmost column in the j-th group when the control signal Sel (3) is at the H level (control signal / Sel (3) Is on).

  The level shift circuit LS has a set of a storage capacitor 44, an N-channel MOS transistor 43 (first transistor), and a P-channel MOS transistor 45 (second transistor) for each column, and a transmission gate for each column. The potential of the data signal output from the output terminal 34 is shifted. Here, one end of the storage capacitor 44 is connected to the data line 14 of the corresponding column and the drain node of the transistor 45, while the other end of the storage capacitor 44 is the output end of the transmission gate 34 and the drain node of the transistor 43. And connected to. That is, the storage capacitor 44 functions as a third storage capacitor having one end connected to the data line 14. Although omitted in FIG. 3, the capacitance value of the storage capacitor 44 is Crf1.

The source nodes of the transistors 45 in each column are commonly connected to the power supply line 61 (first power supply line) across the columns, and the control signal / Gini is commonly supplied from the drive control circuit 5 to the gate nodes across the columns. The For this reason, the transistor 45 electrically connects the node h2 (and the data line 14), which is one end of the storage capacitor 44, and the power supply line 61 when the control signal / Gini is at the L level. Is electrically disconnected when is at the H level. Note that the potential Vini (initial potential) is supplied from the drive control circuit 5 to the power supply line 61.
The source node of the transistor 43 in each column is connected to the power supply line 62 (potential control line) in common across the columns, and the control signal Gref from the drive control circuit 5 is supplied in common across the columns to the gate node. The For this reason, the transistor 43 electrically connects the node h1 which is the other end of the storage capacitor 44 and the power supply line 62 when the control signal Gref is at the H level, and electrically connects when the control signal Gref is at the L level. Not connected to. Note that a potential Vref (potential control signal) is supplied from the drive control circuit 5 to the power supply line 62.

  The pixel circuit 110 will be described with reference to FIG. Since each pixel circuit 110 has the same configuration when viewed electrically, here, the i-th row (3j−) located in the (3j-2) th column of the leftmost column in the j-th group is the i-th row. 2) The pixel circuit 110 in the column will be described as an example. Note that i is a symbol for generally indicating a row in which the pixel circuits 110 are arranged, and is an integer of 1 to m.

  As shown in FIG. 4, the pixel circuit 110 includes P-channel MOS transistors 121 to 125, an OLED 130, and a storage capacitor 132. The pixel circuit 110 is supplied with a scanning signal Gwr (i), control signals Gel (i), Gcmp (i), and Gorst (i). Here, the scanning signal Gwr (i), the control signals Gel (i), Gcmp (i), and Gorst (i) are respectively supplied by the scanning line driving circuit 20 corresponding to the i-th row. Therefore, the scanning signal Gwr (i), the control signals Gel (i), Gcmp (i), and Gorst (i) are columns other than the column of interest (3j-2) if they are the i-th row. Are also commonly supplied to the pixel circuits.

In the transistor 122, the gate node is connected to the i-th scanning line 12, one of the drain and source nodes is connected to the data line 14 in the (3j−2) th column, and the other is connected to the gate node g in the transistor 121. The storage capacitor 132 is connected to one end of the storage capacitor 132 and one of the source node and the drain node of the transistor 123. That is, the transistor 122 is electrically connected between the gate node g of the transistor 121 and the data line 14, and controls the electrical connection between the gate node g of the transistor 121 and the data line 14. It functions as a built-in transistor. Here, the gate node of the transistor 121 is denoted by g to distinguish it from other nodes.
The transistor 121 has a source node connected to the power supply line 116, and a drain node connected to the other of the source node or the drain node of the transistor 123 and the source node of the transistor 124. Here, the power supply line 116 is supplied with a potential Vel that is higher in the power supply in the pixel circuit 110.
In the transistors 121 and 122, the drain node or the source node is described as being electrically connected to another component. However, when the potential relationship is changed, the node described as the drain node becomes the source node and the source node is described. It is possible that this node becomes a drain node. The same applies to the transistors 123 to 125 described below. In any case, for example, one of the source node and the drain node of the transistor 121 is electrically connected to the power supply line 116. The other of the source node and the drain node of the transistor 121 is electrically connected to the OLED 130 through the transistor 124. In FIG. 4, the other of the source node and the drain node of the transistor 121 is electrically connected to the anode of the OLED 130 through the transistor 123. When the transistor 121 operates in the saturation region, the conduction state according to the voltage between the gate and the source of the transistor 121 is controlled, and a current according to the conduction state is supplied to the OLED 130. That is, the transistor 121 functions as a driving transistor that passes a current according to the voltage between the gate node and the source node of the transistor 121.
A control signal Gcmp (i) is supplied to the gate node of the transistor 123. The transistor 123 functions as a threshold compensation transistor that controls electrical connection between the source node and the gate node g of the transistor 121.
The control signal Gel (i) is supplied to the gate node of the transistor 124, and the drain node is connected to the source node of the transistor 125 and the anode of the OLED 130, respectively. That is, the transistor 124 functions as a light emission control transistor that controls electrical connection between the drain node of the transistor 121 and the anode of the OLED 130.
The control signal Gorst (i) corresponding to the i-th row is supplied to the gate node of the transistor 125, and the drain node is connected to the power supply line 16 in the (3j-1) th column and is kept at the potential Vorst. The transistor 125 functions as an initialization transistor that controls electrical connection between the power supply line 16 and the anode of the OLED 130.
In this embodiment, since the display panel 2 is formed on a silicon substrate, the substrate potential of the transistors 121 to 125 is set to the potential Vel.

The storage capacitor 132 has one end connected to the gate node g of the transistor 121 and the other end connected to the power supply line 116. Therefore, the storage capacitor 132 functions as a second storage capacitor that holds the voltage between the gate and the source of the transistor 121. The capacitance value of the storage capacitor 132 is expressed as Cpix. At this time, the capacitance value Cdt of the storage capacitor 50, the capacitance value Crf1 of the storage capacitor 44, and the capacitance value Cpix of the storage capacitor 132 are:
Cdt >> Crf1 >> Cpix
Is set to be That is, Cdt is set to be larger than Crf1, and Cpix is set to be sufficiently smaller than Cdt and Crf1. Note that as the storage capacitor 132, a capacitor parasitic to the gate node g of the transistor 121 may be used, or a capacitor formed by sandwiching an insulating layer between different conductive layers in a silicon substrate may be used.

The anode of the OLED 130 is a pixel electrode provided individually for each pixel circuit 110. On the other hand, the cathode of the OLED 130 is a common electrode 118 that is common to all the pixel circuits 110, and is kept at a potential Vct that is the lower side of the power supply in the pixel circuit 110. The OLED 130 is an element in which a white organic EL layer is sandwiched between an anode and a light-transmitting cathode on the silicon substrate. A color filter corresponding to any of RGB is superimposed on the emission side (cathode side) of the OLED 130.
In such an OLED 130, when current flows from the anode to the cathode, holes injected from the anode and electrons injected from the cathode are recombined in the organic EL layer to generate excitons, and white light is generated. . The white light generated at this time passes through the cathode opposite to the silicon substrate (anode), and is colored by a color filter so as to be visually recognized by the viewer.

<Operation of First Embodiment>
The operation of the electro-optical device 1 will be described with reference to FIG. FIG. 5 is a timing chart for explaining the operation of each part in the electro-optical device 1. As shown in this figure, the scanning line driving circuit 20 sequentially switches the scanning signals Gwr (1) to Gwr (m) to the L level, and sets the scanning lines 12 in the first to mth rows to 1 in the period of one frame. Scan in order for each horizontal scanning period (H). The operation in one horizontal scanning period (H) is common to the pixel circuits 110 in each row. Therefore, in the following, the operation will be described focusing on the pixel circuit 110 in the i-th row (3j-2) column in the scanning period in which the i-th row is horizontally scanned.

  In the present embodiment, the scanning period of the i-th row is roughly divided into an initialization period indicated by (b), a compensation period indicated by (c), and a writing period indicated by (d) in FIG. It is done. Then, after the writing period of (d), the light emission period shown in (a) is reached, and the scanning period of the i-th row is reached again after the elapse of one frame period. Therefore, in the order of time, a cycle of (light emission period) → initialization period → compensation period → writing period → (light emission period) is repeated. In FIG. 5, the scanning signal Gwr (i-1), the control signals Gel (i-1), Gcmp (i-1), Gcmp (i-1), corresponding to the (i-1) th row before the ith row. For each of the Gorst (i-1), one horizontal scan is temporally performed in comparison with the scanning signal Gwr (i) and the control signals Gel (i), Gcmp (i), and Gorst (i) corresponding to the i-th row. The waveform is preceded in time by the period (H).

<Light emission period>
For convenience of explanation, the light emission period which is the premise of the initialization period will be described. As shown in FIG. 5, in the light emission period of the i-th row, the scanning line driving circuit 20 sets the scanning signal Gwr (i) to the H level, the control signal Gel (i) to the L level, and the control signal Gcmp (i ) Is set to H level, and the control signal Gorst (i) is set to H level. For this reason, as shown in FIG. 6, in the pixel circuit 110 in the i row (3j−2) column, the transistor 124 is turned on, while the transistors 122, 123, and 125 are turned off. Therefore, the transistor 121 supplies a current Ids corresponding to the gate-source voltage Vgs to the OLED 130. As will be described later, in this embodiment, the voltage Vgs in the light emission period is a value that is level-shifted from the threshold voltage of the transistor 121 according to the potential of the data signal. Therefore, a current corresponding to the gradation level is supplied to the OLED 130 in a state where the threshold voltage of the transistor 121 is compensated.

  Note that since the light emission period of the i-th row is a period during which horizontal scanning is performed except for the i-th row, the potential of the data line 14 varies appropriately. However, in the pixel circuit 110 in the i-th row, since the transistor 122 is off, the potential fluctuation of the data line 14 is not considered here. Further, in FIG. 6, paths that are important in the explanation of operations are indicated by bold lines (the same applies to FIGS. 7 to 9 and 15 to 18 below).

<Initialization period>
Next, when the scanning period of the i-th row is reached, first, the initialization period (b) is started as the first period. In the initialization period, as shown in FIG. 5, the scanning line driving circuit 20 sets the scanning signal Gwr (i) to the H level, the control signal Gel (i) to the H level, and the control signal Gcmp (i) to the H level. The control signal Gorst (i) is set to the L level.
Therefore, as illustrated in FIG. 7, in the pixel circuit 110 in the i row (3j−2) column, the transistor 124 is turned off and the transistor 125 is turned on. As a result, the path of the current supplied to the OLED 130 is cut off, and the anode of the OLED 130 is reset to the potential Vorst. Since the OLED 130 has a configuration in which the organic EL layer is sandwiched between the anode and the cathode as described above, the capacitance Coled is parasitic between the anode and the cathode in parallel as shown by a broken line in the drawing. When a current flows through the OLED 130 during the light emission period, the voltage across the anode and cathode of the OLED 130 is held by the capacitor Coled, but this holding voltage is reset by turning on the transistor 125. For this reason, in this embodiment, when a current flows again through the OLED 130 in a later light emission period, it is less likely to be affected by the voltage held by the capacitor Coled.

  Specifically, for example, when switching from a high-brightness display state to a low-brightness display state, if the configuration does not reset, the high voltage when the luminance is high (a large current flows) is retained. In addition, even if a small current is applied, an excessive current flows and the display state with low luminance cannot be achieved. On the other hand, in this embodiment, since the potential of the anode of the OLED 130 is reset when the transistor 125 is turned on, the reproducibility on the low luminance side is improved. In the present embodiment, the potential Vorst is set such that the difference between the potential Vorst and the potential Vct of the common electrode 118 is lower than the light emission threshold voltage of the OLED 130. Therefore, the OLED 130 is in an off (non-light emitting) state in the initialization period (a compensation period and a writing period described below).

On the other hand, in the initialization period, the drive control circuit 5 sets the control signal / Gini to the L level and the control signal Gref to the H level, as shown in FIG. Therefore, as shown in FIG. 7, in the level shift circuit LS, the transistor 43 and the transistor 45 are turned on. Thereby, one end of the storage capacitor 44 and the power supply line 61 are electrically connected, and the node h2 and the data line 14 electrically connected to one end of the storage capacitor 44 are initialized to the potential Vini, while the storage capacitor The other end of 44 and the power supply line 62 are electrically connected, and the node h1 electrically connected to the other end of the storage capacitor 44 is initialized to the potential Vref.
In this embodiment, the potential Vini is set such that (Vel−Vini) is larger than the threshold voltage | Vth | of the transistor 121. Note that since the transistor 121 is a P-channel type, the threshold voltage Vth with respect to the potential of the source node is negative. Therefore, in order to prevent confusion in the description of the height relationship, the threshold voltage is expressed by the absolute value | Vth | and defined by the magnitude relationship.

<Compensation period>
In the i-th scanning period, the second period is the compensation period (c). In the compensation period, the drive control circuit 5 sets the control signal / Gini to the H level and the control signal Gref to the H level, as shown in FIG. Therefore, as shown in FIG. 8, in the level shift circuit LS, the transistor 43 is turned on, while the transistor 45 is turned off. As a result, the other end of the storage capacitor 44 and the power supply line 62 are electrically connected, and the node h1 is set to the potential Vref.

  In the compensation period, as shown in FIG. 5, the scanning line driving circuit 20 sets the scanning signal Gwr (i) to the L level, the control signal Gel (i) to the H level, and the control signal Gcmp (i). The control signal Gorst (i) is set to the L level and to the L level. For this reason, as shown in FIG. 8, since the transistor 123 is turned on, the transistor 121 is diode-connected. As a result, a drain current flows through the transistor 121 and charges the gate node g and the data line 14. Specifically, the current flows through a path of the feeder line 116 → the transistor 121 → the transistor 123 → the transistor 122 → the data line 14 in the (3j-2) th column. Therefore, the data line 14 and the gate node g that are connected to each other when the transistor 121 is turned on rise from the potential Vini. However, since the current flowing through the path becomes difficult to flow as the gate node g approaches the potential (Vel− | Vth |), the data line 14 and the gate node g have the potential (Vel−) until the end of the compensation period. | Vth |). Accordingly, the storage capacitor 132 holds the threshold voltage | Vth | of the transistor 121 until the end of the compensation period. Hereinafter, the potential (Vel− | Vth |) of the gate node g at the end of the compensation period may be expressed as a potential Vp.

<Writing period>
After the initialization period, the writing period (d) is reached as the third period. In the writing period, as shown in FIG. 5, the scanning line driving circuit 20 sets the scanning signal Gwr (i) to the L level, the control signal Gel (i) to the H level, and the control signal Gcmp (i) to the H level. The control signal Gorst (i) is set to the L level. As a result, the diode connection of the transistor 121 is released. Further, as shown in FIG. 5, the drive control circuit 5 sets the control signal / Gini to the H level and the control signal Gref to the L level. As a result, the transistor 45 is kept off and the transistor 43 is also turned off. For this reason, although the path from the data line 14 in the (3j-2) th column to the gate node g in the pixel circuit 110 in the i-th row (3j-2) column is in a floating state, the potential in the path is held The capacitances 50 and 132 maintain (Vel− | Vth |), that is, the potential Vp.

  In the writing period of the i-th row, the data signal supply circuit 70, in the j-th group, sequentially outputs the data signal Vd (j) in the i-th row (3j-2) column and the i-th row (3j-1) column. , The potential is switched according to the gradation level of the pixel in the i row (3j) column. On the other hand, the drive control circuit 5 sets the control signals Sel (1), Sel (2), and Sel (3) to the H level exclusively in order in synchronization with the switching of the potential of the data signal. The drive control circuit 5 is omitted in FIG. 5, but the control signals Sel (1), Sel (2), Sel (3) are in a logically inverted relationship with the control signals Sel (1), Sel (2), / Sel ( 2) and / Sel (3) are also output. Accordingly, in the demultiplexer DM, the transmission gates 34 are turned on in the order of the left end column, the center column, and the right end column in each group.

Here, when the transmission gate 34 in the leftmost column is turned on by the control signals Sel (1) and / Sel (1), as shown in FIG. 9, the node h1, which is the other end of the storage capacitor 44, is in the compensation period. It changes from the set potential Vref to the potential of the data signal Vd (j), that is, the potential corresponding to the gradation level of the pixel in the i row (3j-2) column.
The potential change of the gate node g at this time will be described in detail with reference to FIG. FIG. 10 is an explanatory diagram for explaining potential changes of the gate node g and the node h1 in the compensation period and the writing period. FIG. 10A shows the gate node g and the node h1 at the end of the compensation period (strictly, the period from the end of the compensation period until the data signal Vd (j) is supplied to the other end of the storage capacitor 44). FIG. 10B shows the potential at the end of the writing period (strictly speaking, the period after the data signal Vd (j) is supplied to the other end of the storage capacitor 44 in the writing period). The potentials of the gate node g and the node h1 are shown. Hereinafter, the potential of the gate node g after the change is represented as Vgate.
As shown in FIGS. 8 and 9, the storage capacitor 50 and the storage capacitor 132 are electrically connected in parallel in the compensation period and the writing period. Therefore, the capacity value C0 of the combined capacity of the storage capacitor 50 and the storage capacitor 132 is expressed by the following equation (1).
C0 = Cpix + Cdt (1)
Therefore, if the charge accumulated in the combined capacitance of the holding capacitor 50 and the holding capacitor 132 at the end of the compensation period is Q0a (FIG. 10A), and the charge accumulated in the combined capacitor at the end of the writing period is Q0b. (FIG. 10B), the charge (Q0a-Q0b) flowing out from the combined capacitance of the storage capacitor 50 and the storage capacitor 132 in the writing period is expressed by the following equation (2).
Q0a-Q0b = C0 * (Vp-Vgate) (2)
Similarly, Q1a is the charge accumulated in the storage capacitor 44 at the end of the compensation period (FIG. 10A), and Q1b is the charge stored in the storage capacitor 44 at the end of the write period (FIG. 10 ( B)) In the writing period, the charge (Q1b-Q1a) flowing into the storage capacitor 44 is expressed by the following equation (3).
Q1b-Q1a = Crf1 * {(Vgate-Vd (j))-(Vp-Vref)} (3)
In the writing period, since the charge flowing out from the combined capacitance of the storage capacitor 50 and the storage capacitor 132 is equal to the charge flowing into the storage capacitor 44, the following equation (4) is established.
Q0a-Q0b = Q1b-Q1a (4)
Therefore, the potential Vgate of the gate node g in the writing period can be calculated from the equations (1) to (3). Specifically, the potential Vgate is expressed by the following formula (5).
Vgate = {Crf1 / (Crf1 + C0)} * {Vd (j) -Vref} + Vp (5)
Here, when the capacitance ratio k1 shown in the following formula (6) is introduced, the potential Vgate can also be expressed by the following formula (7).
k1 = Crf1 / (Crf1 + Cdt + Cpix) (6)
Vgate = k1 * {Vd (j) -Vref} + Vp (7)
If the potential change amount {Vd (j) −Vref} of the node h1 at this time is expressed by ΔV and the potential change amount (Vgate−Vp) of the gate node g is expressed by ΔVg, the following equation (8) is established.
ΔVg = k1 * ΔV (8)
Thus, the gate node g is shifted upward from the potential Vp = (Vel− | Vth |) in the compensation period by a value (k1 * ΔV) obtained by multiplying the potential change ΔV of the node h1 by the capacitance ratio k1. The value Vgate = Vel− | Vth | + k1 · ΔV.
At this time, the absolute value | Vgs | of the voltage Vgs of the transistor 121 is a value obtained by subtracting the threshold voltage | Vth | That is, the following formula (9) is established.
| Vgs | = | Vth | −k1 * ΔV (9)

FIG. 11 is a diagram showing the relationship between the potential of the data signal and the potential of the gate node g in the writing period. As described above, the data signal supplied from the drive control circuit 5 can take a potential range from the minimum value Vmin to the maximum value Vmax according to the gradation level of the pixel. In this embodiment, the data signal is not directly written to the gate node g, but is level-shifted and written to the gate notebook g as shown in the figure.
At this time, the potential range ΔVgate of the gate node g is compressed to a value obtained by multiplying the potential range ΔVdata (= Vmax−Vmin) of the data signal by the capacitance ratio k1, as shown in the following equation (10).
ΔVgate = k1 * ΔVdata (10)
As described above, since the capacitance value Cpix is sufficiently smaller than the capacitance value Crf1 and the capacitance value Cdt, for example, when the capacitances of the holding capacitors 44 and 50 are set so that Crf1: Cdt = 1: 9, the gate The potential range ΔVgate of the node g can be compressed to 1/10 of the potential range ΔVdata of the data signal.
In addition, the potential Vp (= Vel− | Vth |) and the potential Vref can determine how much the potential range ΔVgate of the gate node g is shifted in which direction with respect to the potential range ΔVdata of the data signal. This is because the potential range ΔVdata of the data signal is compressed with the capacitance ratio k1 with respect to the potential Vref, and the compression range shifted with reference to the potential Vp becomes the potential range ΔVgate of the gate node g. Because.

  Thus, in the writing period of the i-th row, the gate node g of the pixel circuit 110 in the i-th row has a capacitance from the potential Vp (= Vel− | Vth |) in the compensation period to the potential change amount ΔV of the node h. A potential (Vel− | Vth | + k1 · ΔV) shifted by an amount corresponding to the ratio k1 is written.

<Light emission period>
The light emission period is started after the writing period of the i-th row is completed. In the present embodiment, after the writing period of the i-th row ends, the light emission period starts after one horizontal scanning period. In the light emission period, as described above, the scanning line driving circuit 20 sets the scanning signal Gwr (i) to the H level, so that the transistor 122 is turned off. As a result, the potential of the gate node g is maintained at the shifted potential (Vel− | Vth | + k1 · ΔV). In the light emission period, the scanning line driving circuit 20 sets the control signal Gel (i) to the L level as described above, so that the transistor 124 is turned on in the pixel circuit 110 in the i row (3j-2) column. To do. Since the voltage Vgs between the gate and the source is (| Vth | −k1 · ΔV), as shown in FIG. 6, the current corresponding to the gradation level causes the threshold voltage of the transistor 121 to be applied to the OLED 130. It will be supplied in a compensated state.
Such an operation is also executed in parallel in time in other pixel circuits 110 in the i row other than the pixel circuit 110 in the (3j-2) th column in the scanning period of the i row. Further, such an operation on the i-th row is actually executed in the order of 1, 2, 3,..., (M−1), m-th row in the period of one frame, and is repeated for each frame. It is.

  According to the present embodiment, the potential range ΔVgate at the gate node g is narrowed with respect to the potential range ΔVdata of the data signal. Can be applied between the gate and the source. Therefore, the current supplied to the OLED 130 is accurately controlled even when the minute current flowing through the OLED 130 changes relatively greatly with respect to the change in the gate-source voltage Vgs of the transistor 121 in the pixel circuit 110. Is possible.

Note that the transistor 121 supplies the OLED 130 with a current Ids corresponding to the gate-source voltage Vgs shown in Expression (8). The OLED 130 emits light with a luminance corresponding to the magnitude of the current Ids.
Therefore, when the potential range ΔVgate of the gate node g is compressed with respect to the potential range ΔVdata of the data signal, it is difficult to cause the OLED 130 to emit light with high brightness as compared with the case where the potential range ΔVgate is not compressed. In this case, the screen displayed on the display unit 100 becomes dark overall.
On the other hand, in the present embodiment, the drive control circuit 5 controls the potential Vref based on the brightness information Br. Specifically, when the brightness of the entire screen to be displayed on the display unit 100 is bright, the drive control circuit 5 sets the potential Vref to a high potential. As a result, the voltage Vgs can be increased, and both a bright image display and an improvement in the control accuracy of the current Ids can be achieved.

Further, as indicated by a broken line in FIG. 4, there is a case where a capacitance Cprs is parasitic between the data line 14 and the gate node g in the pixel circuit 110. In this case, if the potential change width of the data line 14 is large, it is propagated to the gate node g via the capacitor Cprs, so-called crosstalk or unevenness occurs, and the display quality is deteriorated. The influence of the capacitance Cprs is noticeable when the pixel circuit 110 is miniaturized.
On the other hand, in the present embodiment, the potential change range of the data line 14 is also narrowed with respect to the potential range ΔVdata of the data signal, so that the influence via the capacitor Cprs can be suppressed.

  Further, according to this embodiment, the current Ids supplied to the OLED 130 by the transistor 121 cancels the influence of the threshold voltage. Therefore, according to the present embodiment, even if the threshold voltage of the transistor 121 varies from pixel circuit 110 to pixel circuit 110, the variation is compensated and a current corresponding to the gradation level is supplied to the OLED 130. As a result of suppressing the occurrence of display unevenness that impairs uniformity, high-quality display is possible.

This cancellation will be described with reference to FIG. As shown in this figure, the transistor 121 operates in a weak inversion region (subthreshold region) in order to control a minute current supplied to the OLED 130.
In the figure, A indicates a transistor having a large threshold voltage | Vth |, and B indicates a transistor having a small threshold voltage | Vth |. In FIG. 12, the gate-source voltage Vgs is the difference between the characteristic indicated by the solid line and the potential Vel. In FIG. 10, the current on the vertical scale is shown as a logarithm with the direction from the source to the drain being negative (down).
In the compensation period, the gate node g changes from the potential Vref_H to the potential (Vel− | Vth |). Therefore, the transistor A having a large threshold voltage | Vth | moves from S to Aa while the transistor B having a small threshold voltage | Vth | moves from S to Ba.
Next, when the potential of the data signal to the pixel circuit 110 to which the two transistors belong is the same, that is, when the same gradation level is designated, the potential shift amount from the operating points Aa and Ba is Are the same k1 · ΔV. Therefore, the operating point of the transistor A moves from Aa to Ab, and the operating point of the transistor B moves from Ba to Bb. However, the current at the operating point after the potential shift is almost the same in both the transistors A and B. Ids will be aligned.

Second Embodiment
In the first embodiment, the data signal is directly supplied by the demultiplexer DM to the other end of the storage capacitor 44 of each column, that is, the node h. For this reason, the scanning period of each row is an equal writing period in which a data signal is supplied from the drive control circuit 5, and thus there is a great time restriction.
Next, a second embodiment that can relax such time constraints will be described. In the following, in order to avoid duplication of explanation, a description will be given focusing on portions that are different from the first embodiment.

  FIGS. 13 and 14 are diagrams illustrating the configuration of the electro-optical device 1 according to the second embodiment. The second embodiment shown in this figure is different from the first embodiment shown in FIGS. 2 and 3 mainly in each level shift circuit LS in the storage capacitor 41 (fourth storage capacitor) and the transmission gate 42. (First switch) is provided.

Specifically, as shown in FIG. 14, the transmission gate 42 is electrically interposed between the output end of the transmission gate 34 and the other end of the storage capacitor 44. That is, the input end of the transmission gate 42 is connected to the output end of the transmission gate 34, and the output end of the transmission gate 42 is connected to the other end of the holding capacitor 44.
Further, as shown in FIGS. 13 and 14, the drive control circuit 5 supplies the control signal Gcpl and the control signal / Gcpl in common to the transmission gates 42 in each column. The transmission gates 42 in each column are simultaneously turned on when the control signal Gcpl is at the H level (when the control signal / Gcpl is at the L level).

  In each column, the node h3, which is one end of the holding capacitor 41, is connected to the output end of the transmission gate 34 (and the input end of the transmission gate 42), and the node h4, which is the other end of the holding capacitor 41, has a fixed potential, For example, the power supply line 63 (second power supply line) supplied with the potential Vss is grounded in common. Although omitted in FIG. 14, the capacitance value of the storage capacitor 41 is Crf2. Note that the potential Vss corresponds to an L level of a scanning signal or a control signal that is a logic signal.

<Operation of Second Embodiment>
The operation of the electro-optical device 1 according to the second embodiment will be described with reference to FIG. FIG. 15 is a timing chart for explaining the operation in the second embodiment.
As shown in this figure, the scanning signals Gwr (1) to Gwr (m) are sequentially switched to the L level, and the scanning lines 12 in the 1st to m-th rows in one frame period are in one horizontal scanning period (H). The points that are scanned in turn are the same as in the first embodiment. In the second embodiment, the scanning period of the i-th row is in the order of the initialization period indicated by (b), the compensation period indicated by (c), and the writing period indicated by (d). This is also the same as in the first embodiment. In the second embodiment, during the writing period (d), the scanning signal Gwr is changed from L to H level when the control signal Gcpl is changed from L to H level (when the control signal / Gcpl is changed to L level). It is a period until it becomes.
Also in the second embodiment, as in the first embodiment, in the order of time, a cycle of (light emission period) → initialization period → compensation period → writing period → (light emission period) is repeated. However, the second embodiment is different from the first embodiment in that the data signal supply precedes the write period, not the data signal supply period equal writing period. Specifically, the second embodiment is different from the first embodiment in that a data signal can be supplied over the initialization period (a) and the compensation period (b).

<Light emission period>
As shown in FIG. 15, in the light emission period of the i-th row, the scanning line driving circuit 20 sets the scanning signal Gwr (i) to the H level, the control signal Gel (i) to the L level, and the control signal Gcmp (i ) Is set to H level, and the control signal Gorst (i) is set to H level. Therefore, as shown in FIG. 16, in the pixel circuit 110 in the i row (3j-2) column, the transistor 124 is turned on, while the transistors 122, 123, and 125 are turned off. This is basically the same as in the first embodiment. That is, the transistor 121 supplies a current Ids corresponding to the gate-source voltage Vgs to the OLED 130.

<Initialization period>
In the scanning period of the i-th row, the initialization period (first period) (b) starts first. In the initialization period, as shown in FIG. 15, the scanning line driving circuit 20 sets the scanning signal Gwr (i) to the H level, the control signal Gel (i) to the H level, and the control signal Gcmp (i) to the H level. The control signal Gorst (i) is set to the L level. For this reason, as shown in FIG. 17, in the pixel circuit 110 in the i-th row (3j-2) column, the transistor 124 is turned off and the transistor 125 is turned on. As a result, the path of the current supplied to the OLED 130 is cut off, and the anode of the OLED 130 is reset to the potential Vorst by turning on the transistor 124. Therefore, the operation in the pixel circuit 110 is basically the same as in the first embodiment. Become.

  On the other hand, in the initialization period, as shown in FIG. 15, the drive control circuit 5 sets the control signal / Gini to L level, the control signal Gref to H level, and the control signal Gcpl to L level. Therefore, as shown in FIG. 17, the transistor 43 and the transistor 45 are turned on. As a result, one end of the storage capacitor 44 and the data line 14 are initialized to the potential Vini, and the other end of the storage capacitor 44 is initialized to the potential Vref.

As described above, in the second embodiment, the data signal supply circuit 70 supplies a data signal over the initialization period and the compensation period. That is, in the j-th group, the data signal supply circuit 70 sequentially outputs the data signal Vd (j) in i row (3j-2) column, i row (3j-1) column, i row (3j). The potential is switched according to the gradation level of the pixels in the column. On the other hand, the drive control circuit 5 exclusively sets the control signals Sel (1), Sel (2), Sel (3) to the H level in order in accordance with the switching of the potential of the data signal. As a result, the three transmission gates 34 provided in each demultiplexer DM are turned on in the order of the left end column, the center column, and the right end column, respectively.
Here, in the initialization period, when the transmission gate 34 in the leftmost column belonging to the jth group is turned on by the control signal Sel (1), the data signal Vd (j) is stored in the storage capacitor 41 as shown in FIG. Therefore, the data signal is held by the holding capacitor 41.

<Compensation period>
In the i-th scanning period, the compensation period (c) follows. In the compensation period, as shown in FIG. 15, the scanning line driving circuit 20 sets the scanning signal Gwr (i) to the L level, the control signal Gel (i) to the H level, and the control signal Gcmp (i) to the L level. The control signal Gorst (i) is set to the L level. Therefore, as illustrated in FIG. 18, in the pixel circuit 110 in the i row (3j−2) column, the transistor 122 is turned on and the gate node g is electrically connected to the data line 14, while the transistor 123 Is turned on, the transistor 121 is diode-connected. Therefore, the current flows through the path of the feeder line 116 → the transistor 121 → the transistor 123 → the transistor 122 → the data line 14 in the (3j−2) th column, so that the gate node g rises from the potential Vini and eventually (Vel− | Vth |). Therefore, also in the second embodiment, the storage capacitor 132 holds the threshold voltage | Vth | of the transistor 121 until the end of the compensation period.

  In the compensation period, as shown in FIG. 15, the drive control circuit 5 sets the control signal / Gini to the H level, the control signal Gref to the H level, and the control signal Gcpl to the L level. For this reason, as shown in FIG. 18, in the level shift circuit LS, the transistor 43 is turned on, while the transistor 45 is turned off. As a result, the other end of the storage capacitor 44 and the power supply line 62 are electrically connected, and the node h1 is set to the potential Vref.

In the compensation period, when the transmission gate 34 in the leftmost column belonging to the j-th group is turned on by the control signal Sel (1), the data signal Vd (j) is held by the holding capacitor 41 as shown in FIG. Is done.
Note that when the transmission gate 34 in the leftmost column belonging to the jth group is already turned on by the control signal Sel (1) in the initialization period, the transmission gate 34 is not turned on in the compensation period. There is no change in that the data signal Vd (j) is held in the holding capacitor 41.

When the compensation period ends, the scanning line driving circuit 20 changes the control signal Gcmp (i) from the L level to the H level, so that the diode connection of the transistor 121 is released.
Further, when the compensation period ends, the drive control circuit 5 changes the control signal Gref from the H level to the L level, so that the transistor 43 is turned off. Therefore, although the path from the data line 14 in the (3j-2) column to the gate node g in the pixel circuit 110 in the i row (3j-2) column is in a floating state, the potential of the path is It is maintained at (Vel− | Vth |) by the holding capacitors 50 and 132.

<Writing period>
In the scanning period of the i-th row, the writing period (d) follows. In the writing period, the drive control circuit 5 sets the control signal / Gini to the H level, the control signal Gref to the L level, and the control signal Gcpl to the H level, as shown in FIG. For this reason, as shown in FIG. 19, since the transmission gate 42 is turned on in the level shift circuit LS, the data signal held in the holding capacitor 41 is supplied to the node h 1 which is the other end of the holding capacitor 44. Thereby, the node h1 is shifted from the potential Vref in the compensation period. That is, the node h1 changes to the potential (Vref + ΔVh). Note that the potential (Vref + ΔVh) may be expressed as the potential Vh.
FIG. 20 is an explanatory diagram for explaining the potential change amount ΔVh of the node h1 before and after the start of the writing period. FIG. 20A shows the potential of the node h1 before the start of the writing period, and FIG. 20B shows the node h1 after the start of the writing period (that is, the period after the transmission gate 42 is turned on). It represents about the potential of.
As shown in FIGS. 18 and 19, in the compensation period and the writing period, the storage capacitor 50 and the storage capacitor 132 are electrically connected in parallel, and these and the storage capacitor 44 are electrically connected in series. . Therefore, the capacitance value C1 of the combined capacitance of the holding capacitor 44, the holding capacitor 50, and the holding capacitor 132 is expressed by the following equation (11) using the capacitance value C0 shown by the equation (1).
C1 = (C0 * Crf1) / (C0 + Crf1) (11)
Therefore, the charge accumulated in the combined capacitance of the storage capacitor 44, the storage capacitor 50, and the storage capacitor 132 before the writing period starts is defined as Q1c (FIG. 20A), and is stored in the combined capacitor after the writing period starts. Assuming that the charged charge is Q1d (FIG. 20B), the charge (Q1c−Q1d) flowing out from the combined capacitor in the writing period is expressed by the following equation (12).
Q1c-Q1d = C1 * (Vref-Vh) (12)
Similarly, let Q2c be the charge accumulated in the storage capacitor 41 before the start of the write period (FIG. 20A), and Q2d be the charge accumulated in the storage capacitor 41 after the start of the write period (FIG. 20). (B)) In the writing period, the charge (Q2d−Q2c) flowing into the storage capacitor 41 is expressed by the following equation (13).
Q2d-Q2c = Crf2 * (Vh-Vd (j)) (13)
In the writing period, since the charge flowing out from the combined capacitance of the storage capacitor 44, the storage capacitor 50, and the storage capacitor 132 is equal to the charge flowing into the storage capacitor 41, the following equation (14) is established.
Q1c-Q1d = Q2d-Q2c (14)
Therefore, the potential Vh of the node h1 in the writing period can be calculated from the equations (12) to (14). Specifically, the potential Vh is expressed by the following formula (15).
Vh = {C1 / (C1 + Crf2)} * (Vref)
+ {Crf2 / (C1 + Crf2)} * (Vd (j)) (15)
Therefore, the potential change amount ΔVh at the node h1 is expressed by the following equation (16).
ΔVh = Vh-Vref
= {Crf2 / (C1 + Crf2)} * {Vd (j) -Vref} (16)
Here, when the capacitance ratio k2 shown in the following equation (17) is introduced, the potential change amount ΔVh can also be expressed by the following equation (18).
k2 = Crf2 / (C1 + Crf2) (17)
ΔVh = k2 * {Vd (j) −Vref} (18)

In the writing period, as shown in FIG. 15, the scanning line driving circuit 20 sets the scanning signal Gwr (i) to the L level, the control signal Gel (i) to the H level, and the control signal Gcmp (i). Are set to H level, and the control signal Gorst (i) is set to L level.
At this time, since the gate node g is connected to one end of the storage capacitor 44 via the data line 14, the potential changes from the potential Vp = (Vel− | Vth |) in the compensation period. Note that the potential change of the gate node g in this case is as described in the above-described equations (1) to (10) and FIGS. 10 and 11.
That is, in the first embodiment described above, the potential of the node h1 changes from the potential Vref to the potential indicated by the data signal Vd (j) before and after the start of the writing period, whereas in the second embodiment, the potential Vref. To the potential Vh. Therefore, the potential Vgate of the gate node g in the writing period can be calculated by substituting Vh in Expression (15) for Vd (j) in Expression (7). Specifically, the potential Vgate is expressed by the following equation (19).
Vgate = k1 * ΔVh + (Vel− | Vth |)
= K1 * k2 * {Vd (j) -Vref} + (Vel- | Vth |) (19)
The potential change amount ΔVg of the gate node g before and after the start of the writing period can be calculated by substituting ΔVh in Expression (18) for ΔV in Expression (8). Specifically, the potential change amount ΔVg is represented by the following equation (20).
ΔVg = k1 * ΔVh
= K1 * k2 * {Vd (j) -Vref} (20)
As described above, the potential of the node h1 changes by a value obtained by shifting the potential indicated by the data signal Vd (j) by the potential Vref and compressing it by the capacitance ratio k2. As a result, the potential Vgate of the gate node g changes by a value obtained by further compressing the potential change amount ΔVh of the node h1 with the capacitance ratio k1.
That is, the potential Vgate of the gate node g shifts the data signal Vd (j) by the potential Vref as shown in the equation (19), and the capacitance values Cdt, Crf1, Crf2 with respect to the shifted potential. , A compressed potential is supplied by multiplying by a capacity ratio (capacity ratio k1, capacity ratio k2) determined based on Cpix.

<Light emission period>
In the second embodiment, the light emission period is started after the end of the writing period of the i-th row. In the light emission period, since the scanning line driving circuit 20 sets the control signal Gel (i) to the L level as described above, the transistor 124 is turned on in the pixel circuit 110 in the i row (3j-2) column. For this reason, as shown in FIG. 16, the current corresponding to the gradation level is supplied to the OLED 130 in a state where the threshold voltage of the transistor 121 is compensated.
Such an operation is also executed in parallel in time in other pixel circuits 110 in the i row other than the pixel circuit 110 in the (3j-2) th column in the scanning period of the i row. Further, such an operation on the i-th row is actually executed in the order of 1, 2, 3,..., (M−1), m-th row in the period of one frame, and is repeated for each frame. It is.

According to the second embodiment, as in the first embodiment, even if the minute current flowing through the OLED 130 changes relatively greatly with respect to the voltage Vgs between the gate and the source of the transistor 121 in the pixel circuit 110, It becomes possible to control the current supplied to the OLED 130 with high accuracy.
Further, according to the second embodiment, as in the first embodiment, the OLED 130 is made to have high luminance by setting the potential Vref to a high potential without setting the potential of the data signal Vd (j) to a high potential. The electro-optical device 1 can display a bright image.
According to the second embodiment, as in the first embodiment, the voltage held in the parasitic capacitance of the OLED 130 during the light emission period can be sufficiently initialized, and the threshold voltage of the transistor 121 is set for each pixel circuit 110. Even if there is a variation, the occurrence of display unevenness that impairs the uniformity of the display screen can be suppressed, and as a result, high-quality display can be achieved.

According to the second embodiment, the operation of holding the data signal supplied from the drive control circuit 5 via the demultiplexer DM in the holding capacitor 41 is executed from the initialization period to the compensation period. For this reason, time restrictions can be relaxed for the operation to be executed in one horizontal scanning period.
For example, since the current flowing through the transistor 121 decreases as the gate-source voltage Vgs approaches the threshold voltage in the compensation period, it takes time until the gate node g converges to the potential (Vel− | Vth |). In the second embodiment, it is possible to ensure a longer compensation period as shown in FIG. 15 compared to the first embodiment. For this reason, according to the second embodiment, it is possible to accurately compensate for variations in the threshold voltage of the transistor 121 as compared to the first embodiment. Also, the data signal supply operation can be slowed down.

<Application and modification>
The present invention is not limited to the above-described embodiments and application examples, and various modifications as described below are possible. Moreover, the aspect of the deformation | transformation described below can also combine suitably arbitrarily selected 1 or several.

<Modification>
The present invention is not limited to the above-described embodiments, and various modifications as described below are possible, for example. Moreover, the aspect of the deformation | transformation described below can also combine suitably arbitrarily selected 1 or several.

<Modification 1>
In the embodiment described above, the control unit 3 and the display panel 2 are separated from each other, but the control unit 3 is also integrated with the display unit 100, the data line driving circuit 10, and the scanning line driving circuit 20 on a silicon substrate. Also good.

<Modification 2>
In the embodiment and the modification described above, the electro-optical device 1 is integrated on the silicon substrate. However, the electro-optical device 1 may be integrated on another semiconductor substrate. For example, an SOI substrate may be used. Further, it may be formed on a glass substrate or the like by applying a polysilicon process. In any case, the pixel circuit 110 is miniaturized, and the transistor 121 is effective in a configuration in which the drain current greatly changes exponentially with respect to the change in the gate voltage Vgs.
Further, the present invention may be applied when the pixel circuit does not need to be miniaturized.

<Modification 3>
In the embodiment and the modification described above, the data lines 14 are grouped every three columns, and the data lines 14 are sequentially selected in each group to supply the data signal. The number of lines may be a predetermined number of “2” or more and “3n” or less. For example, the number of data lines constituting the group may be “2”, or may be “4” or more.
Further, a configuration may be employed in which data signals are supplied to the data lines 14 of each column all at once without grouping, that is, without using the demultiplexer DM.

<Modification 4>
In the embodiment and the modification described above, the transistors 121 to 125 in the pixel circuit 110 are unified with the P-channel type, but may be unified with the N-channel type. Further, the P channel type and the N channel type may be appropriately combined.
FIG. 24 is a circuit diagram of a pixel circuit 110 according to Modification 4. As shown in FIG. 24, the pixel circuit 110 according to the modification 4 unifies the transistors 121 to 125 by the N-channel type. As shown in FIG. 24, when the transistors 121 to 125 are unified in the N-channel type, the data signal Vd (j) in the above-described embodiment and the modified example is a potential obtained by reversing the positive / negative in each pixel circuit 110. What is necessary is just to supply.
In the above-described embodiments, the transistor 45 is a P-channel type and the transistor 43 is an N-channel type. However, the transistor 45 may be unified as a P-channel type or an N-channel type. The transistor 45 may be an N-channel type and the transistor 43 may be a P-channel type.

<Modification 5>
In the embodiment and the modification described above, each storage capacitor 50 is a single storage capacitor formed by sandwiching an insulator (dielectric) between the power supply line 16 and the data line 14 adjacent to each other. Each storage capacitor 50 may be formed of a plurality of capacitor elements. In this case, the drive control circuit 5 selects some or all of the plurality of capacitive elements based on the brightness information Br, and performs control for electrically connecting the selected capacitive elements to the feeder line 16 and the data line 14. It is preferable to carry out.
FIG. 21 is a circuit diagram illustrating a configuration of the storage capacitor 50 according to the fifth modification. The storage capacitor 50 according to the modification 5 includes a predetermined number Rcd of individual circuits Ud (first individual circuits) that are electrically connected in parallel between the data line 14 and the power supply line 16 adjacent to each other. Here, the predetermined number Rcd is a natural number of 2 or more.
Each individual circuit Ud includes a storage capacitor 501 (first individual capacitor), a transistor 502, and a transistor 503 that are electrically connected in series between the data line 14 and the power supply line 16. Specifically, each individual circuit Ud includes a storage capacitor 501, a transistor 502 electrically connected between one end of the storage capacitor 501 and the power supply line 16, and the other end of the storage capacitor 501 and the data line 14. A transistor 503 that is electrically connected is provided.
Here, the capacitance values of the predetermined number Rcd of the storage capacitors 501 may all be the same value, or may have different values. For example, when the predetermined number Rcd = “3”, the ratio of the capacitance values of the three storage capacitors 501 of the storage capacitor 50 may be “1: 1: 1” or “1: 2: 4”. It is good.
The display panel 2 according to the modified example 5 includes a predetermined number Rcd of control lines 504 and a predetermined number of Rcd control lines 505 so as to correspond to each of the predetermined number Rcd of individual circuits Ud on a one-to-one basis. Provided. The gate of the transistor 502 provided in the individual circuit Ud is electrically connected to the control line 504 corresponding to the individual circuit Ud, and the gate of the transistor 503 provided in the individual circuit Ud is connected to the individual circuit Ud. It is electrically connected to the corresponding control line 505.
Further, the drive control circuit 5 according to the modified example 5 generates the control signals Gcd (1), Gcd (2),..., Gcd (Rcd) based on the brightness information Br, and the control signal of these predetermined number Rcd. Each of Gcd is supplied to each of the predetermined number Rcd of control lines 504 and is supplied to each of the predetermined number of Rcd control lines 505. As a result, the drive control circuit 5 selectively electrically selects a part or all of the storage capacitors 501 from the predetermined number Rcd of the storage capacitors 501 based on the brightness information Br. Can be connected. In other words, the electro-optical device 1 according to the modification 5 can control the capacitance value Cdt of the storage capacitor 50 based on the brightness information Br.
For example, when the drive control circuit 5 sets the potential Vref to a high potential based on the brightness information Br, the brightness of the entire screen to be displayed on the display unit 100 becomes brighter, for example. When the brightness of the entire screen to be displayed on the display unit 100 becomes bright, even if crosstalk or unevenness due to potential fluctuation of the data line 14 occurs, this may be visually recognized by the user of the electro-optical device 1. Is low. Therefore, in this case, the display unit 100 can display a bright image by reducing the capacitance value Cdt and increasing the capacitance ratio k1 and the capacitance ratio k2 (that is, reducing the compression rate). In addition, a clear image with a large contrast ratio can be displayed.
In the example illustrated in FIG. 21, the transistor 502 and the transistor 503 function as a first individual switch that is electrically connected in series with the storage capacitor 501 between the data line 14 and the power supply line 16.
In the example shown in FIG. 21, each individual circuit Ud includes two transistors 502 and 503. However, the individual circuit Ud may include only one of them. In this case, one of the transistor 502 and the transistor 503 corresponds to the first individual switch.

<Modification 6>
In the embodiment and the modification described above, the storage capacitor 44 is formed from a single capacitor, but the storage capacitor 44 has a plurality of capacitors (similar to the storage capacitor 50 according to the modification 5). You may form with an element. In this case, the drive control circuit 5 performs control for selecting some or all of the plurality of capacitive elements based on the brightness information Br and electrically connecting the selected capacitive elements to the nodes h1 and h2. It is preferable.
FIG. 22 is a circuit diagram showing a configuration of the storage capacitor 44 according to the sixth modification. The storage capacitor 44 according to the modification 6 includes a predetermined number Rc1 of individual circuits U1 (third individual circuits) that are electrically connected in parallel between the node h1 and the node h2. Here, the predetermined number Rc1 is a natural number of 2 or more.
Each individual circuit U1 includes a holding capacitor 441 (third individual capacitor), a transistor 442, and a transistor 443 that are electrically connected in series between the node h1 and the node h2. Specifically, each individual circuit U1 includes a storage capacitor 441, a transistor 442 electrically connected between one end of the storage capacitor 441 and the node h2, and between the other end of the storage capacitor 441 and the node h1. A transistor 443 electrically connected to the transistor 443.
Here, the capacitance values of the predetermined number Rc1 of the storage capacitors 441 may all be the same value, or may have different values.
Further, the display panel 2 according to the modification 6 includes a predetermined number Rc1 of control lines 444 and a predetermined number of Rc1 control lines 445 so as to correspond to each of the predetermined number Rc1 of individual circuits U1. Provided. The gate of the transistor 442 is electrically connected to the corresponding control line 444, and the gate of the transistor 443 is electrically connected to the corresponding control line 445.
Further, the drive control circuit 5 according to the modification 6 generates control signals Gc1 (1), Gc1 (2),..., Gc1 (Rc1) based on the brightness information Br, and these predetermined number Rc1 of control signals. Each of Gc1 is supplied to each of a predetermined number Rc1 of control lines 444 and a predetermined number of Rc1 of control lines 445. As a result, the drive control circuit 5 selectively electrically connects a part or all of the storage capacitors 441 out of the predetermined number Rc1 of the storage capacitors 441 to the node h1 and the node h2 based on the brightness information Br. be able to. That is, the electro-optical device 1 according to the modification 6 can control the capacitance value Crf1 of the storage capacitor 44 based on the brightness information Br. As a result, the capacitance ratio k1 and the capacitance ratio k2 can be controlled, and the compression rate of the potential range ΔVgate of the gate node g, the brightness of the image to be displayed on the display unit 100, the contrast ratio, and the like can be controlled. It becomes possible.
Note that the transistor 442 and the transistor 443 function as a third individual switch connected in series with the storage capacitor 441. The individual circuit U1 may include only one of the two transistors 442 and 443. In this case, one of the transistor 442 and the transistor 443 corresponds to the third individual switch.

<Modification 7>
In the embodiment and the modification described above, the storage capacitor 41 is formed from a single capacitor, but the storage capacitor 41 includes a plurality of capacitors (similar to the storage capacitor 50 according to the modification 5). You may form with an element. In this case, the drive control circuit 5 performs control to select some or all of the plurality of capacitive elements based on the brightness information Br and to electrically connect the selected capacitive elements to the node h3 and the node h4. It is preferable.
FIG. 23 is a circuit diagram showing a configuration of the storage capacitor 41 according to Modification 7. As shown in FIG. The storage capacitor 41 according to Modification 7 includes a predetermined number Rc2 of individual circuits U2 (fourth individual circuit) electrically connected in parallel between the node h3 and the node h4. Here, the predetermined number Rc2 is a natural number of 2 or more.
Each individual circuit U2 includes a holding capacitor 411 (fourth individual capacitor) and a transistor 412 that are electrically connected in series between the node h3 and the node h4. Specifically, each individual circuit U2 includes a storage capacitor 411, and a transistor 412 electrically connected between one end of the storage capacitor 411 and the node h3 (or the node h4). Here, the capacitance values of the predetermined number Rc2 of storage capacitors 411 may all be the same value, or may have different values. In addition, the display panel 2 according to the modification 6 is provided with a predetermined number Rc2 of control lines 413 so as to correspond to each of the predetermined number Rc2 of individual circuits U2. The gate of the transistor 412 is electrically connected to the corresponding control line 413.
Further, the drive control circuit 5 according to the modified example 7 generates control signals Gc2 (1), Gc2 (2),..., Gc2 (Rc2) based on the brightness information Br, and these predetermined number Rc2 of control signals. Each of Gc2 is supplied to each of a predetermined number of control lines 413. Thereby, the drive control circuit 5 selectively electrically connects a part or all of the storage capacitors 411 from among the predetermined number Rc2 of the storage capacitors 411 to the nodes h3 and h4 based on the brightness information Br. be able to. That is, the electro-optical device 1 according to the modified example 7 can control the capacitance value Crf2 of the storage capacitor 41 based on the brightness information Br. As a result, the capacitance ratio k2 can be controlled, and the compression rate of the potential range ΔVgate of the gate node g, the brightness and contrast ratio of the image to be displayed on the display unit 100, and the like can be controlled.
Note that the transistor 412 functions as a fourth individual switch connected in series with the storage capacitor 411. The transistor 412 may be provided between the storage capacitor 411 and the node h4. Furthermore, the individual circuit U2 may include two transistors. In this case, the two transistors correspond to the fourth individual switch.

<Modification 8>
In the embodiment and the modification described above, the display control circuit 4 generates the image signal Vid based on the image data Video and the brightness information Br. However, the display control circuit 4 may generate the image signal Vid based only on the image data Video. . In this case, the storage unit 6 may include one lookup table LUT that stores the potential indicated by the image signal Vid and the luminance of the light emitting element in association with each other.

<Modification 9>
In the above-described embodiment and modification, an OLED that is a light-emitting element is illustrated as an electro-optical element.

<Application example>
Next, an electronic apparatus to which the electro-optical device 1 according to the embodiment and the application example is applied will be described. The electro-optical device 1 is suitable for high-definition display with small pixels. Therefore, a head mounted display will be described as an example of an electronic device.

FIG. 25 is a diagram showing the appearance of the head-mounted display, and FIG. 26 is a diagram showing its optical configuration.
First, as shown in FIG. 25, the head mounted display 300 has a temple 310, a bridge 320, and lenses 301L and 301R in the same manner as general glasses. Further, as shown in FIG. 26, the head mounted display 300 is in the vicinity of the bridge 320 and on the back side (lower side in the drawing) of the lenses 301L and 301R, the electro-optical device 1L for the left eye and the right eye. Electro-optical device 1R.
The image display surface of the electro-optical device 1L is arranged on the left side in FIG. Accordingly, the display image by the electro-optical device 1L is emitted in the direction of 9 o'clock in the drawing through the optical lens 302L. The half mirror 303L reflects the display image by the electro-optical device 1L in the 6 o'clock direction, and transmits light incident from the 12 o'clock direction.
The image display surface of the electro-optical device 1R is disposed on the right side opposite to the electro-optical device 1L. As a result, the display image by the electro-optical device 1R is emitted in the direction of 3 o'clock in the drawing through the optical lens 302R. The half mirror 303R reflects the display image by the electro-optical device 1R in the 6 o'clock direction, and transmits light incident from the 12 o'clock direction.

In this configuration, the wearer of the head mounted display 300 can observe the display image by the electro-optical devices 1L and 1R in a see-through state superimposed on the outside.
Further, in the head-mounted display 300, when the left-eye image is displayed on the electro-optical device 1L and the right-eye image is displayed on the electro-optical device 1R among the binocular images with parallax, the wearer is notified. The displayed image can be perceived as if it had a depth or a stereoscopic effect (3D display).

  In addition to the head mounted display 300, the electro-optical device 1 can be applied to an electronic viewfinder in a video camera, an interchangeable lens digital camera, or the like.

  DESCRIPTION OF SYMBOLS 1 ... Electro-optical device, 2 ... Display panel, 3 ... Control part, 4 ... Display control circuit, 5 ... Drive control circuit, 6 ... Memory | storage part, 10 ... Data line drive circuit, 12 ... Scan line, 14 ... Data line, DESCRIPTION OF SYMBOLS 16 ... Feed line, 20 ... Scanning line drive circuit, 43, 45 ... Transistor, 44, 50 ... Holding capacity, 100 ... Display part, 110 ... Pixel circuit, 121-125 ... Transistor, 130 ... OLED, 132 ... Holding capacity, LS ... level shift circuit, DM ... demultiplexer, 62 ... feed line, Br ... brightness information, Vd ... data signal.

Claims (12)

A display control circuit for generating brightness information based on the brightness designation information input to the input unit;
A drive control circuit that receives the brightness information and outputs a potential control signal;
A potential control line to which a potential control signal is supplied from the drive control circuit;
A display unit including a pixel circuit provided corresponding to the intersection of the scanning line and the data line;
A first holding capacitor for holding the potential of the data line;
A data signal supply circuit for generating a data signal;
A second storage capacitor having one end configured to supply the data signal and the other end connected to the data line;
An electro-optical device comprising: a first transistor electrically connected between one end of the second storage capacitor and the potential control line . When the first value is input to the input unit as the brightness designation information, the drive control circuit outputs a first potential as the potential control signal,
When a second value different from the first value is input to the input unit as the brightness designation information, the drive control circuit outputs a second potential different from the first potential as the potential control signal. The electro-optical device according to claim 1. 3. The electricity according to claim 1 , wherein the display control circuit generates an image signal based on the input image data and the brightness information and supplies the image signal to the data signal supply circuit. Optical device. The pixel circuit includes a light emitting element, a driving transistor that supplies a current to the light emitting element, a writing transistor electrically connected between a gate of the driving transistor and the data line, and a gate of the driving transistor. and characterized in that it has a third holding capacitor for holding the voltage between the source, the electro-optical device according to any one of claims 1 to 3. The display control circuit includes:
A storage unit storing the brightness of the light emitting element, the potential indicated by the image signal, and the brightness information in association with each other;
Generating the image signal defining the luminance of the light emitting element based on the brightness information;
The electro-optical device according to claim 4 . A scanning line driving circuit for controlling the operation of the pixel circuit;
A first feeder for feeding an initial potential;
A second transistor that is electrically connected between the other end and the first feed line of the second storage capacitor,
With
In the first period,
The drive control circuit maintains the second transistor in an on state;
In the second period starting after the first period ends,
The scanning line driving circuit maintains the writing transistor in an on state;
The drive control circuit maintains the first transistor in an on state and maintains the second transistor in an off state;
In a third period starting after the second period ends,
The scanning line driving circuit maintains the writing transistor in an on state;
The drive control circuit maintains the first transistor and the second transistor in an off state,
Wherein the one end of the second storage capacitor, the data signal is supplied,
The electro-optical device according to claim 4, wherein the electro-optical device is characterized. A fourth holding capacity;
The fourth holding capacity is
In at least part of the period from the start of the first period to the start of the third period, the data signal output from the display control circuit is supplied to one end,
In the third period, one end is electrically connected to the other end of the second storage capacitor.
The electro-optical device according to claim 6 . The pixel circuit includes:
A threshold compensation transistor electrically connected between the gate and drain of the driving transistor;
The scanning line driving circuit includes:
In the second period,
Maintaining the threshold compensation transistor on;
In a period other than the second period,
Maintaining the threshold compensation transistor in an off state;
The electro-optical device according to claim 6 , wherein the electro-optical device is provided. A third feed line for supplying a predetermined reset potential;
The pixel circuit includes:
An initialization transistor electrically connected between the third feeder and the light emitting element;
The scanning line driving circuit includes:
Maintaining the initialization transistor in an on state in at least a part of the first period, the second period, and the third period;
The electro-optical device according to claim 6 , wherein the electro-optical device is any one of the above. The third feeder line is provided along the data line;
The first storage capacitor is formed by the data line and the third feeder line.
The electro-optical device according to claim 9. The pixel circuit includes:
A light emission control transistor electrically connected between the drive transistor and the light emitting element;
The scanning line driving circuit includes:
Maintaining the emission control transistor in an off state at least in a period from the start of the first period to the end of the third period;
The electro-optical device according to claim 6 , wherein the electro-optical device is any one of claims 6 to 10 . An electronic apparatus comprising the electro-optical device according to any one of claims 1 to 1 1.

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