JP2016224465A - Electro-optical device and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent both ends of a storage capacitor 44 from being influenced by noise or the like.SOLUTION: A voltage supply line 16 of potential Vorst is provided between storage capacitors 44 adjacent to each other in a column in a planar view. When one end of the storage capacitor 44 is formed of second layer wiring and the other end of the storage capacitor 44 is formed of first layer wiring, the voltage supply line 16 has a laminated portion of first layer wiring 16g and second layer wiring 16a. The wiring 16g and the wiring 16a are connected to each other via one or more contact holes 16e.SELECTED DRAWING: Figure 6

Description

  Some embodiments of the present invention relate to a technique for preventing deterioration in display quality when an image is displayed by, for example, an electro-optical element.

In recent years, various electro-optical devices using light emitting elements such as organic light emitting diode (hereinafter referred to as “OLED”) elements have been proposed. In this electro-optical device, a configuration in which a pixel circuit is provided corresponding to the intersection of a scanning line and a data line is common. The pixel circuit includes the light emitting element and the driving transistor, and is provided corresponding to the pixel of the image to be displayed.
In such a configuration, when a data signal having a potential corresponding to the gradation level of the pixel is applied to the gate of the driving transistor, the driving transistor supplies a current corresponding to the voltage between the gate and the source to the light emitting element. . Accordingly, the light emitting element emits light with luminance according to the gradation level. At this time, if the characteristics such as the threshold voltage of the drive transistor vary for each pixel circuit, display unevenness that impairs the uniformity of the display screen occurs.
For this reason, a technique for compensating the characteristics of the drive transistor in the pixel circuit has been proposed (see, for example, Patent Document 1).

JP 2011-53635 A

By the way, as the miniaturization of the electro-optical device progresses, various wirings, terminals, electrodes, and the like approach each other, so that capacitive coupling becomes easy. For this reason, if the potential of one electrode fluctuates, it affects the potential of another electrode, resulting in a reduction in display quality.
SUMMARY An advantage of some aspects of the invention is that it provides an electro-optical device and an electronic apparatus that can prevent deterioration in display quality even when the electro-optical device is miniaturized. It is to provide.

In order to achieve the above object, an electro-optical device according to an aspect of the present invention includes a plurality of data lines and a first pixel circuit provided corresponding to the first data line among the plurality of data lines. And a second pixel circuit provided corresponding to the second data line among the plurality of data lines, and each of the first pixel circuit and the second pixel circuit includes a light emitting element, a gate, An electro-optical device including a driving transistor that supplies a current corresponding to a voltage between sources to the light-emitting element, one end of which is connected to the first data line and the other end of the first pixel circuit. A first storage capacitor that shifts in potential according to a current to be supplied to the light emitting element, one end connected to the second data line, and the other end according to a current to be supplied to the light emitting element in the second pixel circuit. Second holding capacitor for potential shift and plan view , Characterized by having a a constant potential line provided between the second storage capacitor and the first storage capacitor.
According to the aspect of the present invention, the constant potential line provided between the first storage capacitor and the second storage capacitor functions as a shield line. For this reason, the first data line through the first storage capacitor and the second data line through the second storage capacitor are not easily affected by potential fluctuations, so that the display quality can be prevented from deteriorating.

In the above aspect, one end of the first storage capacitor and one end of the second storage capacitor are formed by either the first conductive layer or the second conductive layer, and the other end of the first storage capacitor and the second The other end of the storage capacitor is formed by either the first conductive layer or the second conductive layer, and the constant potential line is formed by at least the wiring of the first conductive layer and the wiring of the second conductive layer. It is good also as a structure to be performed.
According to this configuration, the first storage capacitor and the second storage capacitor constitute the first storage capacitor and the second storage capacitor. The constant potential line is also constituted by the first conductive layer and the second conductive layer. The function as a shield wire is improved.

In this configuration, it is preferable that the wiring of the first conductive layer and the wiring of the second conductive layer in the constant potential line are electrically connected to each other. According to this configuration, the shielding function in the cross-sectional direction is also improved.
Note that the wiring of the first conductive layer and the wiring of the second conductive layer in the constant potential line may be electrically disconnected from each other. When not connected, the wiring of the first conductive layer and the wiring of the second conductive layer in the constant potential line may have the same or different potential.

In the above embodiment, a wiring to which a reset potential is supplied may be used as the constant potential line. That is, the light-emitting element is a two-terminal element, and the light-emitting element and the driving transistor are electrically connected in series between two different power supply potentials. The terminal on the driving transistor side may be set to a predetermined reset potential after a current is supplied by the driving transistor, and the reset potential may be supplied to the constant potential line.
In the above embodiment, a power supply line of a light emitting element may be used as the constant potential line. That is, the light emitting element and the driving transistor may be connected in series between two different power supply potentials, and one of the two power supply potentials may be supplied to the constant potential line.
The present invention can be conceptualized as an electronic apparatus having the electro-optical device in addition to the electro-optical device. Typically, the electronic apparatus includes a display device such as a head mounted display (HMD) or an electronic viewfinder.

1 is a perspective view illustrating a configuration of an electro-optical device according to an embodiment of the invention. 2 is a diagram illustrating an electrical configuration of the electro-optical device. FIG. It is a figure which shows the pixel circuit in the same electro-optical apparatus. It is a top view which shows the structure of the pixel circuit. It is a top view which shows the equivalent circuit in FIG. It is a top view which shows the principal part structure of the level shift circuit of the same electro-optical apparatus. It is a top view which shows the equivalent circuit in FIG. It is the fragmentary sectional view fractured | ruptured by the Pp line | wire in FIG. It is the fragmentary sectional view fractured | ruptured by the Qq line and RR line | wire in FIG. 6 is a timing chart showing the operation of the electro-optical device. FIG. 6 is an operation explanatory diagram of the same electro-optical device. FIG. 6 is an operation explanatory diagram of the same electro-optical device. FIG. 6 is an operation explanatory diagram of the same electro-optical device. FIG. 6 is an operation explanatory diagram of the same electro-optical device. It is a figure which shows the amplitude compression of the data signal in the same electro-optical apparatus. It is a figure which shows the characteristic of the transistor in the same electro-optical apparatus. It is a top view which shows the principal part structure of the level shift circuit which concerns on an application form. It is a perspective view which shows HMD using the electro-optical apparatus which concerns on embodiment etc. FIG. It is a figure which shows the optical structure of HMD.

  Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.

FIG. 1 is a perspective view showing a configuration of an electro-optical device 10 according to an embodiment of the present invention.
The electro-optical device 10 is a micro display that displays a color image in, for example, an HMD (Head Mount Display). Although details of the electro-optical device 10 will be described later, an organic EL device in which a plurality of pixel circuits, a drive circuit for driving the pixel circuits, and the like are formed on a semiconductor silicon substrate, for example, is an example of a light emitting element. OLEDs are used.

The electro-optical device 10 is housed in a frame-shaped case 72 that opens in a display area, and one end of an FPC (Flexible Printed Circuits) substrate 74 is connected. A plurality of terminals 76 are provided at the other end of the FPC board 74 and connected to a higher-level circuit (not shown). A semiconductor chip control circuit 5 is mounted on the FPC board by COF (Chip On Film) technology, and image (video) data is supplied from the host circuit through a plurality of terminals 76 in synchronization with a synchronization signal. Is done. The synchronization signal includes a vertical synchronization signal, a horizontal synchronization signal, and a dot clock signal. In addition, the image data defines the gradation level of the pixel of the image to be displayed, for example, 8 bits for each RGB.
The control circuit 5 combines the functions of the power supply circuit and the data signal output circuit of the electro-optical device 10. In other words, the control circuit 5 supplies various control signals and various potentials (voltages) generated according to the synchronization signal to the electro-optical device 10 and converts digital image data into an analog data signal, so that the electro-optical device 10 is supplied.

FIG. 2 is a diagram illustrating an electrical configuration of the electro-optical device 10 according to the embodiment. As shown in this figure, the electro-optical device 10 is roughly divided into a scanning line driving circuit 20, a demultiplexer 30, a level shift circuit 40, and a display unit 100.
Among these, in the display unit 100, pixel circuits 110 corresponding to pixels of an image to be displayed are arranged in a matrix. Specifically, in the display unit 100, m rows of scanning lines 12 are provided so as to extend in the horizontal direction in the drawing, and, for example, (3n) columns of data lines 14 grouped every three columns are shown in the drawing. It extends in the vertical direction and is provided so as to intersect with each scanning line 12 while maintaining electrical insulation. A pixel circuit 110 is provided at a position corresponding to the intersection of the m scanning lines 12 and the (3n) column data lines 14.

  Here, m and n are both natural numbers. In order to distinguish rows (rows) in the matrix of the scanning lines 12 and the pixel circuits 110, they may be referred to as 1, 2, 3,..., (M−1), m rows in order from the top in the drawing. Similarly, in order to distinguish the columns of the data line 14 and the matrix of the pixel circuit 110, they may be referred to as 1, 2, 3, ..., (3n-1), (3n) columns in order from the left in the figure. . Further, in order to generalize and describe the group of data lines 14, when an integer j of 1 to n is used, the j-th group counted from the left includes the (3j-2) th column, (3j-1). ) And (3j) th column data lines 14 belong.

The three pixel circuits 110 corresponding to the intersections of the scanning lines 12 in the same row and the three columns of data lines 14 belonging to the same group correspond to R, G, and B pixels, respectively. For this reason, in the present embodiment, the matrix arrangement of the pixel circuit 110 is m vertical rows × horizontal (3n) columns, and is m vertical rows × n horizontal columns in terms of the dot arrangement of the display image.
For convenience, for example, when the (3j-2) th column data line 14 corresponding to R is the first data line, the (3j-1) th column data line 14 corresponding to G is the second data line. Sometimes called. As for the pixel circuit 110, the one corresponding to the R data line 14 (first data line) is the first pixel circuit, and the one corresponding to the G data line 14 (second data line) is the second pixel circuit. .

The following control signals are supplied from the control circuit 5 to the electro-optical device 10. Specifically, the electro-optical device 10 includes a control signal Ctr for controlling the scanning line driving circuit 20 and control signals Sel (1), Sel (2), Sel for controlling selection in the demultiplexer 30. (3), control signals / Sel (1), / Sel (2), / Sel (3) having a logical inversion relationship with these signals, and a control signal / for controlling the level shift circuit 40 Gini, Gref, and Gcpl and a control signal / Gcpl that is in a logic inversion relationship with the control signal Gcpl are supplied. Note that the control signal Ctr actually includes a plurality of signals such as a pulse signal, a clock signal, and an enable signal.
In addition, the electro-optical device 10 receives data signals Vd (1), Vd (2),..., Vd (n) from the control circuits 5, 1, 2,. It is supplied via a common terminal 78 corresponding to the second group.

  Here, in this embodiment, when the gradation level that defines the gradation of the pixel to be displayed is specified in the range from the darkest 0 level to the brightest 255 level, for example, the data signals Vd (1) to Vd. (n) can be stepwise in the range from the potential Vmax corresponding to the 0 level to the potential Vmin corresponding to the 255 level. Here, since the transistor for controlling the current to the OLED is a P-channel type, the data signal decreases from the potential Vmax as the bright gradation level is designated.

  Each data line 14 is provided with a storage capacitor 50. One end of the storage capacitor 50 is connected to the data line 14, and the other end of the storage capacitor 50 is commonly connected to a power supply line 16 having a constant potential, for example, the potential Vorst. As the storage capacitor 50, a capacitance parasitic on the data line 14 may be used, or the storage capacitor 50 is formed by sandwiching an insulator (dielectric) between the parasitic capacitance, a wiring configuring the data line 14, and a separate wiring. A combined capacitor with the above-described capacitor element may be used. Here, the capacity of the storage capacitor 50 is Cdt.

The scanning line driving circuit 20 generates a scanning signal for sequentially scanning the scanning lines 12 for each row over a frame period in accordance with the control signal Ctr. Here, the scanning signals supplied to the scanning lines 12 of 1, 2, 3,..., (M−1) and the m-th row are Gwr (1), Gwr (2), Gwr (3),. It is written as Gwr (m-1) and Gwr (m).
In addition to the scanning signals Gwr (1) to Gwr (m), the scanning line driving circuit 20 generates various control signals synchronized with the scanning signals for each row and supplies them to the display unit 100. Illustration is omitted in FIG. The frame period is a period required for the electro-optical device 10 to display an image for one cut (frame). For example, if the frequency of the vertical synchronization signal included in the synchronization signal is 120 Hz, the first period is 1. This is a period of 8.3 milliseconds corresponding to the period.

The demultiplexer 30 is an assembly of transmission gates 34 provided for each column. The input terminals of the transmission gates 34 corresponding to the (3j-2), (3j-1), and (3j) columns belonging to the jth group are connected to the common terminal 78 and the data signal Vd (j). Are supplied in time division.
When the control signal Sel (1) is at the H level (the control signal / Sel (1) is at the L level), the transmission gate 34 provided in the (3j-2) column which is the leftmost column in the jth group Is turned on (conductive). Similarly, in the transmission gate 34 provided in the (3j−1) column which is the central column in the j-th group, the control signal Sel (2) is at the H level (the control signal / Sel (2) is at the L level. The transmission gate 34 provided in the (3j) column, which is the rightmost column in the jth group, is turned on when the control signal Sel (3) is at the H level (the control signal / Sel (3) is (When at L level).

  The level shift circuit 40 shifts the potential of the data signal in a direction to compress the potential amplitude of the data signal output from the output terminal of the transmission gate 34 of each column. For this reason, the level shift circuit 40 has a set of a storage capacitor 41, a transmission gate 42, an N-channel transistor 43, a storage capacitor 44, and a P-channel transistor 45 for each column.

In each column, the output terminal of the transmission gate 34 of the demultiplexer 30 is connected to one end of the holding capacitor 41 and the input terminal of the transmission gate 42 in the level shift circuit 40 in the level shift circuit 40. The other end of the storage capacitor 41 is commonly grounded to Gnd, which is a fixed potential in each column.
As for the voltage, unless otherwise specified, such as the voltage across the storage capacitor, the voltage between the gate and the source, and the voltage between the anode and the cathode in the OLED 150, the potential Gnd is used as a reference of zero volts.

The transmission gates 42 in each column are turned on when the control signal Gcpl is at the H level (when the control signal / Gcpl is at the L level). The output terminal of the transmission gate 42 is connected to the data line 14 via the storage capacitor 44.
Here, with regard to one end and the other end of the storage capacitor 44, one end is for the data line 14 side and the other end is for the transmission gate 42 side for convenience. At this time, one end of the storage capacitor 44 is connected to the drain node of the transistor 45 in addition to the data line 14, while the other end of the storage capacitor 44 is also connected to the drain node of the transistor 43.
For convenience of explanation, although notation is omitted in FIG. 2, the capacity of the storage capacitor 44 is Cref1, and the other end of the storage capacitor 44 is a node h. Further, when the storage capacitors 44 are distinguished by columns, the one corresponding to the R column is the first storage capacitor, and the one corresponding to the G column is the second storage capacitor.
As shown in FIG. 2, the feeder line 16 extends so as to pass through the inside of the level shift circuit 40.

  As for the transistor 43, the source node is commonly connected across the columns to the power supply line 62 that feeds the potential Vref as a predetermined reference potential, and the gate node is common across the columns to the control line 64 to which the control signal Gref is supplied. Connected to. For this reason, the node h is electrically connected to the power supply line 62 by turning on the transistor 45 when the control signal Gref is at the H level, while turning off the transistor 45 when the control signal Gref is at the L level. Electrically disconnected.

  As for the transistor 45, the source node is commonly connected across the columns to the power supply line 61 that feeds the potential Vini as the initial potential, and the gate node extends across the columns to the control line 63 to which the control signal / Gini is supplied. Connected in common. Therefore, the data line 14 is electrically connected to the power supply line 61 by turning on the transistor 45 when the control signal / Gini is at L level, while the transistor 45 is turned on when the control signal / Gini is at H level. It is electrically disconnected by turning off.

  In the present embodiment, the scanning line driving circuit 20, the demultiplexer 30 and the level shift circuit 40 are divided for convenience, but these can be collectively considered as a driving circuit for driving the pixel circuit 110. .

The pixel circuit 110 will be described with reference to FIG. Since each pixel circuit 110 has the same configuration when viewed electrically, here, the i-th row (3j−) located in the (3j-2) th column of the leftmost column in the j-th group is the i-th row. 2) The pixel circuit 110 in the column will be described as an example.
Note that FIG. 3 only shows an equivalent circuit of the pixel circuit 110 and does not reflect an actual circuit layout. Further, i is a symbol for generally indicating a row in which the pixel circuits 110 are arranged, and is an integer of 1 to m.

As shown in FIG. 3, the pixel circuit 110 includes P-channel transistors 121 to 125, a storage capacitor 140, and an OLED 150. The pixel circuit 110 is supplied with a scanning signal Gwr (i), control signals Gel (i), Gcmp (i), and Gorst (i). Here, the scanning signal Gwr (i), the control signals Gel (i), Gcmp (i), and Gorst (i) are respectively supplied by the scanning line driving circuit 20 corresponding to the i-th row. Among these, the control signal Gel (i) is supplied via the control line 134, and similarly, the control signals Gcmp (i) and Gorst (i) are supplied via the control lines 133 and 135, respectively.
Note that the scanning signal Gwr (i), the control signals Gel (i), Gcmp (i), and Gorst (i) are supplied corresponding to the i-th row. (3j-2) It is also supplied in common to the pixel circuits in other columns than the column.

Now, in the transistor 122 in the pixel circuit 110 in the i-th row (3j-2) column, the gate node is connected to the scanning line 12 in the i-th row, and either the drain or the source node is in the (3j-2) -th column. And the other is connected to the gate node of the transistor 121, one end of the storage capacitor 140, and the drain node of the transistor 123. Here, the gate node of the transistor 121 is denoted by g to distinguish it from other nodes.
In the transistor 121, the source node is connected to the power supply line 116, and the drain node is connected to the source node of the transistor 123 and the source node of the transistor 124. Here, the power supply line 116 is supplied with a potential Vel that is higher in the power supply in the pixel circuit 110.
In the transistor 123, the gate node is connected to the control line 133 of the i-th row and the control signal Gcmp (i) is supplied.
In the transistor 124, the gate node is connected to the i-th control line 134 and the control signal Gel (i) is supplied, and the drain node is connected to the source node of the transistor 125 and the anode Ad of the OLED 150. Yes.
In the transistor 125, the gate node is connected to the control line 135 of the i-th row, the control signal Gorst (i) corresponding to the i-th row is supplied, and the drain node corresponds to the (3j-2) -th column. It is connected to the feeder line 16 and is kept at the potential Vorst.

  Note that in the transistors 121 to 125, the potential relationship may be changed by changing the channel type or the like. When the potential relationship changes, the node described as the drain node may be the source node, and the node described as the source node may be the drain node. For example, one of the source node and the drain node of the transistor 121 may be electrically connected to the power supply line 116, and the other may be electrically connected to the anode Ad of the OLED 150 through the transistor 123.

The other end of the storage capacitor 140 is connected to the power supply line 116. For this reason, the storage capacitor 140 holds the voltage between the source and the drain of the transistor 121. Here, when the capacity of the storage capacitor 140 is expressed as Cpix, the capacity Cdt of the storage capacitor 50, the capacity Cref1 of the storage capacitor 44, and the capacity Cpix of the storage capacitor 140 are:
Cdt, Cref1 >> Cpix
Is set to be
That is, Cpix is sufficiently smaller than Cdt and Cref1. Cref2 is about the same as Cref1 or slightly smaller than Cref1. As the storage capacitor 140, a capacitor parasitic to the gate node g of the transistor 121 may be used, or a capacitor formed by sandwiching an insulating layer between different conductive layers in a semiconductor silicon substrate may be used. .

The anode Ad of the OLED 150 is a pixel electrode provided individually for each pixel circuit 110. On the other hand, the cathode Ct of the OLED 150 is a common electrode 118 that is common to all the pixel circuits 110 and is kept at the potential Vct that is the lower side of the power supply in the pixel circuit 110.
Therefore, the source / drain of the transistor 121 and the OLED 150 are electrically connected in series via the transistor 124 between the higher potential Vel and the lower potential Vct of the power supply.

The OLED 150 is a two-terminal element in which a white organic EL layer is sandwiched between an anode Ad and a light-transmitting cathode Ct on the semiconductor silicon substrate. A color filter corresponding to any of RGB is superimposed on the emission side (cathode side) of the OLED 150.
In the OLED 150 having such a structure, when a current flows from the anode Ad to the cathode Ct, holes injected from the anode Ad and electrons injected from the cathode Ct are recombined in the organic EL layer to generate excitons. White light is generated. The white light generated at this time is transmitted through the cathode opposite to the semiconductor silicon substrate (anode), and is colored by a color filter so as to be visually recognized by the viewer (top emission structure).

  In this embodiment, since the electro-optical device 10 is formed on a semiconductor silicon substrate, the substrate potentials of the transistors 121 to 125 are omitted in FIG.

In such a configuration, when the potential at one end and the potential at the other end of the storage capacitor 44 electrically inserted in the data signal supply path deviate from the target values, the display quality deteriorates. . As described above, when the electro-optical device 10 is miniaturized, a change in the potential of adjacent columns is propagated by capacitive coupling, so that display quality is likely to deteriorate.
For this reason, in the present embodiment, one end and the other end of the storage capacitor 44 are shielded by a constant potential line so that they are not easily affected by potential fluctuations in adjacent columns.

In the description of this configuration, the manufacturing process of the electro-optical device 10 is necessary as prior knowledge. First, a manufacturing process of the electro-optical device 10 will be briefly described.
In the electro-optical device, first, for example, after an island-shaped N-well region serving as a base of a P-channel type transistor is formed on a P-type semiconductor silicon substrate, a first film such as a polycrystalline silicon film is interposed through a gate insulating film. The conductive layer is patterned to form a first wiring such as a gate. After that, the region where the P-channel transistor is formed is protected by a resist, and then the source node and the drain node in the N-channel transistor are formed by ion implantation using the resist or the gate wiring as a mask. An N-type diffusion layer is formed. Subsequently, after protecting a region where an N-channel transistor is to be formed with a resist, ion implantation using the resist or gate wiring as a mask becomes a source node or a drain node in the P-channel transistor. A P-type diffusion layer is formed.
Subsequently, a conductive layer (second conductive layer) such as aluminum or copper is patterned through the first interlayer insulating film, and various wirings to be described later are provided as the second wiring. At this time, the second wiring is connected to the first wiring, the source node, and the drain node through a contact hole that opens the first interlayer insulating film.
Subsequently, a conductive layer (third conductive layer) such as aluminum or copper is similarly patterned through the second interlayer insulating film, and various wirings are provided as third wirings. At this time, the third wiring is connected to the second wiring through a contact hole that opens the second interlayer insulating film.
A rectangular pixel electrode is formed as the anode Ad of the OLED 150 via the third interlayer insulating film and the light shielding layer. Since the following is not directly related to the present invention, the description thereof will be omitted.

How the pixel circuit 110 in the display unit 100 and the level shift circuit 40 in the peripheral circuit are configured by such a manufacturing process will be individually described.
In FIGS. 4 to 9 below, the scale is appropriately changed to explain the structure, and therefore the aspect ratio is not necessarily the same as the scale.

<Pixel circuit>
FIG. 4 is a plan view of the pixel circuit 110 having a top emission structure as viewed from the observation side, and shows various wirings including a first wiring, a second wiring, and a third wiring. FIG. 5 is an explanatory diagram showing the structure in FIG. 4 replaced with a circuit, which is the same as FIG.

As shown in FIG. 4, in the pixel circuit 110, first, transistors 121 to 125 are provided, and gate wirings 121g to 125g are formed as first wirings by patterning the first conductive layer.
The transistor 121 has a rectangular shape that is long in the column direction (extending direction of the data line 14) in plan view, and includes a gate wiring 121g formed through an insulating film with respect to the N well, and two P-types. A diffusion layer (a region indicated by hatching in the figure). Of the two diffusion layers in the transistor 121, the lower side in the figure is the source node and the upper side is the drain node.

  The transistors 122 and 123 are arranged on the right side of the transistor 121 in the drawing and have a rectangular shape that is long in the column direction in plan view. In the transistors 122 and 123, gate wirings 122g and 123g separated from each other are formed, and three P-type diffusion layers are formed. Of these three diffusion layers, the lower side in the figure is one of the drain or source node in the transistor 122, and the center is the common node between the other drain or source node in the transistor 122 and the drain node in the transistor 123, The upper side is a source node in the transistor 123.

As shown in FIG. 4, the transistor 124 has a rectangular shape that is long in the column direction in plan view, and is disposed at a point that is aligned with the transistors 122 and 123 in the column direction. A gate wiring 124g is formed in the transistor 124, and two P-type diffusion layers are formed. Of the two diffusion layers, the lower side in the figure is a source node in the transistor 124 and the upper side is a drain node.
The transistor 125 is arranged on the left side of the transistor 124 in the drawing and at a point aligned with the transistor 121 in the column direction. In the transistor 125, a gate wiring 125g is formed, and two P-type diffusion layers are formed. Of the two diffusion layers, the lower side in the figure is a drain node in the transistor 125, and the upper side is a source node.

After the first interlayer insulating film is provided for the transistors 121 to 125 thus provided, the second conductive layer is patterned to provide the second wiring described below. That is, the scanning line 12, the wirings 81 to 86, the feeder line 116, the wiring 116b, and the control lines 133 to 135 are provided as the second wiring. Among these, the scanning line 12, the feeding line 116, and the control lines 133 to 135 are provided so as to extend in the row direction, respectively.
The scanning line 12 passes through the upper surface side (the front side in the drawing) of the gate wiring 122g. The scanning line 12 is connected to the gate wiring 122g through a contact hole (via, □ in the figure) 12f that opens the first interlayer insulating film. The control line 133 passes through the upper surface side of the gate wiring 123g and is connected to the gate wiring 123g through the contact hole 133f.
The power supply line 116 is provided to extend in the row direction at the boundary between the transistors 121 to 123 and the transistors 124 and 125 in plan view. Both of the control lines 134 and 135 pass through the upper surfaces of the gate wirings 124g and 125g. Among these, the control line 134 is connected to the gate wiring 124g through the contact hole 134f, and the control line 135 passes through the contact hole 135f. To the gate wiring 125g.

One end of the wiring 81 is connected to the data line 14 and one of the drain and source nodes of the transistor 122.
The wiring 82 has one end connected to the common node in the transistors 122 and 123, and the other end connected to the gate wiring 121g in the transistor 121 via the contact hole 82f. The wiring 82 is wide on the upper surface side of the gate wiring 121 g and constitutes one of the pair of electrodes in the storage capacitor 140.

The wiring 83 has one end connected to the drain node in the transistor 121 and the other end connected to the source node in the transistor 123.
The wiring 84 is a relay electrode for connecting the source node in the transistor 124 to the wiring 91 of the second wiring layer described later. One end of the wiring 85 is connected to the drain node of the transistor 125. The wiring 86 is connected to the drain node in the transistor 124, the source node in the transistor 125, and the anode Ad in the OLED 150 (not shown in FIGS. 4 and 5).
The wiring 116b is a relay wiring for connecting the source node in the transistor 121 to the power supply line 116 via the wiring 116a of the second wiring layer described later.

After such a second wiring is provided with a second interlayer insulating film, the third conductive layer is patterned, so that the data line 14, the feed line 16, and the wirings 91 and 116a shown in the figure are connected to the third wiring. As provided.
The data line 14 and the power supply line 16 are provided so as to extend in the column direction. The data line 14 is arranged on the right side of the transistors 122 to 124 in plan view, and is connected to the other end of the wiring 81 through a contact hole 14f that opens the second interlayer insulating film. As a result, the data line 14 is connected to one of the drain and source nodes of the transistor 122 via the wiring 81.
The power supply line 16 is disposed between the transistors 122, 123, and 124 and the transistors 121 and 125 in plan view, and is connected to the other end of the wiring 85 through the contact hole 16f. As a result, the feeder line 16 is connected to the drain node of the transistor 125 via the wiring 85.

On the other hand, the wiring 116a is provided on the left side of the transistor 121 in plan view, and is connected to the power supply line 116 through the contact hole 116e while straddling the control line 133 and the scanning line 12, and is connected to the wiring 116b. 116f is connected. Thus, the power supply line 116 is connected to the source node in the transistor 121 through the wirings 116a and 116b.
In addition, the wiring 116 a is formed so as to overlap with the wiring 82 in plan view, and constitutes the other of the pair of electrodes in the storage capacitor 140. Thus, the storage capacitor 140 has a configuration in which the second interlayer insulating film is sandwiched between the wiring 82 and the wiring 116a.
The wiring 91 connects the wirings 83 and 84 in a state of straddling the power supply line 116. Accordingly, the drain node of the transistor 121, the drain node of the transistor 123, and the source node of the transistor 124 are connected to each other.

  In this manner, in the pixel circuit 110, the transistors 121 to 123 and the transistors 124 and 125 are separated by the power supply line 116 having the potential Vel. In addition, the gate node g of the transistor 121 has a configuration in which the left side in the drawing is shielded by the wiring 116 a and the right side is shielded by the feeder line 16.

<Level shift circuit>
FIG. 6 is a plan view of a region in which the transistors 43 and 45 and the storage capacitor 44 are formed in the level shift circuit 40 as viewed from the observation side, and shows various types of the first wiring, the second wiring, and the third wiring. Wiring is shown.
Note that various wirings in FIG. 6 are formed by a common process with the pixel circuit 110, respectively. FIG. 7 is an explanatory diagram showing the structure in FIG. 6 replaced with a circuit.
8 is a partial cross-sectional view taken along the line P-p in FIG. 6, FIG. 9A is a partial cross-sectional view taken along the line Q-q in FIG. 6, and FIG. These are the fragmentary sectional views fractured | ruptured by the RR line | wire in FIG. In the following, the plan view of FIG. 6 will be mainly described, and the partial cross-sectional views of FIGS.

  6, the storage capacitor 44 is provided at one end of the data line 14, and the power supply line 16 is extended on the left side and the right side, respectively.

  In the figure, a transistor 43 is provided on the lower side (demultiplexer 30 side), and a transistor 45 is provided on the upper side (display unit 100 side). Similar to the transistors 121 to 125 in the pixel circuit 110, the transistors 43 and 45 have a rectangular shape that is long in the column direction in plan view. In addition, gate wirings 43g and 45g, wirings 16g, 61g, and 62g and an electrode 44g are formed as the first wiring by patterning the first conductive layer.

As shown in FIG. 9B, the transistor 43 includes a gate wiring 43g formed on the P-type semiconductor silicon substrate S (P well) through the insulating film L0, and two N-type diffusion layers. And have. Of the two diffusion layers in the transistor 43, the right side (lower side in FIG. 6) in FIG. 9B is the drain node, and the left side (same as above) is the source node.
The transistor 45 has a gate wiring 45g formed with respect to the N well via the insulating film L0, and two P-type diffusion layers. Of the two diffusion layers in the transistor 45, the right side is the source node and the left side is the drain node.

On the other hand, the wiring 16g is provided between the power supply lines 61 and 62 in the row direction in a region where the power supply line 16 is formed in the column direction. The wiring 62g is provided in a region where the power supply line 62 in the row direction is formed, and is provided between the source nodes of the transistors 43 in each column. The wiring 61g is provided in the region where the power supply line 61 in the row direction is formed, and is provided between the source nodes of the transistors 45 in each column.
The electrode 44g is the other end of the storage capacitor 44, and has a rectangular shape that is long in the column direction as shown in the figure.

After the first interlayer insulating film L1 is provided for the transistors 43 and 45, the power supply lines 61 and 62, the control lines 63 and 64, and the wirings 43a, 45a, and 49a are formed as the second wiring by patterning the second conductive layer. 16a and the electrode 44a are formed. Among these, the feeder lines 61 and 62 and the control lines 63 and 64 are provided extending in the row direction, respectively.
The power supply line 62 is provided on the upper surface side of the wiring 62g, and is connected to the source node of the transistor 43 through a contact hole 43e that opens the first interlayer insulating film L1. The power supply line 62 is connected to the wiring 62g through the contact hole 62e. For this reason, the feeder line 62 has a two-layer structure partially with the wiring 62g as a lower layer. The control line 64 is provided so as to pass through the upper surface side of the gate wiring 43g, and is connected to the gate wiring 43g through a contact hole 43f that opens the first interlayer insulating film. One end of the wiring 43a is connected to the drain node of the transistor 43 through a contact hole.

  On the other hand, the power supply line 61 is provided on the upper surface side of the wiring 61g and connected to the source node of the transistor 45 through the contact hole 445e. The power supply line 61 is connected to the wiring 61g via the contact hole 61e. For this reason, the feeder line 61 has a two-layer structure partially with the wiring 61g as a lower layer. The control line 63 is provided so as to pass through the upper surface side of the gate wiring 45g and is connected to the gate wiring 45g through the contact hole 45f. One end of the wiring 45a is connected to the source node of the transistor 45 through a contact hole.

The wiring 49a relays the electrode 44g, which is the other end of the storage capacitor 44, to the wiring 48 described later, and is connected to the electrode 44a through a contact hole 49e.
The wiring 16a is provided on the upper surface side of the wiring 16g and is connected to the wiring 16g through a plurality of contact holes 16e.
The electrode 44 a overlaps the electrode 44 g and becomes one end of the storage capacitor 44. Since the first interlayer insulating film L1 is sandwiched between the electrode 44g and the electrode 44a as shown in FIG. 9A, the storage capacitor 44 is thereby formed.

After the second interlayer insulating film L2 is provided for the second wiring, the data line 14, the feeder line 16, and the wiring 48 are provided as the third wiring by patterning the third conductive layer.
The data line 14 is connected to the electrode 44a through a plurality of contact holes 44f that open the second interlayer insulating film L2. The data line 14 is connected to the other end of the wiring 45 a through the contact hole 55. Thereby, the data line 14 is connected to the drain node of the transistor 45 through the contact hole 55 and the wiring 45a in this order.

  The power supply line 16 is connected to the wiring 16a through a plurality of contact holes 16f. As a result, the feeder line 16 has a three-layer structure partially by the wirings 16g and 16a. Accordingly, the three-layered feeder line 16 is arranged as a shield wiring on both the left and right sides of the storage capacitor 44.

  The wiring 48 is routed from the output end of the transmission gate 42 (see FIG. 2), and is connected to the wiring 49a through the contact hole 49f. For this reason, the wiring 48 is connected to the electrode 44g which is the other end of the storage capacitor 44 by the relay of the wiring 49a. Further, the wiring 48 is connected to the other end of the wiring 43 a through the contact hole 53. As a result, the wiring 48 is connected to the drain node of the transistor 43 through the contact hole 43 and the wiring 43a in this order.

  In this way, in the level shift circuit 40, the power supply line 16 is provided on the left and right sides, the power supply line 61 is provided on the upper side, and the power supply line 62 is provided on the lower side, as viewed in FIG. For this reason, the four sides of the storage capacitor 44 are shielded by the constant potential lines.

<Operation of First Embodiment>
The operation of the electro-optical device 10 will be described with reference to FIG. FIG. 10 is a timing chart for explaining the operation of each part in the electro-optical device 10.
As shown in this figure, the scanning signals Gwr (1) to Gwr (m) are sequentially switched to the L level, and the scanning lines 12 in the 1st to m-th rows in one frame period are in one horizontal scanning period (H). Scanned sequentially.
The operation in one horizontal scanning period (H) is common to the pixel circuits 110 in each row. Therefore, in the following, the operation will be described focusing on the pixel circuit 110 in the i-th row (3j-2) column in the scanning period in which the i-th row is horizontally scanned.

The i-th scanning period is roughly divided into an initialization period shown in FIG. 10B, a compensation period shown in FIG. 10C, and a writing period shown in FIG. Then, after the writing period of (d), the light emission period shown in (a) is reached, and the scanning period of the i-th row is reached again after the elapse of one frame period. Therefore, in the order of time, a cycle of (light emission period) → initialization period → compensation period → writing period → (light emission period) is repeated.
In FIG. 10, the scanning signal Gwr (i-1), control signals Gel (i-1), Gcmp (i-1), Gcmp (i-1), corresponding to the (i-1) th row before the ith row. For each of the Gorst (i-1), one horizontal scan is temporally performed in comparison with the scanning signal Gwr (i) and the control signals Gel (i), Gcmp (i), and Gorst (i) corresponding to the i-th row. The waveform is preceded in time by the period (H).

<Light emission period>
For convenience of explanation, the light emission period which is the premise of the initialization period will be described. As shown in FIG. 10, in the light emission period of the i-th row, the scanning signal Gwr (i) is at the H level, and the control signals Gel (i), Gcmp (i), and Gorst (i) that are logic signals. Among them, the control signal Gel (i) is at the L level, and the control signals Gcmp (i) and Gorst (i) are at the H level.
For this reason, as shown in FIG. 11, in the pixel circuit 110 in the i row (3j-2) column, the transistor 124 is turned on, while the transistors 122, 123, and 125 are turned off. Therefore, the transistor 121 functions as a driving transistor that supplies the current Ids corresponding to the gate-source voltage Vgs to the OLED 150. As will be described later, in this embodiment, the voltage Vgs in the light emission period is a value that is level-shifted from the threshold voltage of the transistor 121 according to the potential of the data signal. Therefore, a current corresponding to the gradation level is supplied to the OLED 150 in a state where the threshold voltage of the transistor 121 is compensated.

  Note that since the light emission period of the i-th row is a period during which horizontal scanning is performed except for the i-th row, the potential of the data line 14 varies appropriately. However, in the pixel circuit 110 in the i-th row, since the transistor 122 is off, the potential fluctuation of the data line 14 is not considered here. Further, in FIG. 11, paths that are important in the explanation of the operation are indicated by bold lines (the same applies to FIGS. 12 to 14 below).

<Initialization period>
Next, when the scanning period of the i-th row is reached, the initialization period of (b) is reached. In the initialization period, the control signal Gel (i) changes to the H level and the control signal Gorst (i) changes to the L level as compared with the light emission period.
Therefore, as shown in FIG. 12, in the pixel circuit 110 in the i row (3j-2) column, the transistor 124 is turned off and the transistor 125 is turned on. As a result, the path of the current supplied to the OLED 150 is cut off, and the anode Ad of the OLED 150 is reset to the potential Vorst.
Since the OLED 150 has a configuration in which the organic EL layer is sandwiched between the anode Ad and the cathode Ct as described above, the capacitance Coled is parasitic between the anode Ad and the cathode Ct in parallel as shown by a broken line in the drawing. . When a current flows through the OLED 150 during the light emission period, the voltage between the anode and the cathode of the OLED 150 is held by the capacitor Coled. This holding voltage is reset by turning on the transistor 125. For this reason, in this embodiment, when a current flows again through the OLED 150 in a later light emission period, it is less likely to be affected by the voltage held by the capacitor Coled.

Specifically, for example, when switching from a high-brightness display state to a low-brightness display state, if the configuration does not reset, the high voltage when the luminance is high (a large current flows) is retained. In addition, even if a small current is applied, an excessive current flows and the display state with low luminance cannot be achieved. On the other hand, in this embodiment, the potential of the anode Ad of the OLED 150 is reset by turning on the transistor 125, so that the reproducibility on the low luminance side is improved.
In the present embodiment, the potential Vorst is set such that the difference between the potential Vorst and the potential Vct of the common electrode 118 is lower than the light emission threshold voltage of the OLED 150. Therefore, in the initialization period (compensation period and writing period described below), the OLED 150 is in an off (non-light emitting) state.

On the other hand, in the initialization period, the control signal / Gini becomes L level, the control signal Gref becomes H level, and the control signal Gcpl becomes L level. For this reason, in the level shift circuit 40, as shown in FIG. 12, the transistors 45 and 43 are turned on, and the transmission gate 42 is turned off. Therefore, the data line 14 that is one end of the storage capacitor 44 is initialized to the potential Vini, and the node h that is the other end of the storage capacitor 44 is initialized to the potential Vref.
Here, the potential Vini is set so that (Vel−Vini) is larger than the threshold voltage | Vth | of the transistor 121. Note that since the transistor 121 is a P-channel type, the threshold voltage Vth with respect to the potential of the source node is negative. Therefore, in order to avoid confusion in the description of the height relationship, the threshold voltage is expressed by the absolute value | Vth | and defined by the magnitude relationship.

The control circuit 5 supplies a data signal over the initialization period and the compensation period. That is, in the j-th group, the control circuit 5 sequentially outputs the data signal Vd (j) in the pixels of i rows (3j-2) columns, i rows (3j-1) columns, i rows (3j) columns. On the other hand, the control signals Sel (1), Sel (2), and Sel (3) are sequentially set to the H level exclusively in accordance with the switching of the potential of the data signal. As a result, in the demultiplexer 30, the transmission gates 34 are turned on in the order of the left end column, the center column, and the right end column in each group.
Here, in the initialization period, when the transmission gate 34 in the leftmost column belonging to the jth group is turned on by the control signal Sel (1), the data signal Vd (j) is stored in the storage capacitor 41 as shown in FIG. Therefore, the data signal is held by the holding capacitor 41.

<Compensation period>
In the i-th scanning period, the compensation period (c) follows. In the compensation period, the scanning signal Gwr (i) and the control signal Gcmp (i) are at the L level as compared with the initialization period. On the other hand, in the compensation period, the control signal / Gini becomes H level while the control signal Gref is maintained at H level.
Therefore, as illustrated in FIG. 13, in the pixel circuit 110 in the i row (3j−2) column, the transistor 122 is turned on and the gate node g is electrically connected to the data line 14, while the transistor 123 When turned on, the transistor 121 is diode-connected.
Therefore, the current flows through the path of the feeder line 116 → the transistor 121 → the transistor 123 → the transistor 122 → the data line 14 in the (3j−2) th column, so that the gate node g rises from the potential Vini. However, since the current flowing through the path becomes difficult to flow as the gate node g approaches the potential (Vel− | Vth |), the data line 14 and the gate node g have the potential (Vel−) until the end of the compensation period. | Vth |).
Therefore, the storage capacitor 140 holds the threshold voltage | Vth | of the transistor 121 until the end of the compensation period.

  On the other hand, in the level shift circuit 40, the control signal / Gini becomes the H level while the control signal Gref is maintained at the H level. Therefore, in the level shift circuit 40, the node h is fixed at the potential Vref.

If the transmission gate 34 in the leftmost column belonging to the jth group is already turned on by the control signal Sel (1) in the initialization period, the transmission gate 34 is not turned on in the compensation period.
When the compensation period ends, the control signal Gcmp (i) becomes H level, so that the diode connection of the transistor 121 is released.

  Note that since the control signal Gref is at the L level between the end of the compensation period and the start of the next writing period, the transistor 43 is turned off. Therefore, although the path from the data line 14 in the (3j-2) column to the gate node g in the pixel circuit 110 in the i row (3j-2) column is in a floating state, the potential of the path is It is maintained at (Vel− | Vth |) by the holding capacitors 50 and 140.

<Writing period>
In the scanning period of the i-th row, the writing period (c) follows the compensation period. In the writing period, the control signal Gcmp (i) is at the H level, while in the compensation period, the control signal / Gini is at the H level (the control signal / Gcpl is at the L level) while the control signal Gref is at the L level. ).
Therefore, as shown in FIG. 14, in the level shift circuit 40, the transmission gate 42 is turned on, so that the data signal held in the holding capacitor 41 is supplied to the node h that is the other end of the holding capacitor 44. That is, a signal having a potential corresponding to the luminance of the OLED 150 is supplied to the node h. For this reason, the node h shifts from the potential Vref in the compensation period. The change in potential of the node h at this time is expressed as ΔV, and the potential after the change is expressed as (Vref + ΔV).

On the other hand, since the gate node g is connected to one end of the storage capacitor 44 via the data line 14, the capacitance ratio k2 is changed from the potential (Vel− | Vth |) in the compensation period to the potential change ΔV of the node h. Shift by the multiplied value. That is, the potential of the gate node g is a value (Vel− | Vth | + k2 · ΔV) shifted from the potential (Vel− | Vth |) in the compensation period by a value obtained by multiplying the potential change ΔV of the node h by the capacitance ratio k2. ) When this is expressed as an absolute value by the voltage Vgs of the transistor 121, it becomes a value (| Vth | −k2 · ΔV) shifted from the threshold voltage | Vth | by the potential shift of the gate node g.
The capacity ratio k2 is a capacity ratio determined by Cdt, Cref1, and Cref2. Strictly speaking, the capacitance Cpix of the storage capacitor 140 must be taken into consideration, but the capacitance Cpix is neglected because it is set to be sufficiently smaller than the capacitances Cdt, Cref1, and Cref2.

FIG. 15 is a diagram showing the relationship between the potential of the data signal and the potential of the gate node g in the writing period. As described above, the data signal supplied from the control circuit 5 can take a potential range from the minimum value Vmin to the maximum value Vmax according to the gradation level of the pixel. In this embodiment, the data signal is not directly written to the gate node g, but is level-shifted and written to the gate notebook g as shown in the figure.
At this time, the potential range ΔVgate of the gate node g is compressed to a value obtained by multiplying the potential range ΔVdata (= Vmax−Vmin) of the data signal by the capacitance ratio k2.
In addition, the potential Vp (= Vel− | Vth |) and Vref can determine how much the potential range ΔVgate of the gate node g is shifted with respect to the potential range ΔVdata of the data signal. This is because the potential range ΔVdata of the data signal is compressed with the capacitance ratio k2 with respect to the potential Vref, and the compression range shifted with reference to the potential Vp becomes the potential range ΔVgate of the gate node g. Because.

Thus, in the writing period of the i-th row, the gate node g of the pixel circuit 110 of the i-th row has a capacitance ratio k2 from the potential (Vel− | Vth |) in the compensation period to the potential change ΔV of the node h. The potential (Vel− | Vth | + k 2 · ΔV) shifted by an amount corresponding to the above is written.
Eventually, the scanning signal Gwr (i) becomes H level, and the transistor 122 is turned off. Thus, the writing period ends, and the potential of the gate node g is fixed to the shifted value.

<Light emission period>
In the present embodiment, after the writing period of the i-th row ends, the light emission period starts after one horizontal scanning period (H) has elapsed. In this light emission period, the control signal Gel (i) is at the L level as described above, so that the transistor 124 is turned on in the pixel circuit 110 in the i row (3j-2) column. Since the voltage Vgs between the gate and the source is (| Vth | −k 2 · ΔV), the current corresponding to the gray level in the OLED 150 causes the threshold voltage of the transistor 121 to be set as shown in FIG. It will be supplied in a compensated state.
Such an operation is also executed in parallel in time in other pixel circuits 110 in the i row other than the pixel circuit 110 in the (3j-2) th column in the scanning period of the i row. Further, such an operation on the i-th row is actually executed in the order of 1, 2, 3,..., (M−1), m-th row in the period of one frame, and is repeated for each frame. It is.

  According to the present embodiment, the potential range ΔVgate at the gate node g is narrowed with respect to the potential range ΔVdata of the data signal. Can be applied between the gate and the source. For this reason, even in the case where the minute current flowing through the OLED 150 changes relatively greatly with respect to the change in the gate-source voltage Vgs of the transistor 121 in the fine pixel circuit 110, the current supplied to the OLED 150 is accurately controlled. It becomes possible to do.

  In the level shift circuit 40, when the data signal is supplied to the data line 14 via the storage capacitor 44, the data signal is level-shifted so that the potential amplitude is compressed. During this level shift, if the potential of one end (data line 14) or the other end (node h) of the storage capacitor 44 is affected by potential fluctuations of other elements via the coupling capacitor, the data signal There is a concern that a potential whose level has been accurately level-shifted cannot be supplied to the data line 14, and as a result, the display quality is degraded.

On the other hand, in this embodiment, as shown in FIG. 6 in particular, the power supply line 16 that supplies the potential Vorst is provided as a constant potential line on each of the left and right sides of the storage capacitor 44 in plan view. For this reason, since both ends of the storage capacitor 44 are shielded from fluctuations in potential of adjacent columns, it is possible to suppress deterioration in display quality.
Further, the portion of the feeder line 16 that shields both ends of the storage capacitor 44, as shown in FIG. 8 in particular, is a wiring 16a made of the same conductive layer as the electrode 44a that is one end of the storage capacitor 44, and the storage capacitor 44. The other end of the electrode 44g and the wiring 16g made of the same conductive layer are laminated. For this reason, as compared with the case where the feeder line 16 is formed by a single layer different from the conductive layer constituting the storage capacitor 44, the capacitive coupling in the oblique direction is reduced when viewed in cross section. The shield function can be further improved.
In addition, in the present embodiment, the wirings 16g and 16a are connected to the power supply line 16 through the contact holes 16e and 16f. Since the contact holes 16a and 16f serve as a kind of charge barrier in the first interlayer insulating film L1 and the second interlayer insulating L2, the shield function can be further improved.

In the present embodiment, as shown in FIG. 6, not only the left and right sides of the storage capacitor 44, but also a stacked body of the power supply line 61 and the wiring 61g on the upper side of the storage capacitor 44, and the power supply line 62 on the lower side. A laminate with the wiring 62g is provided.
The feed line 61 is composed of the same conductive layer as the electrode 44a, the wiring 61g is composed of the same conductive layer as the electrode 44g, and the feed line 61 and the wiring 61g are connected via a contact hole 61e. Since the control signal / Gini is supplied to the control line 63, the potential changes depending on the L level and the H level of the logic signal, but the storage capacitor 44 is shielded by the laminate of the feeder line 61 and the wiring 61g. Therefore, it becomes difficult to be affected by the potential change in the control line 63.
On the other hand, the power supply line 62 is composed of the same conductive layer as the electrode 44a, the wiring 62g is composed of the same conductive layer as the electrode 44g, and the power supply line 62 and the wiring 62g are connected via a contact hole 62e. Since the control signal Gref is supplied to the control line 64, the potential changes depending on the L level and the H level of the logic signal, but the storage capacitor 44 is shielded by the stacked body of the feeder line 62 and the wiring 62g. Thus, the control line 64 is less susceptible to changes in potential.

As described above, in this embodiment, when viewed in plan, the four sides of the storage capacitor 44 are surrounded by the power supply lines 16, 61, 62. Effectively shielded. For this reason, the deterioration of display quality can be suppressed.
Since the storage capacitor 44 has a longitudinal shape when viewed in a plan view, shielding by the power supply line 16 is more important than the power supply lines 61 and 62.

  In the present embodiment, the power supply line 16 that supplies the potential Vorst is used as the constant potential line provided on the left and right of the storage capacitor 44. However, it is preferable that the constant potential is supplied to the pixel circuit 110. Therefore, it is not limited to the feeder line 16. For example, while the power supply line 16 extends in the row direction, a power supply line 116 that supplies the potential Vel on the higher power supply side may be provided on the left and right sides of the storage capacitor 44 instead. In addition, power supply lines connected to the common electrode 118 of the lower potential Vct of the power source may be provided on the left and right of the storage capacitor 44.

  In the embodiment, for example, the wiring 16a is connected to the wiring 16g via a plurality of contact holes 16e, and the power supply line 16 is connected to the wiring 16a via a plurality of contact holes 16f. Is defined by a predetermined design rule. For this reason, depending on the design rule, the number may be one when viewed in a plan view, or the opening portion may have a rectangular shape that is long in the vertical direction.

  The wirings 16g and 16a are connected to the power supply line 16 through the contact holes 16e and 16f so as to have a common potential Vorst. However, the wirings 16g and 16a may have different potentials without being connected to each other. For example, as shown in FIG. 17, for the wiring 16g, as the wiring branched from the wiring 61g, the initial potential Vref of the electrode 44g may be supplied through the contact hole 62e. The initial potential Vini of the electrode 44a may be supplied as a wiring branched from the power supply line 61.

  On the other hand, according to the present embodiment, the current Ids supplied to the OLED 150 by the transistor 121 cancels the influence of the threshold voltage. For this reason, according to the present embodiment, even if the threshold voltage of the transistor 121 varies from pixel circuit 110 to pixel circuit 110, the variation is compensated and a current corresponding to the gradation level is supplied to the OLED 150. As a result of suppressing the occurrence of display unevenness that impairs uniformity, high-quality display is possible.

This cancellation will be described with reference to FIG. As shown in this figure, the transistor 121 operates in a weak inversion region (subthreshold region) in order to control a minute current supplied to the OLED 150.
In the figure, A indicates a transistor having a large threshold voltage | Vth |, and B indicates a transistor having a small threshold voltage | Vth |. In FIG. 16, the gate-source voltage Vgs is the difference between the characteristic indicated by the solid line and the potential Vel. In FIG. 16, the current on the vertical scale is shown as a logarithm with the direction from the source to the drain being positive (upper).
In the compensation period, the gate node g changes from the potential Vini to the potential (Vel− | Vth |). Therefore, the transistor A having a large threshold voltage | Vth | moves from S to Aa while the transistor B having a small threshold voltage | Vth | moves from S to Ba.
Next, when the potential of the data signal to the pixel circuit 110 to which the two transistors belong is the same, that is, when the same gradation level is designated, the potential shift amount from the operating points Aa and Ba is Are the same k 2 · ΔV. Therefore, the operating point of the transistor A moves from Aa to Ab, and the operating point of the transistor B moves from Ba to Bb. However, the current at the operating point after the potential shift is almost the same in both the transistors A and B. Ids will be aligned.
Thus, according to the present embodiment, even if the threshold voltage of the transistor 121 varies for each pixel circuit 110, the variation is compensated.

  Further, according to the present embodiment, the data signal supplied from the control circuit 5 is once held in the holding capacitor 41 from the initialization period to the compensation period, and then the holding potential is level-shifted in the writing period. Supply to the data line 14 above. For this reason, from the viewpoint of the control circuit 5, the data signal may be supplied over a relatively long period from the initialization period to the compensation period, not the writing period. it can.

<Application and modification>
The present invention is not limited to the above-described embodiments and application examples, and various modifications as described below are possible. Moreover, the aspect of the deformation | transformation described below can also combine suitably arbitrarily selected 1 or several.

<Electrode for holding capacitor>
In the embodiment, the electrode 44g of the storage capacitor 44 is configured from the first conductive layer, and the electrode 44a is configured from the second conductive layer. For example, the electrode 44g is configured from the second conductive layer, and the electrode 44a is configured as the third conductive layer. You may comprise from a layer. In the embodiment, the electrode 44g is the lower electrode of the electrode 44a in a cross-sectional view, but the electrode 44g may be the upper electrode of the electrode 44a.

<Control circuit>
In the embodiment, the control circuit 5 that supplies the data signal is separated from the electro-optical device 10. It may be integrated on a substrate.

<Board>
In the embodiment, the electro-optical device 10 is integrated on the semiconductor silicon substrate. However, the electro-optical device 10 may be integrated on another semiconductor substrate. For example, an SOI substrate may be used. Further, it may be formed on a glass substrate or the like by applying a polysilicon process.

<Control signal Gcmp (i)>
In the embodiment and the like, in the i-th row, the control signal Gcmp (i) is set to the H level in the writing period, but may be set to the L level. That is, the threshold compensation by turning on the transistor 123 and the writing to the node gate g may be executed in parallel.

<Demultiplexer>
In the embodiment and the like, the data lines 14 are grouped every three columns, and the data lines 14 are sequentially selected in each group to supply data signals. However, the number of data lines constituting the group is as follows. "2" may be sufficient and "4" or more may be sufficient.
Further, a configuration may be adopted in which data signals are supplied to the data lines 14 of each column all at once without grouping, that is, without using the demultiplexer 30.

<Transistor channel type>
In the above-described embodiments and the like, the transistors 121 to 125 in the pixel circuit 110 are unified with the P-channel type, but may be unified with the N-channel type. Further, the P channel type and the N channel type may be appropriately combined.

<Others>
In the embodiments and the like, an OLED that is a light emitting element is illustrated as an electro-optical element, but any light emitting element may be used as long as it emits light with a luminance according to current, such as an inorganic light emitting diode or LED (Light Emitting Diode).

<Electronic equipment>
Next, an electronic apparatus to which the electro-optical device 10 according to the embodiment and the application example is applied will be described. The electro-optical device 10 is suitable for high-definition display with small pixels. Therefore, a head mounted display will be described as an example of an electronic device.

FIG. 18 is a diagram showing the external appearance of a head-mounted display, and FIG. 19 is a diagram showing its optical configuration.
First, as shown in FIG. 18, the head mounted display 300 has a temple 310, a bridge 320, and lenses 301L and 301R in the same manner as general glasses. Further, as shown in FIG. 19, the head mounted display 300 is in the vicinity of the bridge 320 and on the back side (lower side in the drawing) of the lenses 301L and 301R, the electro-optical device 10L for the left eye and the right eye. Electro-optical device 10R.
The image display surface of the electro-optical device 10L is arranged on the left side in FIG. Accordingly, the display image by the electro-optical device 10L is emitted in the direction of 9 o'clock in the drawing through the optical lens 302L. The half mirror 303L reflects the display image from the electro-optical device 10L in the 6 o'clock direction, and transmits light incident from the 12 o'clock direction.
The image display surface of the electro-optical device 10R is disposed on the right side opposite to the electro-optical device 10L. As a result, the display image by the electro-optical device 10R is emitted in the direction of 3 o'clock in the drawing through the optical lens 302R. The half mirror 303R reflects the display image by the electro-optical device 10R in the 6 o'clock direction, and transmits light incident from the 12 o'clock direction.

In this configuration, the wearer of the head mounted display 300 can observe the display image by the electro-optical devices 10L and 10R in a see-through state superimposed on the outside.
In the head-mounted display 300, when a left-eye image is displayed on the electro-optical device 10L and a right-eye image is displayed on the electro-optical device 10R among binocular images with parallax, The displayed image can be perceived as if it had a depth or a stereoscopic effect (3D display).

  The electro-optical device 10 can be applied to an electronic viewfinder in a video camera, an interchangeable lens digital camera, etc. in addition to the head mounted display 300.

DESCRIPTION OF SYMBOLS 10 ... Electro-optical apparatus, 12 ... Scanning line, 14 ... Data line, 16 ... Feeding line, 20 ... Scanning line drive circuit, 30 ... Demultiplexer, 40 ... Level shift circuit, 41, 44, 50 ... Retention capacity, 100 ... Display unit 110... Pixel circuit 116 116 power supply line 118 common electrode 121 to 125 transistor 140 holding capacitor 150 OLED 300 head mounted display

Claims (6)

Multiple data lines,
A first pixel circuit provided corresponding to the first data line among the plurality of data lines;
A second pixel circuit provided corresponding to a second data line among the plurality of data lines;
Have
Each of the first pixel circuit and the second pixel circuit includes:
A light emitting element;
A driving transistor for supplying a current corresponding to the voltage between the gate and the source to the light emitting element;
An electro-optical device comprising:
A first storage capacitor having one end connected to the first data line and the other end shifted in potential according to a current to be supplied to a light emitting element in the first pixel circuit;
A second storage capacitor having one end connected to the second data line and the other end shifted in potential according to a current to be supplied to a light emitting element in the second pixel circuit;
A constant potential line provided between the first storage capacitor and the second storage capacitor in plan view;
An electro-optical device comprising: One end of the first storage capacitor and one end of the second storage capacitor are formed by either the first conductive layer or the second conductive layer,
The other end of the first storage capacitor and the other end of the second storage capacitor are formed of either the first conductive layer or the second conductive layer,
The electro-optical device according to claim 1, wherein the constant potential line is formed by at least the wiring of the first conductive layer and the wiring of the second conductive layer. The electro-optical device according to claim 2, wherein the wiring of the first conductive layer and the wiring of the second conductive layer in the constant potential line are electrically connected to each other. The light emitting element is a two-terminal element,
The light emitting element and the driving transistor are electrically connected in series between two different power supply potentials,
Of the two terminals of the light emitting element, the terminal on the drive transistor side is set to a predetermined reset potential after current is supplied by the drive transistor,
The electro-optical device according to claim 1, wherein the reset potential is supplied to the constant potential line. The light emitting element and the driving transistor are connected in series between two different power supply potentials,
The electro-optical device according to claim 1, wherein one of the two power supply potentials is supplied to the constant potential line. An electronic apparatus comprising the electro-optical device according to claim 1.

Images