JP7124341B2 - electro-optical devices and electronic devices - Google Patents

Description

The present invention relates to an electro-optical device, and an electronic apparatus and the like having the electro-optical device.

In recent years, various electro-optical devices using light-emitting elements such as organic light-emitting diodes (hereinafter referred to as OLED (Organic Light Emitting Diode)) have been proposed. In a conventional electro-optical device, a pixel includes a light-emitting element, a selection transistor that takes in a voltage corresponding to the display gradation of the light-emitting element, and a drive transistor that supplies a current to the light-emitting element, corresponding to the intersection of the scanning line and the data line. A circuit is provided.
Patent Document 1 discloses a layout in which the source, gate, and drain of the driving transistor are arranged along the scanning line direction.

Japanese Patent Application Laid-Open No. 2003-332072

However, in the conventional technology, when the size of the electro-optical device is reduced, crosstalk tends to occur between pixel circuits adjacent to each other in the scanning line direction. Specifically, when the voltage of the drain of the drive transistor of the pixel circuit fluctuates, the voltage of the gate of the drive transistor in the pixel circuit adjacent to the pixel circuit in the scanning line direction is affected. As a result, there is a problem that image quality deteriorates.

In order to solve the above-described problems, an electro-optical device according to the present invention provides first light-emitting elements that are provided corresponding to scanning lines and that emit light with luminance corresponding to the supplied current, and an electric current supplied to the first light-emitting elements. a first pixel circuit that controls a current to be applied according to a first gradation voltage; and a second pixel circuit that is adjacent to the first pixel circuit in the scanning line direction. a fixed a fixed potential line to which a potential is applied and provided in a direction intersecting the scanning line, along the scanning line, the source of the first driving transistor, the gate of the first driving transistor, and the first driving transistor; A drain of a transistor and a source of the second driving transistor are arranged side by side, and the fixed potential line is provided between the drain of the first driving transistor and the source of the second driving transistor.

According to this aspect, a fixed potential line to which a fixed potential is applied is provided between the drain of the first drive transistor and the source of the second drive transistor. It acts as a shield to prevent fluctuations from affecting the gate voltage of the second drive transistor. Therefore, according to this aspect, crosstalk can be suppressed even if the first driving transistor and the second driving transistor are arranged in the scanning line direction. As a result, the image quality of the electro-optical device can be improved.

In the electro-optical device described above, a substrate provided with a first region of a first conductivity type in which the source of the second drive transistor is formed, and a second region of a second conductivity type different from the first conductivity type are provided. , wherein the fixed potential is applied to the second region, and the fixed potential line is connected to the second region. According to this aspect, the potential of the fixed potential line is fixed to the substrate potential, which is the potential of the second region.

The electro-optical device described above has a first wiring connected to the drain of the first driving transistor and extending in a direction intersecting the scanning line, the fixed potential line being provided in parallel with the first wiring, and the fixed The potential line may be longer than the first wiring.

According to this aspect, the shielding effect is higher than when the length of the fixed potential line is shorter than the length of the first wiring.

The electro-optical device described above includes a light-emitting layer in which the first light-emitting element and the second light-emitting element are formed, and a first metal layer provided closer to the substrate than the light-emitting layer, wherein the first wiring and the fixed potential line, a second metal layer provided closer to the light-emitting layer than the first metal layer, and connecting the fixed potential line and the second metal layer. and a relay electrode.

According to this aspect, since the second metal layer also functions as a shield in addition to the fixed potential line, the shield effect is further enhanced.

The electro-optical device described above may be characterized in that the fixed potential line is connected to the source of the second drive transistor.

Also in this aspect, the fixed potential line serves as a shield that prevents the fluctuation of the drain voltage of the first drive transistor from affecting the gate voltage of the second drive transistor.

The electro-optical device described above is a light emission control transistor that controls on or off of the current flowing from the second drive transistor to the second light emitting element, the drain is connected to the source of the second drive transistor, and the source is and a light emission control transistor connected to the fixed potential line.

Also in this aspect, the fixed potential line serves as a shield that prevents the fluctuation of the drain voltage of the first drive transistor from affecting the gate voltage of the second drive transistor.

Further, the present invention can be conceptualized not only as an electro-optical device but also as an electronic device including the electro-optical device. Electronic devices typically include display devices such as head-mounted displays (HMDs) and electronic viewfinders.

1 is a perspective view showing the configuration of an electro-optical device according to a first embodiment of the invention; FIG. 1 is a diagram showing an electrical configuration of an electro-optical device; FIG. FIG. 4 is a diagram showing the configuration of a demultiplexer of the electro-optical device; 2 is a circuit diagram showing configurations of a pixel circuit and a switch section of an electro-optical device; FIG. 3A and 3B are diagrams showing the layout of a light emitting portion of a pixel and the layout of a circuit portion corresponding to the light emitting portion in an electro-optical device; FIG. 2 is a perspective view showing a planar structure of a circuit portion of a pixel circuit; FIG. 3 is a cross-sectional view of a pixel circuit; FIG. FIG. 5 is a circuit diagram showing the configuration of a pixel circuit of an electro-optical device according to a second embodiment of the invention; It is a perspective view showing the plane structure of the circuit part of the same pixel circuit. 1 is a perspective view of a head mounted display 300 according to the invention; FIG. 1 is a perspective view of a personal computer 400 according to the invention; FIG.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings. However, in each drawing, the dimensions and scale of each part are appropriately different from the actual ones. In addition, since the embodiments described below are preferred specific examples of the present invention, various technically preferable limitations are attached, but the scope of the present invention is particularly limited in the following description. It is not limited to these forms unless otherwise stated.

<A: First Embodiment>
FIG. 1 is a perspective view showing the configuration of an electro-optical device 1 according to an embodiment of the invention. The electro-optical device 1 is, for example, a microdisplay that displays images in a head-mounted display.

As shown in FIG. 1 , the electro-optical device 1 includes a display panel 10 and a control circuit 3 that controls the operation of the display panel 10 . The display panel 10 includes a plurality of pixel circuits and a drive circuit that drives the pixel circuits. In this embodiment, the plurality of pixel circuits and drive circuits included in the display panel 10 are formed on a silicon substrate, and OLEDs, which are an example of electro-optical elements, are used for the pixel circuits. The display panel 10 is housed in, for example, a frame-shaped case 82 that opens at the display portion, and one end of an FPC (Flexible Printed Circuits) substrate 84 is connected. The control circuit 3 of the semiconductor chip is mounted on the FPC board 84 by COF (Chip On Film) technology, and a plurality of terminals 86 are provided and connected to an upper circuit (not shown).

FIG. 2 is a block diagram showing the configuration of the electro-optical device 1 according to the embodiment. As described above, the electro-optical device 1 has the display panel 10 and the control circuit 3 . Digital image data Video is supplied to the control circuit 3 from a higher-level circuit (not shown) in synchronization with a synchronizing signal. Here, the image data Video is data that defines, for example, 8-bit display gradation of pixels of an image to be displayed on the display panel 10 (strictly speaking, the display unit 100 described later). A synchronization signal is a signal including a vertical synchronization signal, a horizontal synchronization signal, and a dot clock signal.

The control circuit 3 generates various control signals based on the synchronization signal and supplies them to the display panel 10 . Specifically, the control circuit 3 controls the control signals Ctr1 to Ctr3, Gref, /Gini, Gcpl, /Gcpl, Sel(1), Sel(2), Sel(3), /Sel(1), /Sel( 2), /Sel(3), is supplied to the display panel 10 . Each of the control signals Ctr1 to Ctr3 is a signal including a plurality of signals such as pulse signals, clock signals, and enable signals. The control signal Gref is a positive logic control signal, and the control signal /Gini is a negative logic control signal. The control signal Gcpl is also a positive logic control signal, and the control signal /Gcpl is a negative logic control signal having a logic inversion relationship with the control signal Gcpl. Control signal /Sel(1) has a relationship of logic inversion with control signal Sel(1). Similarly, control signal /Sel(2) and control signal Sel(2), and control signal /Sel(3) and control signal Sel(3) are in a logically inverted relationship. Control signals Sel(1), Sel(2), and Sel(3) are collectively referred to as control signals Sel, and control signals /Sel(1), /Sel(2), and /Sel(3) are referred to as control signals /Sel. The voltage generating circuit 31 receives power from a power supply circuit (not shown) and supplies the display panel 10 with a reset potential Vorst, a reference potential Vref and an initialization potential Vini.

Furthermore, the control circuit 3 generates an analog image signal Vid based on the image data Video. Specifically, the control circuit 3 is provided with a lookup table that stores the potential indicated by the image signal Vid and the luminance of the electro-optical element included in the display panel 10 in association with each other. By referring to the lookup table, the control circuit 3 generates an image signal Vid indicating a potential corresponding to the luminance of the electro-optical element specified in the image data Video, and sends it to the display panel 10. supply.

As shown in FIG. 2, the display panel 10 includes a display section 100 and drive circuits (scanning line drive circuit 4 and data line drive circuit 5) for driving the display section 100. FIG. Although the drive circuit is divided into the scanning line drive circuit 4 and the data line drive circuit 5 in this embodiment, the drive circuit may be configured by integrating these into one circuit. As shown in FIG. 2, in the display unit 100, pixel circuits 110 corresponding to pixels of an image to be displayed are arranged in a matrix. Although detailed illustration is omitted in FIG. 2, the display unit 100 is provided with M rows of scanning lines 12 extending in the horizontal direction (X direction) in the figure, and grouped every three columns. (3N) columns of data lines 14 are provided extending in the vertical direction (Y direction) in the figure. Each scanning line 12 and each data line 14 are electrically isolated from each other. The pixel circuits 110 are provided at the intersections of the scanning lines 12 of M rows and the data lines 14 of (3N) columns. Therefore, in the present embodiment, the pixel circuits 110 are arranged in a matrix of M rows×(3N) columns.

Here, both M and N are natural numbers. In order to distinguish the rows in the matrix of the scanning lines 12 and the pixel circuits 110, they are sometimes referred to as 1, 2, 3, . Similarly, in order to distinguish the columns of the matrix of the data lines 14 and the pixel circuits 110, they may be referred to as columns 1, 2, 3, . . Here, in order to generalize and explain the groups of the data lines 14, if an arbitrary integer of 1 or more is represented by n, the n-th group counting from the left includes the (3n-2)th column, (3n The data lines 14 in the -1)th and (3n)th columns belong. Three pixel circuits 110 corresponding to scanning lines 12 in the same row and data lines 14 in three columns belonging to the same group correspond to R (red), G (green), and B (blue) pixels, respectively.

In addition, as shown in FIG. 2 , the display unit 100 is provided with (3N) rows of feeder lines 16 that extend in the vertical direction and are electrically insulated from the scanning lines 12 . Each power supply line 16 is a fixed potential line to which a predetermined reset potential Vorst is commonly supplied from the voltage generation circuit 31 . In order to distinguish the columns of the feeder lines 16, the feeder lines 16 may be called the 1st, 2nd, 3rd, . . . , (3N)th columns from the left in the drawing. Each of the feeder lines 16 of the 1st to (3N) columns is provided corresponding to the data lines 14 of the 1st to (3N) columns.

The scanning line driving circuit 4 generates a scanning signal Gwr for sequentially selecting the M scanning lines 12 row by row within one frame period according to the control signal Ctr1. 2, the scanning signals Gwr supplied to the 1st, 2nd, 3rd, . . . , Mth scanning lines 12 are Gwr(1), Gwr(2), Gwr(3), . 1), denoted as Gwr(M). In addition to the scanning signals Gwr(1) to Gwr(M), the scanning line driving circuit 4 generates various control signals synchronized with the scanning signal Gwr for each row and supplies them to the display unit 100. Illustration is omitted in FIG. A frame period is a period required for the electro-optical device 1 to display an image for one cut (frame). A period of 8.3 milliseconds.

As shown in FIG. 2, the data line drive circuit 5 includes (3N) switch sections SW provided in one-to-one correspondence with the data lines 14 of (3N) columns, and 3 switch sections SW constituting each group. It has N demultiplexers DM provided for each column data line 14 and a data signal supply circuit 70 .

The data signal supply circuit 70 generates data signals Vd(1), Vd(2), . That is, the data signal supply circuit 70 generates the data signals Vd(1), Vd(2) based on the image signal Vid obtained by time division multiplexing the data signals Vd(1), Vd(2), . . . , Vd(N). , . . . , Vd(N). Then, the data signal supply circuit 70 supplies the data signals Vd(1), Vd(2), . . . , Vd(N) to the demultiplexers DM corresponding to the 1st, 2nd, . supply each.

The configurations of the pixel circuit 110, the switch section SW, and the demultiplexer DM will be described with reference to FIGS. 3 and 4. FIG. FIG. 3 is a diagram showing the configuration of the demultiplexer DM, and FIG. 4 is a diagram showing the configurations of the pixel circuit 110 and the switch section SW. Since each pixel circuit 110 has the same configuration from an electrical point of view, the pixel circuit of the m row (3n) column located in the mth (1≦m≦M)th row and the (3n)th column. 110 will be described as an example. A scanning signal Gwr(m) and control signals Gcmp(m), Gorst(m), and Gel(m) are supplied from the scanning line driving circuit 4 to the pixel circuits 110 on the m-th row.

As shown in FIG. 4 , the display area 112 of the display unit 100 is provided with pixel circuits 110 and data lines 14 that supply gradation voltages to the pixel circuits 110 . In addition, in the display area 112, along the data lines 14, signal lines 15, feed lines 16, feed lines 17, and signal lines 20 are provided for each column. The power supply line 17 of each column is a fixed potential line to which the voltage generation circuit 31 commonly supplies the potential Vel, which is the high-potential side of the power supply in the pixel circuit 110 . In FIG. 3, the pixel circuit 110 of the m row (3n) column is indicated by the code "110 (m, 3n)", and the data line 14 of the (3n)th column is indicated by the code "14 (3n)". ing. Similarly to the data line 14, in FIG. The feeder line 17 in the )th column is indicated by the code "17 (3n)", and the signal line 20 in the (3n)th column is indicated by the code "20 (3n)".

As shown in FIG. 4, a capacitor 44 is provided between the data line 14(3n) and the feeder line 16(3n), and a capacitor 44 is provided between the data line 14(3n) and the feeder line 17(3n). is provided with a capacitor 46 . A capacitor 50 is provided between the signal line 15 (3n) and the signal line 20 (3n). The capacitance 44 may be an inter-wiring capacitance between the feeder line 16 (3n) and the data line 14 (3n). Similarly, the capacitance 46 may also be the inter-wiring capacitance between the data line 14 (3n) and the feeder line 17 (3n), and the capacitance 50 may also be the capacitance between the signal line 20 (3n) and the signal line 15 (3n). It may be an inter-wiring capacitance between. As shown in FIG. 4, the data line 14 (3n), the signal line 15 (3n), and the signal line 20 (3n) are all connected to the switch section SW, and the pixel circuit 110 connects the signal line 15 (3n) and the signal line 20 (3n). It is connected to the feed line 16 (3n). In FIG. 3, the switch section SW connected to the data line 14 (3n) is indicated by the symbol "SW (3n)", and the demultiplexer DM connected to the switch section SW (3n) is indicated by the symbol " DM(n)”.

First, the configuration of the demultiplexer DM(n) will be described with reference to FIG. As shown in FIG. 3, the demultiplexer DM(n) is a set of transmission gates 34 provided for each column, and supplies data signals in order to the three columns forming each group. The input terminals of the transmission gates 34 corresponding to the (3n-2), (3n-1), and (3n) columns belonging to the n-th group are commonly connected to each other, and the data signal Vd(n) is applied to each common terminal. supplied. Although detailed illustration is omitted in FIG. 3, the output end of the transmission gate 34 corresponding to the (3n) column is connected to the input end of the switch section SW(3n) via the signal line 18(3n). Similarly, the output terminal of the transmission gate 34 corresponding to the (3n-1) column is connected to the input terminal of the switch section SW (3n-1) through the signal line 18 (3n-1). 2) The output terminal of the transmission gate 34 corresponding to the column is connected to the input terminal of the switch section SW(3n-2) via the signal line 18(3n-2). The transmission gate 34 provided in the (3n-2) column, which is the leftmost column in the n-th group, operates when control signal Sel(1) is at H level (when control signal /Sel(1) is at L level). ). Similarly, the transmission gate 34 provided in the (3n-1) column, which is the center column in the n-th group, operates when control signal Sel(2) is at H level (control signal /Sel(2) is at L level). ), and the transmission gate 34 provided in the (3n) column, which is the rightmost column in the n-th group, turns on when the control signal Sel(3) is at H level (control signal /Sel(3) is at L level).

Next, the configuration of the switch section SW(3n) will be described with reference to FIG. As shown in FIG. 4, the switch section SW (3n) has a capacitor 41, a transmission gate 42, an N-channel MOS transistor 43 and a P-channel MOS transistor 45, and a signal line 18 (3n). to shift the potential of the data signal input through the . As shown in FIG. 4, data line 14 (3n) is connected to one electrode of capacitor 41 and is connected to signal line 18 (3n) at node h, and signal line 20 (3n) is connected to transmission gate 42. (switch) output end. Transmission gate 42 is supplied with control signal Gcpl and control signal /Gcpl from control circuit 3 . Transmission gate 42 is turned on when control signal Gcpl is at H level (when control signal /Gcpl is at L level). When transmission gate 42 is turned on, signal line 18(3n) and data line 14(3n) connected to signal line 18(3n) at node h are electrically connected to signal line 20(3n). be done.

The drain of the transistor 45 is connected to the signal line 15 (3n), and the source of the transistor 45 is connected to the power supply line 61 supplied with a predetermined initialization potential Vini. The control circuit 3 supplies a control signal /Gini to the gate of the transistor 45 . The transistor 45 electrically connects the signal line 15 (3n) and the feeder line 61 when the control signal /Gini is at L level, and electrically disconnects it when the control signal /Gini is at H level. . When the signal line 15(3n) and the feeder line 61 are electrically connected, the potential of the signal line 15(3n) becomes the initialization potential Vini.

The drain of the transistor 43 is connected to the signal line 20(3n), and the source of the transistor 43 is connected to the feed line 62 supplied with the reference potential Vref. The reference potential Vref is the potential used in the compensation operation for compensating the threshold voltage of the driving transistor of the pixel circuit 110 . A control signal Gref is supplied to the gate of the transistor 43 . The transistor 43 electrically connects the signal line 20 (3n) and the power supply line 62 when the control signal Gref is at H level, and electrically disconnects them when the control signal Gref is at L level. When the signal line 20(3n) and the feeder line 62 are electrically connected, the potential of the signal line 20(3n) becomes the reference potential Vref.

The other electrode of capacitor 41 is connected to power supply line 64 . A potential VSS, which is a fixed potential, is supplied to the feed line 64 . Here, the potential VSS may correspond to the L level of the scanning signal and the control signal, which are logic signals. When the transmission gate 34 is turned on while the transmission gate 42 is off, the data signal Vd(n) is supplied from the output terminal of the transmission gate 34 to the signal line 18(3n), and the signal is transmitted through the data line 14(3n). Charges corresponding to the gradation voltage indicated by the data signal Vd(n) are accumulated in the capacitors 41, 44 and 46 connected to the line 18(3n). In other words, the capacitors 41, 44, and 46 in the (3n) column play the role of holding capacitors that hold the gradation voltage corresponding to the display gradation of the pixel circuit 110 in the (3n) column. When the transmission gate 42 is turned on and the signal line 18 (3n) and the signal line 20 (3n) are electrically connected, the gradation voltage held in the capacitors 41, 44 and 46 is transferred to the data line. 14(3n), signal line 18(3n), signal line 20(3n), capacitor 50 and signal line 15(3n) to pixel circuit 110(m, 3n). in short. The capacitor 50 plays a role of a transfer capacitor that transfers the gradation voltages held in the capacitors 41, 44 and 46 to the pixel circuit 110 (3n).

Next, the configuration of the pixel circuit 110 (m, 3n) will be described with reference to FIG. As shown in FIG. 4, the pixel circuit 110 (m, 3n) includes a first transistor 121, a second transistor 122, a third transistor 123, a fourth transistor 124 and a fifth transistor 125, each of which is a P-channel MOS type transistor. , an OLED 130 and a capacitor 132 . Hereinafter, the first transistor 121, the second transistor 122, the third transistor 123, the fourth transistor 124, and the fifth transistor 125 may be collectively referred to as "transistors 121 to 125."

The gate of the second transistor 122 is electrically connected to the scanning line 12 (in the case of the pixel circuit 110(m,3n), the scanning line 12 of the m-th row). One of the source and drain of the second transistor 122 is electrically connected to the signal line 15 (3n), and the other is electrically connected to the gate of the first transistor 121 and one electrode of the capacitor 132. It is The second transistor 122 functions as a switching transistor that controls electrical connection between the gate of the first transistor 121 and the signal line 15 (3n).

A source of the first transistor 121 is electrically connected to the power supply line 116 . A power supply circuit (not shown) supplies power to the power supply line 116 from a power supply circuit (not shown), which is a potential Vel on the high side of the power supply in the pixel circuit 110 . The first transistor 121 functions as a drive transistor that causes the OLED 130 to flow a current corresponding to the gate voltage.

One of the source and drain of the third transistor 123 is electrically connected to the signal line 15 (3n) and the other is electrically connected to the drain of the first transistor 121 . A control signal Gcmp(m) is applied to the gate of the third transistor 123 . The third transistor 123 is a transistor for conducting between the gate and source of the first transistor 121 via the signal line 15 (3n) and the second transistor 122 . That is, the third transistor 123 functions as a switching transistor that controls electrical connection between the gate and drain of the first transistor 121 .

The source of fourth transistor 124 is electrically connected to the drain of first transistor 121 and the drain of fourth transistor 124 is electrically connected to the anode of OLED 130 . A control signal Gel(m) is applied to the gate of the fourth transistor 124 . The fourth transistor 124 functions as an emission control transistor that controls the electrical connection between the drain of the first transistor 121 and the anode of the OLED 130, i.e., controls whether the OLED 130 emits light or not.

One of the source and the drain of the fifth transistor 125 is electrically connected to the power supply line 16 (3n), that is, the fixed potential line feeding the reset potential Vorst, and the other is connected to the anode of the OLED 130 . A control signal Gorst(m) is supplied to the gate of the fifth transistor 125 . Fifth transistor 125 functions as a switching transistor that controls the electrical connection between feed line 16 (3n) and the anode of OLED 130 .

Since the display panel 10 is formed on a silicon substrate in this embodiment, the substrate potential of the transistors 121 to 125 is the potential Vel. In addition, the sources and drains of the transistors 121 to 125 may be interchanged according to the relationship between the channel types and potentials of the transistors 121 to 125 . Also, the transistor may be a thin film transistor or a field effect transistor.

One electrode of the capacitor 132 is electrically connected to the gate of the first transistor 121 and the other electrode is electrically connected to the feed line 116 . The capacitor 132 functions as a holding capacitor that holds the gradation voltage applied through the signal line 15 (3n). As the capacitor 132, a capacitor parasitic on the gate of the first transistor 121 may be used, or a capacitor formed by sandwiching an insulating layer between different conductive layers on a silicon substrate may be used.

The anode 130 a of the OLED 130 is a pixel electrode that is individually provided for each pixel circuit 110 . On the other hand, the cathode of the OLED 130 is a common electrode 118 commonly provided over the entire pixel circuit 110 and connected to the feed line 63 . A potential Vct, which is a fixed potential, is supplied to the power supply line 63 . Here, the potential Vct may correspond to the L level of the scanning signal and the control signal, which are logical signals. The OLED 130 is a device in which a white organic EL layer is sandwiched between an anode 130a of the OLED 130 and a light-transmitting cathode on the silicon substrate. A color filter corresponding to any one of RGB is superimposed on the emission side (cathode side) of the OLED 130 . The wavelength of the light emitted from the OLED 130 may be set by adjusting the optical distance between two reflective layers that sandwich the white organic EL layer to form a cavity structure. In this case, it may or may not have a color filter.

When a current flows from the anode 130a of the OLED 130 to the cathode (common electrode 118), the holes injected from the anode 130a and the electrons injected from the cathode recombine in the organic EL layer to generate excitons and emit white light. occurs. The white light generated at this time passes through the cathode on the side opposite to the silicon substrate (anode), is colored by a color filter, and is visually recognized by the observer.

FIG. 5 is a diagram showing the correspondence between the light emitting units and the circuit units in the pixel circuit 110. As shown in FIG. The light-emitting portion includes an OLED 130, and the circuit portion includes transistors 121-125 and a capacitor 132. FIG. In this embodiment, as shown in FIG. 5, the light-emitting portions are laid out in a square. In FIG. 5 , the light-emitting portion of the pixel circuit 110 emitting red light is “R”, the light-emitting portion of the pixel circuit 110 emitting green light is “G”, and the light-emitting portion of the pixel circuit 110 emitting blue light is “R”. Each is indicated by a "B". In FIG. 5 , the circuit portion of the pixel circuit 110 emitting red light is denoted by “RC”, the circuit portion of the pixel circuit 110 emitting green light is denoted by “GC”, and the circuit portion of the pixel circuit 110 emitting blue light is denoted by “RC”. Each is indicated by "BC". The circuit section is formed in a one-to-one correspondence with the light emitting section, and is laid out in the same square as the light emitting section. The reason why the layout of the circuit section is the same as that of the light emitting section is to avoid luminance variations due to the difference in layout between the two. In this embodiment, one dot of a color image is represented by one light emitting portion emitting red light, one light emitting portion emitting green light, and two light emitting portions emitting blue light. The reason is as follows. If a red or green light-emitting portion and a blue light-emitting portion are caused to emit light with the same luminance, the life of the blue light-emitting portion will be shortened. For this reason, in order to equalize the lives of the red, green, and blue light-emitting portions, it is necessary to suppress the emission brightness of the blue light-emitting portion. The number of blue light-emitting portions was increased in order to match the apparent brightness of the original.

6 is a perspective view showing the planar structure of the circuit portion of the pixel circuit 110, and FIG. 7 is a cross-sectional view showing a cross section taken along line AA' in FIG. FIG. 6 illustrates the arrangement of transistors in each of the first pixel circuit 110-1 and the second pixel circuit 110-2 arranged in the scanning line direction (X direction). Hereinafter, when it is necessary to distinguish between the transistors included in the first pixel circuit 110-1 and the transistors included in the second pixel circuit 110-2, the two are distinguished by the reference numerals. For example, the first transistor 121 of the first pixel circuit 110-1 is denoted as "first transistor 121-1", and the first transistor 121 of the second pixel circuit 110-2 is denoted as "first transistor 121-2". is written as The feed line 116, the OLED 130, and the capacitor 132 are also represented in the same way. The first transistor 121-1 is a first drive transistor that controls the current flowing through the OLED 130-1 (first light emitting element) according to the first gradation voltage applied to the gate. The first transistor 121-2 is a second drive transistor that controls the current flowing through the OLED 130-2 (second light emitting element) according to the second gradation voltage applied to the gate.

As shown in FIG. 6, both the first transistor 121-1 and the first transistor 121-2 are arranged in the scanning line direction. That is, the source 121-1S of the first transistor 121-1, the gate 121-1G of the first transistor 121-1, the drain 121-1D of the first transistor 121-1, and the source 121 of the first transistor 121-2 -2S are arranged side by side along the scanning line 12 . The feeder line 116-1 connected to the source 121-1S of the first transistor 121-1 extends in the direction (Y direction) intersecting with the scanning line 12, and the source 121-2S of the first transistor 121-2. The power supply line 116-2 connected to the scanning line 12 also extends in a direction crossing the scanning line 12. FIG. In FIG. 6, reference numeral 19-1 denotes a wiring (first wiring) connecting the drain 121-1D of the first transistor 121-1 and the source of the fourth transistor 124-1, and reference numeral 19-2 denotes the first wiring. A wiring that connects the drain 121-2D of the transistor 121-2 and the source of the fourth transistor 124-2. As is clear from FIG. 6, the wiring 19-1 is provided in the direction (Y direction) intersecting the scanning lines 12, and similarly, the wiring 19-2 is also provided in the direction intersecting the scanning lines 12. ing. As shown in FIG. 6, in this embodiment, the feeder line 116-1 is provided side by side with the wiring 19-1, and the feeder line 116-2 is provided side by side with the wiring 19-2. As is clear from FIG. 6, the feeder line 116-1 is longer than the wiring 19-1, and the feeder line 116-2 is longer than the wiring 19-2.

As shown in FIG. 7, a substrate 140 on which a circuit portion is formed includes a first region A01 of a first conductivity type (indicated as P+ in FIG. 7) and a second conductivity type (indicated as N+ in FIG. 7). A second area A02 and a third area A03 are provided. A source 121-S and a drain 121-1D of the first transistor 121-1, a source 121-2S and a drain 121-2D of the first transistor 121-2 are formed in the first region A01. The second region A02 is a substrate contact and is supplied with the aforementioned substrate potential Vel. The third region A03 is an insulating region formed by STI (Shallow Trench Isolation) for element isolation.

As shown in FIG. 7, a first metal layer M01, a capacitive metal layer MC, a second metal layer M02 to a fifth metal layer M05 are arranged on the substrate side (substrate 140 side) of the light emitting layer in which the light emitting portion is formed. formed. The first metal layer M01, the third metal layer M03 and the fourth metal layer M04 are wiring layers in which various wirings are formed. In this embodiment, the feeder lines 116-1 and 116-2 and the wirings 19-1 and 19-2 are formed in the first metal layer M01. The power supply line 116-1 is connected to the substrate contact (second area A02) through a contact plug (relay electrode contact plug 150-1). Although not shown in detail in FIG. 7, the feed line 116-2 is also connected to another substrate contact. Capacitive metal layer MC forms capacitor 132-1 and capacitor 132-2 together with first metal layer M01.

As shown in FIG. 7, the feed line 116-1 is connected to the source 121-1S of the first transistor 121-1 through the relay electrode 152-1, and the feed line 116-2 connects the relay electrode 152-2. 121-2S of the first transistor 121-2. The wiring 19-1 is connected to the drain 121-1D of the first transistor 121-1 via the relay electrode 154-1, and the wiring 19-2 is connected to the first transistor 121-2 via the relay electrode 154-2. is connected to the drain 121-2D of the .

Further, the feeder line 116-1 is connected to the second metal layer M02 provided closer to the light emitting layer than the first metal layer through the relay electrode 160-1. The feed line 116-2 is also connected to the second metal layer M02 via the relay electrode 160-2. The second metal layer M02 is connected to feeder lines 164-1 and 164-2 provided on the third metal layer M03 via relay electrodes 162-1 and 162-2, respectively. The feeder line 164-1 is connected to the feeder line 168-1 provided on the fourth metal layer M04 through the relay electrode 166-1, and the feeder line 164-2 is connected through the relay electrode 166-2. , are connected to the feed line 168-2 provided on the fourth metal layer M04.

In this embodiment, the power supply line 116-2 and the second metal layer act as a shield to prevent the voltage fluctuation of the drain 121-1D of the first transistor 121-1 from affecting the gate voltage of the first transistor 121-2. Fulfill. Therefore, even if the first transistor 121-1 and the first transistor 121-2 are arranged in the scanning line direction as shown in FIG. 6, no crosstalk occurs. In this embodiment, the length of the feeder line 116-2 is made longer than the length of the wiring 19-1 in order to enhance the effect of the shield.

As described above, according to the present embodiment, it is possible to arrange the driving transistors included in the pixel circuit 110 in the scanning line direction while avoiding the occurrence of crosstalk. Since the driving transistors included in the pixel circuit 110 can be arranged in the scanning line direction, the channel length direction of the driving transistors can be increased, and variations in the driving transistors can be reduced. In addition, in the present embodiment, since contact plugs to the source of the drive transistor and the substrate contact are used, layout efficiency is improved.

<B: Second Embodiment>
FIG. 8 is a circuit diagram showing the configuration of a pixel circuit 110' of an electro-optical device according to the second embodiment of the invention. As is clear from comparing FIG. 4 and FIG. 8, the configuration of the pixel circuit 110' differs from the configuration of the pixel circuit 110 in the following three points. First, it does not have the third transistor 123 . Second, the drain of the first transistor 121 is connected to the anode 130a of the OLED 130, and the fourth transistor 124 is provided between the source of the transistor 121 and the feed line 116. FIG. That is, the drain of the fourth transistor 124 is connected to the source of the first transistor 121 and the source of the fourth transistor 124 is connected to the feed line 116 . Thirdly, in addition to the capacitor 132 , it has a capacitor 133 that functions as a holding capacitor for holding the gate voltage of the first transistor 121 .

FIG. 9 is a perspective view showing a planar structure of each circuit portion of the first pixel circuit 110'-1 and the second pixel circuit 110'-2 arranged in the scanning line direction. As shown in FIG. 9, in the electro-optical device of this embodiment, the fourth transistor 124-1 and the first transistor 121-1 are arranged side by side in the scanning line direction. The transistors 121-2 are also arranged side by side in the scanning line direction. A feeder line 116-1 connected to the source of the fourth transistor 124-1 extends in a direction intersecting with the scanning line in the same manner as the feeder line 116-1 in the first embodiment, and is shown in FIG. Although omitted, it is connected to the aforementioned second area A02. Similarly, the feeder line 116-2 connected to the source of the fourth transistor 124-2 also extends in the direction intersecting the scanning line, similar to the feeder line 116-2 in the first embodiment, and is the second region described above. It is connected to A02.

Also in this aspect, the power supply line 116-2, which is a fixed potential line, is provided between the drain of the first transistor 121-1 and the source of the first transistor 121-2. It acts as a shield to prevent the fluctuation of the drain voltage of the transistor 121-1 from affecting the two voltages of the first transistor 121-2. Also according to the embodiment, it is possible to arrange the driving transistors included in the pixel circuit 110' in the scanning line direction while avoiding the occurrence of crosstalk. Since the driving transistors included in the pixel circuit 110' can be arranged in the scanning line direction, the channel length direction of the driving transistors can be increased, and the variation of the driving transistors can be reduced.

<C. Variation>
Although one embodiment of the present invention has been described above, the following modifications may be added to this embodiment.
(1) In the first embodiment described above, the power supply functioning as a fixed potential line serves as a shield to prevent fluctuations in the drain voltage of the first transistor 121-1 from affecting the gate voltage of the first transistor 121-2. A wire 116-2 was connected to the source of the first transistor 121-2. However, connection of the fixed potential line to the source of the first transistor 121-2 is not always essential. If a fixed potential line extending in a direction crossing the scanning line 12 is provided between the drain of the first transistor 121-1 and the source of the first transistor 121-2, the source of the first transistor 121-2 is connected to the fixed potential line. This is because it is possible to prevent fluctuations in the drain voltage of the first transistor 121-1 from affecting the gate voltage of the first transistor 121-2 regardless of whether or not the first transistor 121-1 is connected to the . When the fixed potential line is not connected to the source of the first transistor 121-2, a potential different from the potential Vel may be applied to the fixed potential line. In this case, the fixed potential line is connected to the second region of the substrate 140. do not have to. Similarly, connection of the fixed potential line to the source of the fourth transistor 124 is not essential in the second embodiment.

(2) In the first embodiment, one pixel circuit emitting red light, one pixel circuit emitting green light, and two pixel circuits emitting blue light form one dot of a color image. One of the two pixel circuits emitting blue light may emit light in a color other than blue (for example, yellow). Alternatively, a single-color display panel may be formed by setting the emission color of four pixel circuits forming one pixel to be the same color (for example, red). In short, a first pixel circuit and a second pixel circuit each having a light-emitting portion laid out in a square and a circuit portion laid out in the same square as the light-emitting portion are provided along the scanning line, and the first pixel circuit and the driving transistor of the second pixel circuit are arranged along the scanning line, and a fixed potential line extending in a direction intersecting the scanning line is provided between the drain of the former and the source of the latter. I wish I had.

<D. Application example>
The electro-optical device according to the above-described embodiments can be applied to various electronic devices, and is particularly suitable for electronic devices that are required to display high-definition images of 2K2K or higher and that are required to be small. be. An electronic device according to the present invention will be described below.

FIG. 10 is a perspective view showing the appearance of a head-mounted display 300 as an electronic device employing the electro-optical device of the invention. As shown in FIG. 11, head mounted display 300 includes temple 310, bridge 320, projection optical system 301L, and projection optical system 301R. In FIG. 10, an electro-optical device (not shown) for the left eye is provided behind the projection optical system 301L, and an electro-optical device (not shown) for the right eye is provided behind the projection optical system 301R. be done.

FIG. 11 is a perspective view of a portable personal computer 400 employing the electro-optical device 1 according to the invention. A personal computer 400 includes an electro-optical device 1 that displays various images, and a main body 403 provided with a power switch 401 and a keyboard 402 . Electronic devices to which the electro-optical device 1 according to the present invention is applied include, in addition to the devices illustrated in FIGS. electronic devices that Furthermore, it can be applied as a display unit provided in electronic devices such as mobile phones, smart phones, personal digital assistants (PDA: Personal Digital Assistants), car navigation devices, and in-vehicle displays (instrument panels).

REFERENCE SIGNS LIST 1 electro-optical device 10 display panel 3 control circuit 4 scanning line driving circuit 5 data line driving circuit 12 scanning lines 14 data lines 16, 17, 61, 62, 63, 64, 116... Feeder line 118... Common electrode 15, 18, 20... Signal line 19... Wiring 31... Voltage generation circuit 41, 44, 46, 50, 132... Capacitance 34, 42... Transmission gate, Reference Signs List 43, 45, 121, 122, 123, 124, 125 Transistor 70 Data signal supply circuit 82 Case 84 FPC board 86 Terminal 100 Display section 112 Display area 110 Pixel circuit , 110-1... first pixel circuit, 110-2... second pixel circuit, 130... OLED, 130a... anode, SW... switch section, DM... demultiplexer.

Claims (7)

a silicon substrate;
a first light emitting element provided corresponding to the scanning line and emitting light with luminance corresponding to the supplied current;
a first pixel circuit having a first driving transistor for controlling a current supplied to the first light emitting element according to a first gradation voltage;
a second pixel circuit adjacent to the first pixel circuit in the direction of the scanning line, the second light emitting element emitting light with luminance corresponding to the supplied current; a second pixel circuit having a second driving transistor controlled according to the two-level voltage;
a fixed potential line provided with a fixed potential and provided in a direction intersecting with the scanning line;
the source of the first drive transistor, the gate of the first drive transistor, the drain of the first drive transistor, and the source of the second drive transistor are arranged side by side along the scan line;
the fixed potential line is provided between the drain of the first drive transistor and the source of the second drive transistor;
the fixed potential line is electrically connected to a first region where the source of the second drive transistor is provided;
the fixed potential line is electrically connected to a second region provided for supplying the fixed potential, which is a substrate potential, to the silicon substrate;
The first region and the second region are provided on the silicon substrate,
The electro-optical device, wherein the first area and the second area are arranged so as to overlap with the fixed potential line in plan view. 2. The electro-optical device according to claim 1, wherein a first conductivity type, which is the conductivity type of the first region, is a conductivity type different from a second conductivity type, which is the conductivity type of the second region. a first wiring connected to the drain of the first driving transistor and extending in a direction intersecting the scanning line;
The fixed potential line is provided in parallel with the first wiring, and the fixed potential line is longer than the first wiring,
3. The electro-optical device according to claim 2, wherein: a light-emitting layer in which the first light-emitting element and the second light-emitting element are formed;
a first metal layer provided closer to the silicon substrate than the light emitting layer, the first metal layer forming the first wiring and the fixed potential line;
a second metal layer provided closer to the light emitting layer than the first metal layer;
a relay electrode connecting the fixed potential line and the second metal layer;
4. The electro-optical device according to claim 3, comprising: 5. The electro-optical device according to claim 1, wherein the fixed potential line is connected to the source of the second drive transistor. A light emission control transistor for controlling on or off of current flowing from the second drive transistor to the second light emitting element, the drain being connected to the source of the second drive transistor and the source being connected to the fixed potential line. 5. The electro-optical device according to any one of claims 1 to 4, further comprising a light emission control transistor. An electronic apparatus comprising the electro-optical device according to any one of claims 1 to 6.

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