CN113508430B

CN113508430B - Pixel circuit, display substrate and display device

Info

Publication number: CN113508430B
Application number: CN202080000102.7A
Authority: CN
Inventors: 黄耀; 邱远游; 黄炜赟; 肖星亮
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Priority date: 2020-01-23
Filing date: 2020-01-23
Publication date: 2023-10-20
Anticipated expiration: 2040-01-23
Also published as: WO2021147083A1; CN113508430A

Abstract

A pixel circuit (100), a display substrate (10) and a display device (20), the pixel circuit (100) including a first drive circuit (101), a second drive circuit (102), a data write circuit (103) and a signal storage circuit (104); the data write circuit (103) is configured to receive a data signal; the first driving circuit (101) is connected with the data writing circuit (103), and is configured to receive a data signal from the data writing circuit (103) and allow the data signal to be written to a control end of the first driving circuit (101); the control terminal of the second drive circuit (102) is configured to receive a data signal written to the control terminal of the first drive circuit (101); the signal storage circuit (104) is configured to store, at a control terminal of the first drive circuit (101), a data signal written to the control terminal of the first drive circuit (101); the first end of the first driving circuit (101) and the first end of the second driving circuit (102) are both configured to receive a first power supply voltage from a first power supply voltage end (VDD), and the second end of the first driving circuit (101) and the second end of the second driving circuit (102) are both configured to be electrically connected to the first end of the light emitting element (116); the first driving circuit (101) and the second driving circuit (102) are configured to control a driving current flowing through the first driving circuit (101) and the second driving circuit (102) from a first power supply voltage terminal (VDD) to the light emitting element (116) for driving the light emitting element (116), respectively, based on the data signal stored in the signal storage circuit (104) and the received first power supply voltage; the brightness of the light emitting element (116) electrically connected to the pixel circuit (100) can be enhanced.

Description

Pixel circuit, display substrate and display device

Technical Field

Embodiments of the present disclosure relate to a pixel circuit, a display substrate, and a display device.

Background

The organic light emitting diode (Organic Light Emitting Diode, OLED) display device has the characteristics of wide viewing angle, high contrast ratio, high response speed and the like. And, the organic light emitting diode display device has advantages of higher light emitting luminance, lower driving voltage, and the like, compared to the inorganic light emitting display device. Due to the above features and advantages, organic Light Emitting Diode (OLED) display devices are receiving attention and can be applied to devices having a display function such as mobile phones, displays, notebook computers, digital cameras, instruments, and the like.

Disclosure of Invention

At least one embodiment of the present disclosure provides a pixel circuit including: the data writing circuit comprises a first driving circuit, a second driving circuit, a data writing circuit and a signal storage circuit. The data write circuit is configured to receive a data signal; the first driving circuit is connected with the data writing circuit and is configured to receive the data signal from the data writing circuit and allow the data signal to be written to a control end of the first driving circuit; the control terminal of the second driving circuit is configured to receive the data signal written to the control terminal of the first driving circuit; the signal storage circuit is configured to store the data signal written to the control terminal of the first driving circuit at the control terminal of the first driving circuit; the first end of the first driving circuit and the first end of the second driving circuit are both configured to receive a first power supply voltage from a first power supply voltage end, and the second end of the first driving circuit and the second end of the second driving circuit are both configured to be electrically connected to the first end of the light emitting element; and the first driving circuit and the second driving circuit are configured to control a driving current flowing through the first driving circuit and the second driving circuit, respectively, from the first power supply voltage terminal to the light emitting element for driving the light emitting element, based on the data signal stored in the signal storage circuit and the received first power supply voltage.

For example, in at least one example of the pixel circuit, a control terminal of the first driving circuit and a control terminal of the second driving circuit are electrically connected to each other.

For example, in at least one example of the pixel circuit, the pixel circuit further includes a compensation connection circuit. The data writing circuit writes the data signal to a first end of the first driving circuit; and the compensation connection circuit is connected between the second end of the first driving circuit and the control end of the first driving circuit, and is configured to write a data signal written to the first end of the first driving circuit to the control end of the first driving circuit via the first driving circuit.

For example, in at least one example of the pixel circuit, the control terminal of the compensation connection circuit and the control terminal of the data write circuit are connected to the same scanning signal line.

For example, in at least one example of the pixel circuit, the pixel circuit further includes a first reset circuit. The first reset circuit is connected with the signal storage circuit; and the first reset circuit is configured to receive a first reset signal and write the first reset signal to the signal storage circuit to reset the signal storage circuit.

For example, in at least one example of the pixel circuit, the pixel circuit further includes a first control circuit and a second control circuit. The first control circuit is connected between a first end of the first driving circuit and the first power supply voltage end and is configured to control whether the first driving circuit is electrically connected with the first power supply end; and the second control circuit is connected between the first end of the second driving circuit and the first power supply voltage end and is configured to control whether the second driving circuit is electrically connected with the first power supply end.

For example, in at least one example of the pixel circuit, the control terminal of the first control circuit and the control terminal of the second control circuit are connected to the same light emission control line.

For example, in at least one example of the pixel circuit, the pixel circuit further includes a second reset circuit. The second reset circuit is configured to receive a second reset signal and write the second reset signal to the first end of the light emitting element to reset the first end of the light emitting element.

For example, in at least one example of the pixel circuit, the pixel circuit further includes a third control circuit and a fourth control circuit. The third control circuit is connected between the second end of the first driving circuit and the first end of the light-emitting element and is configured to control whether the first driving circuit is electrically connected with the first end of the light-emitting element; and the fourth control circuit is connected between the second end of the second driving circuit and the first end of the light emitting element and is configured to control whether the second driving circuit is electrically connected with the first end of the light emitting element.

For example, in at least one example of the pixel circuit, the control terminal of the third control circuit and the control terminal of the fourth control circuit are connected to the same light emission control line.

For example, in at least one example of the pixel circuit, the first driving circuit includes a first transistor, and the second driving circuit includes a second transistor; and a threshold voltage of the first transistor is equal to a threshold voltage of the second transistor.

At least one embodiment of the present disclosure also provides a display substrate including any one of the pixel circuits provided by at least one embodiment of the present disclosure.

For example, in at least one example of the display substrate, the at least one pixel circuit includes a plurality of pixel circuits; the display substrate is provided with a display area, and the display area comprises a first display area and a second display area; the first display area comprises a plurality of first pixel units which are arranged in an array manner, and the second display area comprises a plurality of second pixel units which are arranged in an array manner; the unit area distribution density of the plurality of first pixel units in the first display area is smaller than the unit area distribution density of the plurality of second pixel units in the second display area; each of the plurality of first pixel units includes the light emitting element; and the pixel circuits are electrically connected with the light emitting elements in a one-to-one correspondence.

For example, in at least one example of the display substrate, the first display region further includes a first sub-display region and a second sub-display region that do not overlap each other; the first sub-display area includes a first group of the plurality of first pixel units, and the second sub-display area includes a second group of the plurality of first pixel units, the first and second groups not overlapping each other; and pixel circuits connected with the light emitting elements of the second group of the plurality of first pixel units in one-to-one correspondence are arranged in the first sub-display area.

For example, in at least one example of the display substrate, the display substrate further includes a plurality of transparent traces. The transparent wirings electrically connect the light emitting elements of the second group of the first pixel units with the pixel circuits connected with the light emitting elements of the second group of the first pixel units in a one-to-one correspondence.

For example, in at least one example of the display substrate, the display substrate further has a peripheral region at least partially surrounding the display region, the plurality of pixel circuits being at least partially disposed in the peripheral region.

For example, in at least one example of the display substrate, the display substrate further includes a sensor. The sensor is disposed on a non-display side of the display substrate, overlaps the first display region in a normal direction of a display surface of the display substrate, and is configured to receive and process an optical signal passing through the first display region.

At least one embodiment of the present disclosure also provides a display device including any one of the pixel circuits or any one of the display substrates provided by at least one embodiment of the present disclosure.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure, not to limit the present disclosure.

FIG. 1A is a schematic cross-sectional view of a display substrate;

FIG. 1B is a schematic plan view of the display substrate shown in FIG. 1A;

FIG. 1C is a schematic view of a partial region of the display substrate shown in FIG. 1B;

FIG. 2A is a schematic diagram of a 7T1C pixel circuit;

FIG. 2B is a timing diagram of the driving of the 7T1C pixel circuit shown in FIG. 2A;

FIG. 3 is a schematic diagram of a pixel circuit provided by at least one embodiment of the present disclosure;

fig. 4A is an example of the pixel circuit shown in fig. 3;

fig. 4B is a driving timing chart of the pixel circuit shown in fig. 4A;

FIG. 5A is an exemplary block diagram of a display substrate provided by at least one embodiment of the present disclosure;

FIG. 5B is a schematic cross-sectional view of the display substrate shown in FIG. 5A;

FIG. 6 is a schematic plan view of an example of the display substrate shown in FIG. 5B;

FIG. 7A is a schematic view of a partial region of the first display region of the display substrate shown in FIG. 6;

FIG. 7B illustrates a schematic diagram of a first group of the plurality of first pixel cells shown in FIG. 7A;

FIG. 7C illustrates a schematic diagram of a second group of the plurality of first pixel cells shown in FIG. 7A;

FIG. 8A is a schematic view of a partial area of a second display area of the display substrate shown in FIG. 6;

fig. 8B illustrates an example of the first pixel unit illustrated in fig. 7A;

fig. 8C illustrates another example of the first pixel unit illustrated in fig. 7A;

FIG. 8D is a schematic diagram of the second pixel cell shown in FIG. 8A;

FIG. 8E shows a schematic diagram of the redundant pixel cell shown in FIG. 7A;

FIG. 9 is a schematic plan view of another example of the display substrate shown in FIG. 5B;

fig. 10 is a schematic plan view of still another example of the display substrate shown in fig. 5B; and

fig. 11 is an exemplary block diagram of a display device provided by at least one embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. It will be apparent that the described embodiments are some, but not all, embodiments of the invention. All other embodiments, which can be made by a person skilled in the art without creative efforts, based on the described embodiments of the present invention fall within the protection scope of the present invention.

Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The terms "first," "second," and the like, as used in this disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Likewise, the terms "a," "an," or "the" and similar terms do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed.

The inventors of the present disclosure noted that the current display substrate having an off-screen sensor (camera) has a low light emission luminance of a display region corresponding to the off-screen sensor (camera), thereby affecting the quality of an image displayed by the display substrate. An exemplary description is provided below in connection with fig. 1A, 1B, 2A, and 2B.

Fig. 1A is a schematic cross-sectional view of a display substrate 500, fig. 1B is a schematic plan view of the display substrate 500 shown in fig. 1A, and fig. 1C is a schematic view of a partial region 513 of the display substrate 500 shown in fig. 1B. The display substrate 500 shown in fig. 1B corresponds to the BB' line of the display substrate 10 shown in fig. 1A.

As shown in fig. 1A, the display substrate 500 includes a display layer 510 and a sensing layer 520, and the sensing layer 520 is disposed on a non-display side of the display substrate 500. As shown in fig. 1A to 1C, the display layer 510 includes a first display region 511 and a second display region 512; the first display region 511 includes a plurality of first light emitting elements 531 arranged in an array, and the second display region 512 includes a plurality of second light emitting elements 532 arranged in an array. For example, the plurality of first light emitting elements 531 and the plurality of second light emitting elements 532 have the same structure and performance characteristics.

As shown in fig. 1A, the sensing layer 520 includes a sensor 521, the sensor 521 is overlapped with the first display region 511 in a normal direction of a display surface of the display substrate 500, and is configured to receive and process an optical signal passing through the first display region 511.

As shown in fig. 1C, in order to reduce the shielding of the elements in the first display region 511 from the optical signal that is incident on the first display region 511 and transmitted toward the sensor 521, the unit area distribution density of the plurality of first light emitting elements 531 in the first display region 511 is smaller than the unit area distribution density of the plurality of second light emitting elements 532 in the second display region 512. However, this makes the effective light emitting area of the first display region 511 smaller than that of the second display region 512, and makes the difference in luminance between the image region corresponding to the first display region 511 and the image region corresponding to the second display region 512 relatively large in the image displayed on the display substrate 500.

For example, the display layer 510 further includes a plurality of first pixel circuits and a plurality of second pixel circuits (not shown in fig. 1A to 1C, see fig. 2A); the plurality of first pixel circuits are configured to drive the plurality of first light emitting elements 531 one by one, and the plurality of second pixel circuits are configured to drive the plurality of second light emitting elements 532 one by one. For example, the plurality of first pixel circuits and the plurality of second pixel circuits have the same circuit structure.

For example, in the case where a data signal (e.g., a data voltage) received by a plurality of first pixel circuits driving a plurality of first light emitting elements is equal to a data signal (e.g., a data voltage) received by a plurality of second pixel circuits driving a plurality of second light emitting elements, the light emission luminance of the plurality of first light emitting elements is smaller than the light emission luminance of the plurality of second light emitting elements, and thus the luminance of an image area corresponding to the first display area 511 in an image displayed on the display substrate may be lower than a predetermined luminance.

The circuit structures of the plurality of first pixel circuits and the plurality of second pixel circuits can be set according to actual application requirements. For example, each of the plurality of first pixel circuits and the plurality of second pixel circuits may be implemented as a 2T1C pixel circuit, a 3T1C pixel circuit, a 5T1C pixel circuit 7T1C pixel circuit, or other suitable pixel circuits. Note that the 2T1C pixel circuit is a pixel circuit including two transistors and one storage capacitor Cst, and the 7T1C pixel circuit is a pixel circuit including seven transistors and one storage capacitor Cst.

The display substrate 500 shown in fig. 1A and 1B is exemplarily described below with each of the plurality of first pixel circuits and the plurality of second pixel circuits implemented as a 7T1C pixel circuit 580.

Fig. 2A is a schematic diagram of a 7T1C pixel circuit 580. As shown in fig. 2A, the 7T1C pixel circuit 580 includes a first transistor CT1, a second transistor CT2, a third transistor CT3, a fourth transistor CT4, a fifth transistor CT5, a sixth transistor CT6, a seventh transistor CT7, and a storage capacitor Cst. For example, the first transistor CT1 to the seventh transistor CT7 are P-type transistors.

As shown in fig. 2A, a first terminal of the storage capacitor Cst is connected to a first power voltage terminal VDD to receive a first power voltage V1; the second end of the storage capacitor Cst is connected with the first node N1; the first end of the light emitting element EL is connected to the fourth node N4, and the second end of the light emitting element EL is connected to the second power supply voltage terminal VSS to receive the second power supply voltage V2; the control end of the first transistor CT1 is connected with a first node N1; a first end of the first transistor CT1 is connected to the second node N2, and a second end of the first transistor CT1 is connected to the third node N3; the first terminal of the second transistor CT2 is connected to the second node N2, and the second terminal of the second transistor CT2 is connected to the data signal terminal DAT to receive a data signal (e.g., a data voltage) Vdata; a first end of the third transistor CT3 is connected to the first node N1, and a second end of the third transistor CT3 is connected to the third node N3; the first end of the fourth transistor CT4 is connected to the first node N1; the second end of the fourth transistor CT4 is connected to the first reset signal end Init1, so as to receive the first reset signal Vinit1 provided by the first reset signal end Init1; a first terminal of the fifth transistor CT5 is connected to the first power voltage terminal VDD, and a first terminal of the fifth transistor CT5 is connected to the second node N2; a first end of the sixth transistor CT6 is connected to the fourth node N4; the second terminal of the sixth transistor CT6 is connected to the second reset signal terminal Init2 to receive the second reset signal Vinit2; the first terminal of the seventh transistor CT7 is connected to the third node N3, and the second terminal of the seventh transistor CT7 is connected to the fourth node N4. For example, the control terminal GAT1 of the second transistor CT2 and the control terminal GAT2 of the third transistor CT3 are both connected to the scan signal terminal GAT (not shown in the figure); the control terminal EM1 of the fifth transistor CT5 and the control terminal EM2 of the seventh transistor CT7 are both connected to the emission control terminal EM (not shown in the figure); the control terminal of the fourth transistor CT4 is configured as a first reset control terminal RST1; the control terminal of the sixth transistor CT6 is configured as the second reset control terminal RST2.

For convenience of description, fig. 2A also shows the first node N1, the second node N2, the third node N3, the fourth node N4, and the light emitting element EL.

Fig. 2B is a driving timing diagram of the 7T1C pixel circuit 580 shown in fig. 2A. As shown in fig. 2B, each driving cycle of the 7T1C pixel circuit 580 includes a first stage T1, a second stage T2, and a third stage T3.

As shown in fig. 2A and 2B, in the first stage t1, the first reset control terminal RST1 receives an active level, and the scan signal terminal GAT, the second reset control terminal RST2, and the emission control terminal EM each receive an inactive level; in this case, the fourth transistor CT4 is turned on, and the second, third, fifth, sixth, and seventh transistors CT2, CT3, CT5, CT6, and CT7 are turned off; the fourth transistor CT4 is configured to receive a first reset signal (e.g., a reset voltage) Vinit1 and write the first reset signal Vinit1 to the storage capacitor Cst to reset the storage capacitor Cst; the voltage at the first node N1 is Vinit1, and Vinit1 is, for example, a negative value. For example, after resetting the storage capacitor Cst, the first transistor CT1 is turned on.

As shown in fig. 2A and 2B, in the second phase t2, the scan signal terminal GAT and the second reset control terminal RST2 receive the active level, and the first reset control terminal RST1 and the light emission control terminal EM receive the inactive level; in this case, the first transistor CT 1-the third transistor CT3 and the sixth transistor CT6 are turned on, and the fourth transistor CT4, the fifth transistor CT5 and the seventh transistor CT7 are turned off; the second transistor CT2 receives the data signal Vdata, the data signal Vdata is written to the control terminal of the first transistor CT1 through the turned-on first transistor CT1 and the third transistor CT3, the storage capacitor Cst stores the data signal Vdata written to the control terminal of the first transistor CT1 at the control terminal of the first transistor CT1, and the voltage of the first node N1 is vdata+vth; the sixth transistor CT6 is configured to receive a second reset signal (e.g., a reset voltage) Vinit2, and write the second reset signal Vinit2 to the first terminal of the light emitting element EL to reset the first terminal of the light emitting element EL, and the voltage of the fourth node N4 is Vinit2, where Vinit2 is a negative value, for example.

As shown in fig. 2A and 2B, in the third stage t3, the light emission control terminal EM receives an active level, and the first reset control terminal RST1, the scan signal terminal GAT, and the second reset control terminal RST2 receive an inactive level; in this case, the first, fifth and seventh transistors CT1, CT5 and CT7 are turned on, and the second, third, fourth and sixth transistors CT2, CT3, CT4 and CT6 are turned off; the first transistor CT1 is configured to control a driving current flowing through the first transistor CT1 and from the first power voltage terminal VDD to the light emitting element EL for driving the light emitting element EL based on a data signal (e.g., a data voltage) Vdata stored in the storage capacitor Cst and the received first power voltage V1; the voltage of the first node N1 is Vdata+Vth, and the voltage of the second node N2 is VDD; the driving current Id can be expressed by the following formula.

Here, k=μ×cox×w/L; μ is mobility of carriers in the first transistor CT1, cox is capacitance of a gate oxide layer of the first transistor CT1, W/L is width to length ratio of a channel of the first transistor CT1, vth is threshold voltage of the first transistor CT1, vth is gate-source voltage of the first transistor CT1, vg is gate voltage of the first transistor CT1, and Vs is source voltage of the first transistor CT 1.

As can be seen from the above formula, the driving current Id generated by the first transistor CT1 is independent of the threshold voltage of the first transistor CT1, and thus the 7T1C pixel circuit 580 shown in fig. 2A and 2B has a threshold compensation function.

At least one embodiment of the present disclosure provides a pixel circuit, a display substrate, and a display device. The pixel circuit includes: the data writing circuit comprises a first driving circuit, a second driving circuit, a data writing circuit and a signal storage circuit. The data write circuit is configured to receive a data signal; the first driving circuit is connected with the data writing circuit and is configured to receive the data signal from the data writing circuit and allow the data signal to be written into the control end of the first driving circuit; the control end of the second driving circuit is configured to receive the data signal written to the control end of the first driving circuit; the signal storage circuit is configured to store a data signal written to the control terminal of the first driving circuit at the control terminal of the first driving circuit; the first end of the first driving circuit and the first end of the second driving circuit are configured to receive the first power supply voltage from the first power supply voltage end, and the second end of the first driving circuit and the second end of the second driving circuit are configured to be electrically connected to the first end of the light emitting element; and the first driving circuit and the second driving circuit are configured to control a driving current flowing through the first driving circuit and the second driving circuit, respectively, from the first power supply voltage terminal to the light emitting element for driving the light emitting element, based on the data signal stored in the signal storage circuit and the received first power supply voltage.

For example, by providing a second driving circuit in parallel with the first driving circuit, the pixel circuit can increase the value of the driving current flowing through the light emitting element electrically connected to the pixel circuit and the luminance of the light emitting element electrically connected to the pixel circuit.

The pixel circuit provided in accordance with at least one embodiment of the present disclosure is described below by way of several examples or embodiments, and as described below, different features of these specific examples or embodiments may be combined with one another without contradiction to one another, resulting in new examples or embodiments, which are also within the scope of the present disclosure.

Fig. 3 is a schematic diagram of a pixel circuit 100 provided in at least one embodiment of the present disclosure. As shown in fig. 3, the pixel circuit 100 includes a first driving circuit 101, a second driving circuit 102, a data writing circuit 103, and a signal storage circuit 104.

As shown in fig. 3, the data write circuit 103 is configured to receive a data signal, for example, the data write circuit 103 is configured to be connected to the data signal terminal DAT to receive the data signal provided by the data signal terminal DAT. For example, the data signal is a voltage signal.

As shown in fig. 3, the first driving circuit 101 is connected to the data writing circuit 103, configured to receive a data signal from the data writing circuit 103 and allow the data signal to be written to a control terminal of the first driving circuit 101; the control terminal of the second driving circuit 102 is configured to receive a data signal written to the control terminal of the first driving circuit 101;

as shown in fig. 3, the signal storage circuit 104 is configured to store a data signal written to the control terminal of the first driving circuit 101 at the control terminal of the first driving circuit 101. For example, the signal storage circuit 104 is connected between the first power supply voltage terminal VDD and the control terminal of the first driving circuit 101.

As shown in fig. 3, the first terminal of the first driving circuit 101 and the first terminal of the second driving circuit 102 are each configured to receive the first power supply voltage from the first power supply voltage terminal VDD, and the second terminal of the first driving circuit 101 and the second terminal of the second driving circuit 102 are each configured to be electrically connected to the first terminal of the light emitting element 116; the first driving circuit 101 and the second driving circuit 102 are configured to control a driving current flowing through the first driving circuit 101 and the second driving circuit 102, respectively, from the first power voltage terminal VDD to the light emitting element 116 for driving the light emitting element 116, based on the data signal stored in the signal storage circuit 104 and the received first power voltage.

For example, by providing the second driving circuit 102 in parallel with the first driving circuit 101, in the light emission stage of the pixel circuit 100, the first driving circuit 101 and the second driving circuit 102 generate driving currents flowing through the first driving circuit 101 and the second driving circuit 102 from the first power supply voltage terminal VDD to the light emitting element 116 for driving the light emitting element 116, respectively, whereby the pixel circuit 100 can increase the value of the driving current flowing through the light emitting element 116 electrically connected to the pixel circuit 100 and the luminance of the light emitting element 116 electrically connected to the pixel circuit 100.

For example, at least one embodiment of the present disclosure may increase the brightness of the light emitting element 116 electrically connected to the pixel circuit 100 by connecting a simple first driving circuit 101 in parallel with the pixel circuit 100 shown in fig. 2A, thereby increasing the brightness of the light emitting element 116 electrically connected to the pixel circuit 100 while making the structure of the pixel circuit 100 as simple as possible.

For example, as shown in fig. 3, the control terminal of the first driving circuit 101 and the control terminal of the second driving circuit 102 are electrically connected to each other, thereby enabling the control terminal of the second driving circuit 102 to receive a data signal written to the control terminal of the first driving circuit 101. For example, the control terminal of the first driving circuit 101 and the control terminal of the second driving circuit 102 are directly connected.

For example, as shown in fig. 3, the pixel circuit 100 further includes a compensation connection circuit 105. For example, the data write circuit 103 writes a data signal to a first end of the first drive circuit 101; the compensation connection circuit 105 is connected between the second terminal of the first driving circuit 101 and the control terminal of the first driving circuit 101, and is configured to write a data signal written to the first terminal of the first driving circuit 101 to the control terminal of the first driving circuit 101 via the first driving circuit 101.

For example, by causing the compensation connection circuit 105 to be configured to write a data signal written to the first end of the first driving circuit 101 to the control end of the first driving circuit 101 via the first driving circuit 101, the threshold characteristic of the first driving circuit 101 can be written to the control end of the first driving circuit 101 and stored in the signal storage circuit 104, whereby adverse effects of the threshold characteristic of the first driving circuit 101 on the driving current generated by the first driving circuit 101, which flows through the first driving circuit 101 and from the first power supply voltage end VDD to the light emitting element 116, for driving the light emitting element 116 can be eliminated, that is, by providing the compensation connection circuit 105, the pixel circuit 100 provided by at least one embodiment of the present disclosure can be made to have a threshold compensation function.

For example, the threshold characteristic of the first driving circuit 101 and the threshold characteristic of the second driving circuit 102 are similar, thereby making it possible for the compensation connection circuit 105 to also mitigate adverse effects of the threshold characteristic of the second driving circuit 102 on the driving current generated by the second driving circuit 102, which flows through the second driving circuit 102 and from the first power supply voltage terminal VDD to the light emitting element 116. For example, the threshold characteristic of the first driving circuit 101 and the threshold characteristic of the second driving circuit 102 being similar means that the ratio of the difference between the threshold of the first driving circuit 101 and the threshold of the second driving circuit 102 to the threshold of the first driving circuit 101 is less than 10% (e.g., less than 5%, 3%, or 1%).

For example, the first driving circuit 101 and the second driving circuit 102 have the same threshold characteristic; in this case, the compensation connection circuit 105 may further eliminate an adverse effect of the threshold characteristic of the second driving circuit 102 on the driving current generated by the second driving circuit 102, flowing through the second driving circuit 102 and from the first power supply voltage terminal VDD to the light emitting element 116, thereby further improving the threshold compensation function of the pixel circuit 100 provided in at least one embodiment of the present disclosure.

For example, as shown in fig. 3, the control terminal GAT1 of the data writing circuit 103 and the control terminal GAT2 of the compensation connection circuit 105 are configured to receive the same scanning signal, thereby enabling the data signal written to the first terminal of the first driving circuit 101 to be written to the control terminal of the first driving circuit 101 via turning on the first driving circuit 101 and the compensation connection circuit 105 in the data writing stage of the pixel circuit 100, which is also referred to as the data writing and compensation stage of the pixel circuit 100. For example, the control terminal of the compensation connection circuit 105 and the control terminal of the data writing circuit 103 are connected to the same scan signal terminal GAT or scan signal line (not shown in the figure), whereby the structure of the display substrate including the pixel circuit 100 can be simplified.

For example, as shown in fig. 3, the pixel circuit 100 further includes a first reset circuit 106. The first reset circuit 106 is connected with the signal storage circuit 104; the first reset circuit 106 is configured to receive the first reset signal and write the first reset signal to the signal storage circuit 104 to reset the signal storage circuit 104. For example, the first reset signal may be a first reset voltage. For example, the first reset voltage is negative (e.g., -3V) such that the first drive circuit 101 is still capable of turning on after resetting the memory circuit in the presence of process variations. For example, the first reset circuit 106 may reset the signal storage circuit 104 in a reset phase of the pixel circuit 100.

For example, a first end of the first reset circuit 106 is connected to the signal storage circuit 104; a second end of the first reset circuit 106 is connected to the first reset signal end Init1, so as to receive the first reset signal provided by the first reset signal end Init 1; the control terminal of the first reset circuit 106 is configured as a first reset control terminal RST1.

For example, as shown in fig. 3, the pixel circuit 100 further includes a first control circuit 111; the first control circuit 111 is connected between the first terminal of the first driving circuit 101 and the first power voltage terminal VDD, and is configured to control whether the first driving circuit 101 is electrically connected to the first power voltage terminal VDD. For example, by providing the first control circuit 111, the first power supply voltage supplied from the first power supply voltage terminal VDD can be prevented from adversely affecting the data signal written to the first terminal of the first driving circuit 101 in the data writing and compensating stage.

For example, as shown in fig. 3, the pixel circuit 100 further includes a second reset circuit 115. The second reset circuit 115 is configured to receive a second reset signal and write the second reset signal to the first terminal of the light emitting element 116 to reset the first terminal of the light emitting element 116. For example, a first terminal of the second reset circuit 115 is connected to a first terminal of the light emitting element 116; a second end of the second reset circuit 115 is connected to the second reset signal end Init2, so as to receive a second reset signal provided by the second reset signal end Init 2; the control terminal of the second reset circuit 115 is configured as a second reset control terminal RST2.

For example, the second reset circuit 115 is configured to eliminate charges that may remain on the light emitting element 116. For example, the first end of the light emitting element 116 may be reset before the light emitting stage to improve the accuracy of the brightness of the light emitting element 116 and the contrast of the display substrate including the pixel circuit 100. For example, the first terminal of the light emitting element 116 may be reset in a data writing and compensation phase or a reset phase of the pixel circuit 100.

For example, the second reset signal may be a second reset voltage. For example, the second terminal of the light emitting element 116 is connected to the second power voltage terminal VSS to receive the second power voltage provided by the second power voltage terminal VSS. For example, the second reset voltage is equal to the second power supply voltage to avoid the light emitting element 116 from emitting light during the reset of the first terminal of the light emitting element 116. For example, the second reset voltage and the second power supply voltage are both negative values (e.g., -3V). For example, the second power supply voltage is smaller than the first power supply voltage.

For example, the pixel circuit 100 further includes a third control circuit 113. The third control circuit 113 is connected between the second end of the first driving circuit 101 and the first end of the light emitting element 116, and is configured to control whether the first driving circuit 101 is electrically connected to the first end of the light emitting element 116. For example, by providing the third control circuit 113, the voltage at the second terminal of the first driving circuit 101 and the voltage at the first terminal of the light emitting element 116 can be prevented from interfering with each other in the data writing and compensating stage. For example, by providing the third control circuit 113, it is possible to avoid the voltage of the second terminal of the first driving circuit 101 from adversely affecting the reset of the first terminal of the light emitting element 116 and to avoid the light emitting element 116 from emitting light in the data writing and compensating stage. Also for example, by providing the third control circuit 113, the voltage of the first terminal of the light emitting element 116 can be prevented from adversely affecting the voltage of the second terminal of the first driving circuit 101 and the threshold compensation in the data writing and compensating stage.

For example, as shown in fig. 3, the pixel circuit 100 further includes a second control circuit 112; the second control circuit 112 is connected between the first terminal of the second driving circuit 102 and the first power voltage terminal VDD, and is configured to control whether the second driving circuit 102 is electrically connected to the first power voltage terminal VDD. For example, by providing the second control circuit 112, the second driving circuit 102 can be prevented from driving the light emitting element 116 to emit light at a stage other than the light emitting stage.

For example, as shown in fig. 3, the pixel circuit 100 further includes a fourth control circuit 114; the fourth control circuit 114 is connected between the second end of the second driving circuit 102 and the first end of the light emitting element 116, and is configured to control whether the second driving circuit 102 is electrically connected with the first end of the light emitting element 116. For example, by providing the fourth control circuit 114, the driving current generated by the first driving circuit 101 and flowing from the first power supply voltage terminal VDD to the light emitting element 116 and the driving current generated by the second driving circuit 102 and flowing from the first power supply voltage terminal VDD to the light emitting element 116 can be made similar in electrical environment.

For example, the control terminal EM1 of the first control circuit 111, the control terminal EM2 of the second control circuit 112, the control terminal EM3 of the third control circuit 113, and the control terminal EM4 of the fourth control circuit 114 are configured to receive the same light emission control signal, thereby enabling the first control circuit 111, the second control circuit 112, the third control circuit 113, and the fourth control circuit 114 to be simultaneously turned on and enabling the first driving circuit 101 and the second driving circuit 102 to synchronously drive the light emitting element 116.

For example, the control terminal EM1 of the first control circuit 111, the control terminal EM2 of the second control circuit 112, the control terminal EM3 of the third control circuit 113, and the control terminal EM4 of the fourth control circuit 114 are connected to the same light emission control terminal EM or light emission control line (not shown in the drawings), whereby the structure of the display substrate including the pixel circuit 100 can be simplified.

It should be noted that, the pixel circuit 100 provided in at least one embodiment of the present disclosure is not limited to include the second control circuit 112 and the fourth control circuit 114 at the same time; the pixel circuit 100 provided in at least one embodiment of the present disclosure may further include only one of the second control circuit 112 and the fourth control circuit 114 according to actual application requirements.

It should be noted that, the embodiment shown in fig. 3 illustrates at least one embodiment of the present disclosure by taking the pixel circuit having the compensation function, the reset function and the light emission control function as an example, but at least one embodiment of the present disclosure is not limited thereto, for example, the pixel circuit provided by at least one embodiment of the present disclosure may not have the three functions described above, or may have part of the functions (i.e., less than three functions) described above, as long as the pixel circuit has the first driving circuit and the second driving circuit connected in parallel, according to practical application requirements.

Fig. 4A is an example of the pixel circuit 100 shown in fig. 3, and fig. 4B is a driving timing chart of the pixel circuit 100 shown in fig. 4A. The pixel circuit 100 shown in fig. 3 is exemplarily described below with reference to fig. 4A and 4B.

As shown in fig. 3 and 4A, the first driving circuit 101 includes a first transistor T1, a control terminal of the first transistor T1 is connected to a first node N1, a first terminal of the first transistor T1 is connected to a second node N2, and a second terminal of the first transistor T1 is connected to a third node N3; the second driving circuit 102 includes a second transistor T2, and a control terminal of the second transistor T2 is connected to the first node N1.

For example, the threshold voltage of the first transistor T1 and the threshold voltage of the second transistor T2 are equal. For example, the width and length of the channel of the first transistor T1 are substantially the same as the width and length of the channel of the second transistor T2, respectively. For example, the aspect ratio of the channel of the first transistor T1 (i.e., the ratio of the width to the length of the channel) is substantially the same as the aspect ratio of the channel of the second transistor T2; the capacitance of the gate oxide layer of the first transistor T1 is substantially the same as the capacitance of the gate oxide layer of the second transistor T2; the mobility of the carriers in the first transistor T1 is substantially the same as the mobility of the carriers in the second transistor T2. In some examples, the values of the a parameter and the B parameter being substantially equal means: the ratio of the difference between the value of the a parameter and the value of the B parameter to the value of the a parameter is less than 3% (e.g., less than 1%). For example, the first transistor T1 and the second transistor T2 may be prepared in a symmetrical manner.

As shown in fig. 3 and 4A, the data writing circuit 103 includes a third transistor T3, and the signal storage circuit 104 includes a storage capacitor Cst; the first end of the third transistor T3 is connected to the second node N2; the second end of the third transistor T3 is connected to the data signal end DAT for receiving the data signal Vdata provided by the data signal end DAT; the first terminal of the storage capacitor Cst is connected to the first power voltage terminal VDD, and the second terminal of the storage capacitor Cst is connected to the first node N1.

As shown in fig. 3 and 4A, the compensation connection circuit 105 includes a fourth transistor T4; the first terminal of the fourth transistor T4 is connected to the first node N1, and the second terminal of the fourth transistor T4 is connected to the third node N3.

For example, the control terminal GAT1 of the third transistor T3 and the control terminal GAT2 of the fourth transistor T4 are both connected to the same scan signal terminal GAT or the same scan signal line (not shown in the figure).

For example, as shown in fig. 3 and 4A, the light emitting element 116 may be an organic light emitting element EL, which may be, for example, an organic light emitting diode, but the embodiment of the present disclosure is not limited thereto. For example, the light emitting element 116 may be an inorganic light emitting element.

As shown in fig. 3 and 4A, the first reset circuit 106 includes a fifth transistor T5, the control terminal of the fifth transistor T5 is configured as a first reset control terminal RST1, the first terminal of the fifth transistor T5 is connected to the first node N1, and the second terminal of the fifth transistor T5 is connected to the first reset signal terminal Init1 to receive the first reset signal Vinit1 provided by the first reset signal terminal Init1;

as shown in fig. 3 and 4A, the first control circuit 111 includes a sixth transistor T6, and the second control circuit 112 includes a seventh transistor T7; a first terminal of the sixth transistor T6 is connected to the first power voltage terminal VDD to receive the first power voltage, and a second terminal of the sixth transistor T6 is connected to the second node N2; the first terminal of the seventh transistor T7 is connected to the first power voltage terminal VDD to receive the first power voltage, and the second terminal of the seventh transistor T7 is connected to the first terminal of the second transistor T2.

As shown in fig. 3 and 4A, the second reset circuit 115 includes an eighth transistor T8, the third control circuit 113 includes a ninth transistor T9, and the fourth control circuit 114 includes a tenth transistor T10; the control terminal of the eighth transistor T8 is configured as a second reset control terminal RST2, the first terminal of the eighth transistor T8 is connected to the fourth node N4, and the second terminal of the eighth transistor T8 is connected to the second reset signal terminal Init2 to receive the second reset signal Vinit2 provided by the second reset signal terminal Init2; a first terminal of the ninth transistor T9 is connected to the third node N3, and a second terminal of the ninth transistor T9 is connected to the fourth node N4; a first terminal of the tenth transistor T10 is connected to the second terminal of the second transistor T2, and a second terminal of the tenth transistor T10 is connected to the fourth node N4; the first terminal of the organic light emitting element EL is connected to the fourth node N4, and the second terminal of the organic light emitting element EL is connected to the second power voltage terminal VSS to receive the second power voltage.

For example, the control terminal EM1 of the sixth transistor T6, the control terminal EM2 of the seventh transistor T7, the control terminal EM3 of the ninth transistor T9, and the control terminal EM4 of the tenth transistor T10 are connected to the same emission control terminal EM or the same emission control line (not shown in the figure).

For example, the first transistor T1 to the tenth transistor T10 may be P-type transistors (e.g., PMOS transistors, i.e., n-type substrate, P-channel, MOS transistors carrying current by the flow of holes), in which case the first transistor T1 to the tenth transistor T10 are turned off when receiving a high level (first level), turned on when receiving a low level (second level, the second level being smaller than the first level), i.e., the high level (first level) is an inactive level (i.e., a level that causes the transistor to be turned off), and the low level (second level) is an active level (i.e., a level that causes the transistor to be turned on). It should be noted that, the first transistor T1 to the tenth transistor T10 are not limited to be implemented as P-type transistors, and one or more of the first transistor T1 to the tenth transistor T10 may be implemented as N-type transistors according to practical application requirements.

It should be noted that the first node N1 to the fourth node N4 are introduced to more conveniently describe the connection relationship between the elements, and it is not necessary to provide, for example, a pad or a pad in the pixel circuit 100 as an actual node.

For example, as shown in fig. 4B, each driving cycle of the pixel circuit 100 shown in fig. 4A includes a reset phase s_re, a data writing and compensation phase s_wc, and a light emitting phase s_em.

As shown in fig. 4A and 4B, in the reset phase s_re, the first reset control terminal RST1 receives an active level, and the scan signal terminal GAT (corresponding to the control terminal GAT1 of the second transistor CT2 and the control terminal GAT2 of the third transistor CT 3), the second reset control terminal RST2, and the light emission control terminal EM (corresponding to the control terminal EM1 of the fifth transistor CT5 and the control terminal EM2 of the seventh transistor CT 7) receive an inactive level; in this case, the fifth transistor T5 is turned on, and the third transistor T3, the fourth transistor T4, and the sixth transistor T6-tenth transistor T10 are turned off; the fifth transistor T5 is configured to receive the first reset signal Vinit1, and write the first reset signal Vinit1 to the storage capacitor Cst to reset the storage capacitor Cst; the voltage of the first node N1 is Vinit1, and Vinit1 is, for example, a negative value (e.g., -3V). For example, after the first reset signal Vinit1 is written into the storage capacitor Cst, the first transistor T1 and the second transistor T2 are turned on.

As shown in fig. 4A and 4B, in the data writing and compensation stage s_wc, the scan signal terminal GAT and the second reset control terminal RST2 receive an active level, and the first reset control terminal RST1 and the light emission control terminal EM receive an inactive level; in this case, the first transistor T1-fourth transistor T4 and eighth transistor T8 are turned on (the first transistor T1 and second transistor T2 are turned on due to the first reset signal Vinit1 written to the storage capacitor Cst), and the fifth transistor T5-seventh transistor T7, ninth transistor T9 and tenth transistor T10 are turned off; the third transistor T3 receives the data signal Vdata, the data signal Vdata is written to the control terminal of the first transistor T1 through the turned-on first transistor T1 and the fourth transistor T4, the storage capacitor Cst stores the data signal Vdata written to the control terminal of the first transistor T1 at the control terminal of the first transistor T1, the voltage of the first node N1 is vdata+vth, where Vth is the threshold voltage of the first transistor; the eighth transistor T8 is configured to receive the second reset signal Vinit2, and write the second reset signal Vinit2 to the first terminal of the organic light emitting element EL to reset the first terminal of the organic light emitting element EL, and the voltage of the fourth node N4 is Vinit2, where Vinit2 is, for example, a negative value (e.g., -3V).

As shown in fig. 4A and 4B, in the light emitting period s_em, the light emitting control terminal EM receives an active level, and the first reset control terminal RST1, the scan signal terminal GAT, and the second reset control terminal RST2 receive an inactive level; in this case, the first transistor T1, the second transistor T2, the sixth transistor T6, the seventh transistor T7, the ninth transistor T9, and the tenth transistor T10 are turned on, and the third transistor T3-the fifth transistor T5, and the eighth transistor T8 are turned off; the first transistor T1 is configured to control a driving current flowing through the first transistor T1 and from the first power voltage terminal VDD to the organic light emitting element EL for driving the organic light emitting element EL based on the data signal Vdata stored in the storage capacitor Cst and the received first power voltage VDD, and the second transistor T2 is configured to control a driving current flowing through the second transistor T2 and from the first power voltage terminal VDD to the organic light emitting element EL for driving the organic light emitting element EL based on the data signal Vdata stored in the storage capacitor Cst and the received first power voltage VDD; the voltage of the first node N1 is Vdata+Vth, and the voltage of the second node N2 is VDD.

For example, the inventors of the present disclosure determined that the pixel circuit 100 shown in fig. 4A can enhance the luminance of the organic light emitting element EL driven by the pixel circuit 100 shown in fig. 4A (compared to the pixel circuit 580 shown in fig. 2A) by performing simulation calculation on the display substrate including the pixel circuit 100 shown in fig. 4A. An exemplary description is provided below in connection with a simulation example.

For example, for an example in which the display substrate includes red, green, and blue sub-pixels R, G, and B, each of the red, green, and blue sub-pixels R, G, and B includes the pixel circuit 100 shown in fig. 4A, the first power supply voltage VDD is 4.6V, and the voltages Vdata of the data signals received by the red, green, and blue sub-pixels R, G, and B are 2.7V, 3.3V, and 2.28V, respectively, the calculated voltage values of the first to fourth nodes N1 to N4 of the pixel circuit of each of the red, green, and blue sub-pixels R, G, and B, and the value of the driving current Id may be referred to in table 1.

TABLE 1

As shown in table 1, the ratio of the driving current of the red subpixel R including the pixel circuit 100 shown in fig. 4B to the driving current of the red subpixel R including the pixel circuit 580 shown in fig. 2A is 229.0%, the ratio of the driving current of the green subpixel G including the pixel circuit 100 shown in fig. 4B to the driving current of the green subpixel G including the pixel circuit 580 shown in fig. 2A is 277.1%, and the ratio of the driving current of the blue subpixel B including the pixel circuit 100 shown in fig. 4B to the driving current of the blue subpixel B including the pixel circuit 580 shown in fig. 2A is 252.2%, that is, the driving current of the pixel circuit 100 is at least 2.2 times the driving current of the pixel circuit 580 for the above example.

For example, the inventors of the present disclosure have also found through simulation that by increasing (e.g., from 6.5V to 7.0V) the voltage value of the data signal of the pixel circuit 100 (compared to the pixel circuit 580 shown in fig. 2A), the drive current of the pixel circuit 100 can be made to correspond to the drive current of zero gray scale. For example, the drive current corresponding to zero gray scale is less than 1 picoampere (pA).

It should be noted that, in some examples, the eighth transistor T8 receives the inactive level in the data writing and compensating stage s_wc, and the eighth transistor T8 receives the active level in the resetting stage s_re, that is, the eighth transistor T8 resets the first terminal of the organic light emitting element EL in the resetting stage s_re, instead of resetting the first terminal of the organic light emitting element EL in the data writing and compensating stage s_wc.

At least one embodiment of the present disclosure also provides a display substrate including any one of the pixel circuits provided by at least one embodiment of the present disclosure. For example, the display substrate may be an organic light emitting diode display panel.

Fig. 5A is an exemplary block diagram of a display substrate 10 provided by at least one embodiment of the present disclosure. As shown in fig. 5A, the display substrate 10 includes at least one pixel circuit 100 provided by at least one embodiment of the present disclosure.

For example, the display substrate 10 includes a display side and a non-display side, and the screen displayed on the display substrate 10 is configured to be displayed on the display side of the display substrate 10, that is, the display side of the display substrate 10 is the light emitting side of the display substrate 10. The display side and the non-display side are opposed in a normal direction of the display surface of the display substrate 10 (for example, a direction perpendicular to the display substrate 10).

Fig. 5B is a schematic cross-sectional view of the display substrate 10 shown in fig. 5A. For example, as shown in fig. 5B, the display substrate 10 includes a display layer 260 and a sensing layer 250, the sensing layer 250 being disposed on the non-display side of the display substrate 10; the display layer 260 includes a display area 201, the display area 201 including a first display area 210 and a second display area 220; the sensing layer 250 includes a sensor 251, the sensor 251 overlapping the first display region 210 in a normal direction of a display surface of the display substrate 10, and configured to receive and process an optical signal passing through the first display region 210.

For example, the sensor 251 may be an image sensor, and may be used to capture images of the external environment that the light collecting surface of the sensor 251 faces. For example, in the case where the display device 20 including the display substrate 10 is a mobile terminal such as a cellular phone, a notebook, the sensor 251 may be used to implement a camera of the mobile terminal such as a cellular phone, a notebook. For example, the sensor 251 may include an array arrangement of sensing pixels. For example, each photosensitive pixel may include a photosensitive detector (e.g., photodiode, phototransistor) and a switching transistor (e.g., switching transistor). The photodiode may convert an optical signal irradiated thereto into an electrical signal, and the switching transistor may be electrically connected with the photodiode to control whether the photodiode is in a state of collecting the optical signal and a time of collecting the optical signal.

Fig. 6 is a schematic plan view of an example of the display substrate 10 shown in fig. 5B, and the display substrate 10 shown in fig. 5B corresponds to the AA' line of the display substrate 10 shown in fig. 6.

For example, as shown in fig. 6, the display substrate 10 (e.g., the display layer 260 of the display substrate 10) includes a display region 201 and a peripheral region 202 at least partially surrounding the display region 201; the display area 201 includes a first display area 210 and a second display area 220. For example, as shown in fig. 6, the second display region 220 at least partially surrounds the first display region 210.

Fig. 7A is a schematic view of a partial region REG1 of the first display region 210 of the display substrate 10 shown in fig. 6, and fig. 8A is a schematic view of a partial region REG2 of the second display region 220 of the display substrate 10 shown in fig. 6. As shown in fig. 7A, the first display area 210 includes a plurality of first pixel units 270 arranged in an array; as shown in fig. 8A, the second display area 220 includes a plurality of second pixel units 290 arranged in an array.

For example, the plurality of pixel units included in the display region 201 of the display substrate 10 may include pixel units of different colors (e.g., a red pixel unit, a green pixel unit, and a blue pixel unit), and light emitting areas of light emitting elements in the pixel units of different colors may be the same or not be the same. For example, the light emitting area of the light emitting element in the red pixel unit, the light emitting area of the light emitting element in the green pixel unit, and the light emitting area of the light emitting element in the blue pixel unit are different from each other.

Fig. 8B illustrates one example of the first pixel unit 270 illustrated in fig. 7A, fig. 8C illustrates another example of the first pixel unit 270 illustrated in fig. 7A, and fig. 8D illustrates a schematic diagram of the second pixel unit 290 illustrated in fig. 8A.

For example, as shown in fig. 8B and 8C, each of the plurality of first pixel units 270 includes a light emitting element 301; each of the plurality of second pixel units 290 includes a second light emitting element 302. For example, the light emitting element 301 and the second light emitting element 302 may each be an organic light emitting element, and the organic light emitting element may be an organic light emitting diode, for example, but the embodiment of the present disclosure is not limited thereto. For example, the light emitting element 301 and the second light emitting element 302 may each be an inorganic light emitting element. For example, the light emitting element 301 and the second light emitting element 302 can be realized to have the same structure and performance characteristics. For example, each of the plurality of first pixel units 270 includes the number of light emitting elements 301 equal to the number of second light emitting elements 302 (e.g., equal to one) included in each of the plurality of second pixel units 290.

For example, the light emitting area of the light emitting element 301 included in the first pixel unit 270 of the first display region 210 displaying the first color and the light emitting area of the second light emitting element 302 included in the second pixel unit 290 of the second display region 220 displaying the first color are different from each other. For example, the first color may be red, green, blue, or other suitable colors.

For example, the distribution density per unit area of the plurality of first pixel units 270 in the first display region 210 is smaller than the distribution density per unit area of the plurality of second pixel units 290 in the second display region 220. For example, the distribution density per unit area of the plurality of light emitting elements 301 in the first display region 210 is smaller than the distribution density per unit area of the plurality of second light emitting elements 302 in the second display region 220. For example, since the distribution density per unit area of the plurality of first pixel units 270 in the first display region 210 is smaller than the distribution density per unit area of the plurality of second pixel units 290 in the second display region 220, the display resolution of the first display region 210 is lower than the display resolution of the second display region 220, and thus, the first display region 210 may be referred to as a low resolution region of the display substrate 10.

For example, as shown in fig. 7A, the pitch of two first pixel units 270 adjacent in the first direction D1 is larger than the size of the first pixel unit 270 in the first direction D1, and the pitch of two first pixel units 270 adjacent in the second direction D2 is larger than or equal to the size of the first pixel unit 270 in the second direction D2. For example, the pitch of two first pixel units 270 adjacent in the first direction D1 is equal to three times the size of the first pixel units 270 in the first direction D1; the pitch of two adjacent first pixel units 270 in the second direction D2 is equal to the size of the first pixel unit 270 in the second direction D2. For example, the pitch of the adjacent two first pixel units 270 in the first direction D1 is in the range of 280 to 380 micrometers, the pitch of the adjacent two first pixel units 270 in the second direction D2 is in the range of 100 to 160 micrometers, and the sizes of the first pixel units 270 in the first and second directions D1 and D2 are in the range of 110 to 130 micrometers. In some examples, the spacing of two cells refers to the spacing of the centers of the two cells.

For example, as shown in fig. 8A, the pitch of two second pixel units 290 adjacent in the first direction D1 is smaller than the size of the second pixel unit 290 in the first direction D1, and the pitch of two second pixel units 290 adjacent in the second direction D2 is smaller than the size of the second pixel unit 290 in the second direction D2. For example, as shown in fig. 8A, the pitch of two adjacent second pixel units 290 in the first direction D1 is smaller than one fifth of the size of the second pixel unit 290 in the first direction D1, and the pitch of two adjacent second pixel units 290 in the second direction D2 is smaller than one fifth of the size of the second pixel unit 290 in the second direction D2.

For example, the display substrate 10 includes a plurality of pixel circuits 100, and the plurality of pixel circuits 100 are electrically connected to the plurality of light emitting elements 301 included in the plurality of first pixel units 270 in a one-to-one correspondence. For example, the display substrate 10 further includes a plurality of pixel circuits 580, and the plurality of pixel circuits 580 are electrically connected to the plurality of second light emitting elements 302 included in the plurality of second pixel units 290 in a one-to-one correspondence manner. As shown in fig. 8D, each of the second pixel units 290 includes a second light emitting element 302 and a pixel circuit 580 for driving the second light emitting element 302.

It should be noted that fig. 8B is only for illustrating that the pixel unit 273 includes the light emitting element 301 and the pixel circuit 100, fig. 8C is only for illustrating that the pixel circuit 100 included in the pixel driving unit 281 and the light emitting element 301 included in the pixel unit 274 are electrically connected to each other, and fig. 8D is only for illustrating that the second pixel unit 290 includes the second light emitting element 302 and the pixel circuit 580, and the specific shapes and the relative positional relationship of the light emitting element 301, the second light emitting element 302, the pixel circuit 100 and the pixel circuit 580 are not limited, and may be set according to practical application requirements.

For example, by making a pixel circuit connected in one-to-one correspondence with the light emitting elements of the plurality of first pixel units 270 any one of the pixel circuits 100 provided in at least one embodiment of the present disclosure, the light emitting brightness of the light emitting elements of the plurality of first pixel units 270 may be enhanced, and thus the brightness of the first display region 210 of the display substrate 10 including the plurality of first pixel units 270 (i.e., the brightness of the low resolution region of the display substrate 10) may be enhanced.

For example, as shown in fig. 6 and 7A, the first display region 210 includes a first sub display region 211 and a second sub display region 212 that do not overlap each other. For example, as shown in fig. 6 and 7A, the first sub-display area 211 at least partially surrounds (e.g., completely surrounds) the second sub-display area 212.

For example, as shown in fig. 7A to 7C, the first sub-display area 211 includes a first group 271 of a plurality of first pixel units, and the second sub-display area 212 includes a second group 272 of a plurality of first pixel units, the first and second groups not overlapping each other. As shown in fig. 7A-7C, the first group 271 of the plurality of first pixel units 270 includes a first number of first pixel units 270 (i.e., a first number of pixel units 273); a second group 272 of the plurality of first pixel cells includes a second number of first pixel cells 270 (i.e., a second number of pixel cells 274).

For example, as shown in fig. 8C, the second group 272 includes the pixel units 274 including only the light emitting elements 301, and does not include the pixel circuits 100; as shown in fig. 8C and 7A, the pixel circuit 100 for driving the light emitting element 301 included in the pixel unit 274 is provided in the pixel driving unit 281 included in the first sub-display area 211. Correspondingly, the pixel circuits 100 connected in one-to-one correspondence with the light emitting elements of the second group 272 of the plurality of first pixel units are disposed in the first sub-display area 211 (disposed in the plurality of pixel driving units 281 included in the first sub-display area 211, respectively). For example, the pixel driving unit 281 does not include a light emitting element.

For example, by having the pixel circuits 100 connected in one-to-one correspondence with the light emitting elements of the second group 272 of the plurality of first pixel units provided in the first sub-display area 211, it is possible to dispense with providing the pixel circuits in the second sub-display area 212, whereby the transmittance of the second sub-display area 212 and the aperture ratio of the first pixel units 270 included in the second sub-display area 212 can be improved; in this case, the sensor 251 and the second sub-display area 212 may be overlapped in the normal direction of the display surface of the display substrate 10 (see fig. 5B) to reduce the shielding of the elements in the second sub-display area 212 from the optical signal incident on the second sub-display area 212 and transmitted toward the sensor 251, whereby the signal-to-noise ratio of the image output by the sensor 251 may be improved. For example, the second sub-display area 212 may be referred to as a high light transmission area of the low resolution area of the display substrate 10.

For example, the display substrate 10 further includes a plurality of traces 213. The plurality of wirings 213 electrically connect the light emitting elements of the second group 272 of the plurality of first pixel units and the pixel circuits 100 (pixel driving units 281) connected to the light emitting elements of the second group 272 of the plurality of first pixel units in one-to-one correspondence. For example, each of the plurality of wirings 213 may be implemented as a transparent wiring, thereby further improving the transmittance of the second sub-display area 212 and the signal-to-noise ratio of the image output from the sensor 251.

Note that the pixels connected to the light emitting elements of the second group 272 of the plurality of first pixel units in one-to-one correspondence are not limited to being disposed in the first sub-display area 211, and in some examples, at least part (e.g., all) of the pixels connected to the light emitting elements of the second group 272 of the plurality of first pixel units in one-to-one correspondence may be disposed in the second sub-display area 212 without considering the transmittance of the second sub-display area 212 and the aperture ratio of the first pixel units 270 included in the second sub-display area 212.

For example, as shown in fig. 8B, the pixel unit 273 included in the first group 271 includes both the light emitting element 301 and the pixel circuit 100. Correspondingly, pixel circuits 100, to which light emitting elements of the first group 271 of the plurality of first pixel units are connected in one-to-one correspondence, are also disposed in the first sub-display area 211. For example, the pixel circuits 100 connected in one-to-one correspondence to the light emitting elements of the first group 271 of the plurality of first pixel units are respectively provided in the corresponding first pixel units 270 of the first group 271 of the plurality of first pixel units, that is, each first pixel unit 270 of the first group 271 of the plurality of first pixel units further includes a pixel circuit for driving the light emitting element. For example, each of the first pixel units 270 of the first group 271 of the plurality of first pixel units includes a pixel circuit and a light emitting element as shown in fig. 4A.

For example, as shown in fig. 7A, the first sub-display area 211 may further include a redundant pixel unit 282, and as shown in fig. 8E, the redundant pixel unit 282 includes a pixel circuit (e.g., the pixel circuit 100) but does not include a light emitting element. For example, by providing the redundant pixel unit 282, the electrical environment of the first sub-display area 211 can be made uniform (e.g., the loads of the resistance and the capacitance are made uniform).

For example, the display substrate 10 may further include a plurality of scan signal lines (e.g., gate lines) and a plurality of data lines disposed to cross each other (e.g., vertically), and a plurality of voltage control lines disposed in parallel with the scan signal lines. For example, each pixel circuit is connected to a corresponding scan signal line and a corresponding data line, for example, a corresponding scan signal terminal of each pixel circuit may be connected to a corresponding scan signal line, a corresponding data signal terminal of each pixel circuit may be connected to a corresponding data line, and a corresponding first power voltage terminal and second power voltage terminal of each pixel circuit may be connected to a corresponding voltage control line. For example, the plurality of scan signal lines respectively extend in the row direction (e.g., the first direction D1) of the display substrate 10, and the plurality of scan data lines respectively have portions extending in the column direction (e.g., the second direction D2) of the display substrate 10. For example, the first direction D1 intersects (e.g., is perpendicular to) the second direction D2.

For example, as shown in fig. 7A, the data line DL electrically connected to the pixel driving unit 281 for driving the light emitting element is routed from the region between the first sub-display region 211 and the second sub-display region 212 to the first sub-display region 211, and thus, the data line DL further includes a portion extending in the first direction D1.

For example, as shown in fig. 6, the peripheral region 202 includes a driving chip 230. For example, the driving chip 230 may include a data driver, and the data driver of the driving chip 230 may be bonded on the display substrate 10 via a flexible circuit board and provide data signals for display to a plurality of data lines via the flexible circuit to drive the display substrate 10 to realize a display function. For example, the peripheral region 202 may further include a gate driving assembly (GOA, not shown) on the array substrate, and a plurality of output terminals of the GOA are respectively connected to the plurality of gate lines GL to provide gate scan signals to the plurality of gate lines.

Fig. 9 is a schematic plan view of another example of the display substrate 10 shown in fig. 5B, and the display substrate 10 shown in fig. 5B corresponds to the AA' line of the display substrate 10 shown in fig. 9.

The display substrate 10 shown in fig. 9 is similar to the display substrate 10 shown in fig. 6, and therefore, only the differences between the display substrate 10 shown in fig. 9 and the display substrate 10 shown in fig. 6 will be described herein, and the same points will not be repeated. The display substrate 10 shown in fig. 9 is different from the display substrate 10 shown in fig. 6 in that it includes: the peripheral region 202 of the display substrate 10 shown in fig. 9 includes a pixel driving region 240, and a plurality of pixel circuits electrically connected to the plurality of light emitting elements in one-to-one correspondence are at least partially (e.g., entirely) disposed in the pixel driving region 240; in this case, the first display region 210 of the display substrate 10 shown in fig. 9 does not need to provide the first sub-display region 211 (only the second sub-display region 212 or the high light transmission region of the low resolution region of the display substrate 10 is provided), whereby the size of the first display region 210 can be reduced, that is, the size of the low resolution region of the display substrate 10 can be reduced, and thus the quality of the image displayed by the display substrate 10 can be improved.

For example, as shown in fig. 9, the second display area 220 surrounds the first display area 210. For example, as shown in fig. 9, the pixel driving region 240 and the first display region 210 are arranged side by side in the row direction of the display substrate 10 (for example, corresponding to the first direction D1 of fig. 7A and 8A), and the pixel driving region 240 and the first display region 210 are spaced apart by the second display region 220. In this case, the plurality of wirings 213 extend along the row direction of the display substrate 10, respectively.

It should be noted that, the pixel driving area 240 and the first display area 210 are not limited to be arranged in parallel in the row direction of the display substrate 10, and according to practical application requirements, as shown in fig. 10, the pixel driving area 240 and the first display area 210 may be arranged in parallel in the column direction of the display substrate 10 (for example, the second direction D2 corresponding to fig. 7A and 8A), where the plurality of traces 213 extend along the column direction of the display substrate 10, respectively.

For example, in order to make the brightness of the second display area 220 more uniform with the brightness of the first display area 210, the data signal provided to the pixel circuit 100 of the first display area 210 may be additionally compensated on the basis of the pixel circuit 100 provided by the first display area 210 using at least one embodiment of the present disclosure. For example, the timing controller may be used to compensate for the data signals provided to the pixel circuits 100 of the first display region 210.

For example, as shown in fig. 9, the first display area 210 is circular in shape, but embodiments of the present disclosure are not limited thereto. The shape of the first display area 210 may also be rectangular or other suitable shapes according to practical application requirements.

Fig. 11 is an exemplary block diagram of a display device 20 provided by at least one embodiment of the present disclosure. As shown in fig. 11, the display device 20 includes any one of the pixel circuits 100 or any one of the display substrates 10 provided in at least one embodiment of the present disclosure.

It should be noted that, applicable components may be used for the display substrate and other components of the display device (such as the image data encoding/decoding device, the clock circuit, etc.), which are understood by those of ordinary skill in the art, and are not described herein in detail, and should not be taken as limiting the disclosure. The display substrate and the display device can enhance the luminance (e.g., the overall luminance) of a low resolution region (i.e., a first display region) of the display substrate and the display device.

While the disclosure has been described in detail with respect to the general description and the specific embodiments thereof, it will be apparent to those skilled in the art that certain modifications and improvements may be made thereto based on the embodiments of the disclosure. Accordingly, such modifications or improvements may be made without departing from the spirit of the disclosure and are intended to be within the scope of the disclosure as claimed.

The foregoing is merely exemplary embodiments of the present disclosure and is not intended to limit the scope of the disclosure, which is defined by the appended claims.

Claims

1. A pixel circuit, comprising: a first driving circuit, a second driving circuit, a data writing circuit and a signal storage circuit,

wherein the data write circuit is configured to receive a data signal, the data write circuit writing the data signal to a first end of the first drive circuit;

the first driving circuit is connected with the data writing circuit and is configured to receive the data signal from the data writing circuit and allow the data signal to be written to a control end of the first driving circuit;

the control terminal of the second driving circuit is configured to receive the data signal written to the control terminal of the first driving circuit;

The signal storage circuit is configured to store the data signal written to the control terminal of the first driving circuit at the control terminal of the first driving circuit;

the first end of the first driving circuit and the first end of the second driving circuit are both configured to receive a first power supply voltage from a first power supply voltage end, and the second end of the first driving circuit and the second end of the second driving circuit are both configured to be electrically connected to the first end of the light emitting element; and

the first and second driving circuits are configured to control driving currents flowing through the first and second driving circuits, respectively, from the first power supply voltage terminal to the light emitting element for driving the light emitting element based on the data signal stored in the signal storage circuit and the received first power supply voltage,

wherein the pixel circuit further comprises: a first control circuit, a second control circuit, a third control circuit and a fourth control circuit,

the first control circuit is connected between a first end of the first driving circuit and the first power supply voltage end and is configured to control whether the first driving circuit is electrically connected with the first power supply voltage end;

The second control circuit is connected between a first end of the second driving circuit and the first power supply voltage end and is configured to control whether the second driving circuit is electrically connected with the first power supply voltage end;

the third control circuit is connected between the second end of the first driving circuit and the first end of the light-emitting element and is configured to control whether the first driving circuit is electrically connected with the first end of the light-emitting element;

the fourth control circuit is connected between the second end of the second driving circuit and the first end of the light emitting element and is configured to control whether the second driving circuit is electrically connected with the first end of the light emitting element,

the control end of the first control circuit, the control end of the second control circuit, the control end of the third control circuit and the control end of the fourth control circuit are configured to receive the same light emission control signals.

2. The pixel circuit according to claim 1, wherein a control terminal of the first driving circuit and a control terminal of the second driving circuit are electrically connected to each other.

3. The pixel circuit of claim 1, further comprising a compensation connection circuit,

the compensation connection circuit is connected between the second terminal of the first driving circuit and the control terminal of the first driving circuit, and is configured to write a data signal written to the first terminal of the first driving circuit to the control terminal of the first driving circuit via the first driving circuit.

4. A pixel circuit according to claim 3, wherein the control terminal of the compensation connection circuit and the control terminal of the data write circuit are connected to the same scanning signal line.

5. The pixel circuit according to any one of claims 1 to 4, further comprising a first reset circuit,

the first reset circuit is connected with the signal storage circuit; and

the first reset circuit is configured to receive a first reset signal and write the first reset signal to the signal storage circuit to reset the signal storage circuit.

6. The pixel circuit according to claim 1, wherein a control terminal of the first control circuit and a control terminal of the second control circuit are connected to the same light emission control line.

7. The pixel circuit according to any one of claims 1 to 4, further comprising a second reset circuit,

wherein the second reset circuit is configured to receive a second reset signal and write the second reset signal to the first end of the light emitting element to reset the first end of the light emitting element.

8. The pixel circuit according to claim 1, wherein a control terminal of the third control circuit and a control terminal of the fourth control circuit are connected to the same light emission control line.

9. A pixel circuit according to any one of claims 1 to 4, wherein the first drive circuit comprises a first transistor and the second drive circuit comprises a second transistor; and

the threshold voltage of the first transistor is equal to the threshold voltage of the second transistor.

10. A display substrate comprising at least one pixel circuit as claimed in any one of claims 1 to 9.

11. The display substrate of claim 10, wherein the at least one pixel circuit comprises a plurality of pixel circuits;

the display substrate is provided with a display area, and the display area comprises a first display area and a second display area;

the first display area comprises a plurality of first pixel units which are arranged in an array manner, and the second display area comprises a plurality of second pixel units which are arranged in an array manner;

the unit area distribution density of the plurality of first pixel units in the first display area is smaller than the unit area distribution density of the plurality of second pixel units in the second display area;

each of the plurality of first pixel units includes the light emitting element; and

the pixel circuits are electrically connected with the light emitting elements in a one-to-one correspondence.

12. The display substrate of claim 11, wherein the first display region further comprises a first sub-display region and a second sub-display region that do not overlap each other;

the first sub-display area includes a first group of the plurality of first pixel units, and the second sub-display area includes a second group of the plurality of first pixel units, the first and second groups not overlapping each other; and

pixel circuits connected in one-to-one correspondence with the light emitting elements of the second group of the plurality of first pixel units are disposed in the first sub-display area.

13. The display substrate of claim 12, further comprising a plurality of transparent traces, wherein the plurality of transparent traces electrically connect the light emitting elements of the second group of the plurality of first pixel units to pixel circuits connected in one-to-one correspondence with the light emitting elements of the second group of the plurality of first pixel units.

14. The display substrate of claim 11, wherein the display substrate further has a peripheral region at least partially surrounding the display region, the plurality of pixel circuits being disposed at least partially in the peripheral region.

15. The display substrate of any of claims 11-14, further comprising a sensor, wherein the sensor is disposed on a non-display side of the display substrate, overlaps the first display region in a direction normal to a display surface of the display substrate, and is configured to receive and process an optical signal passing through the first display region.

16. A display device comprising a pixel circuit according to any one of claims 1 to 9 or a display substrate according to any one of claims 10 to 15.