JP2019148737A - Electro-optical device and electronic apparatus - Google Patents

Abstract

To enable a drive transistor included in a pixel circuit to be arranged in the direction of a scan line while avoiding the occurrence of a crosstalk.SOLUTION: Provided is an electro-optical device comprising a first pixel circuit 110-1 and a second pixel circuit 110-2 adjacent to each other in the direction of a scan line, with the source, gate and drain of a first transistor 121-1 in the first pixel circuit 110-1 and the source of a first transistor 121-2 in the second pixel circuit 110-2 arranged in a row in the direction of a scan line (direction X), wherein a power feeding line 116-2, given a fixed potential, which is a fixed potential line extending in a direction crossing the scan line (direction Y) is provided between the drain of the first transistor 121-1 and the source of the first transistor 121-2, and the source of the first transistor 121-2 is connected to the power feeding line 116-2.SELECTED DRAWING: Figure 6

Description

  The present invention relates to an electro-optical device and an electronic apparatus including the electro-optical device.

In recent years, various electro-optical devices using light-emitting elements such as organic light-emitting diode (hereinafter referred to as OLED (Organic Light Emitting Diode)) elements have been proposed. In a conventional electro-optical device, a pixel including a light-emitting element, a selection transistor that takes in a voltage corresponding to the display gradation of the light-emitting element, and a driving transistor that supplies current to the light-emitting element in response to the intersection of a scanning line and a data line A circuit is provided.
Patent Document 1 discloses a layout in which the source, gate, and drain of a driving transistor are arranged along the direction of a scanning line.

JP 2003-332072 A

  However, in the conventional technique, when the electro-optical device is downsized, crosstalk is likely to occur between pixel circuits adjacent to each other in the scanning line direction. Specifically, when the voltage of the drain of the driving transistor of the pixel circuit varies, the voltage of the gate of the driving transistor is affected in the pixel circuit adjacent to the pixel circuit in the scanning line direction. As a result, there is a problem that the image quality deteriorates.

  In order to solve the above problems, an electro-optical device according to the present invention is provided corresponding to a scanning line and emits light with luminance according to a supplied current, and is supplied to the first light-emitting element. A first pixel circuit having a first driving transistor that controls a current to be driven according to a first gradation voltage, and a second pixel circuit adjacent to the first pixel circuit in the scanning line direction, A second pixel circuit having a second light emitting element that emits light with a luminance corresponding to the current to be supplied, and a second driving transistor that controls a current supplied to the second light emitting element according to a second gradation voltage; A fixed potential line provided with a potential and provided in a direction intersecting with the scanning line, and along the scanning line, the source of the first driving transistor, the gate of the first driving transistor, and the first driving Transis Are arranged side by side over the drain and source of the second driving transistor of the fixed potential line is characterized in that provided between the drain and source of the second driving transistor of the first driving transistor.

  According to this aspect, the fixed potential line to which a fixed potential is applied is provided between the drain of the first drive transistor and the source of the second drive transistor, and this fixed potential line is the drain voltage of the first drive transistor. It acts as a shield that prevents fluctuations from affecting the gate voltage of the second driving transistor. For this reason, according to this aspect, even if the first drive transistor and the second drive transistor are arranged in the scanning line direction, crosstalk can be suppressed. As a result, the image quality of the electro-optical device can be improved.

  The electro-optical device described above includes a first conductive type first region where a source of the second driving transistor is formed, and a second conductive type second region different from the first conductive type. The fixed potential may be applied to the second region, and the fixed potential line may be connected to the second region. According to this aspect, the potential of the fixed potential line is fixed to the substrate potential that is the potential of the second region.

  The electro-optical device includes a first wiring connected to the drain of the first driving transistor and extending in a direction intersecting the scanning line, and the fixed potential line is provided side by side with the first wiring, and the fixed The potential line may be longer than the first wiring.

  According to this aspect, the shielding effect is higher than when the length of the fixed potential line is shorter than the length of the first wiring.

  The electro-optical device includes a light emitting layer in which the first light emitting element and the second light emitting element are formed, and a first metal layer provided closer to the substrate than the light emitting layer, wherein the first wiring And the first metal layer in which the fixed potential line is formed, the second metal layer provided closer to the light emitting layer than the first metal layer, and the fixed potential line and the second metal layer are connected to each other. And a relay electrode.

  According to this aspect, since the second metal layer functions as a shield in addition to the fixed potential line, the shielding effect is further enhanced.

  The above-described electro-optical device may be characterized in that the fixed potential line is connected to a source of the second drive transistor.

  Also in this embodiment, the fixed potential line serves as a shield that prevents fluctuations in the drain voltage of the first drive transistor from affecting the gate voltage of the second drive transistor.

  The electro-optical device described above is a light emission control transistor that controls on or off of a current flowing from the second driving transistor to the second light emitting element, the drain being connected to the source of the second driving transistor, and the source being A light emission control transistor connected to the fixed potential line may be included.

  Also in this embodiment, the fixed potential line serves as a shield that prevents fluctuations in the drain voltage of the first drive transistor from affecting the gate voltage of the second drive transistor.

  In addition to the electro-optical device, the present invention can be conceptualized as an electronic apparatus including the electro-optical device. Typically, the electronic apparatus includes a display device such as a head mounted display (HMD) or an electronic viewfinder.

1 is a perspective view showing a configuration of an electro-optical device according to a first embodiment of the present invention. It is a figure which shows the electrical structure of an electro-optical apparatus. It is a figure which shows the structure of the demultiplexer of an electro-optical apparatus. FIG. 3 is a circuit diagram illustrating configurations of a pixel circuit and a switch unit of the electro-optical device. It is a figure which shows the layout of the light emission part of the pixel in an electro-optical apparatus, and the layout of the circuit part corresponding to a light emission part. It is a perspective view showing the planar structure of the circuit part of a pixel circuit. It is sectional drawing of a pixel circuit. It is a circuit diagram which shows the structure of the pixel circuit of the electro-optical apparatus which concerns on 2nd Embodiment of this invention. It is a perspective view showing the planar structure of the circuit part of the pixel circuit. It is a perspective view of the head mounted display 300 concerning the present invention. It is a perspective view of the personal computer 400 concerning this invention.

  Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings. However, in each figure, the size and scale of each part are appropriately changed from the actual ones. In addition, since the embodiments described below are preferable specific examples of the present invention, various technically preferable limitations are given. However, the scope of the present invention particularly limits the present invention in the following description. Unless stated to the effect, the present invention is not limited to these forms.

<A: First Embodiment>
FIG. 1 is a perspective view showing a configuration of an electro-optical device 1 according to an embodiment of the present invention. The electro-optical device 1 is a micro display that displays an image on a head-mounted display, for example.

  As shown in FIG. 1, the electro-optical device 1 includes a display panel 10 and a control circuit 3 that controls the operation of the display panel 10. The display panel 10 includes a plurality of pixel circuits and a drive circuit that drives the pixel circuits. In the present embodiment, the plurality of pixel circuits and drive circuits included in the display panel 10 are formed on a silicon substrate, and an OLED that is an example of an electro-optical element is used for the pixel circuits. The display panel 10 is housed in, for example, a frame-shaped case 82 that opens at the display unit, and one end of an FPC (Flexible Printed Circuits) substrate 84 is connected. On the FPC board 84, the control circuit 3 of the semiconductor chip is mounted by a COF (Chip On Film) technique, and a plurality of terminals 86 are provided, which are connected to an upper circuit (not shown).

  FIG. 2 is a block diagram illustrating a configuration of the electro-optical device 1 according to the embodiment. As described above, the electro-optical device 1 includes the display panel 10 and the control circuit 3. Digital image data Videdo is supplied to the control circuit 3 in synchronization with a synchronization signal from an upper circuit (not shown). Here, the image data Video is data that defines the display gradation of pixels of an image to be displayed on the display panel 10 (strictly speaking, the display unit 100 described later) by, for example, 8 bits. The synchronization signal is a signal including a vertical synchronization signal, a horizontal synchronization signal, and a dot clock signal.

  The control circuit 3 generates various control signals based on the synchronization signal and supplies them to the display panel 10. Specifically, the control circuit 3 controls the control signals Ctr1 to Ctr3, Gref, / Gini, Gcpl, / Gcpl, Sel (1), Sel (2), Sel (3), / Sel (1), / Sel ( 2), / Sel (3) is supplied to the display panel 10. Each of the control signals Ctr1 to Ctr3 is a signal including a plurality of signals such as a pulse signal, a clock signal, and an enable signal. The control signal Gref is a positive logic control signal, and the control signal / Gini is a negative logic control signal. The control signal Gcpl is also a positive logic control signal, and the control signal / Gcpl is a negative logic control signal having a logic inversion relationship with the control signal Gcpl. The control signal / Sel (1) is in a logically inverted relationship with the control signal Sel (1). Similarly, the control signal / Sel (2) and the control signal / Sel (3) are in a logic inversion relationship with the control signal Sel (2) and Sel (3), respectively. The control signals Sel (1), Sel (2), and Sel (3) are collectively referred to as the control signal Sel, and the control signals / Sel (1), / Sel (2), and / Sel (3) are referred to as the control signal. / Sel may be collectively called. The voltage generation circuit 31 receives supply of power from a power supply circuit (not shown), and supplies a reset potential Vrst, a reference potential Vref, and an initialization potential Vini to the display panel 10.

  Further, the control circuit 3 generates an analog image signal Vid based on the image data Video. Specifically, the control circuit 3 is provided with a lookup table that stores the potential indicated by the image signal Vid and the luminance of the electro-optical element included in the display panel 10 in association with each other. Then, the control circuit 3 refers to the lookup table to generate an image signal Vid indicating a potential corresponding to the luminance of the electro-optic element defined in the image data Video, and outputs this to the display panel 10. Supply.

  As shown in FIG. 2, the display panel 10 includes a display unit 100 and drive circuits (scanning line drive circuit 4 and data line drive circuit 5) for driving the display unit 100. In this embodiment, the drive circuit is divided into the scanning line drive circuit 4 and the data line drive circuit 5, but these may be integrated into one circuit to constitute the drive circuit. As shown in FIG. 2, in the display unit 100, pixel circuits 110 corresponding to pixels of an image to be displayed are arranged in a matrix. Although not shown in detail in FIG. 2, M rows of scanning lines 12 are provided in the display unit 100 so as to extend in the horizontal direction (X direction) in the drawing, and are grouped every three columns. (3N) columns of data lines 14 are provided extending in the vertical direction (Y direction) in the drawing. Each scanning line 12 and each data line 14 are provided with electrical insulation. The pixel circuit 110 is provided corresponding to the intersection of the M rows of scanning lines 12 and the (3N) columns of data lines 14. Therefore, in the present embodiment, the pixel circuits 110 are arranged in a matrix with vertical M rows × horizontal (3N) columns.

  Here, M and N are both natural numbers. In order to distinguish rows (rows) in the matrix of the scanning lines 12 and the pixel circuits 110, they may be referred to as 1, 2, 3,... (M-1), M rows in order from the top in the drawing. Similarly, in order to distinguish the columns of the matrix of the data line 14 and the pixel circuit 110, they may be referred to as 1, 2, 3, ..., (3N-1), (3N) columns in order from the left in the figure. . Here, in order to generalize and describe the group of data lines 14, if an arbitrary integer of 1 or more is expressed as n, the n-th group counted from the left includes the (3n-2) th column, (3n -1) The data line 14 of the column and the (3n) column belongs. The three pixel circuits 110 corresponding to the scanning lines 12 in the same row and the three data lines 14 belonging to the same group correspond to R (red), G (green), and B (blue) pixels, respectively.

  In addition, as shown in FIG. 2, (3N) rows of power supply lines 16 are provided in the display unit 100 so as to extend in the vertical direction and to be electrically insulated from each scanning line 12. Each feeder line 16 is a fixed potential line to which a predetermined reset potential Vorst is fed in common from the voltage generation circuit 31. In order to distinguish the columns of the feeder lines 16, they may be called the feeder lines 16 in the first, second, third,..., (3N) columns from the left in the drawing. Each of the power supply lines 16 in the first column to the (3N) column is provided corresponding to the data line 14 in the first column to the (3N) column.

  The scanning line driving circuit 4 generates a scanning signal Gwr for sequentially selecting the M scanning lines 12 for each row within one frame period in accordance with the control signal Ctr1. In FIG. 2, the scanning signals Gwr supplied to the scanning lines 12 in the 1, 2, 3,..., Mth rows are Gwr (1), Gwr (2), Gwr (3),. 1) and Gwr (M). In addition to the scanning signals Gwr (1) to Gwr (M), the scanning line driving circuit 4 generates various control signals synchronized with the scanning signal Gwr for each row and supplies them to the display unit 100. Illustration is omitted in FIG. The frame period is a period required for the electro-optical device 1 to display an image for one cut (frame). For example, if the frequency of the vertical synchronization signal included in the synchronization signal is 120 Hz, the period of one cycle is included. It is a period of 8.3 milliseconds.

  As shown in FIG. 2, the data line driving circuit 5 includes (3N) switch units SW provided in a one-to-one correspondence with each of the (3N) columns of data lines 14, and 3 constituting each group. N demultiplexers DM provided for each column data line 14 and a data signal supply circuit 70 are provided.

  The data signal supply circuit 70 generates data signals Vd (1), Vd (2),..., Vd (N) based on the image signal Vid and the control signal Ctr2 supplied from the control circuit 3. That is, the data signal supply circuit 70 generates the data signals Vd (1), Vd (2) based on the image signal Vid obtained by time-division multiplexing the data signals Vd (1), Vd (2),. ..., Vd (N) is generated. Then, the data signal supply circuit 70 applies the data signals Vd (1), Vd (2),..., Vd (N) to the demultiplexer DM corresponding to the first, second,. Supply each.

  The configuration of the pixel circuit 110, the switch unit SW, and the demultiplexer DM will be described with reference to FIGS. FIG. 3 is a diagram illustrating a configuration of the demultiplexer DM, and FIG. 4 is a diagram illustrating a configuration of the pixel circuit 110 and the switch unit SW. Since each pixel circuit 110 has the same configuration when viewed electrically, it is located in the m (1 ≦ m ≦ M) row and the pixel circuit in the m row (3n) column located in the (3n) column. 110 will be described as an example. A scanning signal Gwr (m), control signals Gcmp (m), Gorst (m), and Gel (m) are supplied from the scanning line driving circuit 4 to the pixel circuit 110 in the m-th row.

  As shown in FIG. 4, the display area 112 of the display unit 100 is provided with a pixel circuit 110 and a data line 14 that supplies a gradation voltage to the pixel circuit 110. In addition, in the display area 112, the signal line 15, the feed line 16, the feed line 17, and the signal line 20 are provided for each column along the data line 14. The power supply line 17 in each column is a fixed potential line that is commonly supplied from the voltage generation circuit 31 with the potential Vel on the higher side of the power supply in the pixel circuit 110. In FIG. 3, the pixel circuit 110 in the m-th row (3n) column is denoted by reference numeral “110 (m, 3n)”, and the data line 14 in the (3n) -th column is denoted by reference numeral “14 (3n)”. ing. 3, the signal line 15 in the (3n) th column is denoted by “15 (3n)” and the feeder line 16 in the (3n) th column is denoted by “16 (3n)” in FIG. The feeder line 17 in the) column is denoted by reference numeral “17 (3n)”, and the signal line 20 in the (3n) column is denoted by reference numeral “20 (3n)”.

  As shown in FIG. 4, a capacitor 44 is provided between the data line 14 (3n) and the power supply line 16 (3n), and between the data line 14 (3n) and the power supply line 17 (3n). Is provided with a capacitor 46. A capacitor 50 is provided between the signal line 15 (3n) and the signal line 20 (3n). The capacitance 44 may be an inter-wiring capacitance between the power supply line 16 (3n) and the data line 14 (3n). Similarly, the capacitor 46 may be an interwiring capacitance between the data line 14 (3n) and the power supply line 17 (3n), and the capacitor 50 may be the signal line 20 (3n) and the signal line 15 (3n). It may be a capacitance between wirings. As shown in FIG. 4, the data line 14 (3n), the signal line 15 (3n), and the signal line 20 (3n) are all connected to the switch unit SW, and the pixel circuit 110 is connected to the signal line 15 (3n). It is connected to the feeder line 16 (3n). In FIG. 3, the switch unit SW connected to the data line 14 (3n) is indicated by a symbol “SW (3n)”, and the demultiplexer DM connected to the switch unit SW (3n) is indicated by a symbol “SW”. DM (n) ".

  First, the configuration of the demultiplexer DM (n) will be described with reference to FIG. As shown in FIG. 3, the demultiplexer DM (n) is an aggregate of transmission gates 34 provided for each column, and sequentially supplies data signals to three columns constituting each group. The input ends of the transmission gates 34 corresponding to the (3n-2), (3n-1), and (3n) columns belonging to the nth group are commonly connected to each other, and the data signal Vd (n) is respectively connected to the common terminal. Supplied. Although not shown in detail in FIG. 3, the output terminal of the transmission gate 34 corresponding to the (3n) column is connected to the input terminal of the switch section SW (3n) via the signal line 18 (3n). Similarly, the output terminal of the transmission gate 34 corresponding to the (3n-1) column is connected to the input terminal of the switch unit SW (3n-1) via the signal line 18 (3n-1), and (3n- 2) The output terminal of the transmission gate 34 corresponding to the column is connected to the input terminal of the switch unit SW (3n-2) via the signal line 18 (3n-2). The transmission gate 34 provided in the (3n-2) column which is the leftmost column in the nth group is when the control signal Sel (1) is at the H level (when the control signal / Sel (1) is at the L level) ) Is turned on (conductive). Similarly, in the n-th group, the transmission gates 34 provided in the (3n-1) column, which is the central column, have the control signal Sel (2) at the H level (the control signal / Sel (2) is at the L level. The transmission gate 34 provided in the (3n) column, which is the rightmost column in the nth group, is turned on when the control signal Sel (3) is at the H level (control signal / Sel (3) Is on).

  Next, the configuration of the switch unit SW (3n) will be described with reference to FIG. As shown in FIG. 4, the switch section SW (3n) includes a capacitor 41, a transmission gate 42, an N-channel MOS transistor 43, and a P-channel MOS transistor 45, and a signal line 18 (3n). The potential of the data signal input via the signal is shifted. As shown in FIG. 4, the data line 14 (3n) is connected to one electrode of the capacitor 41 and is connected to the signal line 18 (3n) at the node h, and the signal line 20 (3n) is connected to the transmission gate 42. It is connected to the output terminal of (switch). A control signal Gcpl and a control signal / Gcpl are supplied from the control circuit 3 to the transmission gate 42. Transmission gate 42 is turned on when control signal Gcpl is at H level (when control signal / Gcpl is at L level). When transmission gate 42 is turned on, signal line 18 (3n) and data line 14 (3n) connected to signal line 18 (3n) at node h are electrically connected to signal line 20 (3n). Is done.

  The drain of the transistor 45 is connected to the signal line 15 (3n), and the source of the transistor 45 is connected to the power supply line 61 to which a predetermined initialization potential Vini is supplied. The control circuit 3 supplies a control signal / Gini to the gate of the transistor 45. The transistor 45 electrically connects the signal line 15 (3n) and the power supply line 61 when the control signal / Gini is at the L level, and electrically disconnects when the control signal / Gini is at the H level. . When the signal line 15 (3n) and the power supply line 61 are electrically connected, the potential of the signal line 15 (3n) becomes the initialization potential Vini.

  The drain of the transistor 43 is connected to the signal line 20 (3n), and the source of the transistor 43 is connected to the power supply line 62 to which the reference potential Vref is supplied. The reference potential Vref is a potential used in the compensation operation for compensating the threshold voltage of the driving transistor of the pixel circuit 110. A control signal Gref is supplied to the gate of the transistor 43. The transistor 43 electrically connects the signal line 20 (3n) and the power supply line 62 when the control signal Gref is at the H level and electrically disconnects when the control signal Gref is at the L level. When the signal line 20 (3n) and the power supply line 62 are electrically connected, the potential of the signal line 20 (3n) becomes the reference potential Vref.

  The other electrode of the capacitor 41 is connected to the feeder line 64. A potential VSS, which is a fixed potential, is supplied to the power supply line 64. Here, the potential VSS may correspond to an L level of a scanning signal or a control signal that is a logic signal. When the transmission gate 34 is turned on while the transmission gate 42 is off, the data signal Vd (n) is supplied to the signal line 18 (3n) from the output end of the transmission gate 34, and the signal is transmitted via the data line 14 (3n). Charges corresponding to the gradation voltage indicated by the data signal Vd (n) are accumulated in the capacitors 41, 44 and 46 connected to the line 18 (3n). That is, the capacitor 41, the capacitor 44, and the capacitor 46 in the (3n) column serve as a storage capacitor that holds a gradation voltage corresponding to the display gradation of the pixel circuit 110 in the (3n) column. When the transmission gate 42 is turned on and the signal line 18 (3n) and the signal line 20 (3n) are electrically connected, the gradation voltages held in the capacitors 41, 44 and 46 are changed to the data lines. 14 (3n), the signal line 18 (3n), the signal line 20 (3n), the capacitor 50, and the signal line 15 (3n) are supplied to the pixel circuit 110 (m, 3n). In other words. The capacitor 50 serves as a transfer capacitor that transfers the grayscale voltages held in the capacitors 41, 44, and 46 to the pixel circuit 110 (3n).

  Next, the configuration of the pixel circuit 110 (m, 3n) will be described with reference to FIG. As shown in FIG. 4, the pixel circuit 110 (m, 3n) includes a first transistor 121, a second transistor 122, a third transistor 123, a fourth transistor 124, and a fifth transistor 125, each of which is a P-channel MOS transistor. , OLED 130, and capacitor 132. Hereinafter, the first transistor 121, the second transistor 122, the third transistor 123, the fourth transistor 124, and the fifth transistor 125 may be collectively referred to as “transistors 121 to 125”.

  The gate of the second transistor 122 is electrically connected to the scanning line 12 (in the case of the pixel circuit 110 (m, 3n), the scanning line 12 in the m-th row). One of the source and the drain of the second transistor 122 is electrically connected to the signal line 15 (3n), and the other is electrically connected to the gate of the first transistor 121 and one electrode of the capacitor 132. Has been. The second transistor 122 functions as a switching transistor that controls electrical connection between the gate of the first transistor 121 and the signal line 15 (3n).

  The source of the first transistor 121 is electrically connected to the feeder line 116. The power supply line 116 is supplied with a potential Vel on the higher side of the power supply in the pixel circuit 110 from a power supply circuit (not shown). The first transistor 121 functions as a driving transistor that causes a current corresponding to the gate voltage to flow through the OLED 130.

  One of the source and the drain of the third transistor 123 is electrically connected to the signal line 15 (3n), and the other is electrically connected to the drain of the first transistor 121. A control signal Gcmp (m) is given to the gate of the third transistor 123. The third transistor 123 is a transistor for conducting between the gate and the source of the first transistor 121 via the signal line 15 (3n) and the second transistor 122. That is, the third transistor 123 functions as a switching transistor that controls electrical connection between the gate and the drain of the first transistor 121.

  The source of the fourth transistor 124 is electrically connected to the drain of the first transistor 121, and the drain of the fourth transistor 124 is electrically connected to the anode of the OLED 130. A control signal Gel (m) is supplied to the gate of the fourth transistor 124. The fourth transistor 124 functions as a light emission control transistor that controls electrical connection between the drain of the first transistor 121 and the anode of the OLED 130, that is, controls light emission or non-light emission of the OLED 130.

  One of the source and the drain of the fifth transistor 125 is electrically connected to the power supply line 16 (3n), that is, the fixed potential line that supplies the reset potential Vorst, and the other is connected to the anode of the OLED 130. A control signal Gorst (m) is supplied to the gate of the fifth transistor 125. The fifth transistor 125 functions as a switching transistor that controls electrical connection between the power supply line 16 (3n) and the anode of the OLED 130.

  In this embodiment, since the display panel 10 is formed on a silicon substrate, the substrate potentials of the transistors 121 to 125 are set to the potential Vel. In addition, the sources and drains of the transistors 121 to 125 in the above may be switched depending on the channel type and potential relationship of the transistors 121 to 125. The transistor may be a thin film transistor or a field effect transistor.

  The capacitor 132 has one electrode electrically connected to the gate of the first transistor 121 and the other electrode electrically connected to the power supply line 116. The capacitor 132 functions as a storage capacitor that holds a gradation voltage supplied via the signal line 15 (3n). As the capacitor 132, a capacitor parasitic to the gate of the first transistor 121 may be used, or a capacitor formed by sandwiching an insulating layer between different conductive layers in a silicon substrate may be used.

  The anode 130 a of the OLED 130 is a pixel electrode provided individually for each pixel circuit 110. On the other hand, the cathode of the OLED 130 is a common electrode 118 provided in common throughout all the pixel circuits 110, and is connected to the power supply line 63. The power supply line 63 is supplied with a potential Vct which is a fixed potential. Here, the potential Vct may correspond to an L level of a scanning signal or a control signal that is a logic signal. The OLED 130 is an element in which a white organic EL layer is sandwiched between the anode 130a of the OLED 130 and a light-transmitting cathode on the silicon substrate. A color filter corresponding to any of RGB is superimposed on the emission side (cathode side) of the OLED 130. Note that the wavelength of light emitted from the OLED 130 may be set by adjusting the optical distance between two reflective layers arranged with the white organic EL layer interposed therebetween to form a cavity structure. In this case, a color filter may or may not be provided.

  When a current flows from the anode 130a to the cathode (common electrode 118) of the OLED 130, holes injected from the anode 130a and electrons injected from the cathode are recombined in the organic EL layer, and excitons are generated. Occurs. The white light generated at this time passes through the cathode opposite to the silicon substrate (anode), and is colored by a color filter so as to be visually recognized by the viewer.

  FIG. 5 is a diagram illustrating a correspondence between the light emitting unit and the circuit unit in the pixel circuit 110. The light emitting unit includes the OLED 130, and the circuit unit includes transistors 121 to 125 and a capacitor 132. In the present embodiment, as shown in FIG. 5, the light emitting units are laid out in a square shape. In FIG. 5, the light emitting portion of the pixel circuit 110 whose emission color is red is “R”, the light emission portion of the pixel circuit 110 whose emission color is green is “G”, and the light emission portion of the pixel circuit 110 whose emission color is blue is Each is indicated by “B”. In FIG. 5, the circuit portion of the pixel circuit 110 whose emission color is red is “RC”, the circuit portion of the pixel circuit 110 whose emission color is green is “GC”, and the circuit portion of the pixel circuit 110 whose emission color is blue is Each is indicated by “BC”. The circuit portions are formed on a one-to-one basis with respect to the light emitting portion, and are laid out in the same square as the light emitting portion. The reason why the layout of the circuit portion is made the same as the layout of the light emitting portion is to avoid the luminance variation caused by the difference between the layouts of the two. In the present embodiment, one dot of a color image is represented by two light emitting portions each having a light emission color of red and one light emission portion having a light emission color of green, and two light emission portions having a light emission color of blue. The reason is as follows. If the light emitting part whose emission color is red or green and the blue light emitting part emit light with the same light emission luminance, the life of the blue light emitting part is shortened. For this reason, it is necessary to suppress the light emission luminance of the blue light emitting portion in order to align the lifetime of the red, green, and blue light emitting portions. Thus, the red or green light emitting portion is suppressed while suppressing the light emission luminance of the blue light emitting portion. The number of blue light emitting portions was increased in order to match the apparent luminance.

  6 is a perspective view showing a planar structure of a circuit portion of the pixel circuit 110, and FIG. 7 is a cross-sectional view showing a cross section taken along the line AA 'in FIG. FIG. 6 illustrates the transistor arrangement in each of the first pixel circuit 110-1 and the second pixel circuit 110-2 arranged in the scanning line direction (X direction). Hereinafter, when it is necessary to distinguish between the transistor included in the first pixel circuit 110-1 and the transistor included in the second pixel circuit 110-2, the two are distinguished by reference numerals with branch numbers. For example, the first transistor 121 of the first pixel circuit 110-1 is referred to as “first transistor 121-1”, and the first transistor 121 of the second pixel circuit 110-2 is “first transistor 121-2”. Is written. The same notation is used for the power supply line 116, the OLED 130, and the capacitor 132. The first transistor 121-1 is a first drive transistor that controls the current flowing through the OLED 130-1 (first light emitting element) according to the first gradation voltage applied to the gate. The first transistor 121-2 is a second drive transistor that controls the current flowing through the OLED 130-2 (second light emitting element) according to the second gradation voltage applied to the gate.

  As shown in FIG. 6, both the first transistor 121-1 and the first transistor 121-2 are arranged in the scanning line direction. That is, the source 121-1S of the first transistor 121-1, the gate 121-1G of the first transistor 121-1, the drain 121-1D of the first transistor 121-1, and the source 121 of the first transistor 121-2. -2S is arranged side by side along the scanning line 12. The power supply line 116-1 connected to the source 121-1 S of the first transistor 121-1 extends in the direction intersecting the scanning line 12 (Y direction), and the source 121-2 S of the first transistor 121-2. The feeder line 116-2 connected to is also extended in the direction intersecting the scanning line 12. In FIG. 6, reference numeral 19-1 indicates a wiring (first wiring) connecting the drain 121-1D of the first transistor 121-1 and the source of the fourth transistor 124-1, and reference numeral 19-2 indicates the first. The wiring line that connects the drain 121-2D of the transistor 121-2 and the source of the fourth transistor 124-2. As apparent from FIG. 6, the wiring 19-1 is provided in the direction (Y direction) intersecting the scanning line 12, and similarly, the wiring 19-2 is provided in the direction intersecting the scanning line 12. ing. As shown in FIG. 6, in the present embodiment, the power supply line 116-1 is provided side by side with the wiring 19-1, and the power supply line 116-2 is provided side by side with the wiring 19-2. As apparent from FIG. 6, the feeder line 116-1 is longer than the wiring 19-1, and the feeder line 116-2 is longer than the wiring 19-2.

  As shown in FIG. 7, the substrate 140 on which the circuit portion is formed includes a first region A01 of the first conductivity type (denoted as P + in FIG. 7) and a second conductivity type (denoted as N + in FIG. 7). The second region A02 and the third region A03 are provided. In the first region A01, the source 121-S and the drain 121-1D of the first transistor 121-1, the source 121-2S of the first transistor 121-2, and the drain 121-2D are formed. The second region A02 is a substrate contact and is supplied with the substrate potential Vel described above. The third region A03 is an insulating region formed by STI (Shallow Trench Isolation) for element isolation.

  As shown in FIG. 7, the first metal layer M01, the capacitor metal layer MC, and the second metal layer M02 to the fifth metal layer M05 are located closer to the substrate side (substrate 140 side) than the light emitting layer where the light emitting unit is formed. Is formed. The first metal layer M01, the third metal layer M03, and the fourth metal layer M04 are wiring layers on which various wirings are formed. In the present embodiment, the power supply line 116-1 and the power supply line 116-2, and the wiring 19-1 and the wiring 19-2 are formed in the first metal layer M01. The power supply line 116-1 is connected to the substrate contact (second region A02) via a contact plug (relay electrode contact plug 150-1). Although not shown in detail in FIG. 7, the power supply line 116-2 is also connected to another substrate contact. The capacitor metal layer MC forms a capacitor 132-1 and a capacitor 132-2 together with the first metal layer M01.

  As shown in FIG. 7, the feed line 116-1 is connected to the source 121-1S of the first transistor 121-1 via the relay electrode 152-1, and the feed line 116-2 is connected to the relay electrode 152-2. To the source 121-2S of the first transistor 121-2. The wiring 19-1 is connected to the drain 121-1D of the first transistor 121-1 via the relay electrode 154-1, and the wiring 19-2 is connected to the first transistor 121-2 via the relay electrode 154-2. Connected to the drain 121-2D.

  In addition, the power supply line 116-1 is connected to the second metal layer M02 provided on the light emitting layer side of the first metal layer via the relay electrode 160-1. The feeder line 116-2 is also connected to the second metal layer M02 via the relay electrode 160-2. The second metal layer M02 is connected to the power supply line 164-1 and the power supply line 164-2 provided in the third metal layer M03 via the relay electrode 162-1 and the relay electrode 162-2. The feed line 164-1 is connected to the feed line 168-1 provided on the fourth metal layer M04 via the relay electrode 166-1, and the feed line 164-2 is connected to the feed electrode 166-2 via the relay electrode 166-2. Are connected to a feeder 168-2 provided in the fourth metal layer M04.

  In the present embodiment, the feeder line 116-2 and the second metal layer serve as a shield that prevents the voltage fluctuation of the drain 121-1D of the first transistor 121-1 from affecting the gate voltage of the first transistor 121-2. Fulfill. For this reason, as shown in FIG. 6, even if the first transistor 121-1 and the first transistor 121-2 are arranged in the scanning line direction, crosstalk does not occur. In the present embodiment, the length of the power supply line 116-2 is made longer than the length of the wiring 19-1 in order to enhance the effect of the shield.

  As described above, according to the present embodiment, it is possible to dispose the driving transistors included in the pixel circuit 110 in the scanning line direction while avoiding the occurrence of crosstalk. Since the driving transistors included in the pixel circuit 110 can be arranged in the scanning line direction, the channel length direction of the driving transistors can be increased, and variations in the driving transistors can be reduced. Further, in this embodiment, since the contact plug to the source of the driving transistor and the substrate contact is used, there is an effect that the layout efficiency is good.

<B: Second Embodiment>
FIG. 8 is a circuit diagram showing a configuration of a pixel circuit 110 ′ of the electro-optical device according to the second embodiment of the present invention. As apparent from the comparison between FIG. 4 and FIG. First, the third transistor 123 is not provided. Second, the drain of the first transistor 121 is connected to the anode 130 a of the OLED 130, and the fourth transistor 124 is provided between the source of the transistor 121 and the feeder line 116. That is, the drain of the fourth transistor 124 is connected to the source of the first transistor 121, and the source of the fourth transistor 124 is connected to the power supply line 116. Third, in addition to the capacitor 132, the capacitor 133 serves as a storage capacitor that holds the gate voltage of the first transistor 121.

  FIG. 9 is a perspective view showing a planar structure of each circuit portion of the first pixel circuit 110′-1 and the second pixel circuit 110′-2 arranged in the scanning line direction. As shown in FIG. 9, in the electro-optical device of the present embodiment, the fourth transistor 124-1 and the first transistor 121-1 are arranged side by side in the scanning line direction, and the fourth transistor 124-2 and the first transistor 122-1 are arranged. Transistors 121-2 are also arranged in the scanning line direction. The power supply line 116-1 connected to the source of the fourth transistor 124-1 extends in the direction intersecting with the scanning line as in the case of the power supply line 116-1 in the first embodiment. Although omitted, it is connected to the second region A02 described above. Similarly, the power supply line 116-2 connected to the source of the fourth transistor 124-2 also extends in the direction intersecting with the scanning line like the power supply line 116-2 in the first embodiment, and the second region described above. Connected to A02.

  Also in this embodiment, the feeder line 116-2, which is a fixed potential line, is provided between the drain of the first transistor 121-1 and the source of the first transistor 121-2. It serves as a shield that prevents the fluctuation of the drain voltage of the transistor 121-1 from affecting the two voltages of the first transistor 121-2. Also according to the embodiment, it is possible to dispose the driving transistors included in the pixel circuit 110 ′ in the scanning line direction while avoiding the occurrence of crosstalk. Since the driving transistors included in the pixel circuit 110 ′ can be arranged in the scanning line direction, the channel length direction of the driving transistors can be increased, and variations in the driving transistors can be reduced.

<C. Modification>
Although one embodiment of the present invention has been described above, the following modifications may be added to this embodiment.
(1) In the first embodiment, the supply voltage functioning as a fixed potential line serving as a shield that prevents the fluctuation of the drain voltage of the first transistor 121-1 from affecting the gate voltage of the first transistor 121-2. The wire 116-2 was connected to the source of the first transistor 121-2. However, the connection of the fixed potential line to the source of the first transistor 121-2 is not always essential. If a fixed potential line extending in a direction crossing the scanning line 12 is provided between the drain of the first transistor 121-1 and the source of the first transistor 121-2, the source of the first transistor 121-2 is fixed to the fixed potential line. This is because it is possible to prevent the fluctuation of the drain voltage of the first transistor 121-1 from affecting the gate voltage of the first transistor 121-2 regardless of whether or not it is connected to. Note that in the case where the fixed potential line is not connected to the source of the first transistor 121-2, a potential different from the potential Vel may be applied to the fixed potential line. In this case, the fixed potential line is connected to the second region of the substrate 140. do not have to. Similarly in the second embodiment, the connection of the fixed potential line to the source of the fourth transistor 124 is not essential.

(2) In the first embodiment, one dot of a color image is formed by one pixel circuit whose emission color is red and one pixel circuit whose emission color is green and two pixel circuits whose emission color is blue. The emission color of one of the two pixel circuits whose emission color is blue may be a color other than blue (for example, yellow). In addition, a display panel with a single color display may be formed by setting all the emission colors of the four pixel circuits forming one pixel to the same color (for example, red). In short, a first pixel circuit and a first pixel circuit each having a light emitting portion laid out in a square shape and a circuit portion laid out in the same square as the light emitting portion are provided along the scanning line, and the first pixel circuit is provided. An electro-optical device in which the driving transistor of the second pixel circuit and the driving transistor of the second pixel circuit are arranged along the scanning line, and a fixed potential line extending in a direction crossing the scanning line is provided between the former drain and the latter source. I just need it.

<D. Application example>
The electro-optical device according to the above-described embodiment can be applied to various electronic devices, and is particularly suitable for an electronic device that is required to display a high-definition image of 2K2K or more and is required to be small. is there. The electronic apparatus according to the present invention will be described below.

  FIG. 10 is a perspective view showing an appearance of a head mounted display 300 as an electronic apparatus employing the electro-optical device of the present invention. As shown in FIG. 11, the head mounted display 300 includes a temple 310, a bridge 320, a projection optical system 301L, and a projection optical system 301R. In FIG. 10, a left-eye electro-optical device (not shown) is provided behind the projection optical system 301L, and a right-eye electro-optical device (not shown) is provided behind the projection optical system 301R. It is done.

  FIG. 11 is a perspective view of a portable personal computer 400 employing the electro-optical device 1 according to the present invention. The personal computer 400 includes the electro-optical device 1 that displays various images, and a main body 403 provided with a power switch 401 and a keyboard 402. The electronic apparatus to which the electro-optical device 1 according to the present invention is applied is arranged close to the eyes such as a digital scope, a digital binocular, a digital still camera, and a video camera in addition to the apparatuses illustrated in FIGS. Electronic equipment to be used. Furthermore, it can be applied as a display unit provided in an electronic device such as a mobile phone, a smart phone, a personal digital assistant (PDA), a car navigation device, and a vehicle-mounted display (instrument panel).

DESCRIPTION OF SYMBOLS 1 ... Electro-optical apparatus, 10 ... Display panel, 3 ... Control circuit, 4 ... Scan line drive circuit, 5 ... Data line drive circuit, 12 ... Scan line, 14 ... Data line, 16, 17, 61, 62, 63, 64, 116 ... feeder line, 118 ... common electrode, 15, 18, 20 ... signal line, 19 ... wiring, 31 ... voltage generation circuit, 41, 44, 46, 50, 132 ... capacity, 34, 42 ... transmission gate, 43, 45, 121, 122, 123, 124, 125 ... transistor, 70 ... data signal supply circuit, 82 ... case, 84 ... FPC board, 86 ... terminal, 100 ... display section, 112 ... display area, 110 ... pixel circuit , 110-1... First pixel circuit, 110-2... Second pixel circuit, 130... OLED, 130a.

Claims (7)

A first light emitting element that is provided corresponding to the scanning line and emits light with a luminance corresponding to the supplied current, and a first driving transistor that controls the current supplied to the first light emitting element according to the first gradation voltage A first pixel circuit comprising:
A second pixel circuit adjacent to the first pixel circuit in the direction of the scanning line, the second light emitting element emitting light with a luminance corresponding to the supplied current; and a current supplied to the second light emitting element. A second pixel circuit having a second driving transistor that is controlled according to the two gradation voltages;
A fixed potential line provided with a fixed potential and provided in a direction crossing the scanning line,
Along the scanning line, the source of the first driving transistor, the gate of the first driving transistor, the drain of the first driving transistor, and the source of the second driving transistor are arranged side by side,
The electro-optical device, wherein the fixed potential line is provided between a drain of the first driving transistor and a source of the second driving transistor. A substrate provided with a first conductivity type first region in which a source of the second drive transistor is formed and a second conductivity type second region different from the first conductivity type;
The electro-optical device according to claim 1, wherein the fixed potential is applied to the second region, and the fixed potential line is connected to the second region. A first wiring connected to the drain of the first driving transistor and extending in a direction crossing the scanning line;
The fixed potential line is provided side by side with the first wiring, and the fixed potential line is longer than the first wiring.
The electro-optical device according to claim 2. A light emitting layer in which the first light emitting element and the second light emitting element are formed;
A first metal layer provided closer to the substrate than the light emitting layer, wherein the first wiring and the fixed potential line are formed;
A second metal layer provided closer to the light emitting layer than the first metal layer;
A relay electrode connecting the fixed potential line and the second metal layer;
The electro-optical device according to claim 3.   The electro-optical device according to claim 1, wherein the fixed potential line is connected to a source of the second drive transistor.   A light emission control transistor for controlling on or off of a current flowing from the second driving transistor to the second light emitting element, a drain connected to a source of the second driving transistor, and a source connected to the fixed potential line; The electro-optical device according to claim 1, further comprising: a light emission control transistor. An electronic apparatus including the electro-optical device according to claim 1.

Images