JP6702352B2 - Electro-optical device and electronic equipment - Google Patents

Description

The present invention relates to an electro-optical device, electronic equipment, and a driving method of an electro-optical device.

In recent years, various electro-optical devices using a light emitting element such as an organic light emitting diode (hereinafter, referred to as OLED (Organic Light Emitting Diode)) element have been proposed. In a general configuration of this electro-optical device, a pixel circuit including a light emitting element, a transistor and the like is provided corresponding to a pixel of an image to be displayed, corresponding to the intersection of the scanning line and the data line.
In such a structure, when a data signal having a potential corresponding to the grayscale level of the pixel is applied to the gate of the transistor, the transistor supplies a current corresponding to the voltage between the gate and the source to the light emitting element. As a result, the light emitting element emits light with a brightness according to the gradation level.

In the driving method in which a transistor is used to adjust the light emission intensity, if the threshold voltage of the transistor provided in each pixel varies, the current flowing through the light emitting element varies, so that the image quality of the display image deteriorates. Therefore, in order to prevent deterioration of image quality, it is necessary to compensate for variations in the threshold voltage of transistors. A period during which an operation related to this compensation (hereinafter, referred to as compensation operation) is performed is called a compensation period. In the compensation period, the drain and the gate of the transistor are connected to a data signal supply line provided for each column, The potential is set to a value corresponding to the threshold voltage of the transistor (see Patent Document 1, for example).

JP, 2013-88611, A

By the way, since the data signal supply line is accompanied by a parasitic capacitance, the parasitic capacitance is also charged or discharged when performing the compensation operation. Then, the compensation period becomes longer by the time required for charging or discharging the parasitic capacitance. Further, if the compensation period is set without considering the time required for charging or discharging the parasitic capacitance associated with the supply line, the compensation in the compensation period becomes insufficient.
The present invention has been made in view of the above-mentioned circumstances, and one of its objects is to realize a high-speed compensation operation for compensating for variations in threshold voltage of a transistor used for adjusting emission intensity.

In order to achieve the above object, an electro-optical device according to an aspect of the present invention includes a scanning line, a first data transfer line, a second data transfer line, and a first data transfer line connected to the first data transfer line. A first capacitor including an electrode and a second electrode connected to the second data transfer line; and a first capacitance that brings the first data transfer line and the second data transfer line into a conductive state or a non-conductive state A pixel circuit provided corresponding to the second data transfer line and the scanning line; and a drive circuit for driving the pixel circuit. The pixel circuit includes a gate electrode and a first current. A driving transistor having an end and a second current terminal, the second data transfer line, a second transistor connected between the gate electrode of the driving transistor, and the first current terminal of the driving transistor. The drive circuit includes a third transistor for electrically connecting the gate electrode of the drive transistor, and a light emitting element that emits light with a brightness according to a magnitude of a current supplied through the drive transistor. During the first period, the first transistor is turned on to bring the first data transfer line and the second data transfer line into conduction, and the second transistor and the third transistor are turned off. An initial potential is supplied to the second data transfer line, and the first transistor is turned off to make the first data transfer line and the second data transfer line non-conductive in a second period following the first period. At the same time, the second transistor and the third transistor are turned on to electrically connect the first current terminal of the driving transistor and the gate electrode of the driving transistor, and the second data transfer line is The above-mentioned second data transfer lines are respectively connected via the first capacitors, and the pixel circuit group is a set of the pixel circuits connected to the same first data transfer line via the second data transfer lines. Then, the second data transfer line is provided for a smaller number of the pixel circuits than the number of the pixel circuits included in the pixel column.

According to this aspect, the second period (compensation period) is shortened as compared with the conventional configuration for the following reason. Here, a set of pixel circuits connected to the same first data transfer line via the second data transfer line and the first capacitor (transfer capacitor) is referred to as a “pixel column”, and the same second data transfer line A group of pixel circuits connected to is called a "block". According to this aspect, the second data transfer line is provided for the number of pixel circuits smaller than the number of pixel circuits included in the pixel column. On the other hand, in the conventional configuration, one first data transfer line and one second data transfer line are provided for one pixel column (all pixel circuits included therein). . Therefore, the second data transfer line is shorter than the conventional configuration. This shortens the time required to charge or discharge the second data transfer line. That is, as compared with the conventional configuration, the time required for charging or discharging the parasitic capacitance associated with the second data transfer line is shortened, and thus the second period (compensation period) is shortened.

An electro-optical device according to another aspect of the present invention is the electro-optical device according to the one aspect, further including a fourth transistor connected between the first current terminal of the drive transistor and the light emitting element. It is characterized by including. According to this aspect, the fourth transistor functions as a switching transistor that controls the electrical connection between the drive transistor and the light emitting element.

An electro-optical device according to another aspect of the present invention is the electro-optical device according to the one aspect, wherein the electro-optical device is connected between a reset potential supply line that supplies a reset potential to the light emitting element and the light emitting element. A fifth transistor is included. According to this aspect, the fifth transistor functions as a switching transistor that controls the electrical connection between the reset potential supply line and the light emitting element.

An electro-optical device according to another aspect of the present invention is the electro-optical device according to the one aspect, wherein the drive circuit turns on the first transistor and the third transistor in a third period following the second period. The second capacitor is turned off and the second transistor is turned on, and the second capacitor for holding the data signal corresponding to the designated gradation is connected to the first data transfer line. According to this aspect, in the third period (writing period), the data signal according to the designated gradation of each pixel is supplied to the pixel circuit via the first data transfer line.

An electro-optical device according to another aspect of the present invention includes a first data transfer line, a second data transfer line, a first electrode connected to the first data transfer line, and a second data transfer line. A first capacitor including a driven second electrode, a driving transistor, a compensator for outputting a potential according to the electrical characteristics of the driving transistor to the second electrode and the second data transfer line, and the data transfer line. And a data transfer line drive circuit that switches the potentials of the data transfer line and the first electrode so that the amount of change in the potential of the first electrode becomes a value according to the gradation level, and the electrical characteristics of the drive transistor. A light emitting element that emits light with a brightness corresponding to the magnitude of the current supplied based on the potential shifted according to the amount of change from the corresponding potential, and the first data transfer line includes M light emitting elements. The second data transfer line is provided for each pixel, and the second data transfer line is divided into K lines, which is a value obtained by dividing M by Nb, and Nb pixels are connected to one second data transfer line. It is characterized by being done.
According to this aspect, for one first data transfer line, K second data transfer lines having a value obtained by dividing M by Nb are provided. Also, the first data transfer line is provided corresponding to the pixel circuits for M rows (M pieces), and the second data transfer line corresponds to the pixel circuits for Nb rows (Nb pieces) that are less than M rows. Will be provided. Therefore, the second data transfer line is shorter than the first data transfer line. This shortens the time required to charge or discharge the second data transfer line. Therefore, compared to the conventional configuration, the time required for charging or discharging the parasitic capacitance associated with the second data transfer line is shortened, and the compensation period itself is shortened.
In order to achieve the above object, an electronic apparatus according to an aspect of the present invention includes the electro-optical device according to any one of the above aspects. According to this aspect, an electronic device including the electro-optical device according to any one of the above aspects is provided.

In order to achieve the above object, a driving method of an electro-optical device according to an aspect of the present invention includes a scanning line, a first data transfer line intersecting the scanning line, a second data transfer line, and the first data transfer line. A first capacitor including a first electrode connected to a data transfer line and a second electrode connected to the second data transfer line, and the first data transfer line and the second data transfer line are electrically connected to each other. A pixel circuit provided corresponding to the second data transfer line and the scanning line, wherein the pixel circuit includes a gate electrode and a first current terminal. And a second transistor connected to the gate electrode of the driving transistor, a driving transistor having a second current terminal, a second transistor connected to the gate electrode of the driving transistor, and a first current terminal of the driving transistor. The first data transfer includes a third transistor for electrically connecting the gate electrode of the driving transistor, and a light emitting element that emits light with a brightness according to a magnitude of a current supplied through the driving transistor. Two or more second data transfer lines are connected to the line via the first capacitors, and the pixel circuit is connected to the same first data transfer line via the second data transfer line. Is a pixel column, the second data transfer line is provided for a smaller number of pixel circuits than the number of pixel circuits included in the pixel column. Then, during the first period, the first transistor is turned on to bring the first data transfer line and the second data transfer line into a conductive state, and the second transistor and the third transistor are turned off. , Supplying an initial potential to the second data transfer line, and turning off the first transistor during a second period following the first period to disconnect the first data transfer line and the second data transfer line from each other. The second transistor and the third transistor are turned on at the same time as the state, and the first current terminal of the drive transistor and the gate electrode of the drive transistor are electrically connected.

According to this aspect, the second period (compensation period) is shortened as compared with the conventional configuration for the following reason. Here, a set of pixel circuits connected to the same first data transfer line via the second data transfer line and the first capacitor (transfer capacitor) is referred to as a “pixel column”, and the same second data transfer line A group of pixel circuits connected to is called a "block". According to this aspect, the second data transfer line is provided for the number of pixel circuits smaller than the number of pixel circuits included in the pixel column. On the other hand, in the conventional configuration, one first data transfer line and one second data transfer line are provided for one pixel column (all pixel circuits included therein). . Therefore, the second data transfer line is shorter than the conventional configuration. This shortens the time required to charge or discharge the second data transfer line. That is, as compared with the conventional configuration, the time required for charging or discharging the parasitic capacitance associated with the second data transfer line is shortened, and thus the second period (compensation period) is shortened.

It is a perspective view showing the composition of the electro-optical device concerning the embodiment of the present invention. It is a block diagram which shows the structure of the same electro-optical device. FIG. 3 is a circuit diagram for explaining configurations of a demultiplexer and a level shift circuit of the same electro-optical device. FIG. 3 is a circuit diagram showing a configuration of a pixel circuit of the same electro-optical device. It is a figure explaining the structure peculiar to the same electro-optical device. It is a figure explaining the conventional structure shown as a comparative example. 3 is a timing chart showing the operation of the same electro-optical device. FIG. 3 is an operation explanatory diagram of the same electro-optical device. FIG. 3 is an operation explanatory diagram of the same electro-optical device. 3 is a timing chart showing the operation of the same electro-optical device. FIG. 3 is an operation explanatory diagram of the same electro-optical device. FIG. 3 is an operation explanatory diagram of the same electro-optical device. It is a circuit diagram which shows the structure of the pixel circuit which concerns on a modification. It is a figure which shows the external appearance structure of HMD. It is a figure which shows the optical structure of HMD.

FIG. 1 is a perspective view showing the configuration of an electro-optical device 1 according to an embodiment of the present invention. The electro-optical device 1 is, for example, a micro display that displays an image on a head mounted display.
As shown in FIG. 1, the electro-optical device 1 includes a display panel 2 and a control circuit 3 that controls the operation of the display panel 2. The display panel 2 includes a plurality of pixel circuits and a drive circuit that drives the pixel circuits. In the present embodiment, the plurality of pixel circuits and drive circuits included in the display panel 2 are formed on a silicon substrate, and an OLED that is an example of a light emitting element is used for the pixel circuits. The display panel 2 is housed in, for example, a frame-shaped case 82 that opens in the display section, and one end of an FPC (Flexible Printed Circuits) substrate 84 is connected to the display panel 2.
The control circuit 3 of the semiconductor chip is mounted on the FPC board 84 by COF (Chip On Film) technology, and a plurality of terminals 86 are provided to be connected to an upper circuit (not shown).

FIG. 2 is a block diagram showing the configuration of the electro-optical device 1 according to the embodiment. As described above, the electro-optical device 1 includes the display panel 2 and the control circuit 3.
Digital image data Video is supplied to the control circuit 3 from a higher-order circuit (not shown) in synchronization with the synchronization signal. Here, the image data Video is data that defines the gradation level of the pixel of the image to be displayed on the display panel 2 (strictly speaking, the display unit 100 described later) with, for example, 8 bits. The sync signal is a signal including a vertical sync signal, a horizontal sync signal, and a dot clock signal.

The control circuit 3 generates various control signals based on the synchronization signal and supplies the control signals to the display panel 2. Specifically, for the display panel 2, the control circuit 3 controls the control signal Ctr, the control signal Gini of positive logic, the control signal /Gini of negative logic which is in a logical inversion relation with this, and the control signal of positive logic. The control signal Gcpl, the negative logic control signal /Gcpl which is in the logical inversion relation with the control signal Gcpl, the control signals Sel(1), Sel(2) and Sel(3), and the inversion relation of these signals. Control signals /Sel(1), /Sel(2), /Sel(3) at
Here, the control signal Ctr is a signal including a plurality of signals such as a pulse signal, a clock signal, and an enable signal.
The control signals Sel(1), Sel(2), and Sel(3) are collectively referred to as the control signal Sel, and the control signals /Sel(1), /Sel(2), and /Sel(3) are referred to as control signals. /Sel may be collectively referred to.
The control circuit 3 also includes a voltage generation circuit 31. The voltage generation circuit 31 supplies various potentials to the display panel 2. Specifically, the control circuit 3 supplies the reset potential Vorst, the initial potential Vini, and the like to the display panel 2.

Further, the control circuit 3 generates an analog image signal Vid based on the image data Video. Specifically, the control circuit 3 is provided with a look-up table that stores the potential indicated by the image signal Vid and the brightness of the light emitting element (OLED 130 described later) included in the display panel 2 in association with each other. Then, the control circuit 3 refers to the lookup table to generate an image signal Vid indicating a potential corresponding to the luminance of the light emitting element defined by the image data Video, and supplies this to the display panel 2. To do.

As shown in FIG. 2, the display panel 2 includes a display unit 100 and a drive circuit (data transfer line drive circuit 10 and scanning line drive circuit 20) that drives the display unit 100.
In the display unit 100, pixel circuits 110 corresponding to the pixels of the image to be displayed are arranged in a matrix. Specifically, in the display unit 100, M rows of scanning lines 12 are provided extending in the horizontal direction (X direction) in the drawing, and the first data of (3N) columns that are grouped every three columns. The transfer line 14-1 extends in the vertical direction (Y direction) in the drawing and is provided so as to be electrically insulated from each scanning line 12.
Although not shown in FIG. 2 in order to avoid complication of the drawing, the second data transfer line 14-2 can be electrically connected to each first data transfer line 14-1. Further, it is provided so as to extend in the vertical direction (Y direction) (see, for example, FIG. 4 ). The pixel circuit 110 is provided corresponding to the M rows of scanning lines 12 and the (3N)th columns of the second data transfer lines 14-2. For this reason, in the present embodiment, the pixel circuits 110 are arranged in a matrix with M rows vertically and 3N columns horizontally.

Here, both M and N are natural numbers. In order to distinguish rows in the matrix of the scanning lines 12 and the pixel circuits 110, they may be referred to as 1, 2, 3,..., (M−1)M rows in order from the top in the drawing. Similarly, in order to distinguish the columns (columns) of the matrix of the first data transfer line 14-1 and the pixel circuit 110, the columns 1, 2, 3,..., (3N-1), (3N) columns from the left in the figure. Sometimes called.
Here, in order to generalize and describe the group of the first data transfer lines 14-1, if an arbitrary integer of 1 or more is represented by n, the nth group counted from the left is (3n-2). This means that the first data transfer lines 14-1 of the (3n−1)th column and the (3n)th column belong.

The three pixel circuits 110 corresponding to the scanning lines 12 in the same row and the second data transfer lines 14-2 in the three columns belonging to the same group are R (red), G (green), and B (blue), respectively. ), these three pixels represent one dot of the color image to be displayed. That is, in the present embodiment, the color of one dot is expressed by the additive color mixture by the light emission of the OLED corresponding to RGB.

Further, as shown in FIG. 2, in the display unit 100, the power supply lines (reset potential supply lines) 16 in the (3N)th column extend in the vertical direction and are electrically insulated from each scanning line 12. It is kept and provided. A predetermined reset potential Vorst is commonly supplied to each power supply line 16. Here, in order to distinguish the rows of the power supply lines 16, they may be referred to as the first, second, third,... Each of the power supply lines 16 in the first to (3N)th columns corresponds to each of the first data transfer lines 14-1 (second data transfer lines 14-2) in the first to (3N)th columns. Is provided.

The scanning line driving circuit 20 generates a scanning signal Gwr for sequentially scanning the M scanning lines 12 row by row within a period of one frame according to the control signal Ctr. Here, the scanning signals Gwr supplied to the scanning lines 12 in the first, second, third,..., Mth rows are respectively Gwr(1), Gwr(2), Gwr(3),..., Gwr(M-1 ), Gwr(M).
In addition to the scanning signals Gwr(1) to Gwr(M), the scanning line driving circuit 20 generates various control signals synchronized with the scanning signal Gwr for each row and supplies them to the display unit 100. Illustration is omitted in FIG. The frame period is a period required for the electro-optical device 1 to display an image for one cut (frame). For example, if the frequency of the vertical synchronizing signal included in the synchronizing signal is 120 Hz, the The period is 8.3 milliseconds.

The data transfer line drive circuit 10 includes (3N) level shift circuits LS provided in a one-to-one correspondence with each of the (3N) columns of the first data transfer lines 14-1, and three columns forming each group. The N number of demultiplexers DM provided for each of the first data transfer lines 14-1 and the data signal supply circuit 70.

The data signal supply circuit 70 generates data signals Vd(1), Vd(2),..., Vd(N) based on the image signal Vid and the control signal Ctr supplied from the control circuit 3. That is, the data signal supply circuit 70 uses the data signals Vd(1), Vd(2),..., Vd(N) as time-division multiplexed image signals Vid based on the data signals Vd(1), Vd(2). ,..., Vd(N) is generated. Then, the data signal supply circuit 70 supplies the data signals Vd(1), Vd(2),..., Vd(N) to the demultiplexers DM corresponding to the 1, 2,. Supply.

FIG. 3 is a circuit diagram for explaining the configurations of the demultiplexer DM and the level shift circuit LS. 3 representatively shows the demultiplexer DM belonging to the n-th group and the three level shift circuits LS connected to the demultiplexer DM. In the following, the demultiplexer DM belonging to the nth group may be referred to as DM(n).

The configurations of the demultiplexer DM and the level shift circuit LS will be described below with reference to FIG. 3 in addition to FIG.
As shown in FIG. 3, the demultiplexer DM is an assembly of transmission gates 34 provided for each column, and sequentially supplies a data signal to the three columns forming each group. Here, the input ends of the transmission gates 34 corresponding to the (3n-2), (3n-1), and (3n) columns belonging to the n-th group are commonly connected to each other, and the data signal Vd( n) is supplied. When the control signal Sel(1) is at the H level (when the control signal /Sel(1) is at the L level), the transmission gate 34 provided in the leftmost column (3n-2) in the n-th group is ) On (conducting). Similarly, the transmission gates 34 provided in the (3n-1)th column, which is the central column in the nth group, have the control signal Sel(2) at the H level (the control signal /Sel(2) at the L level). When the control signal Sel(3) is at H level (control signal /Sel(3)), the transmission gate 34 provided in the rightmost column (3n) in the n-th group Is at the L level).

The level shift circuit LS has a set of a storage capacitor (second capacitor) 41, a transmission gate 45, and a transmission gate 42 for each column, and the potential of the data signal output from the output end of the transmission gate 34 of each column. Is to shift.

The source or drain of the transmission gate 45 of each column is electrically connected to the first data transfer line 14-1. Further, the control circuit 3 commonly supplies the control signal /Gini to the gates of the transmission gates 45 in each column. The transmission gate 45 electrically connects the first data transfer line 14-1 and the supply line of the initial potential Vini when the control signal /Gini is at L level, and when the control signal /Gini is at H level. Electrically disconnected. A predetermined initial potential Vini is supplied from the control circuit 3 to the supply line 61 of the initial potential Vini.

The storage capacitor 41 has two electrodes. One electrode of the storage capacitor 41 is electrically connected to the input end of the transmission gate 42 via the node h. The output end of the transmission gate 42 is electrically connected to the first data transfer line 14-1.
The control circuit 3 commonly supplies the control signal Gcpl and the control signal /Gcpl to the transmission gates 42 in each column. Therefore, the transmission gates 42 in each column are turned on all at once when the control signal Gcpl is at the H level (when the control signal /Gcpl is at the L level).

One electrode of the storage capacitor 41 in each column is electrically connected to the output end of the transmission gate 34 and the input end of the transmission gate 42 via the node h. Then, when the transmission gate 34 is turned on, the data signal Vd(n) is supplied to one electrode of the storage capacitor 41 via the output end of the transmission gate 34. That is, the storage capacitor 41 is supplied with the data signal Vd(n) at one electrode.
The other electrode of the storage capacitor 41 in each column is commonly connected to the power supply line 63 to which the potential Vss which is a fixed potential is supplied. Here, the potential Vss may correspond to the L level of the scanning signal or the control signal which is a logical signal. The capacity value of the storage capacitor 41 is Crf.

The pixel circuit 110 and the like will be described with reference to FIG. In order to generally indicate the rows in which the pixel circuits 110 are arranged, an arbitrary integer of 1 or more and M or less is represented by m. Further, arbitrary integers that are 1 or more and M or less and are continuous are represented as m1 and m2. That is, m is a generalized concept including m1 and m2.
Since the pixel circuits 110 are electrically identical in configuration to each other, here, the m-th row is located in the m-th row and is located in the (3n−2)-th column in the leftmost column of the n-th group. The pixel circuit 110 of the (3n−2) column will be described as an example.

As shown in FIG. 4, the first electrode 133-1 of the transfer capacitance (first capacitance) 133 and one of the source and the drain of the first transistor 126 are electrically connected to the first data transfer line 14-1. It is connected. The second electrode 133-2 of the transfer capacitor 133 and the other of the source and the drain of the first transistor 126 are electrically connected to the second data transfer line 14-2.
That is, the transfer capacitor 133 and the first transistor 126 are connected in parallel between the first data transfer line 14-1 and the second data transfer line 14-2.
Further, the pixel circuit 110 is connected to the second data transfer line 14-2. That is, the pixel circuit 110 is supplied with the gradation potential according to the specified gradation via the first data transfer line 14-1 and the second data transfer line 14-2.

Specifically, Nb pixel circuits 110 are electrically connected to one second data transfer line 14-2. In the present embodiment, Nb=2, and as shown in FIG. 4, the pixel circuit 110 in the m1th row and the pixel circuit 110 in the m2th row are connected to one second data transfer line 14-2. To be done.
That is, in the present embodiment, the two pixel circuits 110 share one second data transfer line 14-2, one transfer capacitor 133, and the first transistor 126.
Here, the number (Nb) of pixel circuits 110 connected to one second data transfer line 14-2 is not limited to two, and may be any number of one or more. The matters to be considered when determining Nb will be described in detail later.
FIG. 5 is a diagram for explaining a configuration unique to this embodiment. In the present embodiment, two or more second data transfer lines 14-2 are connected to the first data transfer line 14-1 via transfer capacitors 133, respectively, as shown in FIG.
Here, a set of pixel circuits 110 connected to the same first data transfer line 14-1 via the second data transfer line 14-2 and the transfer capacitor 133 is referred to as a “pixel column” (in FIG. 5). Pixel row L). Further, a set of pixel circuits 110 connected to the same second data transfer line 14-2 is referred to as a “block” (block B in FIG. 5).
As shown in FIG. 5, the pixel column L includes a plurality of blocks B, and each block B includes a plurality of pixel circuits 110. That is, in the present embodiment, the second data transfer line 14-2 is provided for the number of pixel circuits 110 that is smaller than the number of pixel circuits 110 included in the pixel column L.
On the other hand, the conventional configuration is shown in FIG. FIG. 6 is a diagram illustrating a conventional configuration shown as a comparative example. As shown in the figure, in the conventional configuration, the second data transfer line 14-2 is provided for the pixel column L, and the transfer capacitor 133 and the first data transfer line 14-1 are provided at the ends thereof. ing. That is, in the conventional configuration, one first data transfer line 14-1 and one second data transfer line 14-2 are provided for (one of all the pixel circuits 110 included in) one pixel column L. Is provided. This point is that a configuration peculiar to the present embodiment described with reference to FIG. 5, that is, a plurality of second data transfer lines 14-2 are provided by being divided in units of blocks B constituting the pixel column L. Clearly different.

By the way, as shown in the following (Formula 1), the total number M of rows of the pixel circuits 110 in the display unit 10 is set to the number Nb of rows of the pixel circuits 110 connected to one second data transfer line 14-2. The value divided by is K. In other words, the second data transfer line 14-2 is divided into K lines, which is a value obtained by dividing M by Nb, and Nb pixel circuits 110 are connected to one second data transfer line 14-2. It is supposed to be done.

In the present embodiment, K (K≧2) second data transfer lines 14-2 are provided for one first data transfer line 14-1. In other words, one pixel column L includes K blocks B. The first data transfer line 14-1 is provided corresponding to the pixel circuits 110 for M rows (M pieces), and the second data transfer line 14-2 is provided for the pixel circuits for Nb rows (Nb pieces). It is provided corresponding to 110. Therefore, the second data transfer line 14-2 is shorter than the first data transfer line 14-1.
In this embodiment, the value of Nb is 2. Note that k is used as an arbitrary integer of 1 or more and K or less.
Hereinafter, as shown in FIG. 4, it is assumed that the first transistor 126 corresponding to the block including the m1th row and the m2th row is the kth first transistor 126 counted from the first row, and the control signal Gfix(k) Is supplied.

The pixel circuit 110 includes P-channel MOS type transistors 121 to 125, an OLED 130, and a pixel capacitor 132. The scanning signal Gwr(m), control signals Gcmp(m), Gel(m), and Gorst(m) are supplied to the pixel circuit 110 in the m-th row. Here, the scanning signal Gwr(m), the control signals Gcmp(m), Gel(m), and Gorst(m) are each supplied by the scanning line drive circuit 20 corresponding to the m-th row.

Although not shown in FIG. 2, as shown in FIG. 4, the display panel 2 (display unit 100) has M rows of control lines 143 (first control lines) extending in the horizontal direction (X direction), M rows of control lines 144 (second control lines) extending in the horizontal direction, M rows of control lines 145 (third control lines) extending in the horizontal direction, and K rows of control lines 146 extending in the horizontal direction. (Fourth control line) is provided.

Then, the scanning line drive circuit 20 supplies the control signal Gcmp(m) to the control line 143 of the m-th row and the control signal Gel(m) to the control line 144 of the m-th row, The control signal Gorst(m) is supplied to the control line 145 of the row and the control signal Gfix(k) is supplied to the control line 146 of the kth row.
That is, the scanning line drive circuit 20 supplies the scanning signal Gwr(m), the control signal Gel(m), Gcmp(m), and Gorst(m) to the pixel circuit located in the m-th row in the m-th row. It is supplied through the eye scanning line 12 and the control lines 143, 144, and 145. Further, the control signal Gfix(k) is supplied to the first transistor 126 located in the kth row via the control line 146 in the kth row.
Hereinafter, the scanning line 12, the control line 143, the control line 144, the control line 145, and the control line 146 may be collectively referred to as a “control line”. That is, the display panel 2 according to the present embodiment is provided with four control lines including the scanning lines 12 in each row and one control line 146 for each Nb row.

The pixel capacitor 132 and the transfer capacitor 133 each have two electrodes. The transfer capacitance 133 is an electrostatic capacitance including the first electrode 133-1 and the second electrode 133-2.
The second transistor 122 has a gate electrically connected to the m-th scanning line 12 and one of a source and a drain electrically connected to the second data transfer line 14-2. The other of the source and the drain of the second transistor 122 is electrically connected to the gate of the driving transistor 121 and one electrode of the pixel capacitor 132, respectively. That is, the second transistor 122 is electrically connected between the gate of the driving transistor 121 and the second electrode 133-2 of the transfer capacitor 133. The second transistor 122 is electrically connected between the gate of the driving transistor 121 and the second electrode 133-2 of the transfer capacitor 133 connected to the second data transfer line 14-2 of the (3n−2)th column. Functions as a transistor that controls the electrical connection.

The driving transistor 121 has a source electrically connected to the power supply line 116, and a drain electrically connected to one of a source and a drain of the third transistor 123 and a source of the fourth transistor 124.
Here, the power supply line 116 is supplied with the potential Vel which is the higher side of the power supply in the pixel circuit 110. The drive transistor 121 functions as a drive transistor that supplies a current according to the voltage between the gate and the source of the drive transistor 121.
The gate of the third transistor 123 is electrically connected to the control line 143, and the control signal Gcmp(m) is supplied. The third transistor 123 functions as a switching transistor that controls the electrical connection between the gate and drain of the driving transistor 121. Therefore, the third transistor 123 is a transistor for electrically connecting the gate and drain of the driving transistor 121 via the second transistor 122. Although the second transistor 122 is connected between one of the source and drain of the third transistor 123 and the gate of the driving transistor 121, one of the source and the drain of the third transistor 123 is connected to the driving transistor 121. It can also be interpreted as being electrically connected to the gate.

The gate of the fourth transistor 124 is electrically connected to the control line 144, and the control signal Gel(m) is supplied to the fourth transistor 124. The drain of the fourth transistor 124 is electrically connected to the source of the fifth transistor 125 and the anode 130a of the OLED 130, respectively. The fourth transistor 124 functions as a switching transistor that controls the electrical connection between the drain of the driving transistor 121 and the anode of the OLED 130. Furthermore, although the fourth transistor 124 is connected between the drain of the driving transistor 121 and the anode of the OLED 130, the drain of the driving transistor 121 can be interpreted as being electrically connected to the anode of the OLED 130.
A gate of the fifth transistor 125 is electrically connected to the control line 145, and the control signal Gorst(m) is supplied to the fifth transistor 125. The drain of the fifth transistor 125 is electrically connected to the power supply line 16 of the (3n−2)th column and is kept at the reset potential Vorst. The fifth transistor 125 functions as a switching transistor that controls the electrical connection between the power supply line 16 and the anode 130a of the OLED 130.

The gate of the first transistor 126 is electrically connected to the control line 146, and the control signal Gfix(k) is supplied to the first transistor 126. One of the source and the drain of the first transistor 126 is electrically connected to the second data transfer line 14-2, and the second electrode 133- of the transfer capacitor 133 is connected via the second data transfer line 14-2. It is electrically connected to the other of the source and the drain of the second and third transistors 123. The other of the source and the drain of the first transistor 126 is electrically connected to the first data transfer line 14-1 of the (3n−2)th column.
The first transistor 126 mainly functions as a switching transistor that controls the electrical connection between the first data transfer line 14-1 and the second data transfer line 14-2.
Here, the first transistor 126 and the transfer capacitor 133 are shared by the Nb pixel circuits 110 connected to the same second data transfer line 14-2. In the present embodiment, as shown in FIG. 4, the pixel circuit 110 of the m1th row and the pixel circuit 110 of the m2th row are shared by the two pixel circuits 110.

Since the display panel 2 is formed on the silicon substrate in this embodiment, the substrate potential of the transistors 121 to 126 is set to the potential Vel. Further, the sources and drains of the transistors 121 to 126 in the above may be replaced with each other depending on the relationship between the channel types of the transistors 121 to 126 and potentials. The transistor may be a thin film transistor or a field effect transistor.

The pixel capacitor 132 has one electrode electrically connected to the gate g of the driving transistor 121 and the other electrode electrically connected to the power supply line 116. Therefore, the pixel capacitor 132 functions as a storage capacitor that holds the gate-source voltage of the drive transistor 121. The capacitance value of the pixel capacitance 132 is expressed as Cpix.
As the pixel capacitor 132, a capacitor parasitic on the gate g of the driving transistor 121 may be used, or a capacitor formed by sandwiching an insulating layer between conductive layers different from each other on a silicon substrate may be used.

The anode 130 a of the OLED 130 is a pixel electrode provided individually for each pixel circuit 110. On the other hand, the cathode of the OLED 130 is the common electrode 118 that is commonly provided over the entire pixel circuit 110, and is maintained at the potential Vct that is the lower side of the power supply in the pixel circuit 110. The OLED 130 is an element in which a white organic EL layer is sandwiched between an anode 130a and a light-transmitting cathode on the silicon substrate. Then, on the emission side (cathode side) of the OLED 130, a color filter corresponding to any of RGB is overlaid. Note that the wavelength of light emitted from the OLED 130 may be set by adjusting the optical distance between the two reflective layers arranged with the white organic EL layer interposed therebetween to form a cavity structure. In this case, the color filter may or may not be provided.

In such an OLED 130, when a current flows from the anode 130a to the cathode, holes injected from the anode 130a and electrons injected from the cathode are recombined in the organic EL layer to generate excitons, and white light is emitted. Occur. The white light generated at this time passes through the cathode on the side opposite to the silicon substrate (anode 130a), is colored by the color filter, and is visually recognized by the observer.

The operation of the electro-optical device 1 will be described with reference to FIG. 7. FIG. 7 is a timing chart for explaining the operation of each unit in the electro-optical device 1. As shown in this figure, the scanning line drive circuit 20 sequentially switches the scanning signals Gwr(1) to Gwr(M) to the L level, and sets the scanning lines 12 of the 1st to Mth rows to 1 in the period of one frame. Scanning is performed in sequence for each horizontal scanning period (H).
The operation in one horizontal scanning period (H) is common to the pixel circuits 110 in each row. Therefore, in the following, the operation will be described with particular attention paid to the pixel circuit 110 in the m1 row (3n−2) column in the horizontal scanning period in which the m1 row is horizontally scanned.

In the present embodiment, the horizontal scanning period of the m1th row is roughly divided into a compensation period shown in FIG. 7C and a writing period shown in FIG. The period other than the horizontal scanning period is divided into a light emission period shown in (a) and an initialization period shown in (b). Then, after the writing period of (d), the light emitting period shown in (a) again starts, and after the period of one frame elapses, the horizontal scanning period of the m1th row again occurs. Therefore, in the order of time, the cycle of light emission period→initialization period→compensation period→writing period→light emission period is repeated.

Hereinafter, for convenience of description, the light emitting period which is a prerequisite of the initialization period will be described. FIG. 8 is a diagram illustrating the operation of the pixel circuit 110 and the like during the light emission period. Note that in FIG. 8, a current path that is important in the description of the operation is indicated by a thick line, and an "X" mark is indicated by a thick line on the transistor or the transmission gate in the off state (FIG. 9, FIG. 11, below). And also in FIG. 12).

<Light emitting period>
As shown in the timing chart of FIG. 7, in the light emission period of the m1th row, the scanning signal Gwr(m1) is at H level, the control signal Gel(m1) is at L level, and the control signal Gcmp(m1) is at It is H level, and the control signal Gfix(k) is H level.
Therefore, in the pixel circuit 110 in the m1 row (3n−2) column as shown in FIG. 8, the fourth transistor 124 is turned on while the transistors 122, 123, 125, 126 are turned off. As a result, the drive transistor 121 supplies the OLED 130 with the drive current Ids corresponding to the voltage held by the pixel capacitor 132, that is, the gate-source voltage Vgs. That is, the OLED 130 is supplied with a current according to the gradation potential according to the specified gradation of each pixel by the drive transistor 121, and emits light with a brightness according to the current.

Here, in the level shift circuit LS during the light emission period, the control signal /Gini is at the H level, so the transmission gate 45 is turned off as shown in FIG. 8, and the control signal Gcpl is at the L level. As described above, the transmission gate 42 is turned off. In the demultiplexer DM(n) during the light emission period, the control signal Sel(1) becomes L level, so the transmission gate 34 is turned off.

Note that the light emission period of the m1th row is a period in which the rows other than the m1th row are horizontally scanned. , The potentials of the first data transfer line 14-1 and the second data transfer line 14-2 change appropriately. However, in the pixel circuit 110 on the m1th row, the second transistor 122 is off, so here, the potential fluctuations of the first data transfer line 14-1 and the second data transfer line 14-2 are taken into consideration. Absent.

<Initialization period>
Next, the initialization period of the m1th row starts. As shown in FIG. 7, in the initialization period of the m1th row, the scanning signal Gwr(m1) is at H level, the control signal Gel(m1) is at H level, and the control signal Gcmp(m1) is at H level. And the control signal Gfix(k) is at L level.
Therefore, as shown in FIG. 9, in the pixel circuit 110 in the m1 row (3n−2) column, the transistors 125 and 126 are turned on, while the transistors 122, 123 and 124 are turned off. As a result, the path of the current supplied to the OLED 130 is cut off, so that the OLED 130 is turned off (non-emission).

Here, in the level shift circuit LS in the initialization period, the control signal /Gini becomes L level, so the transmission gate 45 is turned on as shown in FIG. 9, and the control signal Gcpl becomes L level, so that it is shown in FIG. As described above, the transmission gate 42 is turned off. Therefore, as shown in FIG. 9, the first data transfer line 14-1 connected to the first electrode 133-1 of the transfer capacitor 133 is set to the initial potential Vini, and the first transistor 126 is turned on. Therefore, the first data transfer line 14-1 and the second data transfer line 14-2 are electrically connected, and the second electrode 133-2 of the transfer capacitor 133 is also set to the initial potential Vini. As a result, the transfer capacity 133 is initialized.

In the demultiplexer DM(n) in the initialization period, the control signal Sel(1) becomes H level, so that the transmission gate 34 is turned on as shown in FIG. As a result, the gradation potential is written in the storage capacitor 41 having the capacitance value Crf.

By the way, in the present embodiment, as shown in FIG. 9, the second data transfer line 14-2 to which the pixel circuit 110 in the m1 row (3n−2) column is connected is in the m2 row (3n−2) column. The pixel circuit 110 is also connected. Therefore, the first transistor 126 controlled by the control signal Gfix(k) used in the initialization period of the m1th row is also used in the initialization period of the m2th row as shown in FIG.

<Compensation period>
When the initialization period of (b) is finished, the horizontal scanning period starts. First, the compensation period of (c) shown in FIG. 7 starts. In the compensation period of the m1th row, the scanning signal Gwr(m1) is at L level, the control signal Gel(m1) is at H level, the control signal Gcmp(m1) is at L level, and the control signal Gfix(k). Is at the H level.
Therefore, as shown in FIG. 11, in the pixel circuit 110 in the m1 row (3n−2) column, the transistors 122, 123, and 125 are turned on, while the fourth transistors 124 and 126 are turned off. At this time, the gate g of the driving transistor 121 is connected (diode-connected) to its own drain through the second transistor 122 and the third transistor 123, and a drain current flows through the driving transistor 121 to charge the gate g. ..
That is, the drain and gate g of the drive transistor 121 are connected to the second data transfer line 14-2, and when the threshold voltage of the drive transistor 121 is Vth, the potential Vg of the gate g of the drive transistor 121 is (Vel− Asymptotically approaching Vth).

Here, in the level shift circuit LS of the compensation period, the control signal /Gini becomes L level, so that the transmission gate 45 is turned on and the control signal Gcpl becomes L level as shown in FIG. The transmission gate 42 is turned off as shown in FIG. At this time, as described above, since the second data transfer line 14-2 is shorter than the conventional configuration, the time required to charge or discharge the parasitic capacitance associated with the second data transfer line 14-2 is shortened. , The compensation period itself is shortened.

Further, in the demultiplexer DM(n) during the compensation period, the control signal Sel(1) becomes H level, so that the transmission gate 34 is turned on as shown in FIG. As a result, the gradation potential is written in the storage capacitor 41 having the capacitance value Crf.

Since the fourth transistor 124 is off, the drain of the driving transistor 121 is not electrically connected to the OLED 130. Further, as in the initialization period, the fifth transistor 125 is turned on to electrically connect the anode 130a of the OLED 130 and the power supply line 16, and the potential of the anode 130a is set to the reset potential Vorst.

<Writing period>
In the horizontal scanning period of the m1th row, when the above-mentioned compensation period of (c) is finished, the writing period of (d) starts. In the writing period of the m1th row, the scanning signal Gwr(m1) is at the L level, the control signal Gel(m1) is at the H level, the control signal Gcmp(m1) is at the H level, and the control signal Gfix(k ) Is the H level.
Therefore, as shown in FIG. 12, in the pixel circuit 110 in the m1 row (3n−2) column, the transistors 122 and 125 are turned on, while the transistors 123, 124 and 126 are turned off.

Here, in the level shift circuit LS in the writing period, since the control signal /Gini becomes H level, the transmission gate 45 is turned off and the control signal Gcpl becomes H level as shown in FIG. The transmission gate 42 is turned on as indicated by 12. For this reason, the supply of the initial potential Vini to the first data transfer line 14-1 and the first electrode 133-1 is released, and the capacitance with respect to the first data transfer line 14-1 and the first electrode 133-1. One electrode of the storage capacitor 41 having the value Crf is connected, and the gradation potential is supplied to the first electrode 133-1. Then, the signal in which the gradation potential is level-shifted is supplied to the gate of the driving transistor 121 and written in the pixel capacitance Cpix.
In the demultiplexer DM(n) in the writing period, the control signal Sel(1) becomes L level, so that the transmission gate 34 is turned off as shown in FIG.

Since the fourth transistor 124 is off, the drain of the driving transistor 121 is not electrically connected to the OLED 130. Further, as in the initialization period, the fifth transistor 125 is turned on to electrically connect the anode 130a of the OLED 130 to the power supply line 16, and the potential of the anode 130a is initialized to the reset potential Vorst.

In the writing period of the m-th row, the control circuit 3 in the n-th group, in order of the data signal Vd(n), the m-th row (3n−2) column, the m-th row (3n−1). The potential is switched to a potential according to the gradation level of the pixel in the column and the row m (3n).
On the other hand, the control circuit 3 sets the control signals Sel(1), Sel(2), and Sel(3) to the H level in sequence in synchronization with the switching of the potential of the data signal. Although not shown in the figure, the control circuit 3 has control signals /Sel(1), /Sel(2) which are in a logical inversion relationship with the control signals Sel(1), Sel(2), Sel(3). , /Sel(3) is also output. As a result, in the demultiplexer DM, the transmission gates 34 in each group are turned on in the order of the left end column, the center column, and the right end column.

ここでΔＶとΔＶｇとの比を、下記の(式３）で示すように圧縮率Ｒとする。

つまり、書込期間における駆動トランジスター１２１のゲートｇの電位Ｖｇは、補償期間における電位Ｖｇから、第１データ転送線１４−１及び第１電極１３３−１の電位の変化量ΔＶに対して、Ｒを乗じた値だけレベルシフトした（データ圧縮された）値となる。この書込期間を終えると、上述した（ａ）の発光期間が開始する。 By the way, when the transmission gate 34 in the leftmost column is turned on by the control signals Sel(1) and /Sel(1), the change amount of the potentials of the first data transfer line 14-1 and the first electrode 133-1 is ΔV. , The change amount ΔVg of the potential of the second data transfer line 14-2 and the gate g of the driving transistor 121 can be expressed by the following (formula 2). However, the capacitance value C1 of the transfer capacitance 133 can be adjusted in proportion to the number of rows of the pixel circuit 110, and is the capacitance C1a per row. The capacitance value of the parasitic capacitance associated with the second data transfer line 14-2 per row is C3a. Further, as described above, the number of rows of the pixel circuit 110 connected to the one second data transfer line 14-2 is represented by Nb.

Here, the ratio of ΔV and ΔVg is the compression ratio R as shown in the following (formula 3).

That is, the potential Vg of the gate g of the drive transistor 121 in the writing period is R from the potential Vg in the compensation period with respect to the variation amount ΔV of the potentials of the first data transfer line 14-1 and the first electrode 133-1. It is a value that is level-shifted (data compressed) by a value multiplied by. When the writing period ends, the above-described light emitting period (a) starts.

From the relationship shown in (Equation 2) described above, the larger the number Nb of pixel circuits 110 connected to one second data transfer line 14-2, the more the number Nb of pixel circuits 110 included in one block becomes. The larger the value is, the closer ΔVg and ΔV are. In other words, as the value of Nb is larger, R shown in (Equation 4) approaches 1.
Here, the number Nb of pixel circuits 110 connected to the second data transfer line 14-2 (the number Nb of pixel circuits 110 included in one block) is the time required to complete the compensation operation and the compression rate of data compression. It is preferable to decide in consideration of The details will be described below.
First, the time required to complete the compensation operation will be described. It is preferable that the potential Vg (compensation point) of the gate g of the driving transistor 121 at the end of the compensation period is set to an intermediate gray scale of the gray scale voltage. Since the parasitic capacitance associated with the gate g becomes small, the compensation period becomes extremely short, and as a result, the scan signal Gwr(m) is affected by the rounding at the rising (falling) of the scanning signal Gwr(m). There is a possibility that the compensation period may differ between the side that supplies the power and the side that supplies the power. In this case, the scanning line drive circuit 20 having a high drive capability to the extent that this fear is eliminated is required.
Regarding the compression rate of data compression, as shown in (Equation 2), the smaller the value of Nb, the larger the compression rate, and conversely, the larger the value of Nb, the smaller the compression rate.
Therefore, it is preferable to determine the value of Nb to an appropriate value in consideration of the time required to complete the compensation operation and the compression rate of data compression. For example, when the total number of rows M is 720, Nb may be 90 and the total number of blocks K may be 8.

As described above, according to the embodiment of the present invention, the electro-optical device, the electronic device, and the electro-optical device are realized by realizing the high-speed compensation operation for compensating the variation in the threshold voltage of the transistor used for adjusting the emission intensity. A method of driving an electro-optical device can be provided.
The present invention is not limited to the above-described embodiments, and various modifications such as those described below are possible. In addition, one or more arbitrarily selected aspects of the modifications described below can be appropriately combined.

<Modification 1>
In the above-described embodiment, the third transistor 123 in each pixel circuit 110 is connected between the drain of the driving transistor 121 and the second data transfer line 14-2. However, as shown in FIG. May be connected between the drain and the gate g.

<Modification 2>
The fifth transistor 125 may not be provided in each pixel circuit 110 of the above-described embodiments.

<Modification 3>
The above-described first transistor 126 does not necessarily have to be arranged outside the pixel circuit 110, but may be arranged inside each pixel circuit 110.

<Modification 4>
In the above-described embodiment, the first transistor 126 and the transfer capacitor 133 are provided in a ratio of one to two pixel circuits 110, but the second data transfer line 14 has a one-to-one correspondence for each pixel circuit 110. -1, the first transistor 126, and the transfer capacitor 133 may be provided.

<Modification 4>
In the above-described embodiment, the first data transfer lines 14-1 are grouped into three columns, and the first data transfer lines 14-1 are sequentially selected in each group to supply the data signal. However, the number of data lines forming the group may be a predetermined number of “2” or more and “3n” or less. For example, the number of data lines forming a group may be "2" or may be "4" or more.
Further, the data signal may be supplied to the first data transfer line 14-1 of each column all at once without grouping, that is, without using the demultiplexer DM.

<Modification 5>
In the above-described embodiment, the transistors 121 to 126 are the P-channel type, but may be the N-channel type. Further, the P-channel type and the N-channel type may be appropriately combined.
For example, when unifying the transistors 121 to 126 of the N-channel type, it is sufficient to supply to each pixel circuit 110 a potential whose positive and negative sides are opposite to the data signal Vd(n) in the above-described embodiment. Further, in this case, the sources and the drains of the transistors 121 to 126 have a relationship opposite to that of the above-described embodiment and modification.
<Modification 6>
Although the OLED which is a light emitting element is illustrated as the electro-optical element in the above-described embodiments and modified examples, it may be any one that emits light with a brightness according to a current, such as an inorganic light emitting diode or an LED (Light Emitting Diode).

<Application example>
Next, electronic devices to which the electro-optical device 1 according to the embodiments and the application examples are applied will be described. The electro-optical device 1 is suitable for a high-definition display application with a small pixel size. Therefore, as an electronic device, a head mounted display will be described as an example.

FIG. 14 is a diagram showing the external appearance of the head mounted display, and FIG. 15 is a diagram showing its optical f-like configuration.
First, as shown in FIG. 14, the head mounted display 300 externally has a temple 310, a bridge 320, and lenses 301L and 301R, similar to general glasses. In addition, as shown in FIG. 15, the head mounted display 300 includes the electro-optical device 1L for the left eye and the right eye on the back side (lower side in the drawing) of the lenses 301L and 301R in the vicinity of the bridge 320. And an electro-optical device 1R for use.
The image display surface of the electro-optical device 1L is arranged on the left side in FIG. As a result, the display image by the electro-optical device 1L is emitted in the 9 o'clock direction in the figure via the optical lens 302L. The half mirror 303L reflects the display image by the electro-optical device 1L in the 6 o'clock direction, while transmitting the light incident from the 12:00 o'clock direction.
The image display surface of the electro-optical device 1R is arranged on the right side opposite to the electro-optical device 1L. As a result, the display image by the electro-optical device 1R is emitted through the optical lens 302R in the 3 o'clock direction in the figure. The half mirror 303R reflects the display image by the electro-optical device 1R in the 6 o'clock direction, while transmitting the light incident from the 12 o'clock direction.

With this configuration, the wearer of the head-mounted display 300 can observe the display images of the electro-optical devices 1L and 1R in a see-through state in which they are superposed on the outside.
Further, in the head mounted display 300, of the binocular images with parallax, the image for the left eye is displayed on the electro-optical device 1L and the image for the right eye is displayed on the electro-optical device 1R. , The displayed image can be perceived as if it has a depth and a stereoscopic effect (3D display).

The electro-optical device 1 can be applied not only to the head-mounted display 300 but also to an electronic viewfinder in a video camera, a lens-interchangeable digital camera, or the like.

1, 1L, 1R... Electro-optical device, 2... Display panel, 3... Control circuit, 10... Data line drive circuit, 12... Scan line, 14-1... First data transfer line, 14-2... Second data transfer Lines, 16... Feed line, 20... Scan line drive circuit, 31... Voltage generation circuit, 34... Transmission gate, 41... Storage capacitor, 42... Transmission gate, 45... Transmission gate, 70... Data signal supply circuit, 100... Display Part, 110... Pixel circuit, 116... Feed line, 118... Common electrode, 121, 122, 123, 124, 125, 126... Transistor, 130... OLED, 130a... Anode, 132... Pixel capacity, 133... Transfer capacity, 143 , 144, 145, 146... Control line, 300... Display, 301L, 301R... Lens, 302L, 302R... Optical lens, 303L, 303R... Half mirror, 310... Temple, 320... Bridge, DM... Demultiplexer, LS... Level Shift circuit.

Claims (5)

Control lines,
A first data transfer line,
A second data transfer line,
A first capacitor including a first electrode connected to the first data transfer line and a second electrode connected to the second data transfer line;
A first transistor that is provided between the first data transfer line and the second data transfer line and is in a conductive state or a non-conductive state according to a control signal supplied via the control line;
A plurality of pixel circuits connected to the second data transfer line,
A drive circuit that switches the potential of the first data transfer line so that the amount of change in the potential of the first data transfer line and the first electrode becomes a value according to the gradation level;
Have
Any one pixel circuit of the plurality of pixel circuits is,
Drive transistor,
A pixel capacitance that holds the potential of the gate electrode of the drive transistor;
A second transistor connected between the second data transfer line and the gate electrode of the driving transistor;
The drain current of the driving transistor has a third transistor connected between a first current terminal of the driving transistor and a gate electrode of the driving transistor, and a potential according to a gate voltage characteristic at which the driving transistor operates. A compensator capable of outputting to the second electrode and the second data transfer line by charging by
A light-emitting element that emits light with a brightness according to the magnitude of the current supplied from the drive transistor,
Two or more second data transfer lines are connected to the first data transfer line via the first capacitors, respectively.
The number of the plurality of pixel circuits connected to the second data transfer line is smaller than the number of the pixel circuits provided corresponding to the first data transfer line,
An electro-optical device,
The drive circuit
During the first period, the control signal for turning on the first transistor is supplied to the first transistor via the control line to turn on the first transistor to turn on the first data transfer line and the second data transfer. The second line and the third transistor are turned off and the initial potential is supplied to the second data transfer line,
In a second period following the first period, a control signal for turning off the first transistor is supplied to the first transistor via the control line to turn off the first transistor to turn off the first data transfer line. And the second data transfer line are turned off, and the second transistor and the third transistor are turned on to connect the first current terminal of the driving transistor and the gate electrode of the driving transistor. To conduct,
An electro-optical device characterized by the above . The pixel circuit includes a fourth transistor connected between the first current terminal of the driving transistor and the light emitting device.
The electro-optical device according to claim 1, wherein: The pixel circuit includes a reset potential supply line that supplies a reset potential to the light emitting element, and a fifth transistor connected between the light emitting element.
The electro-optical device according to claim 1, wherein: The drive circuit is
In a third period subsequent to the second period, the first transistor and the third transistor are turned off, the second transistor is turned on, and a second capacitor for holding a data signal corresponding to a gradation level is provided. , Connected to the first data transfer line,
The electro-optical device according to claim 1 , wherein: An electro-optical device according to claim 1 ,
An electronic device characterized in that

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