JP6492447B2 - Electro-optical device, electronic apparatus, and driving method of electro-optical device - Google Patents

Description

  The present invention relates to an electro-optical device, an electronic apparatus, and a driving method of the electro-optical device.

In recent years, various electro-optical devices using light-emitting elements such as organic light-emitting diode (hereinafter referred to as OLED (Organic Light Emitting Diode)) elements have been proposed. In a general configuration of this electro-optical device, a pixel circuit including a light emitting element, a transistor, and the like is provided corresponding to a pixel of an image to be displayed, corresponding to the intersection of a scanning line and a data line.
In such a configuration, when a data signal having a potential corresponding to the gray level of the pixel is applied to the gate of the transistor, the transistor supplies a current corresponding to the voltage between the gate and the source to the light emitting element. Accordingly, the light emitting element emits light with luminance according to the gradation level.

  In the driving method in which a transistor is used for adjusting the light emission intensity, if the threshold voltage of the transistor provided in each pixel varies, the current flowing through the light emitting element varies, so that the image quality of the display image is degraded. Therefore, in order to prevent deterioration in image quality, it is necessary to compensate for variations in threshold voltage of transistors. A period in which the operation related to this compensation (hereinafter referred to as compensation operation) is performed is called a compensation period. In the compensation period, the drain and gate of the transistor are connected to a data signal supply line provided for each column, The potential is set to a value corresponding to the threshold voltage of the transistor (see, for example, Patent Document 1).

JP2013-88611A

By the way, since a parasitic capacitance is attached to the data signal supply line, the parasitic capacitance is also charged or discharged when the compensation operation is executed. Then, the compensation period becomes longer by the time required for charging or discharging the parasitic capacitance. Moreover, if the compensation period is set without considering the time required for charging or discharging the parasitic capacitance associated with the supply line, the compensation in the compensation period becomes insufficient.
The present invention has been made in view of the above-described circumstances, and one of its purposes is to realize a high-speed compensation operation that compensates for variations in the threshold voltage of a transistor used for adjusting light emission intensity.

  In order to achieve the above object, an electro-optical device according to one embodiment of the present invention corresponds to a scan line, a data transfer line that intersects the scan line, and an intersection of the scan line and the data transfer line. A first capacitor including a pixel circuit provided and a drive circuit for driving the pixel circuit, the pixel circuit including a first electrode connected to the data transfer line, and a second electrode; A first transistor connected between the second electrode and a reset potential supply line for supplying a reset potential to the data transfer line; a drive transistor including a gate electrode, a first current end, and a second current end; , A second transistor connected between the second electrode of the first capacitor and the gate electrode of the drive transistor, the first current terminal of the drive transistor, and the gate of the drive transistor. A third transistor for conducting the electrode, and a light emitting element that emits light with a luminance corresponding to a magnitude of a current supplied through the driving transistor. The first transistor is turned on, the second transistor and the third transistor are turned off, an initial potential is supplied to the data transfer line, and the first transistor is turned off in a second period following the first period. At the same time, the second transistor and the third transistor are turned on to make the first current terminal of the driving transistor and the gate electrode of the driving transistor conductive, and the first electrode of the first capacitor The electric potential is decreased or increased with time at a constant rate of change.

  According to this aspect, in the second period (compensation period), the potential of the first electrode of the first capacitor is changed (for example, decreased) with time at a constant change rate in a state where the driving transistor is connected in a so-called diode. . As a result, the time required for the compensation period is shortened compared to a configuration in which the initial potential is kept constant during the compensation operation (a configuration in which the potential of the first electrode of the first capacitor is kept constant). That is, speeding up of the compensation operation is realized. This is because, for example, the potential applied to the first electrode of the first capacitor is decreased over time at a constant rate of change, for example, the charge of the first electrode is forcibly moved, and as a result, the potential of the gate electrode of the drive transistor This is because the potential rapidly changes to a potential at which a constant current flows according to the change rate of the potential of the first electrode.

  An electro-optical device according to another aspect of the invention is the electro-optical device according to the one aspect, in which the driving circuit generates a voltage that decreases at a constant change rate in the second period, and the data It includes a voltage generation circuit that is applied to the first electrode of the first capacitor via a transfer line. According to this aspect, by applying a voltage that decreases at a constant rate of change to the first electrode of the first capacitor, the potential of the first electrode can be decreased over time at a constant rate of change.

  An electro-optical device according to another aspect of the present invention is the electro-optical device according to the one aspect, in which the driving circuit includes the first capacitor of the first capacitor via the data transfer line in the second period. It includes a constant current source that draws a constant current from the first electrode. According to this aspect, by drawing a constant current from the first electrode of the first capacitor, the potential of the first electrode can be decreased over time at a constant rate of change.

  An electro-optical device according to another aspect of the present invention is the electro-optical device according to the one aspect, and includes a fourth transistor connected between the first current terminal of the driving transistor and the light-emitting element. Including. According to this aspect, the fourth transistor functions as a switching transistor that controls electrical connection between the drive transistor and the light emitting element.

  An electro-optical device according to another aspect of the invention is the electro-optical device according to the one aspect, and is connected between a reset potential supply line that supplies a reset potential to the light-emitting element and the light-emitting element. A fifth transistor is included. According to this aspect, the fifth transistor functions as a switching transistor that controls electrical connection between the reset potential supply line and the light emitting element.

  An electro-optical device according to another aspect of the present invention is the electro-optical device according to the one aspect, in which the driving circuit includes the first transistor and the third transistor in a third period following the second period. The second transistor is turned off and the second transistor is turned on, and a second capacitor for holding a data signal corresponding to a specified gradation is connected to the data transfer line. According to this aspect, in the third period (writing period), a data signal corresponding to the designated gradation of each pixel is supplied to the pixel circuit via the data transfer line.

  An electro-optical device according to another aspect of the invention includes a data transfer line, a first capacitor connected to the data transfer line, a first capacitor including a second electrode, a drive transistor, and the drive transistor. A compensation unit that outputs a potential according to the electrical characteristics to the second electrode, and a period during which the compensation unit outputs a potential according to the electrical characteristics of the drive transistor to the second electrode. A voltage generation circuit for decreasing or increasing the potential of one electrode over time at a constant rate of change, and the amount of change in potential of the data transfer line and the first electrode to a value corresponding to a gradation level; A data transfer line driving circuit for switching the potentials of the data transfer line and the first electrode, and a potential supplied based on a potential shifted from the potential corresponding to the electrical characteristics of the driving transistor according to the change amount A light emitting element that emits light at luminance corresponding to the magnitude of the flow, characterized in that it contains.

  According to this aspect, in a period (compensation period) in which the compensation unit outputs a potential corresponding to the electrical characteristics of the driving transistor to the second electrode (compensation period), the driving transistor is connected to the first electrode of the first capacitor in a so-called diode-connected state. The potential is changed (eg, decreased) with time at a constant rate of change. As a result, the time required for the compensation period is shortened compared to a configuration in which the initial potential is kept constant during the compensation operation (a configuration in which the potential of the first electrode of the first capacitor is kept constant). That is, speeding up of the compensation operation is realized. This is because, for example, the potential applied to the first electrode of the first capacitor is decreased over time at a constant rate of change, for example, the charge of the first electrode is forcibly moved, and as a result, the potential of the gate electrode of the drive transistor This is because the potential rapidly changes to a potential at which a constant current flows according to the change rate of the potential of the first electrode.

  In order to achieve the above object, an electronic apparatus according to an aspect of the present invention includes the electro-optical device according to any one of the above aspects. According to this aspect, an electronic apparatus including the electro-optical device according to any one of the above aspects is provided.

  In order to achieve the above object, a driving method of an electro-optical device according to an aspect of the present invention includes a scan line, a data transfer line that intersects the scan line, and an intersection of the scan line and the data transfer line. A corresponding pixel circuit, the pixel circuit including a first capacitor connected to the data transfer line, a first capacitor including a second electrode, the second electrode, A first transistor connected between a reset potential supply line for supplying a reset potential to the data transfer line, a drive transistor including a gate electrode, a first current terminal, and a second current terminal; Conducting the second transistor connected between the second electrode and the gate electrode of the driving transistor, the first current terminal of the driving transistor, and the gate electrode of the driving transistor. An electro-optical device driving method comprising: a third transistor; and a light emitting element that emits light with a luminance corresponding to a magnitude of a current supplied through the driving transistor, wherein the first transistor is in a first period. And turning off the second transistor and the third transistor, supplying an initial potential to the data transfer line, turning off the first transistor in a second period following the first period, and The second transistor and the third transistor are turned on to electrically connect the first current terminal of the driving transistor and the gate electrode of the driving transistor, and the potential of the first electrode of the first capacitor is constant. It is characterized by decreasing or increasing over time at a rate of change of.

  According to this aspect, in the second period (compensation period), the potential of the first electrode of the first capacitor is changed (for example, decreased) with time at a constant change rate in a state where the driving transistor is connected in a so-called diode. . As a result, the time required for the compensation period is shortened compared to a configuration in which the initial potential is kept constant during the compensation operation (a configuration in which the potential of the first electrode of the first capacitor is kept constant). That is, speeding up of the compensation operation is realized. This is because, for example, the potential applied to the first electrode of the first capacitor is decreased over time at a constant rate of change, for example, the charge of the first electrode is forcibly moved, and as a result, the potential of the gate electrode of the drive transistor This is because the potential rapidly changes to a potential at which a constant current flows according to the change rate of the potential of the first electrode.

  To achieve the above object, a method for driving an electro-optical device according to one aspect of the present invention includes a data transfer line, a first electrode connected to the data transfer line, and a first capacitor including a second electrode. A driving transistor, a compensation unit that outputs a potential corresponding to the electrical characteristics of the driving transistor to the second electrode, and a light emitting element that emits light with a luminance corresponding to the magnitude of a current supplied through the driving transistor A method of driving an electro-optical device including: reducing or increasing the potential of the first electrode of the first capacitor at a constant rate of change over time; Is output to the second electrode, and the amount of change in the potential of the data transfer line and the first electrode becomes a value corresponding to the gray level. Electric Switching, on the basis of a potential according to the electric characteristics of the drive transistor to the potential of shifting in accordance with the change amount, and supplying a current to the light emitting element

  According to this aspect, in a period (compensation period) in which the compensation unit outputs a potential corresponding to the electrical characteristics of the driving transistor to the second electrode (compensation period), the driving transistor is connected to the first electrode of the first capacitor in a so-called diode connection state. The potential is changed (eg, decreased) with time at a constant rate of change. As a result, the time required for the compensation period is shortened compared to a configuration in which the initial potential is kept constant during the compensation operation (a configuration in which the potential of the first electrode of the first capacitor is kept constant). That is, speeding up of the compensation operation is realized. This is because, for example, the potential applied to the first electrode of the first capacitor is decreased over time at a constant rate of change, for example, the charge of the first electrode is forcibly moved, and as a result, the potential of the gate electrode of the drive transistor This is because the potential rapidly changes to a potential at which a constant current flows according to the change rate of the potential of the first electrode.

1 is a perspective view illustrating a configuration of an electro-optical device according to an embodiment of the invention. 2 is a block diagram illustrating a configuration of the electro-optical device. FIG. FIG. 3 is a circuit diagram for explaining a configuration of a demultiplexer and a level shift circuit of the same electro-optical device. FIG. 3 is a circuit diagram illustrating a configuration of a pixel circuit of the electro-optical device. 6 is a timing chart showing the operation of the electro-optical device. FIG. 6 is an operation explanatory diagram of the same electro-optical device. FIG. 6 is an operation explanatory diagram of the same electro-optical device. FIG. 6 is an operation explanatory diagram of the same electro-optical device. It is a figure which shows the graph explaining the compensation period of the same electro-optical apparatus. FIG. 6 is an operation explanatory diagram of the same electro-optical device. It is a circuit diagram which shows the structure of the pixel circuit which concerns on a modification. It is a figure which shows the external appearance structure of HMD. It is a figure which shows the optical structure of HMD.

FIG. 1 is a perspective view showing a configuration of an electro-optical device 1 according to an embodiment of the present invention. The electro-optical device 1 is a micro display that displays an image on a head-mounted display, for example.
As shown in FIG. 1, the electro-optical device 1 includes a display panel 2 and a control circuit 3 that controls the operation of the display panel 2. The display panel 2 includes a plurality of pixel circuits and a drive circuit that drives the pixel circuits. In the present embodiment, a plurality of pixel circuits and drive circuits included in the display panel 2 are formed on a silicon substrate, and an OLED which is an example of a light emitting element is used for the pixel circuits. The display panel 2 is housed in, for example, a frame-shaped case 82 that opens at the display unit, and one end of an FPC (Flexible Printed Circuits) substrate 84 is connected.
On the FPC board 84, the control circuit 3 of the semiconductor chip is mounted by COF (Chip On Film) technology, and a plurality of terminals 86 are provided, and are connected to an upper circuit (not shown).

FIG. 2 is a block diagram illustrating a configuration of the electro-optical device 1 according to the embodiment. As described above, the electro-optical device 1 includes the display panel 2 and the control circuit 3.
Digital image data Video is supplied to the control circuit 3 from an upper circuit (not shown) in synchronization with a synchronization signal. Here, the image data Video is data that defines, for example, the 8-bit pixel gradation level of an image to be displayed on the display panel 2 (strictly speaking, the display unit 100 described later). The synchronization signal is a signal including a vertical synchronization signal, a horizontal synchronization signal, and a dot clock signal.

The control circuit 3 generates various control signals based on the synchronization signal and supplies them to the display panel 2. Specifically, the control circuit 3 controls the display panel 2 with a control signal Ctr, a positive logic control signal Gini, a negative logic control signal / Gini having a logic inversion relationship therewith, and a positive logic signal. Control signal Gcpl, negative logic control signal / Gcpl in a logic inversion relationship with this, control signals Sel (1), Sel (2), Sel (3), and logic inversion relationship with these signals Control signals / Sel (1), / Sel (2), and / Sel (3).
Here, the control signal Ctr is a signal including a plurality of signals such as a pulse signal, a clock signal, and an enable signal.
The control signals Sel (1), Sel (2), and Sel (3) are collectively referred to as the control signal Sel, and the control signals / Sel (1), / Sel (2), and / Sel (3) / Sel may be collectively called.
The control circuit 3 includes a voltage generation circuit 31. The voltage generation circuit 31 supplies various potentials to the display panel 2. Specifically, the control circuit 3 supplies the display panel 2 with a reset potential Vorst, an initial potential Vini, and the like.

  Further, the control circuit 3 generates an analog image signal Vid based on the image data Video. Specifically, the control circuit 3 is provided with a lookup table that stores the potential indicated by the image signal Vid and the luminance of a light emitting element (an OLED 130 described later) included in the display panel 2 in association with each other. Then, the control circuit 3 refers to the lookup table to generate an image signal Vid indicating a potential corresponding to the luminance of the light emitting element specified in the image data Video, and supplies this to the display panel 2. To do.

As shown in FIG. 2, the display panel 2 includes a display unit 100 and drive circuits (the data transfer line drive circuit 10 and the scanning line drive circuit 20) that drive the display unit 100.
In the display unit 100, pixel circuits 110 corresponding to pixels of an image to be displayed are arranged in a matrix. More specifically, in the display unit 100, M rows of scanning lines 12 are provided extending in the horizontal direction (X direction) in the drawing, and (3N) columns of data transfer lines are grouped every three columns. 14 extends in the vertical direction (Y direction) in the figure, and is provided so as to be electrically insulated from each scanning line 12. A pixel circuit 110 is provided corresponding to the intersection of the M rows of scanning lines 12 and the (3N) columns of data transfer lines 14. Therefore, in the present embodiment, the pixel circuits 110 are arranged in a matrix with vertical M rows × horizontal (3N) columns.

Here, M and N are both natural numbers. In order to distinguish rows (rows) in the matrix of the scanning lines 12 and the pixel circuits 110, they may be referred to as 1, 2, 3,... (M-1), M rows in order from the top in the drawing. Similarly, in order to distinguish the columns of the matrix of the data transfer line 14 and the pixel circuit 110, they may be referred to as 1, 2, 3,..., (3N-1), (3N) columns in order from the left in the figure. is there.
Here, in order to generalize and describe the group of data transfer lines 14, when an arbitrary integer of 1 or more is expressed as n, the n-th group from the left includes the (3n−2) -th column, ( This means that the data transfer lines 14 of the 3n-1) th column and the (3n) th column belong.

  The three pixel circuits 110 corresponding to the intersections of the scanning lines 12 in the same row and the three columns of data transfer lines 14 belonging to the same group have R (red), G (green), and B (blue) pixels, respectively. Corresponding to the above, one dot of a color image to be displayed by these three pixels is expressed. That is, in the present embodiment, one dot color is expressed by additive color mixing by light emission of an OLED corresponding to RGB.

  As shown in FIG. 2, in the display unit 100, (3N) rows of power supply lines (reset potential supply lines) 16 extend in the vertical direction and are electrically insulated from each scanning line 12. Provided. A predetermined reset potential Vorst is commonly supplied to the power supply lines 16. Here, in order to distinguish the columns of the feeder lines 16, they may be referred to as the feeder lines 16 in the first, second, third,. Each of the first to (3N) th column feeder lines 16 is provided corresponding to each of the first to (3N) th column data transfer lines 14.

The scanning line driving circuit 20 generates a scanning signal Gwr for sequentially scanning the M scanning lines 12 for each row within one frame period in accordance with the control signal Ctr. Here, the scanning signals Gwr supplied to the scanning lines 12 in the 1, 2, 3,..., M rows are respectively Gwr (1), Gwr (2), Gwr (3),. ) And Gwr (M).
In addition to the scanning signals Gwr (1) to Gwr (M), the scanning line driving circuit 20 generates various control signals synchronized with the scanning signal Gwr for each row and supplies them to the display unit 100. Illustration is omitted in FIG. The frame period is a period required for the electro-optical device 1 to display an image for one cut (frame). For example, if the frequency of the vertical synchronization signal included in the synchronization signal is 120 Hz, the first period is 1. This is a period of 8.3 milliseconds corresponding to the period.

  The data transfer line driving circuit 10 includes (3N) level shift circuits LS provided in a one-to-one correspondence with each of the (3N) columns of data transfer lines 14, and the three columns of data transfer lines constituting each group. N demultiplexers DM provided for every 14 and a data signal supply circuit 70 are provided.

  The data signal supply circuit 70 generates data signals Vd (1), Vd (2),..., Vd (N) based on the image signal Vid and the control signal Ctr supplied from the control circuit 3. That is, the data signal supply circuit 70 uses the data signals Vd (1), Vd (2),..., Vd (N) based on the image signal Vid obtained by time division multiplexing. ..., Vd (N) is generated. The data signal supply circuit 70 applies the data signals Vd (1), Vd (2),..., Vd (N) to the demultiplexers DM corresponding to the 1, 2,. Supply.

  FIG. 3 is a circuit diagram for explaining the configuration of the demultiplexer DM and the level shift circuit LS. FIG. 3 representatively shows a demultiplexer DM belonging to the nth group and three level shift circuits LS connected to the demultiplexer DM. Hereinafter, the demultiplexer DM belonging to the nth group may be referred to as DM (n).

Hereinafter, the configuration of the demultiplexer DM and the level shift circuit LS will be described with reference to FIG. 3 in addition to FIG.
As shown in FIG. 3, the demultiplexer DM is an aggregate of transmission gates 34 provided for each column, and sequentially supplies data signals to three columns constituting each group. Here, the input ends of the transmission gates 34 corresponding to the (3n-2), (3n-1), and (3n) columns belonging to the nth group are commonly connected to each other, and the data signal Vd ( n) is supplied. The transmission gate 34 provided in the (3n-2) column which is the leftmost column in the nth group is when the control signal Sel (1) is at the H level (when the control signal / Sel (1) is at the L level) ) Is turned on (conductive). Similarly, in the nth group, the transmission gates 34 provided in the (3n-1) column, which is the central column, have the control signal Sel (2) at the H level (the control signal / Sel (2) is at the L level. The transmission gate 34 provided in the (3n) column, which is the rightmost column in the nth group, when the control signal Sel (3) is at the H level (control signal / Sel (3) Is on).

  The level shift circuit LS has a set of a storage capacitor (second capacitor) 41, a transmission gate 45, and a transmission gate 42 for each column, and the potential of the data signal output from the output terminal of the transmission gate 34 in each column. Is to shift.

  The source or drain of the transmission gate 45 in each column is electrically connected to the data transfer line 14. The control circuit 3 supplies the control signal / Gini in common to the gates of the transmission gates 45 in each column. The transmission gate 45 electrically connects the data transfer line 14 and the supply line of the initial potential Vini when the control signal / Gini is at L level, and is electrically disconnected when the control signal / Gini is at H level. Connect. A predetermined initial potential Vini is supplied from the control circuit 3 to the supply line 61 for the initial potential Vini.

The storage capacitor 41 has two electrodes. One electrode of the storage capacitor 41 is electrically connected to the input terminal of the transmission gate 42 via the node h. The output terminal of the transmission gate 42 is electrically connected to the data transfer line 14.
The control circuit 3 supplies the control signal Gcpl and the control signal / Gcpl in common to the transmission gates 42 in each column. For this reason, the transmission gates 42 in each column are simultaneously turned on when the control signal Gcpl is at the H level (when the control signal / Gcpl is at the L level).

One electrode of the storage capacitor 41 in each column is electrically connected to the output end of the transmission gate 34 and the input end of the transmission gate 42 via the node h. When the transmission gate 34 is turned on, the data signal Vd (n) is supplied to one electrode of the storage capacitor 41 via the output terminal of the transmission gate 34. That is, in the storage capacitor 41, the data signal Vd (n) is supplied to one electrode.
The other electrode of the storage capacitor 41 in each column is connected in common to a power supply line to which a potential Vss that is a fixed potential is supplied. Here, the potential Vss may correspond to an L level of a scanning signal or a control signal that is a logic signal. Note that the capacitance value of the storage capacitor 41 is Crf.

The pixel circuit 110 will be described with reference to FIG. In order to generally indicate a row in which the pixel circuit 110 is arranged, an arbitrary integer of 1 to M is represented as m.
Since each pixel circuit 110 has the same configuration when viewed electrically, it is here positioned in the m-th row and is located in the (3n-2) -th column of the leftmost column in the n-th group. The description will be made taking the pixel circuit 110 in the (3n-2) column as an example.

  As shown in FIG. 4, the pixel circuit 110 includes P-channel MOS transistors 121 to 126, an OLED 130, a pixel capacitor 132, and a data transfer capacitor (first capacitor) 133. The pixel circuit 110 is supplied with a scanning signal Gwr (m), control signals Gcmp (m), Gel (m), Gorst (m), and Gfix (m). Here, the scanning signal Gwr (m), the control signals Gcmp (m), Gel (m), Gorst (m), and Gfix (m) are supplied by the scanning line driving circuit 20 corresponding to the m-th row. Is.

  Although not shown in FIG. 2, the display panel 2 (display unit 100) includes m rows of control lines 143 (first control lines) extending in the horizontal direction (X direction) in FIG. M rows of control lines 144 (second control lines), m rows of control lines 145 (third control lines), and m rows of control lines 146 (laterally extending) A fourth control line) is provided.

The scanning line driving circuit 20 applies control signals Gcmp (1), Gcmp (2), Gcmp (3),..., Gcmp to the control lines 143 in the 1, 2, 3,. (m) is supplied, and control signals Gel (1), Gel (2), Gel (3),..., Gel (m ) And control signals Gorst (1), Gorst (2), Gorst (3),..., Gorst (m) to the control lines 145 in the 1, 2, 3,. , And supply control signals Gfix (1), Gfix (2), Gfix (3),..., Gfix (m) to the control lines 146 in the 1, 2, 3,. .
That is, the scanning line driving circuit 20 applies the scanning signal Gwr (m), the control signals Gel (m), Gcmp (m), Gorst (m), (3n) pixel circuits positioned in the m-th row. Gfix (m) is supplied in common through the m-th scanning line 12 and control lines 143, 144, 145, and 146, respectively.
Hereinafter, the scanning line 12, the control line 143, the control line 144, the control line 145, and the control line 146 may be collectively referred to as “control line”. That is, the display panel 2 according to the present embodiment is provided with five control lines including the scanning lines 12 in each row.

  Each of the pixel capacitor 132 and the data transfer capacitor 133 has two electrodes. The data transfer capacitor 133 is a capacitance that includes the first electrode 133-1 and the second electrode 133-2.

  The second transistor 122 has a gate electrically connected to the scanning line 12 in the m-th row, and one of a source and a drain is electrically connected to one electrode (second electrode 133-2) of the data transfer capacitor 133. Has been. In the second transistor 122, the other of the source and the drain is electrically connected to the gate of the driving transistor 121 and one electrode of the pixel capacitor 132. In other words, the second transistor 122 is electrically connected between the gate of the driving transistor 121 and the second electrode 133-2 of the storage capacitor 133, and the gate of the driving transistor 121 and the data transfer in the (3n-2) th column. It functions as a transistor that controls the electrical connection between the second electrode 133-2 of the data transfer capacitor 133 connected to the line 14.

The drive transistor 121 has a source electrically connected to the power supply line 116, and a drain electrically connected to the source or the other of the third transistor 123 and the source of the fourth transistor 124.
Here, the power supply line 116 is supplied with a potential Vel that is higher in the power supply in the pixel circuit 110. The drive transistor 121 functions as a drive transistor that passes a current according to the voltage between the gate and the source of the drive transistor 121.
The third transistor 123 has a gate electrically connected to the control line 143 and is supplied with a control signal Gcmp (m). The third transistor 123 functions as a switching transistor that controls electrical connection between the gate and drain of the driving transistor 121. Therefore, the third transistor 123 is a transistor for conducting between the gate and the drain of the driving transistor 121 through the second transistor 122. The second transistor 122 is connected between one of the source and drain of the third transistor 123 and the gate of the driving transistor 121, but one of the source and drain of the third transistor 123 is connected to the driving transistor 121. It can also be interpreted as being electrically connected to the gate.

The fourth transistor 124 has a gate electrically connected to the control line 144 and is supplied with a control signal Gel (m). The drain of the fourth transistor 124 is electrically connected to the source of the fifth transistor 125 and the anode 130a of the OLED 130, respectively. The fourth transistor 124 functions as a switching transistor that controls electrical connection between the drain of the driving transistor 121 and the anode of the OLED 130. Furthermore, although the fourth transistor 124 is connected between the drain of the driving transistor 121 and the anode of the OLED 130, the drain of the driving transistor 121 can be interpreted as being electrically connected to the anode of the OLED 130.
The fifth transistor 125 has a gate electrically connected to the control line 145 and is supplied with a control signal Gorst (m). The drain of the fifth transistor 125 is electrically connected to the feeder line 16 in the (3n-2) th column and is kept at the reset potential Vorst. The fifth transistor 125 functions as a switching transistor that controls electrical connection between the power supply line 16 and the anode 130 a of the OLED 130.

  The first transistor 126 has a gate electrically connected to the control line 146 and is supplied with a control signal Gfix (m). One of the source and the drain of the first transistor 126 is electrically connected to the power supply line 16 in the (3n-2) th column and is kept at the reset potential Vorst. The first transistor 126 has the other of the source and the drain electrically connected to the second electrode 133-2 of the data transfer capacitor 133 and one of the source and the drain of the third transistor 123. The first transistor 126 mainly functions as a switching transistor that controls electrical connection between the power supply line 16 and the second electrode 133-2 of the data transfer capacitor 133.

  In the present embodiment, since the display panel 2 is formed on a silicon substrate, the substrate potentials of the transistors 121 to 126 are set to the potential Vel. In addition, the sources and drains of the transistors 121 to 126 in the above may be switched depending on the channel type and potential relationship of the transistors 121 to 126. The transistor may be a thin film transistor or a field effect transistor.

In the pixel capacitor 132, one electrode is electrically connected to the gate of the driving transistor 121, and the other electrode is electrically connected to the power supply line 116. Therefore, the pixel capacitor 132 functions as a storage capacitor that holds a voltage between the gate and the source of the driving transistor 121. The capacitance value of the pixel capacitor 132 is expressed as Cpix.
As the pixel capacitor 132, a capacitor parasitic to the gate g of the driving transistor 121 may be used, or a capacitor formed by sandwiching an insulating layer between different conductive layers in a silicon substrate may be used.

  The anode 130 a of the OLED 130 is a pixel electrode provided individually for each pixel circuit 110. On the other hand, the cathode of the OLED 130 is a common electrode 118 provided in common throughout the pixel circuit 110, and is maintained at the potential Vct that is the lower side of the power supply in the pixel circuit 110. The OLED 130 is an element in which a white organic EL layer is sandwiched between an anode 130a and a light-transmitting cathode in the silicon substrate. A color filter corresponding to any of RGB is superimposed on the emission side (cathode side) of the OLED 130.

  In such an OLED 130, when a current flows from the anode 130a to the cathode, holes injected from the anode 130a and electrons injected from the cathode are recombined in the organic EL layer to generate excitons, and white light is generated. Occur. The white light generated at this time is transmitted through the cathode on the opposite side to the silicon substrate (anode 130a), and is colored by a color filter so as to be visually recognized by the viewer. Note that the wavelength of light emitted from the OLED 130 may be set by adjusting the optical distance between two reflective layers arranged with the white organic EL layer interposed therebetween to form a cavity structure. In this case, a color filter may or may not be provided.

The operation of the electro-optical device 1 will be described with reference to FIG. FIG. 5 is a timing chart for explaining the operation of each part in the electro-optical device 1. As shown in this figure, the scanning line driving circuit 20 sequentially switches the scanning signals Gwr (1) to Gwr (M) to the L level, and sets the scanning lines 12 of the 1st to Mth rows to 1 in the period of one frame. Scan in order for each horizontal scanning period (H).
The operation in one horizontal scanning period (H) is common to the pixel circuits 110 in each row. Therefore, in the following, the operation will be described focusing on the pixel circuit 110 in the m-th row (3n-2) column in the horizontal scanning period in which the m-th row is horizontally scanned.

  In the present embodiment, the horizontal scanning period of the m-th row is roughly divided into an initialization period indicated by (b) in FIG. 5, a compensation period indicated by (c), and a writing period indicated by (d). And divided. The period other than the horizontal scanning period is a light emission period shown in (a). Then, after the writing period of (d), the light emission period shown in (a) is reached again, and after the elapse of one frame period, the horizontal scanning period of the m-th row is reached again. For this reason, in the order of time, a cycle of light emission period → initialization period → compensation period → writing period → light emission period is repeated.

  Hereinafter, for convenience of explanation, the light emission period which is a premise of the initialization period will be described. FIG. 6 is a diagram illustrating the operation of the pixel circuit 110 and the like during the light emission period. In FIG. 6, the current path that is important in the explanation of the operation is indicated by a bold line, and an “X” is indicated by a bold line on the transistor or transmission gate in the off state (see FIGS. 7 and 8 below). The same applies to FIG. 10).

<Light emission period>
As shown in FIG. 5, in the light emission period of the m-th row, the scanning signal Gwr (m) is at the H level, the control signal Gel (m) is at the L level, and the control signal Gcmp (m) is at the H level. Yes, the control signal Gfix (m) is at the H level.
Therefore, as shown in FIG. 6, in the pixel circuit 110 of m rows (3n-2) columns, the transistor 124 is turned on, while the transistors 122, 123, 125, and 126 are turned off. As a result, the drive transistor 121 supplies the OLED 130 with a drive current Ids corresponding to the voltage held by the pixel capacitor 132, that is, the gate-source voltage Vgs. That is, the OLED 130 is supplied with a current corresponding to the gradation potential corresponding to the designated gradation of each pixel by the driving transistor 121 and emits light with a luminance corresponding to the current.

  Here, in the light emission period, in the level shift circuit LS, as shown in FIG. 6, since the control signal / Gini becomes H level, the transmission gate 45 is turned off and the control signal Gcpl becomes L level. Turns off. Further, in the demultiplexer DM (n) during the light emission period, the control signal Sel (1) is at the L level, so that the transmission gate 34 is turned off.

  Since the light emission period of the m-th row is a period during which horizontal scanning is performed except for the m-th row, the transmission gate 34, the transmission gate 42, and the transmission gate 45 are turned on or off according to the operation of these rows, and the data The potential of the transfer line 14 varies as appropriate. However, in the pixel circuit 110 in the m-th row, since the second transistor 122 is off, the potential fluctuation of the data transfer line 14 is not considered here.

<Initialization period>
Next, when the horizontal scanning period of the m-th row is reached, first, the initialization period of (b) starts. As shown in FIG. 5, in the initialization period of the m-th row, the scanning signal Gwr (m) is L level, the control signal Gel (m) is H level, and the control signal Gcmp (m) is H level. The control signal Gfix (m) is at L level.
For this reason, as shown in FIG. 7, in the pixel circuit 110 of m rows (3n-2) columns, the transistors 122, 125, and 126 are turned on, while the transistors 123 and 124 are turned off. As a result, the path of the current supplied to the OLED 130 is interrupted, so that the OLED 130 enters an off (non-light emitting) state. The second electrode 133-2 of the data transfer capacitor 133 is electrically connected to the power supply line 16 and set to the reset potential Vorst. Further, when the fifth transistor 125 is turned on, the anode 130a of the OLED 130 and the power supply line 16 are electrically connected, and the potential of the anode 130a is set to the reset potential Vorst.

  Here, in the initialization period, in the level shift circuit LS, as shown in FIG. 7, since the control signal / Gini becomes L level, the transmission gate 45 is turned on and the control signal Gcpl becomes L level. 42 turns off. Therefore, as shown in FIG. 7, the data transfer line 14 connected to the first electrode 133-1 of the data transfer capacitor 133 is set to the initial potential Vini.

In the initialization period, since the control signal Sel (1) is at the H level, the transmission gate 34 is turned on in the demultiplexer DM (n) as shown in FIG. As a result, the gradation potential is written in the storage capacitor 41 having the capacitance value Crf.
Further, as shown in FIG. 7, in the pixel circuit 110 of m rows (3n−2) columns, the second transistor 122 and the first transistor 126 are turned on, so that the gate g is electrically connected to the power supply line 16. It becomes a state. Therefore, since the gate g is also at the reset potential Vorst, the holding voltage of the pixel capacitor 132 is initialized to (Vel−Vorst) from the voltage held during the light emission period.

<Compensation period>
In the horizontal scanning period of the m-th row, when the initialization period (b) described above is completed, the compensation period (c) starts. In the m-th compensation period, the scanning signal Gwr (m) is at the L level, the control signal Gel (m) is at the H level, the control signal Gcmp (m) is at the L level, and the control signal Gfix (m) Is at the H level.
Therefore, as shown in FIG. 8, in the pixel circuit 110 of m rows (3n-2) columns, the transistors 122, 123, 125 are turned on, while the fourth transistors 124, 126 are turned off. At this time, the gate g of the driving transistor 121 is connected (diode-connected) to its own drain via the transistor 122 and the transistor 123, the driving transistor 121 is turned on, and a drain current flows to charge the gate g. The drain of the driving transistor 121 is not electrically connected to the power supply line 16 and is electrically connected to the second electrode 133-2 of the data transfer capacitor 133 and the gate of the driving transistor 121.
That is, the drain and gate of the driving transistor 121 are connected to the second electrode 133-2 of the data transfer capacitor 133 through the second transistor 122 and the third transistor 123. The second transistor 122 and the third transistor 123 function as a compensation unit that outputs a potential corresponding to the electrical characteristics of the driving transistor 121 to the second electrode 133-2.

Here, in the level shift circuit LS in the compensation period, as shown in FIG. 8, since the control signal / Gini becomes L level, the transmission gate 45 is turned on, and the control signal Gcpl becomes L level. 42 turns off. Therefore, as shown in FIG. 7, the initial potential Vini is applied to the first electrode 133-1 and the data transfer line 14 of the data transfer capacitor 133.
Further, since the control signal Sel (1) is at the H level during the compensation period, the transmission gate 34 is turned on in the demultiplexer DM (n) as shown in FIG. As a result, the gradation potential is written in the storage capacitor 41 having the capacitance value Crf.

FIG. 9 is a graph showing a time change graph of the initial potential Vini and the potential Vg of the gate g and a time change graph of the drive current Ids flowing through the drive transistor 121 in the compensation period.
As shown in FIG. 9, during the compensation period, the first electrode 133-1 and the data transfer line 14 of the data transfer capacitor 133 have a constant change rate α (the potential change per unit time) as the initial potential Vini. A potential of a ramp waveform that decreases with time. As a result, a current corresponding to a change in the potential (initial potential Vini) of the first electrode 133-1 of the data transfer capacitor 133 flows from the drain of the driving transistor 121 to the gate g, and the potential of the gate node as shown in FIG. Vg is set to a potential corresponding to the current.

However, since the drive current Ids flowing from the drain of the drive transistor 121 to the gate g becomes difficult to flow as the potential Vg of the gate g approaches the potential Vel, the potential Vg of the gate g does not reach the end of the compensation period. As shown in FIG. 9, the voltage increases with time toward the potential Vel.
The potential Vg of the gate node set in this way is a potential according to electrical characteristics such as the mobility of the driving transistor 121 and the threshold voltage Vth. As a result, variations in the electrical characteristics of the drive transistor 121 in each pixel circuit 110 are compensated.

Specifically, the variation in the electrical characteristics of the drive transistor 121 in each pixel circuit 110 is compensated by the following operation.
That is, when the driving transistor 121, the second transistor 122, and the third transistor 123 are turned on, the source-drain of the driving transistor 121 and the third transistor 123 are connected to the second electrode 133-2 of the data transfer capacitor 133. Via, the potential Vel is supplied from the power supply line 116, and electric charge is supplied (charged).
On the other hand, in the first electrode 133-1, the charge of the first electrode 133-1 is discharged via the data transfer line 14 due to the decrease in the applied initial potential Vini.

  Accordingly, in the data transfer capacitor 133, supply of electric charge to the second electrode 133-2 (current flowing through the drive transistor 121) acts to increase the potential Vg of the gate g of the drive transistor 121, while The discharge of charge from the first electrode 133-1 acts to lower the potential Vg.

Now, when the potential Vg decreases due to the discharge of charge from the first electrode 133-1, the gate-source voltage Vgs of the driving transistor 121 increases, and the driving current Ids increases. This acts to increase the potential Vg.
That is, the drive transistor is configured such that the decrease in the potential Vg resulting from the discharge of the charge from the first electrode 133-1 and the increase in the potential Vg resulting from the supply of the charge to the second electrode 133-2 are balanced with each other. The drive current Ids is adjusted. Here, the drive current Ids is a constant current according to the rate of change α of the initial potential Vini (time change in the charge amount of the first electrode 133-1).

As understood from the above description, in the compensation operation, regardless of the value of the threshold voltage Vth of the driving transistor 121, a constant driving current Ids corresponding to the change rate α of the initial potential Vini is a source-drain of the driving transistor 121. The potential Vg of the gate of the driving transistor 121 is adjusted so as to flow between them.
That is, by the compensation operation, the potential Vg of the gate g of the driving transistor 121 is set to a potential reflecting electrical characteristics such as the mobility of the driving transistor 121 and the threshold voltage Vth. In other words, the potential Vg of the gate g of the drive transistor 121 is set to a potential at which a constant drive current Ids flows under the threshold voltage Vth and mobility that may be different among the individual drive transistors 121. .
As described above, the second transistor 122 and the third transistor 123 function as a compensation unit that outputs a potential corresponding to the electrical characteristics of the driving transistor 121 to the second electrode 133-2.

In the compensation period of the present embodiment, as described above, the potential of the first electrode 133-1 of the data transfer capacitor 133 is decreased with time at a constant change rate α in a state where the driving transistor 121 is diode-connected.
As a result, the time required for the compensation period is shortened compared to a configuration in which the initial potential Vini is kept constant during the compensation operation. That is, speeding up of the compensation operation is realized. This is because the electric potential of the first electrode 133-1 is forcibly moved by changing the initial potential Vini over time at a constant change rate α, and as a result, the potential Vg of the gate g of the driving transistor 121 changes. This is because a constant current Ids corresponding to the rate α quickly changes to a potential flowing therethrough.

  Note that since the fourth transistor 124 is off, the drain of the driving transistor 121 is not electrically connected to the OLED 130. Similarly to the initialization period, when the fifth transistor 125 is turned on, the anode 130a of the OLED 130 and the power supply line 16 are electrically connected, and the potential of the anode 130a is set to the reset potential Vorst.

<Writing period>
In the horizontal scanning period of the m-th row, when the above-described compensation period (c) is completed, the writing period (d) starts. In the writing period of the m-th row, the scanning signal Gwr (m) is at the L level, the control signal Gel (m) is at the H level, the control signal Gcmp (m) is at the H level, and the control signal Gfix (m ) Is H level.
Therefore, as shown in FIG. 10, in the pixel circuit 110 with m rows (3n-2) columns, the transistors 122 and 125 are turned on, while the transistors 123, 124, and 126 are turned off.

Here, in the level shift circuit LS in the writing period, as shown in FIG. 10, since the control signal / Gini becomes H level, the transmission gate 45 is turned off and the control signal Gcpl becomes H level. The gate 42 is turned on. For this reason, the supply of the initial potential Vini to the first electrode 133-1 and the data transfer line 14 of the data transfer capacitor 133 is canceled, and the first electrode 133-1 and the data transfer line 14 of the data transfer capacitor 133 are also connected. On the other hand, one electrode of the storage capacitor 41 having the capacitance value Crf is connected, and the gradation potential is supplied to the first electrode 133-1 of the data transfer capacitor 133. Then, a signal whose grayscale potential is level-shifted is supplied to the gate of the driving transistor 121 and written to the pixel capacitor Cpix.
In the writing period, since the control signal Sel (1) is at the L level, the transmission gate 34 is turned off in the demultiplexer DM (n) as shown in FIG.

  Note that since the fourth transistor 124 is off, the drain of the driving transistor 121 is not electrically connected to the OLED 130. Similarly to the initialization period, when the fifth transistor 125 is turned on, the anode 130a of the OLED 130 and the power supply line 16 are electrically connected, and the potential of the anode 130a is initialized to the reset potential Vorst.

  By the way, in the m-th writing period, in the n-th group, the control circuit 3 sequentially receives the data signal Vd (n) in m rows (3n-2) columns and m rows (3n-1). The potential is switched to the potential corresponding to the gradation level of the pixels in the column and m rows (3n) columns. On the other hand, the control circuit 3 exclusively sets the control signals Sel (1), Sel (2), and Sel (3) to the H level sequentially in accordance with the switching of the potential of the data signal. Although not shown, the control circuit 3 has control signals / Sel (1), / Sel (2) that are in a logically inverted relationship with the control signals Sel (1), Sel (2), and Sel (3). , / Sel (3) is also output. Accordingly, in the demultiplexer DM, the transmission gates 34 are turned on in the order of the left end column, the center column, and the right end column in each group.

つまり、書込期間におけるゲートｇの電位Ｖｇは、補償期間における電位Ｖｇから、データ転送容量１３３の第１電極１３３−１及びゲート線１４の電位の変化量ΔＶに対して、容量比Ｒを乗じた値だけシフトした値となる。この書込期間を終えると、上述した（ａ）の発光期間が開始する。
以上説明したように、本発明の一実施形態によれば、発光強度の調節に用いるトランジスターの閾値電圧のばらつきを補償する補償動作の高速化を実現することで電気光学装置、電子機器、及び、電気光学装置の駆動方法を提供することができる。 Here, when the transmission gate 34 in the leftmost column is turned on by the control signals Sel (1), / Sel (1), the amount of change in potential of the first electrode 133-1 and the data transfer line 14 of the data transfer capacitor 133 is ΔV. Then, the change amount ΔVg of the potential Vg of the gate g can be expressed by the following (formula 1).

That is, the potential Vg of the gate g in the writing period is multiplied by the capacitance ratio R to the potential change amount ΔV of the first electrode 133-1 and the gate line 14 of the data transfer capacitor 133 from the potential Vg in the compensation period. The value is shifted by that value. When this writing period ends, the above-described light emission period (a) starts.
As described above, according to an embodiment of the present invention, an electro-optical device, an electronic apparatus, and an electronic device can be realized by speeding up a compensation operation that compensates for variations in threshold voltage of a transistor used to adjust light emission intensity. A driving method of the electro-optical device can be provided.

The present invention is not limited to the above-described embodiments, and various modifications as described below are possible, for example. Moreover, the aspect of the deformation | transformation described below can also combine suitably arbitrarily selected 1 or several.
<Modification 1>
In the above-described embodiment, the initial potential Vini having a ramp waveform that decreases with time at a constant change rate α is applied to the first electrode 133-1 of the data transfer capacitor 133 in the compensation period. Instead of applying the initial potential Vini, a constant current source that draws a constant current from the first electrode 133-1 of the data transfer capacitor 133 when the transmission gate 45 is turned on may be provided.

<Modification 2>
In the above-described embodiment, the data transfer lines 14 are grouped every three columns, and the data transfer lines 14 are sequentially selected in each group to supply the data signal. The number of lines may be a predetermined number of “2” or more and “3n” or less. For example, the number of data transfer lines constituting the group may be “2”, or may be “4” or more.
Further, a configuration may be adopted in which data signals are supplied to the data transfer lines 14 of each column all at once without grouping, that is, without using the demultiplexer DM.

<Modification 3>
In the above-described embodiment, in each pixel circuit 110, the third transistor 123 is connected between the drain of the drive transistor 121 and the second electrode 133-2 of the data transfer capacitor 133. As shown in FIG. The drive transistor 121 may be connected between the drain and the gate.
<Modification 4>
In each pixel circuit 110 of the above-described embodiment, the fifth transistor 125 may not be provided.

<Modification 5>
In the above-described embodiment, the transistors 121 to 126 in the pixel circuit 110 are unified with the P-channel type, but may be unified with the N-channel type. Further, a P-channel type and an N-channel type may be appropriately combined.
For example, in the case where the transistors 121 to 126 are unified with an N-channel type, the data signal Vd (j) in the above-described embodiment may be supplied to each pixel circuit 110 with a positive / negative potential reversed. In this case, the sources and drains of the transistors 121 to 126 are in a relationship reversed to that of the above-described embodiment and modification. In this case, the initial potential Vini applied to the first electrode 133-1 of the data transfer capacitor 133 in the compensation period may be a ramp waveform potential that increases with time at a constant rate of change.
<Modification 6>
In the above-described embodiment and modification, an OLED that is a light-emitting element is illustrated as an electro-optical element. However, any light-emitting element that emits light with luminance according to current, such as an inorganic light-emitting diode or LED (Light Emitting Diode), may be used.

<Application example>
Next, an electronic apparatus to which the electro-optical device 1 according to the embodiment and the application example is applied will be described. The electro-optical device 1 is suitable for high-definition display with small pixels. Therefore, a head mounted display will be described as an example of an electronic device.

FIG. 12 is a diagram showing the external appearance of the head-mounted display, and FIG. 13 is a diagram showing its optical configuration.
First, as shown in FIG. 12, the head mounted display 300 has a temple 310, a bridge 320, and lenses 301L and 301R in the same manner as general glasses. Further, as shown in FIG. 13, the head mounted display 300 is in the vicinity of the bridge 320 and on the back side (lower side in the drawing) of the lenses 301 </ b> L and 301 </ b> R, Electro-optical device 1R.
The image display surface of the electro-optical device 1L is disposed on the left side in FIG. Accordingly, the display image by the electro-optical device 1L is emitted in the direction of 9 o'clock in the drawing through the optical lens 302L. The half mirror 303L reflects the display image by the electro-optical device 1L in the 6 o'clock direction, and transmits light incident from the 12 o'clock direction.
The image display surface of the electro-optical device 1R is disposed on the right side opposite to the electro-optical device 1L. As a result, the display image by the electro-optical device 1R is emitted in the direction of 3 o'clock in the drawing through the optical lens 302R. The half mirror 303R reflects the display image by the electro-optical device 1R in the 6 o'clock direction, and transmits light incident from the 12 o'clock direction.

In this configuration, the wearer of the head mounted display 300 can observe the display image by the electro-optical devices 1L and 1R in a see-through state superimposed on the outside.
Further, in the head-mounted display 300, when the left-eye image is displayed on the electro-optical device 1L and the right-eye image is displayed on the electro-optical device 1R among the binocular images with parallax, the wearer is notified. The displayed image can be perceived as if it had a depth or a stereoscopic effect (3D display).

  In addition to the head mounted display 300, the electro-optical device 1 can be applied to an electronic viewfinder in a video camera, an interchangeable lens digital camera, or the like.

DESCRIPTION OF SYMBOLS 1, 1L, 1R ... Electro-optical device, 2 ... Display panel, 3 ... Control circuit, 10 ... Data transfer line drive circuit, 12 ... Scan line, 14 ... Data transfer line, 16 ... Feed line, 20 ... Scan line drive circuit , 31 ... Voltage generation circuit, 34 ... Transmission gate, 41 ... Holding capacity, 42 ... Transmission gate, 45 ... Transmission gate, 70 ... Data signal supply circuit, 100 ... Display unit, 110 ... Pixel circuit, 116 ... Feed line, 118 ... Common electrode, 121, 122, 123, 124, 125, 126 ... Transistor, 130 ... OLED, 130a ... Anode, 132 ... Pixel capacity, 133 ... Data transfer capacity, 143, 144, 145, 146 ... Control line, 300 ... Display, 301L, 301R ... lens, 302L, 302R ... optical lens, 303L, 303 ... half mirror, 310 ... Temple, 320 ... bridge, DM ... demultiplexer, LS ... level shift circuit.

Claims (6)

Scanning lines;
A data transfer line intersecting the scan line;
A pixel circuit provided corresponding to the intersection of the scanning line and the data transfer line;
A reset potential supply line for supplying a reset potential to the pixel circuit;
A drive circuit for driving the pixel circuit;
Have
The pixel circuit includes:
A first capacitor including a first electrode and a second electrode connected to the data transfer line;
A first transistor connected between the second electrode and the reset potential supply line;
A drive transistor comprising a gate electrode, a first current end, and a second current end;
A second transistor connected between the second electrode of the first capacitor and the gate electrode of the driving transistor;
A third transistor for conducting the first current terminal of the driving transistor and the gate electrode of the driving transistor;
A light emitting element that emits light with a luminance corresponding to the magnitude of current supplied through the driving transistor;
A fourth transistor connected between the first current terminal of the driving transistor and the light emitting element;
Including
The drive circuit is
In the first period, the first transistor is turned on, the third transistor and the fourth transistor are turned off, and an initial potential is supplied to the data transfer line,
In a second period following the first period, the first transistor is turned off, the second transistor and the third transistor are turned on, the first current terminal of the driving transistor, and the driving transistor Conducting the gate electrode and decreasing or increasing the potential of the first electrode of the first capacitor over time at a constant rate of change;
An electro-optical device. The drive circuit includes a voltage generation circuit that generates a voltage that decreases at a constant rate of change during the second period and applies the voltage to the first electrode of the first capacitor via the data transfer line.
The electro-optical device according to claim 1. The drive circuit includes a constant current source that draws a constant current from the first electrode of the first capacitor via the data transfer line in the second period.
The electro-optical device according to claim 1. A fifth transistor connected between the reset potential supply line and the light emitting element;
The electro-optical device according to any one of claims 1 to 3 . The drive circuit is
In a third period following the second period, the second capacitor that turns off the first transistor and the third transistor, turns on the second transistor, and holds a data signal in accordance with a specified gradation, Connect to data transfer line,
5. The electro-optical device according to claim 1 , wherein the electro-optical device is provided. Scanning lines;
A data transfer line intersecting the scan line;
A pixel circuit provided corresponding to the intersection of the scanning line and the data transfer line;
A reset potential supply line for supplying a reset potential to the pixel circuit;
Have
The pixel circuit includes:
A first capacitor including a first electrode and a second electrode connected to the data transfer line;
A first transistor connected between the second electrode and the reset potential supply line;
A drive transistor comprising a gate electrode, a first current end, and a second current end;
A second transistor connected between the second electrode of the first capacitor and the gate electrode of the driving transistor;
A third transistor for conducting the first current terminal of the driving transistor and the gate electrode of the driving transistor;
A light emitting element that emits light with a luminance corresponding to the magnitude of current supplied through the driving transistor;
A fourth transistor connected between the first current terminal of the driving transistor and the light emitting element;
An electro-optical device driving method including:
In the first period, the first transistor is turned on, the third transistor and the fourth transistor are turned off, and an initial potential is supplied to the data transfer line,
In a second period following the first period, the first transistor is turned off, the second transistor and the third transistor are turned on, the first current terminal of the driving transistor, and the driving transistor Conducting the gate electrode and decreasing or increasing the potential of the first electrode of the first capacitor over time at a constant rate of change;
A driving method for an electro-optical device.

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