JP2017083799A - Electro-optical device, electronic apparatus, and driving method of electro-optical device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress an influence of a variation in potential of an element to which a data signal is supplied to improve display quality.SOLUTION: An electro-optical device comprises first data transfer lines 14-1, second data transfer lines 14-2, and a first transistor that controls the conduction state of the data transfer lines; pixel circuits 110 each include a second transistor that is connected to between the second data transfer line 14-2 and a gate electrode of a drive transistor and a third transistor that establishes conduction between a first current end of the drive transistor and the gate electrode; two or more second data transfer lines 14-2 are connected to the first data transfer line 14-1 via respective transfer capacities 133; the pixel circuits 110 are connected to a single first data transfer line 14-1 via the second data transfer lines 14-2 as a pixel row; the second data transfer lines 14-2 are provided for the pixel circuits 110 the number of which being equal to or less than the number of pixel circuits 110 in the pixel row; and the first transistor is turned on to provide a period to supply an initial potential to the second data transfer lines 14-2.SELECTED DRAWING: Figure 14

Description

  The present invention relates to an electro-optical device, an electronic apparatus, and a driving method of the electro-optical device.

In recent years, various electro-optical devices using light-emitting elements such as organic light-emitting diode (hereinafter referred to as OLED (Organic Light Emitting Diode)) elements have been proposed. In a general configuration of this electro-optical device, a pixel circuit including a light emitting element, a transistor, and the like is provided corresponding to a pixel of an image to be displayed, corresponding to the intersection of a scanning line and a data line.
In such a configuration, when a data signal having a potential corresponding to the gray level of the pixel is applied to the gate of the transistor, the transistor supplies a current corresponding to the voltage between the gate and the source to the light emitting element. Accordingly, the light emitting element emits light with luminance according to the gradation level.

  In the driving method in which a transistor is used for adjusting the light emission intensity, if the threshold voltage of the transistor provided in each pixel varies, the current flowing through the light emitting element varies, so that the image quality of the display image is degraded. Therefore, in order to prevent deterioration in image quality, it is necessary to compensate for variations in threshold voltage of transistors. Therefore, in order to adjust the gate voltage of the transistor to the threshold voltage, a compensation transistor is provided between the transistor gate and the drain or source, and a coupling capacitor is provided between the transistor gate and the data line. Has been proposed (see, for example, Patent Document 1).

JP 2008-191247 A

However, in the device of Patent Document 1, since the electrode connected to the gate of the transistor among the electrodes of the coupling capacitance is in a floating state during the light emission period, it is affected by the potential fluctuation of the data line. As a result, the gate voltage of the transistor cannot be maintained at the threshold voltage, which may cause a display defect.
The present invention has been made in view of the above-described circumstances, and one of its purposes is to suppress the influence of fluctuations in potential of an element to which a data signal is supplied and to improve display quality.

  In order to achieve the above object, an electro-optical device according to one embodiment of the present invention is connected to a first conductive layer, a second conductive layer, a third conductive layer, and the second conductive layer. The first capacitor including the first electrode and the second electrode connected to the third conductive layer, and the second conductive layer and the third conductive layer are in a conductive state or a non-conductive state. A first transistor, a pixel circuit provided corresponding to the third conductive layer and the first conductive layer, and a drive circuit for driving the pixel circuit, the pixel circuit comprising: A driving transistor having a gate electrode, a first current terminal, and a second current terminal; a second transistor connected between the third conductive layer; and the gate electrode of the driving transistor; The first current terminal and the gate power of the driving transistor. And a light emitting element that emits light with a luminance corresponding to the magnitude of the current supplied through the driving transistor, and the driving circuit includes the first transistor in the first period. One transistor is turned on to bring the second conductive layer and the third conductive layer into a conductive state, and the second transistor and the third transistor are turned off so that an initial potential is applied to the third conductive layer. And in a second period following the first period, the first transistor is turned off to make the second conductive layer and the third conductive layer nonconductive, and at least the third transistor To turn on the first current terminal of the driving transistor and the gate electrode of the driving transistor, and in the third period following the second period, the first transistor The first current terminal of the driving transistor is turned off by turning off the second transistor and the third transistor by turning off the second conductive layer and the third conductive layer, and turning off the second transistor and the third transistor. And the light emitting element is electrically connected to cause the light emitting element to emit light. At least one third conductive layer is connected to the second conductive layer via the first capacitor, and A set of the pixel circuits connected to the same second conductive layer through the conductive layer is a pixel column, and the number of pixel circuits equal to or less than the number of the pixel circuits included in the pixel column is one block. Then, a period in which the first transistor is turned on and an initial potential is supplied to the third conductive layer is provided in the third period in one block.

  According to this aspect, the electrode connected to the gate of the drive transistor in the third period (light emission period) is prevented from entering a floating state for the following reason. Here, pixels connected to the first data transfer line as an example of the same second conductive layer via the second data transfer line as an example of the third conductive layer and the first capacitor (transfer capacitor). A set of circuits is referred to as a “pixel column”, and a set of a predetermined number of pixel circuits connected to the second data transfer line is referred to as a “block”. According to this aspect, the period in which the first transistor is turned on and the initial potential is supplied to the second data transfer line is provided in the third period (light emission period) in one block. As a result, the potential of the second data transfer line can be prevented from approaching the power supply voltage. As a result, the second transistor 122 is not turned on, and the gate voltage of the driving transistor is not fluctuated, so that display defects do not occur.

  In the electro-optical device according to another aspect of the invention, the first transistor is turned on during the first period in one of the blocks and in the third period in the other block. An initial potential is supplied to the layer. According to this aspect, in the first period (compensation period) in one block, the first transistor is turned on and the first data transfer line as an example of the second conductive layer and the third conductive layer as an example. The second data transfer line is turned on, the second transistor and the third transistor are turned off, and an initial potential is supplied to the second data transfer line. At this time, since the other period is the third period (light emission period), the first transistor is also turned on in the other block to supply the initial potential to the second data transfer line. Therefore, it is possible to suppress the potential of the second data transfer line from approaching the power supply voltage while simplifying the control. As a result, the second transistor 122 is not turned on, and the gate voltage of the driving transistor is not fluctuated, so that display defects do not occur.

  In the electro-optical device according to another aspect of the invention, the initial potential is supplied to the second conductive layer in the first period in one block, and the first transistor is turned on in another block. The initial potential is supplied to the third conductive layer by bringing the second conductive layer and the third conductive layer into a conductive state. According to this aspect, in the first period (compensation period) in one block, the first transistor is turned on and the first data transfer line as an example of the second conductive layer and the third conductive layer as an example. The second data transfer line is turned on, the second transistor and the third transistor are turned off, and an initial potential is supplied to the second data transfer line. At this time, since the third period (light emission period) is set in the other blocks, the first transistor is also turned on in the other blocks so that the first data transfer line and the second data transfer line are brought into conduction. Thus, an initial potential is supplied to the second data transfer line. Therefore, it is possible to suppress the potential of the second data transfer line from approaching the power supply voltage while simplifying the control. As a result, the second transistor 122 is not turned on, and the gate voltage of the driving transistor is not fluctuated, so that display defects do not occur.

  An electro-optical device according to another aspect of the invention includes a fourth conductive layer that supplies the initial potential, and the first transistor electrically connects the fourth conductive layer and the third conductive layer. A transistor to be in a state or a non-conductive state, in the first period in one of the blocks, and in a third period in the other block, the first transistor is turned on and the fourth conductive layer and An initial potential is supplied to the third conductive layer by bringing the third conductive layer into a conductive state. According to this aspect, in the first period (compensation period) in one block, the first transistor is turned on and the first data transfer line as an example of the second conductive layer and the third conductive layer as an example. The second data transfer line is turned on, the second transistor and the third transistor are turned off, and an initial potential is supplied to the second data transfer line. At this time, since the third period (light emission period) is set in the other blocks, the first transistor is also turned on in the other blocks so that the first data transfer line and the second data transfer line are brought into conduction. Thus, the initial potential is supplied to the second data transfer line by bringing the initial potential supply line and the second data transfer line into a conductive state. Therefore, it is possible to suppress the potential of the second data transfer line from approaching the power supply voltage while simplifying the control. As a result, the second transistor 122 is not turned on, and the gate voltage of the driving transistor is not fluctuated, so that display defects do not occur.

The electro-optical device according to another aspect of the invention is characterized in that the first transistor is provided in common to the plurality of pixel circuits. According to this aspect, the above-described control is performed in the plurality of pixel circuits, and the potential of the second data transfer line can be prevented from approaching the power supply voltage. As a result, the second transistor 122 is not turned on, and the gate voltage of the driving transistor is not fluctuated, so that display defects do not occur. In addition, the number of first transistors in the electro-optical device can be reduced.
In addition, an electro-optical device according to another aspect of the invention is provided for each of the pixel circuits. According to this aspect, the above-described control is performed for each pixel circuit, and the potential of the second data transfer line can be prevented from approaching the power supply voltage. As a result, the second transistor 122 is not turned on, and the gate voltage of the driving transistor is not fluctuated, so that display defects do not occur.

An electro-optical device according to another aspect of the invention is characterized in that the first capacitor is provided for each of the third conductive layers. According to this aspect, the above-described control is performed for each pixel circuit, and the potential of the second data transfer line as an example of the third conductive layer and the potential of the first capacitor connected to the second data transfer line. Can be prevented from approaching the power supply voltage. As a result, the second transistor 122 is not turned on, and the gate voltage of the driving transistor is not fluctuated, so that display defects do not occur.
In order to achieve the above object, an electronic apparatus according to an aspect of the present invention includes the electro-optical device according to any one of the above aspects. According to this aspect, an electronic apparatus including the electro-optical device according to any one of the above aspects is provided.

In order to achieve the above object, a driving method of an electro-optical device according to one embodiment of the present invention includes a first conductive layer, a second conductive layer, a third conductive layer, and the second conductive layer. A first capacitor including a first electrode connected to the second conductive layer, a second capacitor connected to the third conductive layer, and the second conductive layer and the third conductive layer in a conductive state or non-conductive state. A first transistor to be in a conductive state; and a pixel circuit provided corresponding to the third conductive layer and the first conductive layer. The pixel circuit includes a gate electrode, a first current terminal And a driving transistor having a second current end, the third conductive layer, a second transistor connected between the gate electrode of the driving transistor, and the first current end of the driving transistor; A first for electrically connecting the gate electrode of the driving transistor; A light-emitting element that emits light with a luminance corresponding to the magnitude of current supplied through the driving transistor, wherein at least one third conductive layer includes the first capacitor. A set of pixel circuits connected to each other through the third conductive layer and connected to the same second conductive layer as a pixel column, and a number equal to or less than the number of the pixel circuits included in the pixel column The electro-optical device driving method using the pixel circuit as one block, wherein the first transistor is turned on and the second conductive layer and the third conductive layer are in a conductive state in the first period. And turning off the second transistor and the third transistor, supplying an initial potential to the second data transfer line, and turning off the first transistor in a second period following the first period. The second conductive layer and the third conductive layer are brought into a non-conductive state, at least the third transistor is turned on, the first current terminal of the driving transistor, and the gate electrode of the driving transistor And continuity,
In a third period following the second period, the first transistor is turned off to bring the second conductive layer and the third conductive layer into a non-conductive state, and the second transistor and the third transistor To turn off the first current terminal of the driving transistor and the light emitting element, to cause the light emitting element to emit light,
In the third period in one block, a period in which the first transistor is turned on and an initial potential is supplied to the third conductive layer is provided.

  According to this aspect, the electrode connected to the gate of the drive transistor in the third period (light emission period) is prevented from entering a floating state for the following reason. Here, pixels connected to the first data transfer line as an example of the same second conductive layer via the second data transfer line as an example of the third conductive layer and the first capacitor (transfer capacitor). A set of circuits is referred to as a “pixel column”, and a set of a predetermined number of pixel circuits connected to the second data transfer line is referred to as a “block”. According to this aspect, the period in which the first transistor is turned on and the initial potential is supplied to the second data transfer line is provided in the third period (light emission period) in one block. As a result, the potential of the second data transfer line can be prevented from approaching the power supply voltage. As a result, the second transistor 122 is not turned on, and the gate voltage of the driving transistor is not fluctuated, so that display defects do not occur.

1 is a perspective view illustrating a configuration of an electro-optical device according to a first embodiment of the invention. 2 is a block diagram illustrating a configuration of the electro-optical device. FIG. FIG. 3 is a circuit diagram for explaining a configuration of a demultiplexer and a data transfer circuit of the electro-optical device. FIG. 3 is a circuit diagram illustrating a configuration of a pixel circuit of the electro-optical device. It is a figure explaining the structure peculiar to the electro-optical device. It is a figure explaining the conventional structure shown as a comparative example. 6 is a timing chart showing the operation of the electro-optical device. FIG. 6 is an operation explanatory diagram of the same electro-optical device. 6 is a timing chart showing the operation of the electro-optical device. FIG. 6 is an operation explanatory diagram of the same electro-optical device. FIG. 6 is an operation explanatory diagram of the same electro-optical device. FIG. 6 is an operation explanatory diagram of the same electro-optical device. 6 is a timing chart showing the operation of the electro-optical device. FIG. 6 is an operation explanatory diagram of the same electro-optical device. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is sectional drawing of a light-emitting device. FIG. 10 is an explanatory diagram of each element formed on a substrate of an electro-optical device according to a second embodiment of the invention. It is explanatory drawing of each element formed on a board | substrate. It is sectional drawing of a light-emitting device. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. FIG. 6 is a circuit diagram illustrating a configuration of a pixel circuit of an electro-optical device according to a third embodiment of the invention. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is sectional drawing of a light-emitting device. FIG. 10 is a circuit diagram illustrating a configuration of a pixel circuit of an electro-optical device according to a fourth embodiment of the invention. It is explanatory drawing of each element formed on a board | substrate. It is explanatory drawing of each element formed on a board | substrate. It is sectional drawing of a light-emitting device. It is a circuit diagram which shows the structure of the pixel circuit which concerns on a modification. It is a circuit diagram which shows the structure of the pixel circuit which concerns on a modification. It is a figure which shows the relationship between the 1st data transfer line of the pixel circuit which concerns on a modification, transfer capacity, a 2nd data transfer line, and a pixel circuit. It is a figure which shows the external appearance structure of HMD. It is a figure which shows the optical structure of HMD.

<First Embodiment>
FIG. 1 is a perspective view showing a configuration of an electro-optical device 1 according to the first embodiment of the present invention. The electro-optical device 1 is a micro display that displays an image on a head-mounted display, for example.
As shown in FIG. 1, the electro-optical device 1 includes a display panel 2 and a control circuit 3 that controls the operation of the display panel 2. The display panel 2 includes a plurality of pixel circuits and a drive circuit that drives the pixel circuits. In the present embodiment, a plurality of pixel circuits and drive circuits included in the display panel 2 are formed on a silicon substrate, and an OLED which is an example of a light emitting element is used for the pixel circuits. The display panel 2 is housed in, for example, a frame-shaped case 82 that opens at the display unit, and one end of an FPC (Flexible Printed Circuits) substrate 84 is connected.
On the FPC board 84, the control circuit 3 of the semiconductor chip is mounted by COF (Chip On Film) technology, and a plurality of terminals 86 are provided, and are connected to an upper circuit (not shown).

FIG. 2 is a block diagram illustrating a configuration of the electro-optical device 1 according to the embodiment. As described above, the electro-optical device 1 includes the display panel 2 and the control circuit 3.
Digital image data Vdata is supplied to the control circuit 3 in synchronization with a synchronization signal from an upper circuit (not shown). Here, the image data Vdata is data that defines the gradation level of pixels of an image to be displayed on the display panel 2 (strictly speaking, the display unit 100 described later) by, for example, 8 bits. The synchronization signal is a signal including a vertical synchronization signal, a horizontal synchronization signal, and a dot clock signal.

The control circuit 3 generates various control signals based on the synchronization signal and supplies them to the display panel 2. Specifically, the control circuit 3 controls the display panel 2 with a control signal Ctr, a positive logic control signal Gini, a negative logic control signal / Gini having a logic inversion relationship therewith, and a positive logic signal. Control signal Gcpl, negative logic control signal / Gcpl in a logic inversion relationship with this, control signals Sel (1), Sel (2), Sel (3), and logic inversion relationship with these signals Control signals / Sel (1), / Sel (2), and / Sel (3).
Here, the control signal Ctr is a signal including a plurality of signals such as a pulse signal, a clock signal, and an enable signal.
The control signals Sel (1), Sel (2), and Sel (3) are collectively referred to as the control signal Sel, and the control signals / Sel (1), / Sel (2), and / Sel (3) are used as the control signals. / Sel may be collectively called.
The control circuit 3 includes a voltage generation circuit 31. The voltage generation circuit 31 supplies various potentials to the display panel 2. Specifically, the control circuit 3 supplies the display panel 2 with a reset potential Vorst, an initial potential Vini, and the like.

  Further, the control circuit 3 generates an analog image signal Vid based on the image data Vdata. Specifically, the control circuit 3 is provided with a lookup table that stores the potential indicated by the image signal Vid and the luminance of a light emitting element (an OLED 130 described later) included in the display panel 2 in association with each other. The control circuit 3 generates an image signal Vid indicating a potential corresponding to the luminance of the light emitting element specified by the image data Vdata by referring to the lookup table, and supplies the image signal Vid to the display panel 2. To do.

As shown in FIG. 2, the display panel 2 includes a display unit 100 and drive circuits (a data transfer line drive circuit 5 and a scan line drive circuit 6) that drive the display unit 100.
In the display unit 100, pixel circuits 110 corresponding to pixels of an image to be displayed are arranged in a matrix. Specifically, in the display unit 100, M rows of scanning lines 12 are provided extending in the horizontal direction (X direction) in the drawing, and the first data of (3N) columns grouped every three columns. The transfer line 14-1 extends in the vertical direction (Y direction) in the figure, and is provided so as to be electrically insulated from each scanning line 12.
Although not shown in FIG. 2 in order to avoid complication of the drawing, the second data transfer line 14-2 can be electrically connected to each first data transfer line 14-1. And it is extended and provided in the vertical direction (Y direction) (for example, refer FIG. 4). Pixel circuits 110 are provided corresponding to the M rows of scanning lines 12 and the (3N) columns of second data transfer lines 14-2. Therefore, in the present embodiment, the pixel circuits 110 are arranged in a matrix with vertical M rows × horizontal (3N) columns.

Here, M and N are both natural numbers. In order to distinguish rows (rows) in the matrix of the scanning lines 12 and the pixel circuits 110, they may be referred to as 1, 2, 3,. Similarly, in order to distinguish the columns of the first data transfer line 14-1 and the matrix of the pixel circuit 110, 1, 2, 3,..., (3N-1), (3N) columns in order from the left in the figure. Sometimes called.
Here, in order to generalize and describe the group of the first data transfer lines 14-1, when an arbitrary integer of 1 or more is expressed as n, the nth group counted from the left includes (3n-2). That is, the first data transfer line 14-1 of the column, the (3n-1) th column, and the (3n) th column belongs.

  The three pixel circuits 110 corresponding to the scanning lines 12 in the same row and the three columns of the second data transfer lines 14-2 belonging to the same group have R (red), G (green), and B (blue), respectively. ) Represent one dot of a color image to be displayed. That is, in the present embodiment, one dot color is expressed by additive color mixing by light emission of an OLED corresponding to RGB.

  As shown in FIG. 2, in the display unit 100, (3N) rows of power supply lines (reset potential supply lines) 16 extend in the vertical direction and are electrically insulated from each scanning line 12. Provided. A predetermined reset potential Vorst is commonly supplied to the power supply lines 16. Here, in order to distinguish the columns of the feeder lines 16, they may be referred to as the feeder lines 16 in the first, second, third,. Each of the first to (3N) th column feeder lines 16 corresponds to each of the first to (3N) th column first data transfer line 14-1 (second data transfer line 14-2). Provided.

The scanning line driving circuit 6 generates a scanning signal Gwr for sequentially scanning the M scanning lines 12 for each row within a period of one frame in accordance with the control signal Ctr. Here, the scanning signals Gwr supplied to the scanning lines 12 in the 1, 2, 3,..., M rows are respectively Gwr (1), Gwr (2), Gwr (3),. ) And Gwr (M).
In addition to the scanning signals Gwr (1) to Gwr (M), the scanning line driving circuit 6 generates various control signals synchronized with the scanning signal Gwr for each row and supplies them to the display unit 100. Illustration is omitted in FIG. The frame period is a period required for the electro-optical device 1 to display an image for one cut (frame). For example, if the frequency of the vertical synchronization signal included in the synchronization signal is 120 Hz, the first period is 1. This is a period of 8.3 milliseconds corresponding to the period.

  The data transfer line drive circuit 5 includes (3N) data transfer circuits DT provided in a one-to-one correspondence with each of the (3N) columns of the first data transfer lines 14-1, and the three columns constituting each group. N demultiplexers DM provided for each first data transfer line 14-1 and a data signal supply circuit 70.

  The data signal supply circuit 70 generates data signals Vd (1), Vd (2),..., Vd (N) based on the image signal Vid and the control signal Ctr supplied from the control circuit 3. That is, the data signal supply circuit 70 uses the data signals Vd (1), Vd (2),..., Vd (N) based on the image signal Vid obtained by time division multiplexing. ..., Vd (N) is generated. The data signal supply circuit 70 applies the data signals Vd (1), Vd (2),..., Vd (N) to the demultiplexers DM corresponding to the 1, 2,. Supply.

  FIG. 3 is a circuit diagram for explaining the configuration of the demultiplexer DM and the data transfer circuit DT. FIG. 3 representatively shows the demultiplexer DM belonging to the nth group and the three data transfer circuits DT connected to the demultiplexer DM. Hereinafter, the demultiplexer DM belonging to the nth group may be referred to as DM (n).

The configuration of the demultiplexer DM and the data transfer circuit DT will be described below with reference to FIG. 3 in addition to FIG.
As shown in FIG. 3, the demultiplexer DM is an aggregate of transmission gates 34 provided for each column, and sequentially supplies data signals to three columns constituting each group. Here, the input ends of the transmission gates 34 corresponding to the (3n-2), (3n-1), and (3n) columns belonging to the nth group are commonly connected to each other, and the data signal Vd ( n) is supplied. The transmission gate 34 provided in the (3n-2) column which is the leftmost column in the nth group is when the control signal Sel (1) is at the H level (when the control signal / Sel (1) is at the L level) ) Is turned on (conductive). Similarly, in the nth group, the transmission gates 34 provided in the (3n-1) column, which is the central column, have the control signal Sel (2) at the H level (the control signal / Sel (2) is at the L level. The transmission gate 34 provided in the (3n) column, which is the rightmost column in the nth group, when the control signal Sel (3) is at the H level (control signal / Sel (3) Is on).

  The data transfer circuit DT has a set of a storage capacitor (third capacitor) 41, a transmission gate 45, and a transmission gate 42 for each column, and outputs from the transmission gates 34 in each column in an initialization period and a compensation period to be described later. The potential of the data signal output from the end is stored in the storage capacitor (third capacitor) 41, and the potential of the data signal stored in the storage capacitor (third capacitor) 41 in the writing period described later is stored in the transfer capacitor 133. It is a circuit to transfer.

  The source or drain of the transmission gate 45 in each column is electrically connected to the first data transfer line 14-1. The control circuit 3 supplies the control signal / Gini in common to the gates of the transmission gates 45 in each column. The transmission gate 45 electrically connects the first data transfer line 14-1 and the supply line of the initial potential Vini when the control signal / Gini is at L level, and when the control signal / Gini is at H level. Electrically disconnected. A predetermined initial potential Vini is supplied from the control circuit 3 to the supply line 61 for the initial potential Vini.

The storage capacitor 41 has two electrodes. One electrode of the storage capacitor 41 is electrically connected to the input terminal of the transmission gate 42 via the node h. The output terminal of the transmission gate 42 is electrically connected to the first data transfer line 14-1.
The control circuit 3 supplies the control signal Gcpl and the control signal / Gcpl in common to the transmission gates 42 in each column. For this reason, the transmission gates 42 in each column are simultaneously turned on when the control signal Gcpl is at the H level (when the control signal / Gcpl is at the L level).

One electrode of the storage capacitor 41 in each column is electrically connected to the output end of the transmission gate 34 and the input end of the transmission gate 42 via the node h. When the transmission gate 34 is turned on, the data signal Vd (n) is supplied to one electrode of the storage capacitor 41 via the output terminal of the transmission gate 34. That is, in the storage capacitor 41, the data signal Vd (n) is supplied to one electrode.
The other electrode of the storage capacitor 41 in each column is connected in common to a power supply line 63 to which a potential Vss that is a fixed potential is supplied. Here, the potential Vss may correspond to an L level of a scanning signal or a control signal that is a logic signal. Note that the capacitance value of the storage capacitor 41 is Crf.

The pixel circuit 110 and the like will be described with reference to FIG. In order to generally indicate a row in which the pixel circuit 110 is arranged, an arbitrary integer of 1 to M is represented as m. Moreover, it is 1 or more and M or less, and the arbitrary continuous integers are represented as m1 and m2. That is, m is a generalized concept including m1 and m2.
Since each pixel circuit 110 has the same configuration when viewed electrically, it is here positioned in the m-th row and is located in the (3n-2) -th column of the leftmost column in the n-th group. A description will be given by taking the pixel circuit 110 in the (3n-2) column as an example.

As shown in FIG. 4, the first electrode 133-1 of the transfer capacitor (first capacitor) 133 and one of the source and drain of the first transistor 126 are electrically connected to the first data transfer line 14-1. It is connected. The second electrode 133-2 of the transfer capacitor 133 and the other of the source and the drain of the first transistor 126 are electrically connected to the second data transfer line 14-2.
That is, the transfer capacitor 133 and the first transistor 126 are connected in parallel between the first data transfer line 14-1 and the second data transfer line 14-2.
The pixel circuit 110 is connected to the second data transfer line 14-2. In other words, the pixel circuit 110 is supplied with a gradation potential corresponding to the designated gradation via the first data transfer line 14-1 and the second data transfer line 14-2.

In the present embodiment, one pixel circuit 110 is electrically connected to one second data transfer line 14-2.
However, the present invention is not limited to such a configuration, and Nb pixel circuits 110 may be electrically connected to one second data transfer line 14-2. That is, the plurality of pixel circuits 110 may share one second data transfer line 14-2, one transfer capacitor 133, and the first transistor 126.

FIG. 5 is a diagram for explaining a configuration unique to the present embodiment. In the present embodiment, two or more second data transfer lines 14-2 are connected to the first data transfer line 14-1 via transfer capacitors 133, as shown in FIG.
Here, a set of pixel circuits 110 connected to the same first data transfer line 14-1 via the second data transfer line 14-2 and the transfer capacitor 133 is referred to as a “pixel column” (in FIG. 5). Pixel column P). A set of a predetermined number of pixel circuits 110 is referred to as a “block” (block B in FIG. 5).
As shown in FIG. 5, the pixel column P includes a plurality of blocks B, and each block B includes a plurality of pixel circuits 110. That is, in the present embodiment, the second data transfer line 14-2 is provided for the number of pixel circuits 110 equal to the number of pixel circuits 110 included in the pixel column P.
In contrast, the conventional configuration is shown in FIG. FIG. 6 is a diagram illustrating a conventional configuration shown as a comparative example. As shown in the figure, in the conventional configuration, the second data transfer line 14-2 is provided for the pixel column P, and the transfer capacitor 133 and the first data transfer line 14-1 are provided at the end thereof. ing. That is, in the conventional configuration, one first data transfer line 14-1 and one second data transfer line 14-2 are provided for one pixel column P (all the pixel circuits 110 included therein). Is provided. This point is a configuration peculiar to the present embodiment described with reference to FIG. 5, that is, a plurality of second data transfer lines 14-2 are divided and provided for each block B constituting the pixel column P. Clearly different.

By the way, as shown in the following (Formula 1), the total number of rows M of the pixel circuits 110 in the display unit 100 is set to the number of rows Nb of the pixel circuits 110 connected to one second data transfer line 14-2. Let K be the value divided by. In other words, the second data transfer line 14-2 is divided into K lines, which is a value obtained by dividing M by Nb, and Nb pixel circuits 110 are connected to one second data transfer line 14-2. Suppose that

In the present embodiment, K (K ≧ 2) × Nb second data transfer lines 14-2 are provided for one first data transfer line 14-1. In other words, one pixel column P includes K blocks B. The first data transfer line 14-1 is provided corresponding to M rows (M pieces) of pixel circuits 110, and the second data transfer line 14-2 is provided for Nb rows (Nb pieces) of pixel circuits 110. 110 is provided. Therefore, the second data transfer line 14-2 is shorter than the first data transfer line 14-1.
In the present embodiment, the value of Nb is 1. Note that k is used as an arbitrary integer of 1 to K.
Hereinafter, the first transistor 126 corresponding to each pixel circuit 110 in the m-th row counted from the first row is assumed to be the m-th first transistor 126 counted from the first row, and the control signal Gfix (m) is Suppose that it is supplied.

  The pixel circuit 110 includes P-channel MOS transistors 121 to 125, an OLED 130, and a pixel capacitor 132. A scanning signal Gwr (m), control signals Gcmp (m), Gel (m), and Gorst (m) are supplied to the pixel circuit 110 in the m-th row. Here, the scanning signal Gwr (m), the control signals Gcmp (m), Gel (m), and Gorst (m) are respectively supplied by the scanning line driving circuit 6 corresponding to the m-th row.

  Although not shown in FIG. 2, as shown in FIG. 4, the display panel 2 (display unit 100) has M rows of control lines 143 (first control lines) extending in the horizontal direction (X direction), M rows of control lines 144 (second control lines) extending in the horizontal direction, M rows of control lines 145 (third control lines) extending in the horizontal direction, and K rows of control lines 146 extending in the horizontal direction. (Fourth control line) is provided.

Then, the scanning line driving circuit 6 supplies the control signal Gcmp (m) to the m-th control line 143, supplies the control signal Gel (m) to the m-th control line 144, and m A control signal Gorst (m) is supplied to the control line 145 in the row, and a control signal Gfix (m) is supplied to the control line 146 in the mth row.
That is, the scanning line driving circuit 6 sends the scanning signal Gwr (m), the control signals Gel (m), Gcmp (m), and Gorst (m) to the pixel circuit located in the m-th row, respectively. It is supplied through the scanning line 12 of the eye and the control lines 143, 144 and 145. Further, the control signal Gfix (m) is supplied to the first transistor 126 located in the m-th row via the control line 146 in the m-th row.
Hereinafter, the scanning line 12, the control line 143, the control line 144, the control line 145, and the control line 146 may be collectively referred to as “control line”. That is, in the display panel 2 according to the present embodiment, four control lines including the scanning lines 12 are provided in each row, and one control line 146 is provided for each row.

Each of the pixel capacitor 132 and the transfer capacitor 133 has two electrodes. The transfer capacitor 133 is a capacitance that includes the first electrode 133-1 and the second electrode 133-2.
The second transistor 122 has a gate electrically connected to the m-th scanning line 12 and one of a source and a drain electrically connected to the second data transfer line 14-2. In the second transistor 122, the other of the source and the drain is electrically connected to the gate of the driving transistor 121 and one electrode of the pixel capacitor 132. That is, the second transistor 122 is electrically connected between the gate of the driving transistor 121 and the second electrode 133-2 of the transfer capacitor 133. The second transistor 122 is electrically connected between the gate of the driving transistor 121 and the second electrode 133-2 of the transfer capacitor 133 connected to the second data transfer line 14-2 in the (3n-2) th column. Functions as a transistor that controls general connections.

The source of the driving transistor 121 is electrically connected to the power supply line 116, and the drain thereof is electrically connected to one of the source and the drain of the third transistor 123 and the source of the fourth transistor 124.
Here, the power supply line 116 is supplied with a potential Vel that is higher in the power supply in the pixel circuit 110. The drive transistor 121 functions as a drive transistor that passes a current according to the voltage between the gate and the source of the drive transistor 121.
The third transistor 123 has a gate electrically connected to the control line 143 and is supplied with a control signal Gcmp (m). The third transistor 123 functions as a switching transistor that controls electrical connection between the gate and drain of the driving transistor 121. Therefore, the third transistor 123 is a transistor for conducting between the gate and the drain of the driving transistor 121 through the second transistor 122. The second transistor 122 is connected between one of the source and drain of the third transistor 123 and the gate of the driving transistor 121, but one of the source and drain of the third transistor 123 is connected to the driving transistor 121. It can also be interpreted as being electrically connected to the gate.

The fourth transistor 124 has a gate electrically connected to the control line 144 and is supplied with a control signal Gel (m). The drain of the fourth transistor 124 is electrically connected to the source of the fifth transistor 125 and the anode 130a of the OLED 130, respectively. The fourth transistor 124 functions as a switching transistor that controls electrical connection between the drain of the driving transistor 121 and the anode of the OLED 130. Furthermore, although the fourth transistor 124 is connected between the drain of the driving transistor 121 and the anode of the OLED 130, the drain of the driving transistor 121 can be interpreted as being electrically connected to the anode of the OLED 130.
The fifth transistor 125 has a gate electrically connected to the control line 145 and is supplied with a control signal Gorst (m). The drain of the fifth transistor 125 is electrically connected to the feeder line 16 in the (3n-2) th column and is kept at the reset potential Vorst. The fifth transistor 125 functions as a switching transistor that controls electrical connection between the power supply line 16 and the anode 130 a of the OLED 130.

The first transistor 126 has a gate electrically connected to the control line 146 and is supplied with a control signal Gfix (k). The first transistor 126 has one of a source and a drain electrically connected to the second data transfer line 14-2, and the second electrode 133- of the transfer capacitor 133 via the second data transfer line 14-2. The second and third transistors 123 are electrically connected to the other of the source and the drain. The other of the source and the drain of the first transistor 126 is electrically connected to the first data transfer line 14-1 in the (3n-2) th column.
The first transistor 126 mainly functions as a switching transistor that controls electrical connection between the first data transfer line 14-1 and the second data transfer line 14-2.
Here, the first transistor 126 and the transfer capacitor 133 are shared by the Nb pixel circuits 110 connected to the same second data transfer line 14-2. In the present embodiment, as shown in FIG. 4, the pixel circuits 110 in each row are connected to one identical second data transfer line 14-2.

  In the present embodiment, since the display panel 2 is formed on a silicon substrate, the substrate potentials of the transistors 121 to 126 are set to the potential Vel. In addition, the sources and drains of the transistors 121 to 126 in the above may be switched depending on the channel type and potential relationship of the transistors 121 to 126. The transistor may be a thin film transistor or a field effect transistor.

In the pixel capacitor 132, one electrode is electrically connected to the gate g of the driving transistor 121, and the other electrode is electrically connected to the power supply line 116. Therefore, the pixel capacitor 132 functions as a storage capacitor that holds a voltage between the gate and the source of the driving transistor 121. The capacitance value of the pixel capacitor 132 is expressed as Cpix.
As the pixel capacitor 132, a capacitor parasitic to the gate g of the driving transistor 121 may be used, or a capacitor formed by sandwiching an insulating layer between different conductive layers in a silicon substrate may be used.

  In the transfer capacitor 133, the first electrode 133-1 is electrically connected to one electrode of the storage capacitor 41 via the first data transfer line 14-1 and the transmission gate 42. In the transfer capacitor 133, the second electrode 133-2 is electrically connected to the gate g of the driving transistor 121 through the second data transfer line 14-2 and the second transistor 122. For this reason, the transfer capacitor 133 sets the potential of the gate g to the transfer capacitor 133 and the storage capacitor with respect to the amount of change in the potential of the first data transfer line 14-1 and the first electrode 133-1 in a compensation period to be described later. It functions as a transfer capacity for level shifting by a value obtained by multiplying the capacity ratio with 41. Details will be described later. The capacity value of the transfer capacity 133 is expressed as C1.

  In the present embodiment, a shield capacitor 134 is provided between the power supply line 16 to which the reset potential Vorst is supplied and the first data transfer line 14-1. The transfer capacitor 133 is a capacitance including the first electrode 134-1 and the second electrode 134-2. The shield capacitor 134 functions as a shield capacitor that shields the first data transfer line 14-1. The capacitance value of the shield capacitor 134 is expressed as C2.

  The anode 130 a of the OLED 130 is a pixel electrode provided individually for each pixel circuit 110. On the other hand, the cathode of the OLED 130 is a common electrode 118 provided in common throughout the pixel circuit 110, and is maintained at the potential Vct that is the lower side of the power supply in the pixel circuit 110. The OLED 130 is an element in which a white organic EL layer is sandwiched between an anode 130a and a light-transmitting cathode in the silicon substrate. A color filter corresponding to any of RGB is superimposed on the emission side (cathode side) of the OLED 130. Note that the wavelength of light emitted from the OLED 130 may be set by adjusting the optical distance between two reflective layers arranged with the white organic EL layer interposed therebetween to form a cavity structure. In this case, a color filter may or may not be provided.

  In such an OLED 130, when a current flows from the anode 130a to the cathode, holes injected from the anode 130a and electrons injected from the cathode are recombined in the organic EL layer to generate excitons, and white light is generated. Occur. The white light generated at this time is transmitted through the cathode on the opposite side to the silicon substrate (anode 130a), and is colored by a color filter so as to be visually recognized by the viewer.

The operation of the electro-optical device 1 will be described with reference to FIG. FIG. 7 is a timing chart for explaining the operation of each part in the electro-optical device 1. As shown in this figure, the scanning line driving circuit 6 sequentially switches the scanning signals Gwr (1) to Gwr (M) to the L level, and sets the scanning lines 12 in the 1st to Mth rows to 1 in the period of one frame. Scan in order for each horizontal scanning period (H).
The operation in one horizontal scanning period (H) is common to the pixel circuits 110 in each row. Therefore, in the following, the operation will be described focusing on the pixel circuit 110 in the m1 row (3n-2) column in the horizontal scanning period in which the m1 row is horizontally scanned.

  In the present embodiment, the horizontal scanning period of the m1th row is roughly divided into an initialization period indicated by (a) in FIG. 7, a compensation period indicated by (b), and a writing period indicated by (c). And a non-light emitting period indicated by (d). In the next horizontal scanning period, the non-light emission period indicated by (d) continues, and the next horizontal scanning period becomes the light emission period indicated by (e), after the elapse of one frame period, the m1th row again. The horizontal scanning period is reached. For this reason, in the order of time, the cycle of initialization period → compensation period → writing period → non-light emission period → light emission period is repeated.

  FIG. 8 is a diagram illustrating the operation of the pixel circuit 110 and the like during the light emission period. In FIG. 8, the current path that is important in the description of the operation is indicated by a bold line, and an “X” is indicated by a bold line on the transistor or transmission gate in the off state (see FIGS. 9, 10, and 10 below). The same applies to FIGS. 11 and 14).

<Initialization period>
As shown in FIG. 7, in the initialization period of the m1th row, the scanning signal Gwr (m1) is at the H level, the control signal Gel (m1) is at the H level, and the control signal Gcmp (m1) is at the H level. The control signal Gfix (m1) is at L level. The control signal Gorst (m1) is at the L level.
Therefore, as shown in FIG. 8, in the pixel circuit 110 in the m1 row (3n-2) column, the fifth transistor 125 and the first transistor 126 are turned on, while the driving transistor 121, the second transistor 122, the third transistor The transistor 123 and the fourth transistor 124 are turned off. Thereby, the path of the current supplied to the OLED 130 is interrupted, so that the OLED 130 is turned off (non-light emitting).

  As shown in FIG. 8, when the fifth transistor 125 is turned on, the anode 130a of the OLED 130 and the power supply line 16 are electrically connected, and the potential of the anode 130a is set to the reset potential Vorst.

  Here, in the initialization period, in the data transfer circuit DT, the control signal / Gini becomes L level and the control signal Gini becomes H level, so that the transmission gate 45 is turned on as shown in FIG. Since it becomes L level and the control signal / Gcpl becomes H level, the transmission gate 42 is turned off as shown in FIG. Further, since the control signal Gfix (k) is at the L level, the first transistor 126 is turned on. For this reason, as shown in FIG. 8, the first data transfer line 14-1 connected to the first electrode 133-1 of the transfer capacitor 133 is set to the initial potential Vini, and the first data transfer line 14-1 is set. And the second data transfer line 14-2 are electrically connected, and the second electrode 133-2 of the transfer capacitor 133 is also set to the initial potential Vini. As a result, the transfer capacity 133 is initialized.

  Further, in the demultiplexer DM (n) in the initialization period, the control signal Sel (1) becomes H level and the control signal / Sel (1) becomes L level, so that the transmission gate 34 is shown in FIG. Turns on. As a result, the gradation potential is written in the storage capacitor 41 having the capacitance value Crf.

  By the way, in the present embodiment, the second data transfer line 14-2 to which the pixel circuit 110 in the m1 row (3n-2) column is connected to the pixel circuit 110 in the m2 row (3n-2) column. It is separate from the second data transfer line 14-2. Therefore, the first transistor 126 controlled by the control signal Gfix (m1) is used in the initialization period of the m1st row, and the control signal Gfix (m2) is used in the initialization period of the m2th row as shown in FIG. ) Is used to control the first transistor 126.

<Compensation period>
When the initialization period ends, the compensation period starts. In the compensation period of the m1st row, the scanning signal Gwr (m1) is at the L level, the control signal Gel (m1) is at the H level, the control signal Gcmp (m1) is at the L level, and the control signal Gfix (m1) Is at the H level. The control signal Gorst (m1) is at the L level.
For this reason, as shown in FIG. 10, in the pixel circuit 110 in the m1 row (3n-2) column, the second transistor 122, the third transistor 123, and the fifth transistor 125 are turned on, while the fourth transistor 124 and the second transistor 125 are turned on. One transistor 126 is turned off. At this time, the gate g of the driving transistor 121 is connected (diode-connected) to its own drain through the second transistor 122 and the third transistor 123, and a drain current flows through the driving transistor 121 to charge the gate g. .
That is, the drain and gate g of the driving transistor 121 are connected to the second data transfer line 14-2, and when the threshold voltage of the driving transistor 121 is Vth, the potential Vg of the gate g of the driving transistor 121 is (Vel− Vth) asymptotically.

  Here, in the data transfer circuit DT in the compensation period, since the control signal / Gini becomes L level and the control signal Gini becomes H level, the transmission gate 45 is turned on as shown in FIG. 10, and the control signal Gcpl Becomes L level and the control signal / Gcpl becomes H level, the transmission gate 42 is turned off. At this time, as described above, since the second data transfer line 14-2 is shorter than the conventional configuration, the time required for charging or discharging the parasitic capacitance associated with the second data transfer line 14-2 is shortened. The compensation period itself is shortened.

  Further, in the demultiplexer DM (n) in the compensation period, the control signal Sel (1) is at the H level and the control signal / Sel (1) is at the L level. Therefore, as shown in FIG. Turn on. As a result, the gradation potential is written in the storage capacitor 41 having the capacitance value Crf.

  Note that since the fourth transistor 124 is off, the drain of the driving transistor 121 is not electrically connected to the OLED 130. Similarly to the initialization period, when the fifth transistor 125 is turned on, the anode 130a of the OLED 130 and the power supply line 16 are electrically connected, and the potential of the anode 130a is set to the reset potential Vorst.

<Writing period>
When the compensation period ends, the writing period starts. In the writing period of the m1st row, the scanning signal Gwr (m1) is at the L level, the control signal Gel (m1) is at the H level, the control signal Gcmp (m1) is at the H level, and the control signal Gfix (m1) ) Is H level. The control signal Gorst (m1) is at the L level.
Therefore, as shown in FIG. 11, in the pixel circuit 110 in the m1 row (3n-2) column, the transistors 122 and 125 are turned on, while the transistors 123, 124, and 126 are turned off.

  Here, in the data transfer circuit DT in the writing period, since the control signal / Gini is at H level, the transmission gate 45 is turned off and the control signal Gcpl is at H level as shown in FIG. 11, the transmission gate 42 is turned on. For this reason, the supply of the initial potential Vini to the first data transfer line 14-1 and the first electrode 133-1 is canceled, and the capacitance to the first data transfer line 14-1 and the first electrode 133-1. One electrode of the storage capacitor 41 having the value Crf is connected, and a gradation potential is supplied to the first electrode 133-1. Then, a signal whose gradation potential is level-shifted is supplied to the gate of the driving transistor 121 and written to the pixel capacitor 132. As described above, in this embodiment, the level shift of the gradation potential is performed using the transmission gate 42, the holding capacitor 41, and the transfer capacitor 133 of the data transfer circuit DT. Note that, in the demultiplexer DM (n) in the writing period, the control signal Sel (1) becomes L level, so that the transmission gate 34 is turned off as shown in FIG.

  Note that since the fourth transistor 124 is off, the drain of the driving transistor 121 is not electrically connected to the OLED 130. Similarly to the initialization period, when the fifth transistor 125 is turned on, the anode 130a of the OLED 130 and the power supply line 16 are electrically connected, and the potential of the anode 130a is initialized to the reset potential Vorst.

Note that until the writing period of the m-th row is started (between the initialization period and the compensation period), the control circuit 3 sequentially outputs the data signal Vd (n) to m in the n-th group. The potential is switched to a potential corresponding to the gradation level of the pixels in the row (3n-2) column, the m row (3n-1) column, and the m row (3n) column.
On the other hand, the control circuit 3 exclusively sets the control signals Sel (1), Sel (2), and Sel (3) to the H level in order in accordance with the switching of the potential of the data signal. Although not shown, the control circuit 3 has control signals / Sel (1), / Sel (2) that are in a logically inverted relationship with the control signals Sel (1), Sel (2), and Sel (3). , / Sel (3) is also output. Accordingly, in the demultiplexer DM, the transmission gates 34 are turned on in the order of the left end column, the center column, and the right end column in each group.

ここでΔＶとΔＶｇとの比を、下記の(式３）で示すように圧縮率Ｒとする。

つまり、書込期間における駆動トランジスター１２１のゲートｇの電位Ｖｇは、補償期間における電位Ｖｇから、第１データ転送線１４−１及び第１電極１３３−１の電位の変化量ΔＶに対して、Ｒを乗じた値だけレベルシフトした（データ圧縮された）値となる。この書込期間を終えると、後述する発光期間が開始する。 By the way, when the transmission gate 34 in the leftmost column is turned on by the control signals Sel (1), / Sel (1), the amount of change in potential of the first data transfer line 14-1 and the first electrode 133-1 is ΔV. The change amount ΔVg of the potential of the gate g of the second data transfer line 14-2 and the driving transistor 121 can be expressed by the following (formula 2). However, the capacitance value C1 of the transfer capacitor 133 can be adjusted in proportion to the number of rows of the pixel circuit 110, and is assumed to be a capacitance C1a per row. The capacitance value of the parasitic capacitance associated with the second data transfer line 14-2 per row is C3a. As described above, the number of rows of the pixel circuits 110 connected to one second data transfer line 14-2 is represented as Nb.

Here, the ratio of ΔV and ΔVg is a compression ratio R as shown in the following (Equation 3).

That is, the potential Vg of the gate g of the driving transistor 121 in the writing period is R with respect to the amount of change ΔV in the potential of the first data transfer line 14-1 and the first electrode 133-1 from the potential Vg in the compensation period. The value is level-shifted (data compressed) by the value multiplied by. When this writing period ends, a light emission period to be described later starts.

From the relationship shown in (Equation 2), as the number Nb of pixel circuits 110 connected to one second data transfer line 14-2 increases, the number Nb of pixel circuits 110 included in one block increases. ΔVg and ΔV are close to each other. In other words, R shown in (Expression 4) approaches 1 as the value of Nb increases.
Here, the number Nb of pixel circuits 110 connected to the second data transfer line 14-2 (the number Nb of pixel circuits 110 included in one block) is the time required for completing the compensation operation and the compression rate of data compression. It is preferable to determine in view of the above. This will be specifically described below.
First, the time required for completing the compensation operation will be described. The potential Vg (compensation point) of the gate g of the driving transistor 121 at the end of the compensation period is preferably set to the intermediate gradation of the gradation voltage. However, the smaller the value of Nb, the more the driving transistor 121 has. Since the parasitic capacitance associated with the gate g becomes small, the compensation period becomes extremely short. As a result, the scanning signal Gwr (m) is affected by the rounding at the rising (falling) of the scanning signal Gwr (m). There is a risk that the compensation period will be different between the supply side and the supply side. In this case, the scanning line driving circuit 6 having a high driving capability to the extent that the concern is eliminated is necessary.
As for the compression ratio of data compression, as shown in (Equation 2), the smaller the Nb value, the larger the compression ratio, and conversely, the larger the Nb value, the smaller the compression ratio.
Therefore, it is preferable to determine the value of Nb to an appropriate value in view of the time required for completing the compensation operation and the compression rate of data compression. For example, when the total number of rows M is 720, Nb may be 90 and the total number of blocks K may be 8.

<Non-light emission period>
As shown in the timing chart of FIG. 7, when the scanning signal Gwr (m1) rises from the L level to the H level and the writing period ends, the remaining period of the one horizontal scanning period (H) and the next one horizontal scanning are performed. The period (H) is a non-light emitting period. In the non-light emitting period, all the transistors are turned off, and the control signal Gorst (m1) is at the L level.

<Light emission period>
When the non-light emission period ends, the light emission period starts. As shown in the timing chart of FIG. 7, in the light emission period of the m1th row, the scanning signal Gwr (m1) is at the H level, the control signal Gel (m1) is at the L level, and the control signal Gcmp (m1) is The control signal Gfix (k) is at the H level. The control signal Gorst (m1) is at the H level.
For this reason, as shown in FIG. 12, in the pixel circuit 110 of the m1 row (3n-2) column, the fourth transistor 124 is turned on, while the second transistor 122, the third transistor 123, the fifth transistor 125, One transistor 126 is turned off. As a result, the drive transistor 121 supplies the OLED 130 with a drive current Ids corresponding to the voltage held by the pixel capacitor 132, that is, the gate-source voltage Vgs. That is, the OLED 130 is supplied with a current corresponding to the gradation potential corresponding to the designated gradation of each pixel by the driving transistor 121 and emits light with a luminance corresponding to the current.

  Here, in the data transfer circuit DT during the light emission period, the control signal / Gini becomes H level and the control signal Gini becomes L level, so that the transmission gate 45 is turned off and the control signal Gcpl is L as shown in FIG. Since the control signal / Gcpl becomes H level, the transmission gate 42 is turned off. Further, in the demultiplexer DM (n) during the light emission period, the control signal Sel (1) becomes L level and the control signal / Sel (1) becomes H level, so that the transmission gate 34 is turned off.

  Since the light emission period of the m1st row is a period during which horizontal scanning is performed except for the m1st row, the transmission gate 34, the transmission gate 42, and the transmission gate 45 are turned on or off according to the operation of these rows. The potentials of the first data transfer line 14-1 and the second data transfer line 14-2 change as appropriate. In particular, when the first transistor 126, the second transistor 122, and the third transistor 123 are off, the second data transfer line 14-2 is in a floating state, and the potential is likely to fluctuate.

Therefore, in the present embodiment, the first data transfer line 14-1 and the second data transfer line 14-2 are made conductive by turning on the first transistor 126 during the light emission period in one block B. A period for supplying the initial potential Vini to the second data transfer line 14-2 is provided.
Assuming that the block to which the pixel circuit 110 such as the m1st row and the m2th row belongs is a block B (m), the initialization period in the block B (n) that is the next block after the block B (m) ) Is the light emission period. In the present embodiment, for example, if the block (n) next to the block B (m) is one block and the block B (m) is another block, the block B (n) that is one block is During the light emission period in the block B (m), which is another block, during the initialization period, the first transistor 126 is turned on to make the first data transfer line 14-1 and the second data transfer line 14-2 conductive. In this state, the initial potential Vini is supplied to the second data transfer line 14-2.

As shown in FIG. 13, in the period from time t1 to time t4, the initialization period, the compensation period, and the writing period are executed in block B (m).
From time t5 to time t6, the process of the initialization period is executed in the block B (n) that is the next block of the block B (m), and this period is the light emission period in the block B (m). However, in this embodiment, when the initialization period process is executed in the block B (n), the control signal Gfix is set to the L level in the block B (m) and other blocks B. As a result, as shown in FIG. 14, the first transistor 126 is turned on, and the first data transfer line 14-1 and the second data transfer line 14-2 in the other blocks B including the block B (m) Becomes conductive, and the initial potential Vini is supplied to the second data transfer line 14-2.

  Hereinafter, similarly, in the period from time t8 to time t9, the period from time t11 to time t12, and the period from time t14 to time t15 in which the process of the initialization period is executed in the block B (n), In other blocks B including the block B (m), the control signal Gfix is set to L level. As a result, as shown in FIG. 14, the first transistor 126 is turned on, and the first data transfer line 14-1 and the second data transfer line 14-2 in the other blocks B including the block B (m) Becomes conductive, and the initial potential Vini is supplied to the second data transfer line 14-2.

  As described above, according to the present embodiment, the second data transfer line 14-2 on the transfer capacitor 133 side of the second transistor 122 that becomes a floating node during the light emission period is processed in the initialization period in another block. Since the fixed potential is set to the initial potential Vini during the period to be performed, the potential of the second data transfer line 14-2 can be prevented from approaching the power supply voltage. As a result, the second transistor 122 is not turned on, the voltage is held in the pixel capacitor 132, and display defects do not occur.

<Structure>
Next, a specific structure of the electro-optical device 1 in the present embodiment will be described in detail below. In the drawings referred to in the following description, the dimensions and scales of the elements are different from those of the actual electro-optical device 1 for convenience of description. FIGS. 15 and 16 are plan views illustrating the state of the surface of the substrate 10 at each stage of forming each element of the electro-optical device 1 focusing on one pixel circuit 110. FIG. FIG. 17 is a cross-sectional view of the electro-optical device 1. A sectional view corresponding to the section including the line II ′ in FIGS. 15 and 16 corresponds to FIG. In addition, although it is a top view of FIG.15 and FIG.16, from the viewpoint of facilitating visual grasp of each element, the hatching of the same aspect as FIG. Yes.

As understood from the portion showing the active layer in FIG. 15 and FIG. 17, the transistors 121, 122, 123, 124, 125, 126 of the pixel circuit 110 are formed on the surface of the substrate 10 made of a semiconductor material such as silicon. Active region 10A (source / drain region) is formed. Ions are implanted into the active region 10A. An active layer of each of the transistors 121, 122, 123, 124, 125, 126 of the pixel circuit 110 exists between the source region and the drain region, and ions of a different type from the active region 10A are implanted. Are described integrally with the active region 10A.
As can be understood from the portion showing the gate layer in FIG. 15 and FIG. 17, the surface of the substrate 10 on which the active region 10A is formed is covered with an insulating film L0 (gate insulating film), and each of the transistors 121, 122, 123, 124 is covered. , 125, 126 are formed on the surface of the insulating film L0 (GTdr, GTwr, GTcmp, GTel, GTTorst, GTfix). The gate layer GT of each transistor 121, 122, 123, 124, 125, 126 is opposed to the active layer with the insulating film L0 interposed therebetween.

  As understood from FIG. 17, a plurality of insulating layers L (LA to LH) and a plurality of insulating layers L (LA to LH) are formed on the surface of the insulating film L0 on which the gate layers GT of the transistors 121, 122, 123, 124, 125, and 126 are formed. A multilayer wiring layer in which conductive layers (wiring layers) are alternately stacked is formed. Each insulating layer L is formed of an insulating inorganic material such as a silicon compound (typically silicon nitride or silicon oxide). In the following description, a relationship in which a plurality of elements are collectively formed in the same process by selective removal of a conductive layer (single layer or a plurality of layers) is referred to as “formed from the same layer”.

  The insulating layer LA is formed on the surface of the insulating film L0 on which the gate layer GT of each transistor 121, 122, 123, 124, 125, 126 is formed. As understood from the portion showing the metal layer A in FIG. 15 and FIG. 17, a plurality of relay electrodes QA (QA1 to Q12) are formed on the surface of the insulating layer LA.

  As understood from the portion showing the metal layer A in FIG. 15 and FIG. 17, the relay electrode QA1 is connected to the drain region or the source region of the first transistor 126 through the conduction hole HA2 penetrating the insulating film L0 and the insulating layer LA. Conductive to the active region 10A forming the. The relay electrode QA2 is electrically connected to the gate layer GTfix of the first transistor 126 through a conduction hole HB1 that penetrates the insulating layer LA. The relay electrode QA3 is electrically connected to the active region 10A that forms the drain region or the source region of the first transistor 126 through the conduction hole HA1 that penetrates the insulating film L0 and the insulating layer LA. The relay electrode QA3 is electrically connected to the active region 10A that forms the drain region or the source region of the third transistor 123 through the conduction hole HA7 that penetrates the insulating film L0 and the insulating layer LA. Further, the relay electrode QA3 is electrically connected to the active region 10A that forms the drain region or the source region of the second transistor 122 through the conduction hole HA9 that penetrates the insulating film L0 and the insulating layer LA. As described above, the relay electrode QA3 is a source electrode, and the active region 10A that forms the drain region or the source region of the first transistor 126, the active region 10A that forms the drain region or the source region of the third transistor 123, and the first region This is an electrode formed in direct contact with the active region 10A forming the drain region or source region of the two-transistor 122.

  The relay electrode QA4 is electrically connected to the active region 10A that forms the drain region or the source region of the fifth transistor 125 through the conduction hole HA4 that penetrates the insulating film L0 and the insulating layer LA. The relay electrode QA5 is electrically connected to the gate layer GTorst of the fifth transistor 125 through a conduction hole HB2 that penetrates the insulating layer LA. The relay electrode QA6 is electrically connected to the active region 10A that forms the drain region or the source region of the fifth transistor 125 through the conduction hole HA3 that penetrates the insulating layer LA and the insulating film L0.

  Further, the relay electrode QA6 is electrically connected to the active region 10A that forms the drain region or the source region of the fourth transistor 124 via the conduction hole HA5 that penetrates the insulating layer LA and the insulating film L0. The relay electrode QA7 is electrically connected to the gate layer GTel of the fourth transistor 124 through the conduction hole HB3 penetrating the insulating layer LA. The relay electrode QA8 is electrically connected to the active region 10A that forms the drain region or the source region of the fourth transistor 124 through the conduction hole HA6 that penetrates the insulating layer LA and the insulating film L0. The relay electrode QA8 is electrically connected to the active region 10A that forms the drain region or the source region of the third transistor 123 through the conduction hole HA8 that penetrates the insulating layer LA and the insulating film L0. Further, the relay electrode QA8 is electrically connected to the active region 10A that forms the drain region or the source region of the drive transistor 121 through the conduction hole HA12 that penetrates the insulating layer LA and the insulating film L0. As described above, the relay electrode QA6 is a source electrode, and is an electrode formed in direct contact with the active region 10A that forms the drain region or the source region of the fourth transistor 124. The relay electrode QA8 is also a source electrode, and the active region 10A that forms the drain region or the source region of the fourth transistor 124, the active region 10A that forms the drain region or the source region of the third transistor 123, and the drive transistor 121 This is an electrode formed in direct contact with the active region 10A forming the drain region or the source region.

  The relay electrode QA9 is electrically connected to the gate layer GTcmp of the third transistor 123 through a conduction hole HB4 that penetrates the insulating layer LA. The relay electrode QA10 is electrically connected to the gate layer GTwr of the second transistor 122 through a conduction hole HB5 that penetrates the insulating layer LA. The relay electrode QA11 is electrically connected to the active region 10A that forms the drain region or the source region of the second transistor 122 through the conduction hole HA10 that penetrates the insulating layer LA and the insulating film L0. The relay electrode QA11 is electrically connected to the gate layer GTdr of the drive transistor 121 through the conduction hole HB6 that penetrates the insulating layer LA. The relay electrode QA12 is electrically connected to the active region 10A that forms the drain region or the source region of the drive transistor 121 through the conduction hole HA11 that penetrates the insulating layer LA and the insulating film L0.

The insulating layer LB is formed on the surface of the insulating layer LA on which a plurality of relay electrodes QA (QA1, QA2, QA3, QA4, QA5, QA6, QA7, QA8, QA9, QA10, QA11, QA12) are formed. As can be understood from the portion showing the metal layer B in FIG. 15 and FIG. 17, the scanning line 12, the feeder line 116, the plurality of control lines 143 to 146, and the plurality of relay electrodes QB ( QB1, QB2, QB3, QB4) are formed.
As can be understood from the portion showing the metal layer B in FIG. 15 and FIG. 17, the scanning line 12 as an example of the first conductive layer is connected to the gate of the second transistor 122 through the conduction hole HC9 penetrating the insulating layer LB. Conductive to layer GTwr. The scanning line 12 extends along the channel length direction (X direction) of the second transistor 122 over the plurality of pixel circuits 110.

The power supply line 116 is electrically connected to a mounting terminal to which a higher power supply potential Vel is supplied via a wiring (not shown) in the multilayer wiring layer. The power supply line 116 is formed of a conductive material containing, for example, silver or aluminum and has a thickness of about 100 nm, for example. The power supply line 116 is electrically connected to the active region 10A that forms the drain region or the source region of the driving transistor 121 through the conduction hole HC10 that penetrates the insulating layer LB. The power supply line 116 extends along the channel length direction (X direction) of the driving transistor 121 over the plurality of pixel circuits 110. The feeder 116 is electrically insulated from the second electrode 133-2 of the transfer capacitor 133 described later by the insulating layer LC.
The control line 143 passes through the conduction hole HC7 penetrating the insulating layer LB, the relay electrode QA9, and the HB4 penetrating the insulating layer LA as understood from the portion showing the metal layer B in FIG. 15 and FIG. It is conducted to the gate layer GTcmp of the third transistor 123. The control line 143 extends along the channel length direction (X direction) of the third transistor 123.

The control line 144 passes through the conduction hole HC6 penetrating the insulating layer LB, the relay electrode QA7, and HB3 penetrating the insulating layer LA as understood from the portion showing the metal layer B in FIG. 15 and FIG. The fourth transistor 124 is electrically connected to the gate layer GTel. The control line 144 extends along the channel length direction (X direction) of the fourth transistor 124.
The control line 145 is electrically connected to the gate layer GTorst of the fifth transistor 125 through the conduction hole HC3 penetrating the insulating layer LB, the relay electrode QA5, and HB2 penetrating the insulating layer LA. The control line 145 extends along the channel length direction (X direction) of the fifth transistor 125.
The control line 146 is electrically connected to the gate layer GTfix of the first transistor 126 through the conduction hole HC2 penetrating the insulating layer LB, the relay electrode QA2, and HB1 penetrating the insulating layer LA. The control line 146 extends along the channel length direction (X direction) of the first transistor 126.

  The relay electrode QB1 is electrically connected to the relay electrode QA1 through the conduction hole HC1 penetrating the insulating layer LB as understood from the portions of the metal layer B and the metal layer A in FIG. The relay electrode QB2 is electrically connected to the relay electrode QA4 through a conduction hole HC4 penetrating the insulating layer LB. The relay electrode QB3 is electrically connected to the relay electrode QA6 through a conduction hole HC5 that penetrates the insulating layer LB. The relay electrode QB4 is electrically connected to the relay electrode QA3 through a conduction hole HC8 that penetrates the insulating layer LB.

The insulating layer LC is formed on the surface of the insulating layer LB on which the scanning lines 12, the plurality of control lines 143 to 146, and the plurality of relay electrodes QB (QB1, QB2, QB3, QB4) are formed. As understood from the portion of the metal layer C in FIG. 15 and FIG. 17, on the surface of the insulating layer LC, the second data transfer line 14-2, the second electrode 133-2 of the transfer capacitor 133, a plurality of Relay electrodes QC (QC1, QC2, QC3) are formed.
The second data transfer line 14-2 as an example of the third conductive layer extends along the Y direction across the plurality of pixel circuits 110. The second data transfer line 14-2 is connected to the second transistor 122 via the conduction hole HD4 penetrating the insulating layer LC, the relay electrode QB4, the conduction hole HC8 penetrating the insulating layer LB, and the relay electrode QA3. Conduction is made to the active region 10A forming the drain region or the source region. The second data transfer line 14-2 is electrically connected to the active region 10A that forms the drain region or the source region of the third transistor 123 and the active region 10A that forms the drain region or the source region of the first transistor 126. The
The second electrode 133-2 of the transfer capacitor (first capacitor) 133 is a rectangular electrode that covers the scanning line 12, the control line 143, and the control line 144 in the pixel circuit 110, and the second data transfer line 14-2. And formed integrally.

  As understood from FIGS. 15 and 17, the relay electrode QC1 is electrically connected to the relay electrode QB1 through the conduction hole HD1 penetrating the insulating layer LC. The relay electrode QC2 is electrically connected to the relay electrode QB2 through a conduction hole HD2 penetrating the insulating layer LC. The relay electrode QC3 is electrically connected to the relay electrode QB3 through a conduction hole HD3 that penetrates the insulating layer LC.

The insulating layer LD is on the surface of the insulating layer LC on which the second data transfer line 14-2, the second electrode 133-2 of the transfer capacitor 133, and the plurality of relay electrodes QC (QC1, QC2, QC3) are formed. Formed. As is understood from the portion of the capacitor electrode layer in FIG. 15 and FIG. 17, the first electrode 133-1 of the transfer capacitor 133 is formed on the surface of the insulating layer LD.
The first electrode 133-1 of the transfer capacitor (first capacitor) 133 is a rectangular capacitor electrode facing the second electrode 133-2 via the insulating layer LD. The first electrode 133-1 is opposed to the second electrode 133-2 through the insulating layer LD. As described above, the transfer capacitor 133 includes the first electrode 133-1 that is a metal, the insulating layer LD, and the second electrode 133-2 that is a metal, and has a MIM (Metal-Insulator-Metal) structure. doing. Therefore, the transfer capacity 133 can be easily increased in capacity. In addition, since the transfer capacitor 133 is formed in the display area of the pixel circuit 110, the electro-optical device can be downsized.

The insulating layer LE is formed on the surface of the insulating layer LD on which the first electrode 133-1 of the transfer capacitor 133 is formed. As understood from the portion of the metal layer D in FIG. 16 and FIG. 17, the first data transfer line 14-1, the feed line 16, and the relay electrode QD1 are formed on the surface of the insulating layer LE.
The first data transfer line 14-1 as an example of the second conductive layer extends along the Y direction across the plurality of pixel circuits 110. The first data transfer line 14-1 is electrically connected to the first electrode 133-1 of the transfer capacitor 133 through the conduction holes HF1, HF2, and HF3 penetrating the insulating layer LE. The first data transfer line 14-1 includes a conduction hole HE1 that penetrates the insulating layer LE and the insulation layer LD, a relay electrode QC1, a conduction hole HD1 that penetrates the insulation layer LC, a relay electrode QB1, and an insulation layer. Via the conduction hole HC1 penetrating LB, the relay electrode QA1, and the conduction hole HA2 penetrating the insulating layer LA and the insulating film L0, the active region 10A forming the drain region or the source region of the first transistor 126 is formed. Conducted.

The power supply line 16 extends along the Y direction across the plurality of pixel circuits 110. The feeder 16 includes a conduction hole HE2 that penetrates the insulating layer LE and the insulating layer LD, a relay electrode QC2, a conduction hole HD2 that penetrates the insulating layer LC, a relay electrode QB2, and a conduction hole HC4 that penetrates the insulating layer LB. And the relay electrode QA4 and the active region 10A forming the drain region or the source region of the fifth transistor 125 through the conductive hole HA4 penetrating the insulating layer LA and the insulating film L0. The relay electrode QD1 is electrically connected to the relay electrode QC3 through a conduction hole HE3 that penetrates the insulating layer LE.
The feeder line 16 is formed in the same layer as the first data transfer line 14-1, and is arranged with a predetermined gap between the first data transfer line 14-1 and the insulating layer LF. The In this way, the shield capacitor (second capacitor) 134 is formed, and the first data transfer line 14-1 is shielded by the power supply line 16 as a shield line.

  The insulating layer LF is formed on the surface of the insulating layer LE on which the first data transfer 14-1, the feeder line 16, and the relay electrode QD1 are formed. As understood from the portion of the reflective layer in FIG. 16 and FIG. 17, the reflective layer 50 is formed on the surface of the insulating layer LF. The reflective layer 50 is formed individually for each pixel circuit 110. The reflective layer 50 is a light-reflective conductive material containing, for example, silver or aluminum, and is formed to a thickness of about 100 nm, for example. As can be understood from the portion of the reflective layer in FIG. 16 and FIG. 17, the reflective layer 50 is electrically connected to the relay electrode QD1 through the conductive hole HG1 penetrating the insulating layer LF. The relay electrode QD1 is connected to the drain region or the source of the fourth transistor 124 through the conduction hole HE3, the relay electrode QC3, the conduction hole HD3, the relay electrode QB3, the conduction hole HC5, the relay electrode QA6, the conduction hole HA5, and the conduction hole HA3. The region and the drain region or the source region of the fifth transistor 124 are electrically connected.

  On the surface of the insulating layer LF on which the reflective layer 50 is formed, an optical path adjusting layer LG is formed as shown in FIG. The optical path adjustment layer LG is a light-transmitting film body that defines the resonance wavelength (that is, display color) of the resonance structure of each pixel circuit 110. In pixels with the same display color, the resonance wavelength of the resonance structure is substantially the same, and in pixels with different display colors, the resonance wavelength of the resonance structure is set to be different.

  An anode 130a for each pixel circuit 110 is formed on the surface of the optical path adjustment layer LG as shown in the pixel electrode layer portion of FIG. 16 and FIG. The anode 130a is formed of a light-transmitting conductive material such as ITO (Indium Tin Oxide). The anode 130a is electrically connected to the reflective layer 50 through a conduction hole HH1 that penetrates the optical path adjustment layer LG. Accordingly, the anode 130 a is electrically connected to the drain region or the source region of the fourth transistor 124 and the drain region or the source region of the fifth transistor 124 through the reflective layer 50.

  On the surface of the optical path adjustment layer LG on which the anode 130a is formed, the pixel definition film 51 is formed over the entire area of the substrate 10 as illustrated in FIG. The pixel definition film 51 is formed of an insulating inorganic material such as a silicon compound (typically silicon nitride or silicon oxide). As understood from the pixel definition film portion of FIG. 16, the pixel definition film 51 has openings 51A corresponding to the respective anodes 130a. A region of the pixel definition film 51 in the vicinity of the inner periphery of the opening 51A overlaps with the periphery of the anode 130a. That is, the inner peripheral edge of the opening 51A is located inside the peripheral edge of the anode 130a in plan view. Each opening 51A has a common planar shape (rectangular shape) and size, and is arranged in a matrix at a common pitch in each of the X direction and the Y direction. As understood from the above description, the pixel defining film 51 is formed in a lattice shape in plan view. Note that the planar shape and size of the opening 51A are the same if the display color is the same, and may be different if the display color is different. Further, the pitch of the openings 51A may be the same between openings having the same display color, and may be different between openings having different display colors.

  In addition, although detailed explanation is omitted, a light emitting functional layer, a cathode of the OLED 130, and a sealing body are laminated on the upper layer of the anode 130a, and the surface of the substrate 10 on which each of the above elements is formed is sealed. A stop substrate (not shown) is joined with an adhesive, for example. The sealing substrate is a light-transmitting plate member (for example, a glass substrate) for protecting each element on the substrate 10. Note that a color filter may be formed for each pixel circuit 110 on the surface of the sealing substrate or the surface of the sealing body.

  Although not shown, the pixel circuit 110 is provided with a common electrode 118 as another power supply line layer. The common electrode 118 is electrically connected to a mounting terminal to which the lower power supply potential Vct is supplied via wiring (not shown) in the multilayer wiring layer. The common electrode 118 to which the power supply line 116 and the lower power supply potential Vct are supplied is formed of a conductive material containing, for example, silver or aluminum and has a thickness of about 100 nm, for example. The common electrode 118 is electrically connected to the anode 130a.

As described above, in order to increase the data compression rate of the potential Vg supplied to the gate g of the driving transistor 121, it is desirable to increase the transfer capacity (first capacity) 133. A capacitor 133 is formed by a first electrode 133-1, a second electrode 133-2, and an insulating layer LD between these electrodes formed in different layers, and has an MIM (Metal-Insulator-Metal) structure. Therefore, the transfer capacity 133 can be increased while preventing the chip area from increasing. Further, since the transfer capacitor 133 is formed above the layer where the source electrodes of the second transistor 122 and the third transistor 123 are formed, the transfer capacitor 133 is formed in the display region of the pixel circuit 110, and thus the chip area. Can be prevented.
The shield capacitor (second capacitor) 134 is formed by disposing the first data transfer line 14-1 and the feeder line 16 as a shield line with a predetermined gap through the insulating layer LF. Therefore, since the shield capacitor 134 is formed by two parallel wires, the shield capacitor 134 has a predetermined length in the Y direction, and a predetermined capacitance can be ensured. Further, since the shield capacitor 134 is also formed in the display region of the pixel circuit 110, an increase in chip area can be prevented.

  In this embodiment, the transfer capacitor 133 is formed for each pixel circuit 110. However, the transfer capacitor 133 may be formed for each second data transfer line 14-2. An increase in the chip area can be further prevented.

  As can be understood from FIGS. 15 to 17, in the present embodiment, the first data transfer line 14-1 having a large amplitude of the supplied signal is connected to the second data signal line 14 to which the compressed signal is supplied. -2 is formed in an upper layer than -2. That is, the influence of a signal having a large amplitude supplied to the first data transfer line 14-1 on the gate of the driving transistor 121 is reduced, and the fluctuation of the potential of the gate of the driving transistor 121 is suppressed to improve the display quality. be able to.

15 and 17, in the present embodiment, the second data transfer line 14-2 includes the driving transistor 121, the first transistor 126, the second transistor 122, and the third transistor 123. It is formed above the layer where the source electrode is formed. Therefore, an increase in chip area can be prevented.
Further, as can be understood from FIGS. 15 and 17, the power supply line 116 as a power supply line connected to the second current terminal of the driving transistor 121 is formed below the second data transfer line 14-2. Therefore, the power supply line 116 functions as a shield, and the variation in the potential of the gate of the driving transistor 121 can be further effectively suppressed to improve the display quality.
Further, as can be understood from FIG. 15, since the driving transistor 121 is covered with the power supply line 116 as the power supply line, the power supply line 116 functions as a shield, and the fluctuation of the gate potential of the driving transistor 121 is further increased. It can suppress effectively and can improve display quality.

  As understood from FIGS. 15 to 17, the first electrode 133-1 and the second electrode 133-2 of the transfer capacitor 133 are formed in a layer different from the layer in which the first data transfer line 14-1 is formed. Has been. Therefore, even when the insulating layer is thinned to ensure a certain amount of capacitance in a small area, the transfer capacitor 133 having a uniform layer can be formed without causing a short circuit.

  As shown in the metal layer A portion of FIG. 15, the connection position of the first transistor 126 and the first data transfer line 14-1 is indicated by a dotted ellipse A, and the first current terminal of the driving transistor 121 and the third transistor The connection position with the 123 is indicated by a dotted ellipse B. A connection position between the fourth transistor 124 and the OLED 130 as a light emitting element is indicated by a dotted ellipse C. In this way, in a plan view of the pixel circuit, the dotted ellipse A indicating the connection position between the first transistor 126 and the first data transfer line 14-1 represents the first current end of the driving transistor 121 and the third current end. It is set so as to be closer to the dotted ellipse C indicating the connection position between the fourth transistor 124 and the OLED 130 as the light emitting element than to the dotted ellipse B indicating the connection position with the transistor 123.

  A signal having a high amplitude is supplied to the first data transfer line 14-1, and noise may occur at a connection position (ellipse A) between the first transistor 126 and the first data transfer line 14-1. However, the connection position (ellipse A) between the first transistor 126 and the first data transfer line 14-1 is greater than the connection position (ellipse C) between the fourth transistor 124 and the OLED 130 as the light emitting element in the plan view of the pixel circuit. Also, it is set at a position far from the connection position (ellipse B) between the first current terminal of the driving transistor 121 and the third transistor 123. Therefore, even if noise occurs at the connection position (ellipse A) between the first transistor 126 and the first data transfer line 14-1, the influence of noise on the driving transistor 121 can be suppressed, and the display quality can be improved. it can.

  Further, the connection position (ellipse A) of the first transistor 126 and the first data transfer line 14-1, the connection position (elliptical B) of the first current terminal of the driving transistor 121 and the third transistor 123, and the fourth transistor 124. And the OLED 130 as the light emitting element are connected at a position (ellipse C) of a power supply line 116 as a power supply line in the pixel circuit 110 and a power supply line 116 as a power supply line in the pixel circuit 110 of a block adjacent in the Y direction. Will be placed between. Therefore, the feeder line 116 serves as a shield, and the influence of noise can be reduced.

  As shown in FIG. 15, the connection position (ellipse A) of the first transistor 126 and the first data transfer line 14-1 is the gate of the fifth transistor 125 connected to the feeder line 16 as the reset potential supply line. The control line 145 connected to the layer GTorst and the control line 146 connected to the gate layer GTfix of the first transistor 126 are arranged. Therefore, even if a signal with high amplitude is supplied to the first data transfer line 14-1 and noise is generated, the control line 145 and the control line 146 function as a shield, and the influence of noise on the driving transistor 121 is reduced. Can do.

  Further, as shown in FIG. 15, the connection position (ellipse C) between the fourth transistor 124 and the OLED 130 as the light emitting element is the gate layer GTorst of the fifth transistor 125 connected to the power supply line 16 as the reset potential supply line. Is disposed between the control line 145 connected to the control line 144 and the control line 144 connected to the gate layer GTel of the fourth transistor 124. Therefore, even if a signal with high amplitude is supplied to the first data transfer line 14-1 and noise is generated, the control line 145 and the control line 144 function as a shield, and the influence of noise on the driving transistor 121 is reduced. Can do.

Second Embodiment
Next, a second embodiment of the present invention will be described with reference to FIGS. 18 to 20 of the accompanying drawings. In addition, about a common part with 1st Embodiment, the same code | symbol is attached | subjected and description is abbreviate | omitted.
The circuit of this embodiment is the same as the circuit of the first embodiment shown in FIG. As shown in FIGS. 18 to 20, the present embodiment is different from the first embodiment in the arrangement of the transistors in plan view. However, the positional relationship on each wiring layer is the same as in the first embodiment.

  Also in this embodiment, as can be understood from FIGS. 18 and 20, the transfer capacitor (first capacitor) 133 includes the first electrode 133-1 that is a metal, the insulating layer LD, and the first electrode that is a metal. 133-2 and is formed by a MIM (Metal-Insulator-Metal) structure. Therefore, the capacity of the transfer capacitor 133 can be increased, and the data compression rate of the potential Vg supplied to the gate g of the driving transistor 121 can be increased. Further, since the transfer capacitor 133 is formed above the layer where the source electrodes of the second transistor 122 and the third transistor 123 are formed, the transfer capacitor 133 is formed in the display region of the pixel circuit 110, and thus the chip area. Can be prevented.

  As understood from FIGS. 19 and 20, for the shield capacitor (second capacitor) 134, the first data transfer line 14-1 and the feeder line 16 as the shield line are connected to each other through the insulating layer LF. It is formed by disposing with a gap. Therefore, since the shield capacitor 134 is formed by two parallel wires, the shield capacitor 134 has a predetermined length in the Y direction, and a predetermined capacitance can be ensured. Further, since the shield capacitor 134 is also formed in the display region of the pixel circuit 110, an increase in chip area can be prevented.

  Also in this embodiment, the transfer capacitor 133 is formed for each pixel circuit 110, but the transfer capacitor 133 may be formed for each second data transfer line 14-2. An increase in the chip area can be further prevented.

  As understood from FIGS. 18 to 20, in the present embodiment, the first data transfer line 14-1 having a large amplitude of the supplied signal is connected to the second data signal line 14 to which the compressed signal is supplied. -2 is formed in an upper layer than -2. That is, the influence of a signal having a large amplitude supplied to the first data transfer line 14-1 on the gate of the driving transistor 121 is reduced, and the fluctuation of the potential of the gate of the driving transistor 121 is suppressed to improve the display quality. be able to.

18 and 20, in the present embodiment, the second data transfer line 14-2 includes the driving transistor 121, the first transistor 126, the second transistor 122, and the third transistor 123. It is formed above the layer where the source electrode is formed. Therefore, an increase in chip area can be prevented.
The relay electrode QA3 shown in FIG. 18 is a source electrode, and the active region 10A that forms the drain region or source region of the first transistor 126, the active region 10A that forms the drain region or source region of the third transistor 123, and the second region This is an electrode formed in direct contact with the active region 10A forming the drain region or source region of the transistor 122.
The relay electrode QA8 shown in FIG. 18 is also a source electrode, and an active region 10A that forms the drain region or source region of the fourth transistor 124, an active region 10A that forms the drain region or source region of the third transistor 123, and This is an electrode formed in direct contact with the active region 10A forming the drain region or source region of the driving transistor 121.
Further, the relay electrode QA11 shown in FIG. 18 is also a source electrode, and is an electrode formed in direct contact with the active region 10A that forms the drain region or the source region of the second transistor 122.
Further, as can be understood from FIGS. 18 and 20, the power supply line 116 as a power supply line connected to the second current terminal of the driving transistor 121 is formed in a lower layer than the second data transfer line 14-2. Therefore, the power supply line 116 functions as a shield, and the variation in the potential of the gate of the driving transistor 121 can be further effectively suppressed to improve the display quality.
In addition, as can be understood from FIG. 18, since the driving transistor 121 is covered with a power supply line 116 as a power supply line, the power supply line 116 functions as a shield, and the variation in the potential of the gate of the driving transistor 121 is further increased. It can suppress effectively and can improve display quality.

  As can be understood from FIGS. 18 to 20, the first electrode 133-1 and the second electrode 133-2 of the transfer capacitor 133 are formed in a layer different from the layer in which the first data transfer line 14-1 is formed. Has been. Therefore, even when the insulating layer is thinned to ensure a certain amount of capacitance in a small area, the transfer capacitor 133 having a uniform layer can be formed without causing a short circuit.

  As shown in the portion of the metal layer A in FIG. 18, the connection position between the first transistor 126 and the first data transfer line 14-1 is indicated by a dotted ellipse A, and the first current terminal of the driving transistor 121 and the third transistor The connection position with the 123 is indicated by a dotted ellipse B. A connection position between the fourth transistor 124 and the OLED 130 as a light emitting element is indicated by a dotted ellipse C. In this way, when viewed in one pixel circuit 110, the dotted ellipse A indicating the connection position between the first transistor 126 and the first data transfer line 14-1 is emitted from the fourth transistor 124. It is closer to the dotted ellipse B indicating the connection position between the first current terminal of the driving transistor 121 and the third transistor 123 than the dotted ellipse C indicating the connection position with the OLED 130 as the element.

  However, as shown in FIGS. 21 and 22, when viewed between different pixel circuits 110 adjacent in the Y direction and the X direction, the connection position of the first transistor 126 and the first data transfer line 14-1 is determined. The dotted ellipse A shown is a dotted line indicating the connection position between the fourth transistor 124 and the OLED 130 as the light emitting element, rather than the dotted ellipse B indicating the connection position between the first current terminal of the driving transistor 121 and the third transistor 123. It is close to the ellipse C.

  Therefore, even if a signal having a high amplitude is supplied to the first data transfer line 14-1 and noise occurs at the connection position (ellipse A) between the first transistor 126 and the first data transfer line 14-1, the drive transistor The influence of noise on 121 can be suppressed, and the display quality can be improved.

  In addition, as shown in FIGS. 21 and 22, when viewed between different pixel circuits 110 adjacent in the Y direction and the X direction, the connection position between the first transistor 126 and the first data transfer line 14-1 is determined. A dotted ellipse A is disposed between the control line 145 connected to the gate of the fifth transistor 125 and the scanning line 12 connected to the gate of the driving transistor 126. Therefore, the gate of the driving transistor 126 is disposed between the control line 145 and the scanning line 12 and is shielded by the control line 145 and the scanning line 12. As a result, a signal having a high amplitude is supplied to the first data transfer line 14-1, and even if noise occurs at the connection position (ellipse A) of the first transistor 126 and the first data transfer line 14-1, driving is performed. The influence of noise on the transistor 121 can be suppressed, and display quality can be improved.

  As shown in FIG. 18, the connection position (ellipse A) of the first transistor 126 and the first data transfer line 14-1, and the connection position (ellipse B) of the first current terminal of the driving transistor 121 and the third transistor 123. ), And the connection position (ellipse C) of the fourth transistor 124 and the OLED 130 as the light emitting element are the power supply line 116 as the power supply line in the pixel circuit 110 and the pixel circuit 110 in the block adjacent to the Y direction. The power supply line 116 is disposed between the power supply line 116 and the power supply line 116. Therefore, the feeder line 116 serves as a shield, and the influence of noise can be reduced.

  As shown in FIG. 18, the connection position (ellipse A) of the first transistor 126 and the first data transfer line 14-1 is the control line 143 connected to the gate layer GTcmp of the third transistor 123 and the first transistor. The control line 146 is connected to the 126 gate layer GTfix. Therefore, even if a signal with high amplitude is supplied to the first data transfer line 14-1 and noise occurs, the control line 143 and the control line 146 function as a shield, and the influence of noise on the driving transistor 121 is reduced. Can do.

  As shown in FIG. 18, the connection position (ellipse C) between the fourth transistor 124 and the OLED 130 as the light emitting element is the gate layer GTorst of the fifth transistor 125 connected to the power supply line 16 as the reset potential supply line. Is disposed between the control line 145 connected to the control line 144 and the control line 144 connected to the gate layer GTel of the fourth transistor 124. Therefore, even if a signal with high amplitude is supplied to the first data transfer line 14-1 and noise is generated, the control line 145 and the control line 144 function as a shield, and the influence of noise on the driving transistor 121 is reduced. Can do.

<Third Embodiment>
Next, a third embodiment of the present invention will be described with reference to FIGS. 23 to 26 of the accompanying drawings. In each of the embodiments described above, six transistors are used, but in this embodiment, five transistors are used.

<Circuit diagram>
As shown in FIG. 23, in the present embodiment, the configuration in which the fifth transistor 125 is not provided is different from the above-described embodiments. The power supply line 17 as an example of a fourth conductive layer to which the initial potential Vini is supplied is connected to the drain or source of the first transistor 126. The first data transfer line 14-1 is supplied with a voltage Vref for initializing the first data transfer line 14-1 via the transmission gate 45. The voltage Vref may be the same as the initial potential Vini.
The operation in this embodiment is the same as that in each of the above-described embodiments, and the second data transfer line 14-2 on the transfer capacitor 133 side of the second transistor 122 that becomes a floating node during the light emission period is initially set in another block. Since the fixed potential is set to the initial potential Vini during the period in which the processing of the conversion period is performed, it is possible to suppress the potential of the second data transfer line 14-2 from approaching the power supply voltage. As a result, the second transistor 122 is not turned on, the voltage is held in the pixel capacitor 132, and display defects do not occur.

<Structure>
Next, a specific structure of the electro-optical device 1 according to the third embodiment will be described in detail below. In the drawings referred to in the following description, the dimensions and scales of the elements are different from those of the actual electro-optical device 1 for convenience of description. 24 and 25 are plan views illustrating the appearance of the surface of the substrate 10 at each stage of forming each element of the electro-optical device 1 focusing on one pixel circuit 110. FIG. FIG. 26 is a cross-sectional view of the electro-optical device 1. A cross-sectional view corresponding to the cross section including the line II ′ in FIGS. 24 and 25 corresponds to FIG. 24 and 25 are plan views, but from the viewpoint of facilitating visual grasp of each element, hatching in the same manner as FIG. 26 is added to each element common to FIG. 26 for convenience. Yes.

26 and 24, the active region of each transistor 121, 122, 123, 124, 126 of the pixel circuit 110 is formed on the surface of the substrate 10 formed of a semiconductor material such as silicon. 10A (source / drain region) is formed. Ions are implanted into the active region 10A. An active layer of each of the transistors 121, 122, 123, 124, and 126 of the pixel circuit 110 exists between the source region and the drain region, and ions of a different type from the active region 10A are implanted. It is described integrally with the region 10A. In the present embodiment, the active region 10A is also formed in the region constituting the pixel capacitor 132, and impurities are implanted into the active region 10A and connected to the power source. Then, a so-called MOS capacitor is formed in which the active region 10A is used as one electrode and the capacitor electrode formed via the insulating layer is used as the other electrode. In addition, the active region 10A in the region constituting the pixel capacitor 132 also functions as a power supply potential unit. 24, the active region 10A of the third transistor 123 is connected to the active region 10A of the second transistor 122 in the portion where the conduction hole HA13 is provided. Therefore, the current end of the third transistor 123 also functions as the current end of the second transistor 122. As understood from the gate layer portion of FIG. 24 and FIG. 26, the surface of the substrate 10 on which the active region 10A is formed is covered with an insulating film L0 (gate insulating film), and the transistors 121, 122, 123, 124, 126 gate layers GT (GTdr, GTwr, GTcmp, GTel, GTfix) are formed on the surface of the insulating film L0. The gate layer GT of each transistor 121, 122, 123, 124, 126 is opposed to the active layer with the insulating film L0 interposed therebetween.
24, the gate layer GTdr of the driving transistor 121 is formed to extend to the active region 10A formed in the region constituting the capacitive element, thereby constituting the pixel capacitor 132. As illustrated in the gate layer portion of FIG. Yes.

  As understood from FIG. 26, a plurality of insulating layers L (LA to LH) are formed on the surface of the insulating film L0 on which the gate layers GT and the pixel capacitors 132 of the transistors 121, 122, 123, 124, and 126 are formed. And a multilayer wiring layer in which a plurality of conductive layers (wiring layers) are alternately stacked. Each insulating layer L is formed of an insulating inorganic material such as a silicon compound (typically silicon nitride or silicon oxide). In the following description, a relationship in which a plurality of elements are collectively formed in the same process by selective removal of a conductive layer (single layer or a plurality of layers) is referred to as “formed from the same layer”.

The insulating layer LA is formed on the surface of the insulating film L0 on which the gate layer GT of each transistor 121, 122, 123, 124, 126 is formed. As understood from the part of the metal layer A in FIG. 24 and FIG. 26, the feeder line 116 and the plurality of relay electrodes QA (QA13, QA14, QA15, QA16, QA17, QA18, QA19) are formed on the surface of the insulating layer LA. , QA20, QA21) are formed from the same layer.
In addition, as can be understood from FIG. 24, in the present embodiment, the source electrode of the driving transistor 121, the first transistor 126, the second transistor 122, and the third transistor 123 is included in the second data transfer line 14-2. It is formed above the layer to be formed. Therefore, an increase in chip area can be prevented.
The relay electrode QA13 shown in FIG. 24 is a source electrode, and is an electrode formed in direct contact with the active region 10A that forms the drain region or source region of the second transistor 122.
The relay electrode QA15 shown in FIG. 24 is also a source electrode, and an active region 10A that forms the drain region or source region of the third transistor 123, an active region 10A that forms the drain region or source region of the fourth transistor 124, and This is an electrode formed in direct contact with the active region 10A forming the drain region or source region of the driving transistor 121.
Further, the relay electrode QA17 shown in FIG. 24 is also a source electrode, an active region 10A that forms the drain region or source region of the third transistor 123, an active region 10A that forms the drain region or source region of the second transistor 122, and This is an electrode formed in direct contact with the active region 10A forming the drain region or source region of the first transistor 126.
As understood from the portion of the metal layer A in FIG. 24 and FIG. 26, the feeder line 116 forms the source region or the drain region of the driving transistor 121 through the conduction hole HA16 penetrating the insulating layer LA and the insulating film L0. Conductive to the active region 10A. The feeder line 116 is electrically connected to the active region 10A forming the pixel capacitor 132 through the conduction hole HA15 penetrating the insulating layer LA and the insulating film L0. The power supply line 116 extends along the channel width direction (X direction) of the driving transistor 121 over the plurality of pixel circuits 110. The power supply line 116 is electrically connected to a mounting terminal to which a higher power supply potential Vel is supplied via a wiring (not shown) in the multilayer wiring layer. Although not shown, another power line layer is also formed in the peripheral region of the pixel circuit 110. The power supply line layer is electrically connected to a mounting terminal to which a lower power supply potential Vct is supplied via a wiring (not shown) in the multilayer wiring layer. The power supply line 116 and the power supply line layer to which the lower power supply potential Vct is supplied are formed of a conductive material containing, for example, silver or aluminum and have a thickness of about 100 nm, for example.

  The gate layer GTdr of the drive transistor 121 is connected to the source of the second transistor 122 via the relay electrode QA13, the conduction hole HB13 that penetrates the insulating layer LA, and the conduction hole HA14 that penetrates the insulating layer LA and the insulating film L0. It conducts to the active region 10A that forms the region or drain region.

  The relay electrode QA15 and the relay electrode QA17 are the same as the feeder line 116 in the conductive portion between the driving transistor 121 and the third transistor 123 and the fourth transistor 124, and the conductive portion between the third transistor 123 and the sixth transistor 126, respectively. Formed in layers. In addition, the relay electrode QA14 and the relay electrode QA16 are connected to the conductive portion of the gate layer GTwr of the second transistor 122, the gate layer GTcmp of the third transistor 123, the gate layer GTel of the fourth transistor 124, and the gate layer GTfix of the sixth transistor 124. The relay electrode QA19 and the relay electrode QA18 are formed in the same layer as the feeder line 116. Further, the relay electrode QA20 and the relay electrode QA21 are provided in the same layer as the feeder line 116 in the conduction portion of the source region or drain region of the fourth transistor 124 and the conduction portion of the source region or drain region of the first transistor 126. It is formed.

  As understood from the portion of the metal layer A in FIG. 24 and FIG. 26, the relay electrode QA15 has a drain region or a source region of the driving transistor 121 via the conduction hole HA17 that penetrates the insulating film L0 and the insulating layer LA. It conducts to the active region 10A to be formed. The relay electrode QA15 is electrically connected to the active region 10A that forms the drain region or the source region of the third transistor 123 through the conduction hole HA18 penetrating the insulating film L0 and the insulating layer LA. Further, the relay electrode QA15 is electrically connected to the active region 10A that forms the drain region or the source region of the fourth transistor 124 through the conduction hole HA19 penetrating the insulating film L0 and the insulating layer LA.

  The relay electrode QA17 is electrically connected to the active region 10A forming the drain region or the source region of the second transistor 122 and the third transistor 122 through the conduction hole HA13 penetrating the insulating film L0 and the insulating layer LA. The relay electrode QA17 is electrically connected to the active region 10A that forms the drain region or the source region of the first transistor 126 through the conduction hole HA21 that penetrates the insulating film L0 and the insulating layer LA.

  The relay electrode QA20 is electrically connected to the active region 10A forming the drain region or the source region of the fourth transistor 124 through the conduction hole HA20 penetrating the insulating film L0 and the insulating layer LA. The relay electrode QA21 is electrically connected to the active region 10A that forms the drain region or the source region of the first transistor 126 through the conduction hole HA22 that penetrates the insulating film L0 and the insulating layer LA. Further, the relay electrode QA21 is connected to the power supply line 17 to which the initial potential is supplied.

  The insulating layer LB is formed on the surface of the insulating layer LA on which the feeder line 116 and a plurality of relay electrodes QA (QA13, QA14, QA15, QA16, QA17, QA18, QA19, QA20, QA21) are formed. As understood from the portion of the metal layer B in FIG. 24 and FIG. 26, on the surface of the insulating layer LB, the scanning line 12, the control line 143 of the third transistor 123, and the control line 144 of the fourth transistor 124 The control line 146 of the first transistor 126 and the plurality of relay electrodes QB (QB5, QB6) are formed from the same layer.

  As understood from the portion of the metal layer B in FIG. 24 and FIG. 26, the scanning line 12 as an example of the first conductive layer is relayed via the conduction hole HC15 formed in the insulating layer LB for each pixel circuit 110. Conductive to the electrode QA14. Therefore, as understood from FIGS. 24 and 26, the scanning line 12 includes the second transistor through the conduction hole HC15 penetrating the insulating layer LB, the relay electrode QA14, and the conduction hole HB15 penetrating the insulating layer LA. Conductive to 121 gate layer GTwr. The scanning line 12 extends linearly in the X direction across the plurality of pixel circuits 110, and is electrically insulated from the first capacitor 133 and the second data transfer line 14-2 by the insulating layer LC.

  As understood from FIG. 24, the control line 143 is electrically connected to the relay electrode QA16 via the conduction hole HC14 formed in the insulating layer LB for each pixel circuit 110. Therefore, as understood from FIGS. 24 to 26, the control line 143 is connected to the third transistor through the conduction hole HC14 penetrating the insulating layer LB, the relay electrode QA16, and the conduction hole HB14 penetrating the insulating layer LA. Conductive to 123 gate layer GTcmp. The control line 143 extends linearly in the X direction across the plurality of pixel circuits 110, and is electrically insulated from the first capacitor 133 and the second data transfer line 14-2 by the insulating layer LC.

  As understood from FIG. 24, the control line 144 is electrically connected to the relay electrode QA19 through the conduction hole HC11 formed in the insulating layer LB for each pixel circuit 110. Therefore, as understood from FIGS. 24 to 26, the control line 144 is connected to the fourth transistor through the conduction hole HC11 that penetrates the insulating layer LB, the relay electrode QA19, and the conduction hole HB16 that penetrates the insulating layer LA. Conductive to 124 gate layer GTel. The control line 144 extends linearly in the X direction across the plurality of pixel circuits 110, and is electrically insulated from the first capacitor 133 and the second data transfer line 14-2 by the insulating layer LC.

  As understood from FIG. 24, the control line 146 is electrically connected to the relay electrode QA18 through the conduction hole HC13 formed in the insulating layer LB for each pixel circuit 110. Therefore, as understood from FIGS. 24 to 26, the control line 146 is connected to the first transistor through the conduction hole HC13 penetrating the insulating layer LB, the relay electrode QA18, and the conduction hole HB17 penetrating the insulating layer LA. Conductive to 126 gate layer GTfix. The control line 146 extends linearly in the X direction across the plurality of pixel circuits 110, and is electrically insulated from the first capacitor 133 and the second data transfer line 14-2 by the insulating layer LC.

  The relay electrode QB5 is electrically connected to the relay electrode QA17 through a conduction hole HC12 formed in the insulating layer LB for each pixel circuit 110. Therefore, as understood from FIGS. 24 to 26, the relay electrode QB5 is connected via the conduction hole HC12 penetrating the insulating layer LB, the relay electrode QA17, and the conduction hole HA21 penetrating the insulating film L0 and the insulating layer LA. The first transistor 126 is electrically connected to the active region 10A that forms the drain region or the source region.

  The relay electrode QB6 is electrically connected to the relay electrode QA20 through a conduction hole HC16 formed in the insulating layer LB for each pixel circuit 110. Therefore, as understood from FIGS. 24 to 26, the relay electrode QB6 is connected via the conduction hole HC16 penetrating the insulating layer LB, the relay electrode QA20, and the conduction hole HA20 penetrating the insulating film L0 and the insulating layer LA. The fourth transistor 124 is electrically connected to the active region 10A that forms the drain region or the source region.

  The insulating layer LC includes the scanning line 12, the control line 143 of the third transistor 123, the control line 144 of the fourth transistor 124, the control line 146 of the first transistor 126, and a plurality of relay electrodes QB (QB5, QB6). Are formed on the surface of the insulating layer LB. As understood from FIGS. 24 and 26, the second data transfer line 14-2 and the transfer capacitor 133 formed integrally with the second data transfer line 14-2 are formed on the surface of the insulating layer LC. The two electrodes 133-2 and the relay electrode QC4 are formed from the same layer.

The second data transfer line 14-2 as an example of the third conductive layer extends along the Y direction across the plurality of pixel circuits 110. The second data transfer line 14-2 includes a conduction hole HD5 penetrating the insulating layer LC, a relay electrode QB5, a conduction hole HC12 penetrating the insulating layer LB, the relay electrode QA17, the insulating film L0, and the insulating layer LA. Conduction is conducted to the active region 10A forming the drain region or the source region of the first transistor 126 through the conduction hole HA21 that penetrates. The second data transfer line 14-2 includes the conduction hole HD5 that penetrates the insulating layer LC, the relay electrode QB5, the conduction hole HC12 that penetrates the insulating layer LB, the relay electrode QA17, the insulating film L0, and the insulating layer. Conduction is conducted to the active region 10A forming the drain region or the source region of the third transistor 123 and the second transistor 122 through the conduction hole HA13 penetrating LA.
The second electrode 133-2 of the transfer capacitor 133 (first capacitor) is a rectangular electrode that covers the scanning line 12, the control line 143, and the control line 146 in the pixel circuit 110, and the second data transfer line 14-2. And formed integrally.

The insulating layer LD is formed on the surface of the insulating layer LC on which the second data transfer line 14-2, the second electrode 133-2 of the transfer capacitor 133, and the relay electrode QC4 are formed. As understood from the portion of the capacitor electrode layer in FIG. 24 and FIG. 26, the first electrode 133-1 of the transfer capacitor 133 is formed on the surface of the insulating layer LD.
The first electrode 133-1 of the transfer capacitor 133 (first capacitor) is a rectangular capacitor electrode facing the second electrode 133-2 via the insulating layer LD. The first electrode 133-1 is opposed to the second electrode 133-2 through the insulating layer LD. As described above, since the transfer capacitor 133 is formed by an MIM (Metal-Insulator-Metal) structure, the capacity can be increased.

The insulating layer LE is formed on the surface of the insulating layer LD on which the first electrode 133-1 of the transfer capacitor 133 is formed. As understood from the portion of the metal layer D in FIG. 25 and FIG. 26, the first data transfer line 14-1, the feed line 16, and the relay electrode QD2 are formed on the surface of the insulating layer LE.
The first data transfer line 14-1 as an example of the second conductive layer extends along the Y direction across the plurality of pixel circuits 110. The first data transfer line 14-1 is electrically connected to the first electrode 133-1 of the transfer capacitor 133 through the conduction holes HF4, HF5, and HF6 penetrating the insulating layer LE.

  The power supply line 16 extends along the Y direction across the plurality of pixel circuits 110. The power supply line 16 is formed in the same layer as the first data transfer line 14-1, and is disposed with a predetermined gap between the first data transfer line 14-1 and the insulating layer LF. Thus, the shield capacitor 134 is formed, and the first data transfer line 14-1 is shielded by the power supply line 16.

  The relay electrode QD2 is electrically connected to the relay electrode QC4 through a conduction hole HE4 penetrating the insulating layer LE and the insulating layer LD. Therefore, the relay electrode QD2 has a conduction hole HE4 that penetrates the insulating layer LE and the insulating layer LD, a relay electrode QC4, a conduction hole HD6 that penetrates the insulating layer LC, a relay electrode QB6, and a conduction that penetrates the insulating layer LB. The hole HC16, the relay electrode QA20, and the conductive region HA20 penetrating the insulating film L0 and the insulating layer LA are electrically connected to the active region 10A forming the drain region or the source region of the fourth transistor 124.

  The insulating layer LF is formed on the surface of the insulating layer LE on which the first data transfer line 14-1, the feeder line 16, and the relay electrode QD2 are formed. As understood from the portion of the reflective layer in FIG. 25 and FIG. 26, the reflective layer 50 is formed on the surface of the insulating layer LF. The reflective layer 50 is formed individually for each pixel circuit 110. The reflective layer 50 is a light-reflective conductive material containing, for example, silver or aluminum, and is formed to a thickness of about 100 nm, for example. As understood from FIGS. 25 and 26, the reflective layer 50 is electrically connected to the relay electrode QD2 through the conductive hole HG2 penetrating the insulating layer LF. Therefore, the reflective layer 50 is electrically connected to the active region 10A that forms the drain region or the source region of the fourth transistor 124 via the relay electrode QD2.

  On the surface of the insulating layer LF on which the reflective layer 50 is formed, as shown in FIG. 26, an optical path adjustment layer LG is formed. The optical path adjustment layer LG is a light-transmitting film body that defines the resonance wavelength (that is, display color) of the resonance structure of each pixel circuit 110. In pixels with the same display color, the resonance wavelength of the resonance structure is substantially the same, and in pixels with different display colors, the resonance wavelength of the resonance structure is set to be different.

  As shown in FIG. 25 and the surface of the optical path adjustment layer LG, an anode 130a for each pixel circuit 110 is formed. The anode 130a is formed of a light-transmitting conductive material such as ITO (Indium Tin Oxide). The anode 130a is electrically connected to the reflective layer 50 through a conduction hole HH2 that penetrates the optical path adjustment layer LG. Therefore, the anode 130a is electrically connected to the active region 10A that forms the drain region or the source region of the fourth transistor 124 via the reflective layer 50.

  On the surface of the optical path adjustment layer LG on which the anode 130a is formed, the pixel definition film 51 is formed over the entire area of the substrate 10 as illustrated in FIG. The pixel definition film 51 is formed of an insulating inorganic material such as a silicon compound (typically silicon nitride or silicon oxide). As understood from the pixel definition film portion of FIG. 25, the pixel definition film 51 has openings 51A corresponding to the respective anodes 130a. A region of the pixel definition film 51 in the vicinity of the inner periphery of the opening 51A overlaps with the periphery of the anode 130a. That is, the inner peripheral edge of the opening 51A is located inside the peripheral edge of the anode 130a in plan view. Each opening 51A has a common planar shape (rectangular shape) and size, and is arranged in a matrix at a common pitch in each of the X direction and the Y direction. As understood from the above description, the pixel defining film 51 is formed in a lattice shape in plan view. Note that the planar shape and size of the opening 51A are the same if the display color is the same, and may be different if the display color is different. Further, the pitch of the openings 51A may be the same between openings having the same display color, and may be different between openings having different display colors.

  In addition, although detailed explanation is omitted, a light emitting functional layer, a cathode of the OLED 130, and a sealing body are laminated on the upper layer of the anode 130a, and the surface of the substrate 10 on which each of the above elements is formed is sealed. A stop substrate (not shown) is joined with an adhesive, for example. The sealing substrate is a light-transmitting plate member (for example, a glass substrate) for protecting each element on the substrate 10. Note that a color filter may be formed for each pixel circuit 110 on the surface of the sealing substrate or the surface of the sealing body.

  Although not shown, the pixel circuit 110 is provided with a common electrode 118 as another power supply line layer. The common electrode 118 is electrically connected to a mounting terminal to which the lower power supply potential Vct is supplied via wiring (not shown) in the multilayer wiring layer. The common electrode 118 to which the power supply line 116 and the lower power supply potential Vct are supplied is formed of a conductive material containing, for example, silver or aluminum and has a thickness of about 100 nm, for example. The common electrode 118 is electrically connected to the anode 130a.

In order to increase the data compression rate of the potential Vg supplied to the gate g of the driving transistor 121, it is desirable to increase the transfer capacity (first capacity) 133. However, according to the present embodiment, the transfer capacity 133 is reduced to MIM ( Since it is formed by a (Metal-Insulator-Metal) structure, the transfer capacity 133 can be increased. Further, since the transfer capacitor 133 is formed above the layer where the source electrodes of the second transistor 122 and the third transistor 123 are formed, the transfer capacitor 133 is formed in the display region of the pixel circuit 110, and thus the chip area. Can be prevented.
The shield capacitor (second capacitor) 134 is formed by disposing the first data transfer line 14-1 and the feeder line 16 as a shield line with a predetermined gap through the insulating layer LF. Therefore, since the shield capacitor 134 is formed by two parallel wires, the shield capacitor 134 has a predetermined length in the Y direction, and a predetermined capacitance can be ensured. Further, since the shield capacitor 134 is also formed in the display region of the pixel circuit 110, an increase in chip area can be prevented.

  In this embodiment, the transfer capacitor 133 is formed for each pixel circuit 110. However, the transfer capacitor 133 may be formed for each second data transfer line 14-2. An increase in the chip area can be further prevented.

  As understood from FIGS. 24 to 26, in the present embodiment, the first data transfer line 14-1 having a large amplitude of the supplied signal is connected to the second data signal line 14 to which the compressed signal is supplied. -2 is formed in an upper layer than -2. That is, the influence of a signal having a large amplitude supplied to the first data transfer line 14-1 on the gate of the driving transistor 121 is reduced, and the fluctuation of the potential of the gate of the driving transistor 121 is suppressed to improve the display quality. be able to.

24 and 26, in the present embodiment, the second data transfer line 14-2 includes the driving transistor 121, the first transistor 126, the second transistor 122, and the third transistor 123. It is formed above the layer where the source electrode is formed. Therefore, an increase in chip area can be prevented.
Further, as can be understood from FIGS. 24 and 26, the power supply line 116 as a power supply line connected to the second current terminal of the driving transistor 121 is formed below the second data transfer line 14-2. Therefore, the power supply line 116 functions as a shield, and the variation in the potential of the gate of the driving transistor 121 can be further effectively suppressed to improve the display quality.
In addition, as can be understood from FIG. 24, since the driving transistor 121 is covered with the power supply line 116 as a power supply line, the power supply line 116 functions as a shield, and the variation in the potential of the gate of the driving transistor 121 is further increased. It can suppress effectively and can improve display quality.

  As can be understood from FIGS. 24 to 26, the first electrode 133-1 and the second electrode 133-2 of the transfer capacitor 133 are formed in a layer different from the layer in which the first data transfer line 14-1 is formed. Has been. Therefore, even when the insulating layer is thinned to ensure a certain amount of capacitance in a small area, the transfer capacitor 133 having a uniform layer can be formed without causing a short circuit.

<Fourth embodiment>
Next, a fourth embodiment of the present invention will be described with reference to FIGS. 27 to 30 of the attached drawings. In addition, about a common location with 3rd Embodiment, the same code | symbol is attached | subjected and description is abbreviate | omitted.

<Circuit diagram>
As shown in FIG. 27, the circuit according to the present embodiment includes five transistors as in the third embodiment, but the power supply line 17 is not provided. Instead, the drain or source of the first transistor 126 is connected to the first data transfer line 14-1, and the initial potential Vini is supplied to the first data transfer line 14-1 through the transmission gate 45. The Other configurations are the same as those of the third embodiment.
The operation in this embodiment is the same as that in each of the above-described embodiments, and the second data transfer line 14-2 on the transfer capacitor 133 side of the second transistor 122 that becomes a floating node during the light emission period is initially set in another block. Since the fixed potential is set to the initial potential Vini in the period in which the processing of the conversion period is performed, the potential of the second data transfer line 14-2 can be suppressed from approaching the power supply potential. As a result, the second transistor 122 is not turned on, the voltage is held in the pixel capacitor 132, and display defects do not occur.

<Structure>
In the present embodiment, as shown in FIG. 28, the arrangement and shape of the second data transfer line 14-2 are different from those in the third embodiment. The node region 10A constituting the drain or source of the first transistor 126 is connected to the first data transfer line 14-1 via the conduction hole HA22, the relay electrode QA22, the conduction hole HD7, and the relay electrode QB8. Other structures are the same as those of the third embodiment.

In order to increase the data compression rate of the potential Vg supplied to the gate g of the driving transistor 121, it is desirable to increase the transfer capacity (first capacity) 133. However, according to the present embodiment, the transfer capacity 133 is reduced to MIM ( Since it is formed by a (Metal-Insulator-Metal) structure, the transfer capacity 133 can be increased. Further, since the transfer capacitor 133 is formed above the layer where the source electrodes of the second transistor 122 and the third transistor 123 are formed, the transfer capacitor 133 is formed in the display region of the pixel circuit 110, and thus the chip area. Can be prevented.
The relay electrode QA13 shown in FIG. 28 is a source electrode, and is an electrode formed in direct contact with the active region 10A that forms the drain region or source region of the second transistor 122.
The relay electrode QA15 shown in FIG. 28 is also a source electrode, and an active region 10A that forms the drain region or source region of the third transistor 123, an active region 10A that forms the drain region or source region of the fourth transistor 124, and This is an electrode formed in direct contact with the active region 10A forming the drain region or source region of the driving transistor 121.
Further, the relay electrode QA17 shown in FIG. 28 is also a source electrode, an active region 10A that forms the drain region or source region of the third transistor 123, an active region 10A that forms the drain region or source region of the second transistor 122, and This is an electrode formed in direct contact with the active region 10A forming the drain region or source region of the first transistor 126.
The shield capacitor (second capacitor) 134 is formed by disposing the first data transfer line 14-1 and the feeder line 16 as a shield line with a predetermined gap through the insulating layer LF. Therefore, since the shield capacitor 134 is formed by two parallel wires, the shield capacitor 134 has a predetermined length in the Y direction, and a predetermined capacitance can be ensured. Further, since the shield capacitor 134 is also formed in the display region of the pixel circuit 110, an increase in chip area can be prevented.

  In this embodiment, the transfer capacitor 133 is formed for each pixel circuit 110. However, the transfer capacitor 133 may be formed for each second data transfer line 14-2. An increase in the chip area can be further prevented.

  As can be understood from FIGS. 28 to 30, in the present embodiment, the first data transfer line 14-1 having a large amplitude of the supplied signal is connected to the second data signal line 14 to which the compressed signal is supplied. -2 is formed in an upper layer than -2. That is, the influence of a signal having a large amplitude supplied to the first data transfer line 14-1 on the gate of the driving transistor 121 is reduced, and the fluctuation of the potential of the gate of the driving transistor 121 is suppressed to improve the display quality. be able to.

In addition, as can be understood from FIGS. 28 and 30, in the present embodiment, the second data transfer line 14-2 includes the drive transistor 121, the first transistor 126, the second transistor 122, and the third transistor 123. It is formed above the layer where the source electrode is formed. Therefore, an increase in chip area can be prevented.
Furthermore, as can be understood from FIGS. 28 and 30, the power supply line 116 as a power supply line connected to the second current terminal of the drive transistor 121 is formed in a layer lower than the second data transfer line 14-2. Therefore, the power supply line 116 functions as a shield, and the variation in the potential of the gate of the driving transistor 121 can be further effectively suppressed to improve the display quality.
In addition, as can be understood from FIG. 28, since the driving transistor 121 is covered with the power supply line 116 as a power supply line, the power supply line 116 functions as a shield, and the variation in the gate potential of the driving transistor 121 is further increased. It can suppress effectively and can improve display quality.

  As can be understood from FIGS. 28 to 30, the first electrode 133-1 and the second electrode 133-2 of the transfer capacitor 133 are formed in a layer different from the layer in which the first data transfer line 14-1 is formed. Has been. Therefore, even when the insulating layer is thinned to ensure a certain amount of capacitance in a small area, the transfer capacitor 133 having a uniform layer can be formed without causing a short circuit.

As shown in the part of the metal layer A in FIG. 28, the connection position between the first transistor 126 and the first data transfer line 14-1 is indicated by a dotted ellipse A, and the first current terminal of the driving transistor 121 and the third transistor The connection position with the 123 is indicated by a dotted ellipse B. A connection position between the fourth transistor 124 and the OLED 130 as a light emitting element is indicated by a dotted ellipse C. In this way, when viewed in one pixel circuit 110, the connection point between the first transistor 126 and the first data transfer line 14-1 is the dotted ellipse A is the first current of the driving transistor 121. The connection position between the end and the third transistor 123 is closer to the dotted ellipse C than the dotted ellipse B is connected to the fourth transistor 124 and the OLED 130 as the light emitting element.
Therefore, even if a signal having a high amplitude is supplied to the first data transfer line 14-1 and noise occurs at the connection position (ellipse A) between the first transistor 126 and the first data transfer line 14-1, the drive transistor The influence of noise on 121 can be suppressed, and the display quality can be improved.

  Further, as shown in FIG. 28, the connection position (ellipse A) of the first transistor 126 and the first data transfer line 14-1, and the connection position (elliptical B) of the first current terminal of the driving transistor 121 and the third transistor 123. ), And the connection position (ellipse C) of the fourth transistor 124 and the OLED 130 as the light emitting element are the power supply line 116 as the power supply line in the pixel circuit 110 and the pixel circuit 110 in the block adjacent to the Y direction. The power supply line 116 is disposed between the power supply line 116 and the power supply line 116. Therefore, the feeder line 116 serves as a shield, and the influence of noise can be reduced.

<Modification>
The present invention is not limited to the above-described embodiments, and various modifications as described below are possible, for example. Moreover, the aspect of the deformation | transformation described below can also combine suitably arbitrarily selected 1 or several.
<Modification 1>
In the embodiment described above, in each pixel circuit 110, the third transistor 123 is connected between the drain of the drive transistor 121 and the second data transfer line 14-2. However, as shown in FIG. May be connected between the drain and the gate g.

<Modification 2>
In the first embodiment, the initial potential Vini is supplied to the first data transfer line 14-1 via the transmission gate 45, and the first transistor 126 is turned on, so that the second data transfer line 14-2 is turned on. Was supplied with the initial potential Vini. However, as shown in FIG. 32, a power supply line 17 that supplies the initial potential Vini is provided, and the drain or source of the first transistor 126 is connected to the power supply line 17 as an example of the fourth conductive layer. Good. In this case, by turning on the first transistor 126, the initial potential Vini is supplied from the feeder line 17 to the second data transfer line 14-2.

<Modification 3>
In the circuit diagram of the above-described embodiment, the first transistor 126 and the transfer capacitor 133 are provided in one-to-one correspondence for each pixel circuit 110. However, as illustrated in FIG. 33, the first transistor 126 and the transfer capacitor 133 are provided. One Nb pixel circuit 110 may be provided at a rate of one each.

<Modification 4>
In the above-described embodiment, the first data transfer lines 14-1 are grouped every three columns, and the first data transfer lines 14-1 are sequentially selected in each group to supply data signals. However, the number of data lines constituting the group may be a predetermined number from “2” to “3n”. For example, the number of data lines constituting the group may be “2”, or may be “4” or more.
Further, a configuration may be adopted in which data signals are supplied all at once to the first data transfer lines 14-1 of each column without grouping, that is, without using the demultiplexer DM.

<Modification 5>
In the above-described embodiment, the transistors 121 to 126 are unified with the P-channel type, but may be unified with the N-channel type. Further, a P-channel type and an N-channel type may be appropriately combined.
For example, in the case where the transistors 121 to 126 are unified with the N-channel type, the data signal Vd (n) in the above-described embodiment may be supplied to each pixel circuit 110 with a positive / negative inverted potential. In this case, the sources and drains of the transistors 121 to 126 are in a relationship reversed to that of the above-described embodiment and modification.
<Modification 6>
In the above-described embodiment and modification, an OLED that is a light-emitting element is illustrated as an electro-optical element.

<Application example>
Next, an electronic apparatus to which the electro-optical device 1 according to the embodiment and the application example is applied will be described. The electro-optical device 1 is suitable for high-definition display with small pixels. Therefore, a head mounted display will be described as an example of an electronic device.

FIG. 34 is a diagram showing the external appearance of a head-mounted display, and FIG. 35 is a diagram showing its optical configuration.
First, as shown in FIG. 34, the head mounted display 300 has a temple 310, a bridge 320, and lenses 301L and 301R in the same manner as general glasses. Further, as shown in FIG. 35, the head mounted display 300 is in the vicinity of the bridge 320 and on the back side of the lenses 301L and 301R (the lower side in the drawing), the electrooptic device 1L for the left eye and the right eye. Electro-optical device 1R.
The image display surface of the electro-optical device 1L is arranged on the left side in FIG. Accordingly, the display image by the electro-optical device 1L is emitted in the direction of 9 o'clock in the drawing through the optical lens 302L. The half mirror 303L reflects the display image by the electro-optical device 1L in the 6 o'clock direction, and transmits light incident from the 12 o'clock direction.
The image display surface of the electro-optical device 1R is disposed on the right side opposite to the electro-optical device 1L. As a result, the display image by the electro-optical device 1R is emitted in the direction of 3 o'clock in the drawing through the optical lens 302R. The half mirror 303R reflects the display image by the electro-optical device 1R in the 6 o'clock direction, and transmits light incident from the 12 o'clock direction.

In this configuration, the wearer of the head mounted display 300 can observe the display image by the electro-optical devices 1L and 1R in a see-through state superimposed on the outside.
Further, in the head-mounted display 300, when the left-eye image is displayed on the electro-optical device 1L and the right-eye image is displayed on the electro-optical device 1R among the binocular images with parallax, the wearer is notified. The displayed image can be perceived as if it had a depth or a stereoscopic effect (3D display).

  In addition to the head mounted display 300, the electro-optical device 1 can be applied to an electronic viewfinder in a video camera, an interchangeable lens digital camera, or the like.

DESCRIPTION OF SYMBOLS 1, 1L, 1R ... Electro-optical device, 2 ... Display panel, 3 ... Control circuit, 5 ... Data line drive circuit, 6 ... Scan line drive circuit, 12 ... Scan line, 14-1 ... 1st data transfer line, 14 -2 ... 2nd data transfer line, 16 ... Feed line, 31 ... Voltage generation circuit, 34 ... Transmission gate, 41 ... Holding capacitor, 42 ... Transmission gate, 45 ... Transmission gate, 70 ... Data signal supply circuit, 100 ... Display 110, pixel circuit, 116, feeder line, 118, common electrode, 121, 122, 123, 124, 125, 126 ... transistor, 130 ... OLED, 130a ... anode, 132 ... pixel capacity, 133 ... transfer capacity, 143 144, 145, 146 ... control line, 300 ... display, 301L, 301R ... lens, 302L, 302R ... optical recording 'S, 303L, 303R ... half mirror, 310 ... Temple, 320 ... bridge, DM ... demultiplexer, DT ... data transfer circuit.

Claims (9)

A first conductive layer;
A second conductive layer;
A third conductive layer;
A first capacitor including a first electrode connected to the second conductive layer and a second electrode connected to the third conductive layer;
A first transistor for bringing the second conductive layer and the third conductive layer into a conductive state or a non-conductive state;
A pixel circuit provided corresponding to the third conductive layer and the first conductive layer;
A drive circuit for driving the pixel circuit;
Have
The pixel circuit includes:
A drive transistor comprising a gate electrode, a first current end, and a second current end;
A second transistor connected between the third conductive layer and the gate electrode of the driving transistor;
A third transistor for conducting the first current terminal of the driving transistor and the gate electrode of the driving transistor;
A light emitting element that emits light with a luminance corresponding to the magnitude of current supplied through the driving transistor;
Including
The drive circuit is
In the first period, the first transistor is turned on to bring the second conductive layer and the third conductive layer into a conductive state, and the second transistor and the third transistor are turned off. 3 to supply an initial potential to the conductive layer,
In a second period following the first period, the first transistor is turned off to bring the second conductive layer and the third conductive layer into a non-conductive state, and at least the third transistor is turned on. , Electrically connecting the first current terminal of the driving transistor and the gate electrode of the driving transistor;
In a third period following the second period, the first transistor is turned off to bring the second conductive layer and the third conductive layer into a non-conductive state, and the second transistor and the third transistor To turn off the first current terminal of the driving transistor and the light emitting element, to cause the light emitting element to emit light,
At least one third conductive layer is connected to the second conductive layer via the first capacitor, and is connected to the same second conductive layer via the third conductive layer. When the set of the pixel circuits is a pixel column, and the number of the pixel circuits equal to or less than the number of the pixel circuits included in the pixel column is a block,
Providing a period for turning on the first transistor and supplying an initial potential to the third conductive layer in the third period in one block;
An electro-optical device. In the first period in one of the blocks and in the third period in the other block, the first transistor is turned on to supply an initial potential to the third conductive layer.
The electro-optical device according to claim 1. In the first period of one block, in the other block, the initial potential is supplied to the second conductive layer, and the first transistor is turned on to turn on the second conductive layer and the third conductive layer. Supplying an initial potential to the third conductive layer by bringing the layer into conduction;
The electro-optical device according to claim 1, wherein the electro-optical device is provided. A fourth conductive layer for supplying the initial potential;
The first transistor is a transistor that brings the fourth conductive layer and the third conductive layer into a conductive state or a non-conductive state,
In the first period in one of the blocks and in the third period in the other block, the first transistor is turned on to bring the fourth conductive layer and the third conductive layer into a conductive state. Thereby supplying an initial potential to the third conductive layer,
The electro-optical device according to claim 1, wherein the electro-optical device is provided. The first transistor is provided in common for the plurality of pixel circuits.
The electro-optical device according to claim 1, wherein The first transistor is provided for each of the pixel circuits.
The electro-optical device according to claim 1, wherein The first capacitor is provided for each of the third conductive layers.
The electro-optical device according to claim 1, wherein The electro-optical device according to claim 1.
An electronic device characterized by that. A first conductive layer;
A second conductive layer;
A third conductive layer;
A first capacitor including a first electrode connected to the second conductive layer and a second electrode connected to the third conductive layer;
A first transistor for bringing the second conductive layer and the third conductive layer into a conductive state or a non-conductive state;
A pixel circuit provided corresponding to the third conductive layer and the first conductive layer;
Have
The pixel circuit includes:
A drive transistor comprising a gate electrode, a first current end, and a second current end;
A second transistor connected between the third conductive layer and the gate electrode of the driving transistor;
A third transistor for conducting the first current terminal of the driving transistor and the gate electrode of the driving transistor;
A light emitting element that emits light with a luminance according to the magnitude of the current supplied through the driving transistor,
At least one third conductive layer is connected to the second conductive layer via the first capacitor, and is connected to the same second conductive layer via the third conductive layer. A method of driving an electro-optical device, wherein a set of the pixel circuits is a pixel column, and the number of pixel circuits equal to or less than the number of the pixel circuits included in the pixel column is one block,
In the first period, the first transistor is turned on to bring the first data transfer line and the second data transfer line into a conductive state, and the second transistor and the third transistor are turned off, 2 Supply the initial potential to the data transfer line,
In a second period following the first period, the first transistor is turned off to bring the second conductive layer and the third conductive layer into a non-conductive state, and at least the third transistor is turned on. , Electrically connecting the first current terminal of the driving transistor and the gate electrode of the driving transistor;
In a third period following the second period, the first transistor is turned off to bring the second conductive layer and the third conductive layer into a non-conductive state, and the second transistor and the third transistor To turn off the first current terminal of the driving transistor and the light emitting element, to cause the light emitting element to emit light,
Providing a period for turning on the first transistor and supplying an initial potential to the third conductive layer in the third period in one block;
A driving method for an electro-optical device.

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