JP6015115B2 - Electro-optical device and electronic apparatus - Google Patents

Description

  The present invention relates to an electro-optical device and an electronic apparatus that can suppress fluctuations in potential of an anode due to, for example, noise of a signal line or a data line.

  In recent years, various electro-optical devices using light emitting elements such as organic light emitting diode (hereinafter referred to as “OLED”) elements have been proposed. In this electro-optical device, a configuration in which a pixel circuit including the light emitting element, the transistor, and the like is provided corresponding to the pixel of the image to be displayed corresponding to the intersection of the scanning line and the data line. A pixel circuit using an OLED generally includes a write transistor that determines whether a data signal supplied via a data line can be input, a drive transistor that determines an amount of current supplied to the OLED based on the data signal, And a holding capacitor for holding a data signal supplied from the data line. Furthermore, there is a technique using more elements for the purpose of improving the image quality (see, for example, Patent Document 1).

JP 2002-341790 A

By the way, in the pixel circuit having the above-described structure, it is necessary to connect the active region constituting the transistor to the anode layer of the upper OLED using a contact hole. When this connection portion is affected by noise of signal lines and data lines located in the surrounding intermediate layer, the anode potential of the OLED fluctuates.
As a result, the light emission luminance of the OLED is affected by the potential fluctuation of the anode, and display defects such as display unevenness occur.
The present invention has been made in view of the above-described circumstances, and an object of the present invention is to reduce image quality degradation caused by noise associated with potential fluctuations of signal lines and data lines.

In order to solve the above problems, the electro-optical device according to the present invention is provided corresponding to a plurality of scanning lines and a plurality of data lines intersecting each other, and corresponding to the intersection of the scanning lines and the data lines. A plurality of pixel circuits; and a power supply wiring that is provided corresponding to each of the plurality of pixel circuits and supplies a predetermined potential. Each of the plurality of pixel circuits includes a light emitting element and the light emitting element. A plurality of transistors for controlling a current flowing through the plurality of transistors, wherein a source region or a drain region of at least one of the plurality of transistors and an anode of the light emitting element are the source region, the drain region, and the anode The intermediate electrode is electrically connected through an intermediate electrode formed in a layer between the intermediate electrode and at least three sides of the intermediate electrode formed in the same layer as the intermediate electrode. Characterized in that it is surrounded by a wire.
According to the present invention, the anode of the light emitting element and the semiconductor layer of at least one transistor connected to the anode are connected via the intermediate electrodes formed in different layers of the plurality of layers, Of the intermediate electrodes formed in different layers, at least three of the intermediate electrodes are surrounded by the power supply wiring. For this reason, it is difficult to be affected by noise due to potential fluctuations of surrounding signal lines and data lines, and potential fluctuations at the anode of the light emitting element are suppressed. As a result, a desired current can be supplied to the light emitting element, display defects such as display unevenness can be reduced, and display quality can be improved.

In the present invention, the power supply wiring may be a power supply wiring for initialization, a power supply wiring on the high potential side of the power supply, or a power supply wiring on the low potential side of the power supply.
Since these power supply wirings have a low impedance as compared with power supply wirings used in a scanning line driving circuit or a data line driving circuit, the shielding effect is further improved.

  Preferably, in the present invention, the power supply wiring surrounding the intermediate electrode may be formed in the same layer as the layer in which the data line is formed. The potential fluctuation of the anode of the light emitting element is most often caused by noise accompanying the fluctuation of the potential of the data line, etc., but a power supply wiring is formed in the same layer as the layer where this data line is formed. Since the electrode is surrounded, the fluctuation of the potential of the anode of the light emitting element is more reliably suppressed, and the display quality is improved.

  In the electro-optical device described above, the power supply wiring may be formed between the intermediate electrode and the data line, and the power supply wiring may surround the intermediate electrode. Since the power supply wiring surrounding the intermediate electrode is located between the intermediate electrode and the data line, noise from the data line is shielded by the power supply wiring. Therefore, it is possible to reliably suppress the potential fluctuation of the anode of the light emitting element and prevent image deterioration.

  In the electro-optical device described above, the one intermediate electrode may be surrounded by four openings by openings formed in the power supply wiring layer. In this case, one of the intermediate electrodes formed in different layers of the plurality of layers is surrounded by the openings formed in the power supply wiring layer, so that the shielding effect is further improved. To do.

  In addition to the electro-optical device, the present invention can be conceptualized as a driving method of the electro-optical device or an electronic apparatus having the electro-optical device. Typically, the electronic device includes a display device such as a head mounted display (HMD) or an electronic viewfinder.

1 is a perspective view illustrating a configuration of an electro-optical device according to an embodiment of the invention. 2 is a block diagram illustrating a configuration of the electro-optical device. FIG. It is a figure which shows the pixel circuit in the same electro-optical apparatus. 6 is a timing chart showing the operation of the electro-optical device. 2 is a plan view illustrating a configuration of a pixel circuit of the electro-optical device. FIG. It is a fragmentary sectional view which shows the structure fractured | ruptured by the A-A 'line | wire in FIG. It is a fragmentary sectional view which shows the structure fractured | ruptured by the B-B 'line | wire in FIG. It is a perspective view which shows HMD using the electro-optical apparatus which concerns on embodiment etc. FIG. It is a figure which shows the optical structure of HMD.

  Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.

<Embodiment>
FIG. 1 is a perspective view showing a configuration of an electro-optical device 10 according to an embodiment of the present invention.
The electro-optical device 10 is a micro display that displays an image on a head-mounted display, for example. Although details of the electro-optical device 10 will be described later, an organic EL device in which a plurality of pixel circuits, a drive circuit for driving the pixel circuits, and the like are formed on a silicon substrate, for example, is an example of a light emitting element. Some OLEDs are used.
The electro-optical device 10 is housed in a frame-like case 72 that opens at a display unit, and one end of an FPC (Flexible Printed Circuits) substrate 74 is connected. A semiconductor chip control circuit 5 is mounted on the FPC board 74 by a COF (Chip On Film) technique, and a plurality of terminals 76 are provided to be connected to an upper circuit (not shown). Image data is supplied from the upper circuit via a plurality of terminals 76 in synchronization with the synchronization signal. The synchronization signal includes a vertical synchronization signal, a horizontal synchronization signal, and a dot clock signal. Further, the image data defines the gradation level of the pixel of the image to be displayed by, for example, 8 bits.
The control circuit 5 combines the functions of the power supply circuit and the data signal output circuit of the electro-optical device 10. That is, the control circuit 5 supplies various control signals and various potentials generated according to the synchronization signal to the electro-optical device 10, converts digital image data into an analog data signal, and supplies the analog data signal to the electro-optical device 10. To do.

FIG. 2 is a diagram illustrating a configuration of the electro-optical device 10 according to the first embodiment. As shown in this figure, the electro-optical device 10 is roughly divided into a scanning line driving circuit 20, a data line driving circuit 30, and a display unit 100.
Among these, in the display unit 100, pixel circuits 110 corresponding to pixels of an image to be displayed are arranged in a matrix. In detail, in the display unit 100, m rows of scanning lines 12 are provided so as to extend in the horizontal direction in the drawing, and n columns of data lines 14 extend in the vertical direction in the drawing, and each scanning is performed. The wires 12 are provided so as to be electrically insulated from each other. A pixel circuit 110 is provided corresponding to the intersection of the m rows of scanning lines 12 and the n columns of data lines 14. Therefore, in the present embodiment, the pixel circuits 110 are arranged in a matrix with m rows × n columns.

  Here, m and n are both natural numbers. In order to distinguish rows (rows) in the matrix of the scanning lines 12 and the pixel circuits 110, they may be referred to as 1, 2, 3,..., (M−1), m rows in order from the top in the drawing. Similarly, in order to distinguish the columns (columns) of the data lines 14 and the pixel circuits 110, they may be referred to as 1, 2, 3,.

  In the present embodiment, the power supply line 16 is provided along the data line 14 for each column. The power supply lines 16 are commonly supplied with a potential Vorst as a reset potential.

  The following control signals are supplied to the electro-optical device 10 by the control circuit 5. Specifically, the electro-optical device 10 is supplied with a control signal Ctr1 for controlling the scanning line driving circuit 20 and a control signal Ctr2 for controlling the data line driving circuit 30.

The scanning line driving circuit 20 generates a scanning signal for sequentially scanning the scanning lines 12 for each row over a frame period in accordance with the control signal Ctr1. Here, the scanning signals supplied to the scanning lines 12 of 1, 2, 3,..., (M−1) and the m-th row are Gwr (1), Gwr (2), Gwr (3),. It is written as Gwr (m-1) and Gwr (m).
In addition to the scanning signals Gwr (1) to Gwr (m), the scanning line driving circuit 20 generates various control signals synchronized with the scanning signals for each row and supplies them to the display unit 100. Illustration is omitted in FIG. The frame period is a period required for the electro-optical device 10 to display an image for one cut (frame). For example, if the frequency of the vertical synchronization signal included in the synchronization signal is 120 Hz, the first period is 1. This is a period of 8.3 milliseconds corresponding to the period.

  Further, the data line driving circuit 30 gives the data signals Vd (1) and Vd (2) of the potential corresponding to the gradation data of the pixel circuit 110 to the pixel circuit 110 located in the row selected by the scanning line driving circuit 20. ,..., Vd (n) are supplied by the control circuit 5 to the data lines 14 in the 1, 2,.

  The pixel circuit 110 will be described with reference to FIG. FIG. 3 shows a pixel circuit 110 for one pixel corresponding to the intersection of the scanning line 12 in the i-th row and the data line 14 in the j-th column. Here, i is a symbol for generally indicating a row in which the pixel circuit 110 is arranged, and is an integer of 1 to m. Similarly, j is a symbol for generally indicating a column in which the pixel circuits 110 are arranged, and is an integer of 1 to n.

  As illustrated in FIG. 3, the pixel circuit 110 includes P-channel transistors 121 to 125, an OLED 130, and a storage capacitor 132. Since each pixel circuit 110 has the same configuration, the pixel circuit 110 will be described as being representatively located at i rows and j columns.

In the pixel circuit 110 in the i-th row and j-th column, the transistor 122 functions as a writing transistor, its gate node is connected to the scanning line 12 in the i-th row, and one of its drain or source node is in the j-th column. The other is connected to the data line 14, and the other is connected to the gate node g of the transistor 121, one end of the storage capacitor 132, and the drain node of the transistor 123. Here, the gate node of the transistor 121 is denoted by g to distinguish it from other nodes.
The scanning signal Gwr (i) is supplied to the i-th scanning line 12, that is, the gate node of the transistor 122.

  The transistor 121 functions as a driving transistor, and its source node is connected to the power supply line 116, and its drain node is connected to the source node of the transistor 123 and the source node of the transistor 124. Here, the power supply line 116 is supplied with a substrate potential Vel that is on the higher side of the power supply in the pixel circuit 110.

The transistor 123 functions as a compensation transistor, and a control signal Gcmp (i) is supplied to its gate node.
The transistor 124 functions as a light emission control transistor, a control signal Gel (i) is supplied to the gate node, and the drain node is connected to the source node of the transistor 125 and the anode of the OLED 130, respectively.

  The transistor 125 functions as an initialization transistor, and a control signal Gorst (i) is supplied to its gate node, and its drain node is connected to a power supply line (fixed potential wiring) 16 corresponding to the jth column. And maintained at the potential Vorst. Note that the sources and drains of the transistors 121 to 125 in the above may be switched depending on the channel type and potential relationship of each transistor.

  The other end of the storage capacitor 132 is connected to the power supply line 116. For this reason, the storage capacitor 132 holds the voltage between the source and the drain of the transistor 121. Note that as the storage capacitor 132, a capacitor parasitic to the gate node g of the transistor 121 may be used, or a capacitor formed by sandwiching an insulating layer between different conductive layers may be used.

  In the present embodiment, since the electro-optical device 10 is formed on a silicon substrate, the substrate potential of the transistors 121 to 125 is set to the potential Vel.

The anode of the OLED 130 is a pixel electrode provided individually for each pixel circuit 110. On the other hand, the cathode of the OLED 130 is a common electrode 118 provided in common throughout the pixel circuit 110, and is maintained at the potential Vct that is the lower side of the power supply in the pixel circuit 110.
The OLED 130 is an element in which an organic EL layer that emits white light is sandwiched between an anode and a light-transmitting cathode on the silicon substrate. A color filter corresponding to any of RGB is superimposed on the emission side (cathode side) of the OLED 130.
In such an OLED 130, when current flows from the anode to the cathode, holes injected from the anode and electrons injected from the cathode are recombined in the organic EL layer to generate excitons, and white light is generated. . The white light generated at this time is transmitted through the cathode on the side opposite to the silicon substrate side (anode), is colored by the color filter, and is visually recognized on the viewer side.

<Operation of electro-optical device>
Next, the operation of the electro-optical device 10 will be described with reference to FIG. FIG. 4 is a timing chart for explaining the operation of each part in the electro-optical device 10.
As shown in this figure, the scanning signals Gwr (1) to Gwr (m) are sequentially switched to the L level, and the scanning lines 12 in the 1st to m-th rows in one frame period are in one horizontal scanning period (H). Scanned sequentially.
The operation in one horizontal scanning period (H) is common to the pixel circuits 110 in each row. Therefore, in the following, the operation will be described focusing on the pixel circuit 110 in the i-th row and j-th column in the scanning period in which the i-th row is horizontally scanned.

  In this embodiment, the scanning period of the i-th row is roughly divided into an initialization period indicated by (b), a compensation period indicated by (c), and a writing period indicated by (d) in FIG. It is done. Then, after the writing period of (d), the light emission period shown in (a) is reached, and the scanning period of the i-th row is reached again after the elapse of one frame period. Therefore, in the order of time, a cycle of (light emission period) → initialization period → compensation period → writing period → (light emission period) is repeated.

<Light emission period>
For convenience of explanation, the light emission period which is the premise of the initialization period will be described. As shown in FIG. 4, in the light emission period of the i-th row, the scanning signal Gwr (i) is at the H level and the control signal Gel (i) is at the L level. Of the control signals Gel (i), Gcmp (i), and Gorst (i) that are logic signals, the control signal Gel (i) is at the L level, and the control signals Gcmp (i) and Gorst (i) are at the H level. Is a level.
For this reason, in the pixel circuit 110 in the i row and j column shown in FIG. 3, the transistor 124 is turned on, while the transistors 122, 123, and 125 are turned off. Therefore, the transistor 121 supplies a current Ids corresponding to the gate-source voltage Vgs to the OLED 130. As will be described later, in this embodiment, the voltage Vgs in the light emission period is a value that is level-shifted from the threshold voltage of the transistor 121 according to the potential of the data signal. Therefore, a current corresponding to the gradation level is supplied to the OLED 130 in a state where the threshold voltage of the transistor 121 is compensated.

  Note that since the light emission period of the i-th row is a period during which horizontal scanning is performed except for the i-th row, the potential of the data line 14 varies appropriately. However, in the pixel circuit 110 in the i-th row, since the transistor 122 is off, the potential fluctuation of the data line 14 is not considered here.

<Initialization period>
Next, when the scanning period of the i-th row is reached, first, the initialization period (b) is started as the first period. In the initialization period, the control signal Gel (i) changes to the H level and the control signal Gorst (i) changes to the L level as compared with the light emission period.
Therefore, in the pixel circuit 110 in the i row and j column shown in FIG. 3, the transistor 124 is turned off and the transistor 125 is turned on. As a result, the path of the current supplied to the OLED 130 is cut off, and the anode of the OLED 130 is reset to the potential Vorst.
Since the OLED 130 has a configuration in which the organic EL layer is sandwiched between the anode and the cathode as described above, a capacitance is parasitic between the anode and the cathode in parallel. When a current flows through the OLED 130 during the light emission period, the voltage across the anode and cathode of the OLED 130 is held by the capacitor, but this holding voltage is reset by turning on the transistor 125. For this reason, in this embodiment, when a current flows again through the OLED 130 in a later light emission period, it is less likely to be affected by the voltage held in the capacitor.

Specifically, for example, when switching from a high-brightness display state to a low-brightness display state, if the configuration does not reset, the high voltage when the luminance is high (a large current flows) is retained. In addition, even if a small current is applied, an excessive current flows and the display state with low luminance cannot be achieved. On the other hand, in this embodiment, since the potential of the anode of the OLED 130 is reset when the transistor 125 is turned on, the reproducibility on the low luminance side is improved.
In the present embodiment, the potential Vorst is set such that the difference between the potential Vorst and the potential Vct of the common electrode 118 is lower than the light emission threshold voltage of the OLED 130. Therefore, the OLED 130 is in an off (non-light emitting) state in the initialization period (a compensation period and a writing period described below).

<Compensation period>
In the i-th scanning period, the second period is the compensation period (c). In the compensation period, the scanning signal Gwr (i) and the control signal Gcmp (i) are at the L level as compared with the initialization period. On the other hand, in the compensation period, the control signal / Gini becomes H level while the control signal Gref is maintained at H level.
Since the transistor 123 is turned on during the compensation period, the transistor 121 is diode-connected. Therefore, a drain current flows through the transistor 121 and charges the gate node g and the data line 14. Specifically, the current flows through a path of the feeder line 116 → the transistor 121 → the transistor 123 → the transistor 122 → the data line 14 in the j-th column. For this reason, when the transistor 121 is turned on, the potentials of the data line 14 and the gate node g that are connected to each other rise.
However, if the threshold voltage of the transistor 121 is | Vth |, the current flowing through the path becomes difficult to flow as the gate node g approaches the potential (Vel− | Vth |). The data line 14 and the gate node g are saturated with the potential (Vel− | Vth |). Accordingly, the storage capacitor 132 holds the threshold voltage | Vth | of the transistor 121 until the end of the compensation period.

<Writing period>
After the initialization period, the writing period (d) is reached as the third period. In the writing period, the control signal Gcmp (i) is at the H level, so that the diode connection of the transistor 121 is released. The potential in the path from the data line 14 in the j-th column to the gate node g in the pixel circuit 110 in the i-th row and j-th column is maintained at (Vel− | Vth |) by the storage capacitor 132.

<Light emission period>
After the end of the writing period for the i-th row, a light emission period is reached after one horizontal scanning period. In this light emission period, the control signal Gel (i) is at the L level as described above, so that the transistor 124 is turned on in the pixel circuit 110 in the i row and j column. A current corresponding to the gradation level is supplied to the OLED 130 in a state where the threshold voltage of the transistor 121 is compensated.
Such an operation is also performed in parallel in time in the other pixel circuits 110 in the i-th row other than the pixel circuit 110 in the j-th column in the i-th row scanning period. Further, such an operation on the i-th row is actually executed in the order of 1, 2, 3,..., (M−1), m-th row in the period of one frame, and is repeated for each frame. It is.

In the pixel circuit 110 as described above, the anode (anode) of the OLED 130 is connected to the node N connected to the source or drain node of the transistor 124 and the source or drain node of the transistor 125. When the node N is affected by the noise of the surrounding signal lines or data lines, the potential of the node N fluctuates, and the potential fluctuation at the node N greatly affects the light emission luminance of the OLED 130.
However, in the present invention, as will be described later, since the contact portion of the node N is surrounded by the power supply line (fixed potential wiring) 16, the anode potential fluctuation due to the noise of the signal line or the data line is suppressed. , A desired current can be supplied to the OLED 130. As a result, display defects such as display unevenness can be reduced.
Details will be described later.

  According to the present embodiment, a period longer than the scanning period, for example, two horizontal scanning periods can be secured as a period during which the transistor 125 is turned on, that is, a reset period of the OLED 130. The applied voltage can be sufficiently initialized.

  Further, according to this embodiment, the current Ids supplied to the OLED 130 by the transistor 121 cancels the influence of the threshold voltage. Therefore, according to the present embodiment, even if the threshold voltage of the transistor 121 varies from pixel circuit 110 to pixel circuit 110, the variation is compensated and a current corresponding to the gradation level is supplied to the OLED 130. As a result of suppressing the occurrence of display unevenness that impairs uniformity, high-quality display is possible.

  Furthermore, according to the present embodiment, since the contact portion of the node N connected to the anode (anode) of the OLED 130 is surrounded by the power supply line (fixed potential wiring) 16, the noise of the signal line or the data line As a result, the anode potential fluctuation due to the current can be suppressed, and a desired current can be supplied to the OLED 130. As a result, display defects such as display unevenness can be reduced.

<Structure of pixel circuit>
Next, the structure of the pixel circuit 110 will be described with reference to FIGS.
5 is a plan view showing the configuration of one pixel circuit 110, FIG. 6 is a partial sectional view taken along line AA ′ in FIG. 5, and FIG. 7 is taken along line BB ′ in FIG. It is a fragmentary sectional view broken.
FIG. 5 shows a wiring structure when the top emission pixel circuit 110 is viewed in plan view from the observation side. However, for simplification, the pixel circuit 110 is formed above the feeder line 16 (on the organic EL layer side). Structure is omitted. Further, in each of the following drawings, the scales are varied in order to make each layer, each member, each region, etc. recognizable.

First, as shown in FIG. 6, a base substrate 2 is provided. Although the board | substrate 2 is provided in flat form, in FIG. 5, it represents in island shape so that the position of each transistor can be understood easily.
The substrate 2 is provided with an active region 143 for forming a transistor. Here, the active region is a region for forming a MOS transistor and corresponds to a source / drain region. The semiconductor layer 143 constitutes the transistor 124. Similarly to the semiconductor layer 143, the substrate 2 is provided with active regions 140, 141, 142 as shown in FIG. The active region 140 constitutes the transistor 122 and the transistor 123, the active region 141 constitutes the transistor 121, and the active region 142 constitutes the transistor 125.

  As shown in FIG. 6, the gate insulating film 17 is provided so as to cover the entire surface of the active region 143. The gate insulating film 17 is provided so as to cover almost the entire surface of the active regions 140 to 142. A gate wiring layer such as aluminum or polysilicon is provided on the surface of the gate insulating film 17, and a gate electrode 148 is provided by patterning the gate wiring layer, for example, as shown in FIG. The gate electrode 148 is a gate electrode of the transistor 124. As shown in FIG. 5, the gate electrode 148 includes the gate electrode 144 of the transistor 121, the gate electrode 145 of the transistor 122, the gate electrode 146 of the transistor 123, as shown in FIG. A gate electrode 147 of the transistor 125 is provided.

  In FIG. 7, a first interlayer insulating film 18 is formed so as to cover the gate electrode 148 or the gate insulating film 17. A conductive wiring layer is formed on the surface of the first interlayer insulating film 18, and a relay electrode 45 is formed by patterning the wiring layer. Further, as shown in FIG. 5, relay electrodes 41, 42, 43, 44, 45, 46 are formed in the same level as the relay electrode 45.

Among these, the relay electrode 45 is connected to the gate electrode active region 143 of the transistor 124 through a contact hole 39 provided in the first interlayer insulating film 18. The relay electrode 45 is connected to the active region 142 of the transistor 125 through contact holes 50 provided in the first interlayer insulating film 18 and the gate insulating film 17, respectively.
In FIG. 5, a portion where “□” mark is added to “□” mark in a portion where different wiring layers overlap each other is a contact hole.

In FIG. 5, one end of the relay electrode 41 is connected to the gate electrode 144 of the transistor 121 via the contact hole 31 provided in the first interlayer insulating film 18, while the other end of the relay electrode 41 is connected to the contact hole 32. To the active region 140 of the transistor 122.
One end of the relay electrode 42 is connected to the active region 140 of the transistor 122 through contact holes 33 provided in the first interlayer insulating film 18 and the gate insulating film 17, while the other end of the relay electrode 42 is described later. It is connected to a data line 14 to be described later through a contact hole 34 provided in the second interlayer insulating film 19.
One end of the relay electrode 43 is connected to the active region 141 of the transistor 121 through a contact hole 35 provided in each of the first interlayer insulating film 18 and the gate insulating film 17, while the other end of the relay electrode 43 is It is connected to the active region 140 of the transistor 123 through a contact hole 36 provided in each of the first interlayer insulating film 18 and the gate insulating film 17.
One end of the relay electrode 44 is connected to the active region 142 of the transistor 125 through contact holes 37 provided in the first interlayer insulating film 18 and the gate insulating film 17, respectively, while the other end of the relay electrode 44 is described later. The second interlayer insulating film 19 is connected to a power supply line 16 to be described later through a contact hole 38 provided in the second interlayer insulating film 19.
One end of the relay electrode 45 is connected to the active region 143 of the transistor 124 through a contact hole 39 provided in each of the first interlayer insulating film 18 and the gate insulating film 17, while the other end of the relay electrode 45 is connected to the first The first interlayer insulating film 18 and the gate insulating film 17 are connected to the active region 142 of the transistor 125 through contact holes 50 provided respectively.
One end of the relay electrode 46 is connected to the active region 143 of the transistor 124 via the contact hole 40 provided in the first interlayer insulating film 18 and the gate insulating film 17 respectively, while the other end of the relay electrode 46 is connected to the first It is connected to the active region 141 of the transistor 121 through a contact hole 35 provided in each of the first interlayer insulating film 18 and the gate insulating film 17.

Further, connection electrodes to the scanning line 12, the control line 118, and the power supply line 116 are formed in the same level as the above-described relay electrodes 41, 42, 43, 44, 45, and 46, and as shown in FIG. Control lines 114 and 115 are formed.
The scanning line 12 is connected to the gate electrode 145 of the transistor 122 through a contact hole 51 provided in the first interlayer insulating film 18.
The control line 118 is connected to the gate electrode 146 of the transistor 123 through the contact hole 52 provided in the first interlayer insulating film 18.
The control line 114 is connected to the gate electrode 148 of the transistor 124 through the contact hole 53 provided in the first interlayer insulating film 18.
The control line 115 is connected to the gate electrode 147 of the transistor 125 through the contact hole 54 that opens the first interlayer insulating film 18.
A connection electrode to the power supply line 116 is connected to the active region 141 of the transistor 121 through a contact hole 56 provided in the first interlayer insulating film 18 and the gate insulating film 17.

The relay electrode 41, 42, 43, 44, 45, 46 and the second interlayer insulating film so as to cover the connection electrode to the scanning line 12, the control lines 118, 114, 115, and the power supply line 116 or the first interlayer insulating film 18 19 is formed. A conductive wiring layer is formed on the surface of the second interlayer insulating film 19, and a data line 14 and a power supply line 16 are formed by patterning the wiring layer.
Among these, the feeder line 16 is connected to the relay electrode 44 through a contact hole 38 provided in the second interlayer insulating film 19, and is connected to the active region 142 of the transistor 125 through the relay electrode 44.
Further, the data line 14 is connected to the relay electrode 42 through a contact hole 34 provided in the second interlayer insulating film 19.

  Note that the capacitor 132 shown in FIG. 3 is formed in an upper layer than the power supply line 16 and the data line 14 described above, but the illustration is omitted.

Further, as shown in FIGS. 5 and 6, the feeder line 16 is formed so as to cover the transistor 121 and the transistor 124, but at the connection portion from the active region 143 of the transistor 124 to the anode (anode) of the OLED 130. An opening 154 is provided so as to surround the intermediate electrode 150 in a certain node N. Note that the intermediate electrode 150 is not shown in FIG.
As shown in FIGS. 6 and 7, the relay electrode 45 is connected to the gate electrode of the lowermost transistor 124 through the contact hole 39, and the contact hole 152 is provided in the second interlayer insulating film 19. .
The relay electrode 45 is connected to the intermediate electrode 150 through the contact hole 152, and the intermediate electrode 150 is connected to the anode layer 151 through the contact hole 153 provided in the third interlayer insulating film 15. The anode layer 151 is a layer connected to the anode (anode) of the OLED 130.
As in the case of the intermediate electrode 150, the anode layer 151 and the contact holes 152 and 153 are not shown in FIG.

As described above, in this embodiment, the four sides of the intermediate electrode 150 that is a connection point from the active region 143 of the transistor 124 to the anode (anode) of the OLED 130 are supplied as shown in FIGS. 5, 6, and 7. It is configured to be surrounded by an electric wire (fixed potential wiring) 16.
Therefore, as shown in FIG. 6, even if noise is generated due to potential fluctuations of the data line 14 formed in the same layer as the power supply line 16, the intermediate electrode 150 electrically connected to the anode (anode) Since the four sides are surrounded by a power supply line (fixed potential wiring) 16, it is not affected by noise or can be reduced, and the anode of the OLED 130 connected to the intermediate electrode 150 and the anode layer 151 can be reduced. The potential fluctuation of (anode) is suppressed.
As a result, a desired current can be supplied to the OLED 130, and display defects such as display unevenness can be reliably prevented.
Further, the power supply line (fixed potential wiring) 16 that is the power supply wiring for initialization has a lower impedance than the power supply wiring used in the scanning line driving circuit 20, the data line driving circuit 30, and the like, and therefore has a more shielding effect. Will improve.

  Although the illustration of the subsequent structure as the electro-optical device 10 is omitted, a light-emitting layer made of an organic EL material is laminated on the anode for each pixel circuit 110, and a common transparent electrode across the pixel circuits 110 serves as a cathode. Is provided as a common electrode 118 serving as both. As a result, the light emitting element is composed of an OLED 130 in which a light emitting layer is sandwiched between an anode and a cathode facing each other, emits light with a luminance corresponding to a current flowing from the anode to the cathode, and travels in a direction opposite to the substrate 2. Will be observed (top emission structure). In addition, a sealing glass or the like for shielding the light emitting layer from the atmosphere is provided, but the description is omitted.

<Application and modification>
The present invention is not limited to the above-described embodiments and application examples, and various modifications as described below are possible. Moreover, the aspect of the deformation | transformation described below can also combine suitably arbitrarily selected 1 or several.

<Control circuit>
In the embodiment, the control circuit 5 that supplies the data signal is separated from the electro-optical device 10. However, the control circuit 5 also includes a silicon substrate along with the scanning line driving circuit 20, the demultiplexer 30, and the level shift circuit 40. It may be integrated in.

<Board>
In the embodiment, the electro-optical device 10 is integrated on the silicon substrate. However, the electro-optical device 10 may be integrated on another semiconductor substrate. Further, it may be formed on a glass substrate or the like by applying a polysilicon process. In any case, the pixel circuit 110 is miniaturized, and the transistor 121 is effective in a configuration in which the drain current greatly changes exponentially with respect to the change in the gate voltage Vgs.

<Control signal Gcmp (i)>
In the embodiment and the like, in the i-th row, the control signal Gcmp (i) is set to the H level in the writing period, but may be set to the L level. That is, the threshold compensation by turning on the transistor 123 and the writing to the node gate g may be executed in parallel.

<Transistor channel type>
In the above-described embodiments and the like, the transistors 121 to 125 in the pixel circuit 110 are unified with the P-channel type, but may be unified with the N-channel type. Further, the P channel type and the N channel type may be appropriately combined.

<Shield of intermediate electrode of node N>
In the above-described embodiment, the data line 14 that is a noise generation source and the power supply line 16 that is a wiring (shield wiring) for reducing the influence of noise on the intermediate electrode 150 are in the same level. Although an example in which the four sides are surrounded by the power supply line 16 has been described, the present invention is not limited to such a configuration.
For example, the relay electrode 45 or the anode layer 151 may be surrounded by a wiring layer at the same level as the relay electrode 45 or the anode layer 151 shown in FIGS. That is, the wiring that becomes a noise generation source and the shield wiring may be arranged in different layers. For example, the wiring layer may be connected to the power supply line 16 using a contact hole.
In the above-described embodiment, the power supply wiring that surrounds the intermediate electrode of the node N has been described using the power supply line 16 that is a power supply wiring for initialization. However, the present invention is limited to such a configuration. It is not a thing.
The wiring serving as a shield may be a constant potential wiring. Note that constant potential wiring in this specification means wiring that is not expected to vary in applied potential. For example, it may be a power supply line 116 to which the substrate potential Vel is supplied, or a wiring that is kept at the potential Vct on the lower side of the power source.
All of these wirings have a low impedance compared to the power supply wiring used in the scanning line driving circuit 20 or the data line driving circuit 30, and the shielding effect is further improved when used as a shielding line.
In the above-described embodiment, the example in which the four sides of the intermediate electrode of the node N are surrounded by the power supply wiring has been described. However, the present invention is not limited to such a configuration, and it is sufficient that at least three sides are surrounded. . For example, even if a slit that is continuous with the opening 154 shown in FIG. 5 is formed in the feeder line 16, if the majority of the intermediate electrode of the node N is surrounded by the feeder line 16, a desired shielding effect can be obtained. It is done. In this specification, surrounding the intermediate electrode means that the feeder line 16 is arranged around the intermediate electrode, and the intermediate electrode and the feeder line 16 are disposed between the intermediate electrode and the feeder line 16 in the layer where the intermediate electrode and the feeder line 16 are arranged. Means a state in which no other wiring is arranged. When the configuration is such that three sides of the intermediate electrode are surrounded by the power supply line 16, the power supply line 16 is preferably disposed between the intermediate electrode and the data line 14. Further, when the power supply line 16 and the data line 14 are alternately arranged, that is, the n + 1-th power supply line 16 is arranged between the n-th data line 14 and the n + 1-th data line, and n + 1 When three sides of the intermediate electrode are surrounded by the power supply line 16 in the column, the distance between the power supply line 16 in the n + 1th column and the intermediate electrode is larger than the distance between the data line 14 in the nth column and the intermediate electrode. It is preferable that the distance is shorter. Thereby, the influence which the noise from a data line has on an intermediate electrode can be reduced.

<Others>
In the embodiments and the like, an OLED that is a light emitting element is illustrated as an electro-optical element, but any light emitting element may be used as long as it emits light with a luminance according to current, such as an inorganic light emitting diode or LED (Light Emitting Diode).

<Electronic equipment>
Next, an electronic apparatus to which the electro-optical device 10 according to the embodiment and the application example is applied will be described. The electro-optical device 10 is suitable for high-definition display with small pixels. Therefore, a head mounted display will be described as an example of an electronic device.

FIG. 8 is a diagram showing the external appearance of the head-mounted display, and FIG. 9 is a diagram showing its optical configuration.
First, as shown in FIG. 8, the head mounted display 300 has a temple 310, a bridge 320, and lenses 301L and 301R in the same manner as general glasses. Further, as shown in FIG. 9, the head-mounted display 300 is in the vicinity of the bridge 320 and on the back side (lower side in the drawing) of the lenses 301L and 301R, the electro-optical device 10L for the left eye and the right eye. Electro-optical device 10R.
The image display surface of the electro-optical device 10L is arranged on the left side in FIG. Accordingly, the display image by the electro-optical device 10L is emitted in the direction of 9 o'clock in the drawing through the optical lens 302L. The half mirror 303L reflects the display image from the electro-optical device 10L in the 6 o'clock direction, and transmits light incident from the 12 o'clock direction.
The image display surface of the electro-optical device 10R is disposed on the right side opposite to the electro-optical device 10L. As a result, the display image by the electro-optical device 10R is emitted in the direction of 3 o'clock in the drawing through the optical lens 302R. The half mirror 303R reflects the display image by the electro-optical device 10R in the 6 o'clock direction, and transmits light incident from the 12 o'clock direction.

In this configuration, the wearer of the head mounted display 300 can observe the display image by the electro-optical devices 10L and 10R in a see-through state superimposed on the outside.
In the head-mounted display 300, when a left-eye image is displayed on the electro-optical device 10L and a right-eye image is displayed on the electro-optical device 10R among binocular images with parallax, The displayed image can be perceived as if it had a depth or a stereoscopic effect (3D display).

  The electro-optical device 10 can be applied to an electronic viewfinder in a video camera, an interchangeable lens digital camera, etc. in addition to the head mounted display 300.

DESCRIPTION OF SYMBOLS 10 ... Electro-optical apparatus, 12 ... Scanning line, 14 ... Data line, 16 ... Feeding line (fixed potential wiring), 20 ... Scanning line drive circuit, 30 ... Data line drive circuit, 30-39 ... Contact hole, 41-46 ... Relay electrode, 50-56 ... Contact hole, 100 ... Display unit, 110 ... Pixel circuit, 114, 115 ... Control line feed line, 116 ... Feed line, 118 ... Control line, 121-125 ... Transistor, 130 ... OLED, 132: holding capacitor, 140-143: active region, 144-148: gate electrode, 150 ... intermediate electrode, 151 ... anode layer, 152, 153 ... contact hole, 154 ... opening, 300 ... head mounted display.

Claims (5)

A plurality of scan lines and a plurality of data lines intersecting each other;
A plurality of pixel circuits provided corresponding to intersections of the scanning lines and the data lines;
A feeder line;
Power supply wiring for initialization, and
Each of the plurality of pixel circuits is
A light emitting element;
A transistor for controlling a current flowing through the light emitting element,
One of a source region or a drain region of the transistor is electrically connected to the feeder line,
Before and the other of the source region or the drain region of Quito lunge star, said the anode of the light emitting element, the source region and the drain region and through an intermediate electrode formed in a layer between the anode electrically Connected,
At least three sides of the intermediate electrode are surrounded by the power supply wiring formed in the same layer as the intermediate electrode,
The electro-optical device , wherein the power supply wiring surrounding the intermediate electrode is formed in the same layer as the data line . In the first period, the feeder line is used to supply a current controlled by the transistor to the light emitting element,
2. The electro-optical device according to claim 1 , wherein the power supply wiring is used to reset a potential of an anode of the light emitting element in a second period different from the first period . The power supply wire surrounds the intermediate electrode such that the power supply wire is positioned between the intermediate electrode and the data line;
The electro-optical device according to claim 1 , wherein the electro-optical device is provided. The intermediate electrode is surrounded on all four sides by openings formed in the power supply wiring.
The electro-optical device according to any one of claims 1 to 3, characterized in that. An electronic apparatus comprising the electro-optical device according to any one of claims 1 to 4.

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