CN107393463B - Electro-optical device and electronic apparatus - Google Patents

Electro-optical device and electronic apparatus Download PDF

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Publication number
CN107393463B
CN107393463B CN201710224074.7A CN201710224074A CN107393463B CN 107393463 B CN107393463 B CN 107393463B CN 201710224074 A CN201710224074 A CN 201710224074A CN 107393463 B CN107393463 B CN 107393463B
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transistor
period
potential
electro
optical device
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CN107393463A (en
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太田人嗣
石黑英人
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Seiko Epson Corp
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Seiko Epson Corp
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0294—Details of sampling or holding circuits arranged for use in a driver for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

The present invention relates to an electro-optical device and an electronic apparatus. A1 st holding capacitance is provided corresponding to the data line. The pixel circuit includes: a 1 st transistor for supplying a current corresponding to a gate-source voltage; a light emitting element which emits light in accordance with a current supplied from the 1 st transistor; and a 2 nd transistor that is turned on or off between the data line and the gate node. In the 1 st period, the 2 nd transistor is turned on to supply an initial potential to the data line, and in the 2 nd period, the 2 nd transistor is turned on to supply a data signal of a potential corresponding to a gradation to the other end of the 1 st holding capacitor. After the 2 nd period, the 2 nd transistor is turned off.

Description

Electro-optical device and electronic apparatus
The present application is a divisional application of an invention patent application having an application number of 201210375917.0, an application date of 2012, 9/29, and an application title of "electro-optical device, method of driving electro-optical device, and electronic apparatus", from seiko eprinon corp.
Technical Field
The present invention relates to an electro-optical device, a driving method of the electro-optical device, and an electronic apparatus, which are effective when a pixel circuit is miniaturized, for example.
Background
In recent years, various electro-optical devices using Light Emitting elements such as Organic Light Emitting Diode (hereinafter referred to as "OLED") elements have been proposed. In general, in the electro-optical device, a pixel circuit including the light-emitting element, the transistor, and the like is provided corresponding to a pixel of an image to be displayed, in correspondence with an intersection of a scanning line and a data line. In such a configuration, when a data signal of a potential corresponding to the gradation level of the pixel is applied to the gate of the transistor, the transistor supplies a current corresponding to the voltage between the gate and the source to the light-emitting element. This light-emitting element thereby emits light with a luminance corresponding to the gray scale (see, for example, patent document 1).
In addition, in many electro-optical devices, downsizing of a display size and high definition of display are strongly required. In order to achieve both downsizing of a display size and high definition of a display, it is necessary to miniaturize a pixel circuit, and therefore, a technique of providing an electro-optical device on a silicon integrated circuit, for example, has been proposed (for example, see patent document 2).
Patent document 1: japanese laid-open patent publication No. 2007-316462
Patent document 2: japanese laid-open patent publication No. 2009-288435
However, when the pixel circuit is miniaturized, it is necessary to control the supply of current to the light-emitting element in a minute region. Although the current supplied to the light emitting element is controlled by the voltage between the gate and the source of the transistor, the current supplied to the light emitting element greatly changes in a minute region with respect to a small change in the voltage between the gate and the source.
On the other hand, a circuit for outputting a data signal has a driving capability improved in order to charge a data line in a short time. Thus, in a circuit having a high driving capability, it is difficult to output a data signal with very high accuracy.
Disclosure of Invention
The present invention has been made in view of the above circumstances, and an object thereof is to provide an electro-optical device, a driving method of the electro-optical device, and an electronic apparatus, which are capable of accurately controlling a current supplied to a light emitting element without requiring a high-precision data signal.
In order to achieve the above object, an electro-optical device according to the present invention includes: a plurality of scan lines; a plurality of data lines; a 1 st holding capacitor having one end connected to the data line; a 2 nd holding capacitor for holding potentials of the plurality of data lines, respectively; pixel circuits provided in correspondence with intersections of the plurality of scanning lines and the plurality of data lines; and a drive circuit that drives the pixel circuit; the pixel circuit includes: a 1 st transistor for supplying a current corresponding to a gate-source voltage; a light emitting element that emits light at a luminance corresponding to the current supplied by the transistor; and a 2 nd transistor which is turned on or off between the data line and a gate of the 1 st transistor; the drive circuit turns on the 2 nd transistor in the 1 st period, supplies a data signal of a potential corresponding to a gray scale to the other end of the 1 st storage capacitor in a state where the 2 nd transistor is turned on in the 2 nd period immediately after the 1 st period while supplying an initial potential to the data line, and turns off the 2 nd transistor after the 2 nd period. According to the present invention, in the 1 st period, the gate of the 1 st transistor is held at an initial potential together with the data line by the 2 nd holding capacitance. In the 2 nd period, when a data signal of a potential corresponding to a gradation level is supplied to the other end of the 1 st holding capacitor in a state where the 2 nd transistor is turned on, potentials of the data line and the gate of the 1 st transistor are shifted by an amount of dividing the potential variation of the other end of the 1 st holding capacitor by a capacitance ratio of the 1 st holding capacitor and the 2 nd holding capacitor. Therefore, according to the present invention, since the potential range of the gate of the 1 st transistor is narrowed with respect to the potential range of the data signal, even when the current change is large with respect to the voltage change between the gate and the source of the 1 st transistor, the current can be accurately controlled.
In the present invention, it is preferable that the drive circuit starts to supply the initial potential to the data line in a state where the 2 nd transistor is turned off before the 1 st period. According to this configuration, first, after the data line is reset to the initial potential alone, the 2 nd transistor is turned on in the 1 st period, and the gate of the 1 st transistor is also initialized.
In this configuration, it is preferable that the pixel circuit includes a 3 rd transistor which is turned on or off between the 1 st transistor and the light emitting element, and the driving circuit turns on the 3 rd transistor in a 3 rd period immediately after the 2 nd period. According to this aspect, after the shift potential of the data signal is written to the gate of the 1 st transistor, a current is supplied to the light-emitting element.
In the above aspect, the drive circuit may turn off the 3 rd transistor before the 1 st period. Thus, no current can be supplied to the light-emitting element in the 1 st period in which the gate of the 1 st transistor is at the initial potential and the 2 nd period shifted from the initial potential.
The pixel circuit may further include a 3 rd storage capacitor for storing a voltage between the gate and the source of the 1 st transistor. The 3 rd holding capacitor may be a parasitic capacitor of the 1 st transistor or may be a capacitor element separately provided.
The present invention can be configured as a method of driving an electro-optical device in addition to the electro-optical device, and an electronic apparatus including the electro-optical device. As the electronic apparatus, a display device such as a Head Mounted Display (HMD) or an electronic viewfinder can be typically cited.
Drawings
Fig. 1 is a perspective view showing a configuration of an electro-optical device according to embodiment 1 of the present invention.
Fig. 2 is a diagram showing a structure of the electro-optical device.
Fig. 3 is a diagram showing a pixel circuit in the electro-optical device.
Fig. 4 is a timing chart showing an operation of the electro-optical device.
Fig. 5 is an explanatory view of the operation of the electro-optical device.
Fig. 6 is an explanatory view of the operation of the electro-optical device.
Fig. 7 is an explanatory view of the operation of the electro-optical device.
Fig. 8 is an explanatory view of the operation of the electro-optical device.
Fig. 9 is an explanatory view of the operation of the electro-optical device.
Fig. 10 is a diagram showing amplitude compression of a data signal in the electro-optical device.
Fig. 11 is a diagram showing a configuration of an electro-optical device according to embodiment 2.
Fig. 12 is a diagram showing a pixel circuit in the electro-optical device.
Fig. 13 is a timing chart showing an operation of the electro-optical device.
Fig. 14 is an explanatory view of an operation of the electro-optical device.
Fig. 15 is an explanatory view of an operation of the electro-optical device.
Fig. 16 is an explanatory view of an operation of the electro-optical device.
Fig. 17 is an explanatory view of an operation of the electro-optical device.
Fig. 18 is a diagram showing characteristics of transistors in the electro-optical device.
Fig. 19 is a diagram showing a configuration of an electro-optical device according to embodiment 3.
Fig. 20 is a timing chart showing an operation of the electro-optical device.
Fig. 21 is an explanatory view of the operation of the electro-optical device.
Fig. 22 is an explanatory view of an operation of the electro-optical device.
Fig. 23 is an explanatory view of an operation of the electro-optical device.
Fig. 24 is an explanatory view of the operation of the electro-optical device.
Fig. 25 is a perspective view showing an HMD using an electro-optical device according to an embodiment and the like.
Fig. 26 is a diagram showing an optical configuration of the HMD.
Detailed Description
Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.
< embodiment 1 >
Fig. 1 is a perspective view showing a configuration of an electro-optical device 10 according to an embodiment of the present invention.
The electro-optical device 10 is, for example, a microdisplay that displays an image on a head-mounted display. As will be described in detail later, the electro-optical device 10 is an organic EL device in which a plurality of pixel circuits, a driver circuit for driving the pixel circuits, and the like are formed on a silicon substrate, for example, and an OLED, which is an example of a light-emitting element, is used for the pixel circuits.
The electro-optical device 10 is housed in a frame-shaped case 72 that is open in the display section, and is connected to one end of an FPC (flexible printed Circuits) substrate 74. The FPC board 74 is mounted with the control circuit 5 of a semiconductor Chip by COF (Chip on film) technology, and is provided with a plurality of terminals 76 to be connected to an upper circuit (not shown). Image data is supplied from the upper circuit in synchronization with the synchronization signal via a plurality of terminals 76. The synchronization signals include a vertical synchronization signal, a horizontal synchronization signal, and a dot clock signal. The image data defines, for example, 8 bits of gray scale of a pixel of an image to be displayed.
The control circuit 5 is a circuit having both functions of a power supply circuit and a data signal output circuit of the electro-optical device 10. That is, the control circuit 5 supplies various control signals and various potentials generated based on the synchronization signal to the electro-optical device 10, and converts digital image data into an analog data signal and supplies the analog data signal to the electro-optical device 10.
Fig. 2 is a diagram showing a configuration of the electro-optical device 10 according to embodiment 1. As shown in the figure, the electro-optical device 10 is roughly divided into a scanning line driver circuit 20, a demultiplexer (demultiplexer)30, a level shifter circuit 40, and a display section 100.
In the display unit 100, pixel circuits 110 corresponding to pixels of an image to be displayed are arranged in a matrix. Specifically, in the display unit 100, m rows of scanning lines 12 extend in the horizontal direction in the drawing, and 3n columns of data lines 14 grouped in 3 columns extend in the vertical direction in the drawing and are provided so as to be electrically insulated from the scanning lines 12. The pixel circuits 110 are provided corresponding to intersections of the m rows of scanning lines 12 and the (3n) columns of data lines 14. Therefore, in the present embodiment, the pixel circuits 110 are arranged in a matrix form in m vertical rows × 3n horizontal columns.
Here, m and n are both natural numbers. In order to distinguish between the scanning line 12 and the row (row) in the matrix of the pixel circuits 110, the rows are sometimes referred to as 1, 2, 3, …, (m-1), m rows in the order from top to bottom in the drawing. Similarly, in order to distinguish between the data line 14 and the Column (Column) of the matrix of the pixel circuits 110, the columns are sometimes referred to as 1, 2, 3, …, (3 n-1), (3n) in order from left to right in the drawing. In order to describe the group of data lines 14 in a general manner, if an integer j of 1 to n is used, the (3 j-2) th column, the (3 j-1) th column, and the (3j) th column from the left belong to the j-th group.
The 3 pixel circuits 110 corresponding to the intersections of the scanning lines 12 in the same row and the 3 columns of data lines 14 belonging to the same group correspond to R (red), G (green), and B (blue) pixels, respectively, and these 3 pixels represent 1 dot of a color image to be displayed. That is, in the present embodiment, the color of 1 dot is expressed by additive color mixing by the light emission of the OLED corresponding to RGB.
The control circuit 5 supplies the following control signals to the electro-optical device 10. Specifically, the following signals are supplied to the electro-optical device 10: a control signal Ctr for controlling the scanning line driving circuit 20; control signals Sel (1), Sel (2), Sel (3) for controlling selection of the demultiplexer 30; control signals/Sel (1), (2), and/Sel (3) in a logically inverted relationship with these signals; a control signal/Gini for controlling the negative logic of the level shift circuit 40. In practice, the control signal Ctr includes a plurality of signals such as a pulse signal, a clock signal, and an enable signal.
In the electro-optical device 10, the data signals Vd (1), Vd (2), …, Vd (n) are supplied to the 1 st, 2 nd, … th and nth groups through the control circuit 5 according to the selection timing of the demultiplexer 30. The maximum value of the potential that can be obtained by the data signals Vd (1) to Vd (n) is Vmax, and the minimum value is Vmin.
The scanning line driving circuit 20 is a circuit that generates a scanning signal for sequentially scanning the scanning lines 12 line by line in the entire frame period based on the control signal Ctr. Here, the scanning signals supplied to the scanning lines 12 in the 1 st, 2 nd, 3 rd, … th, (m-1) th and m-th rows are represented as Gwr (1), Gwr (2), Gwr (3), …, Gwr (m-1) and Gwr (m), respectively.
In addition to the scanning signals Gwr (1) to Gwr (m), the scanning line driving circuit 20 generates various control signals in synchronization with the scanning signals for each row and supplies the control signals to the display unit 100, but they are not shown in fig. 2. The frame period is a period required for the electro-optical device 10 to display an image of 1 lens (segment), and is, for example, a period of 8.3 milliseconds of 1 cycle when the frequency of the vertical synchronization signal included in the synchronization signal is 120 Hz.
The demultiplexer 30 is an aggregate of transmission gates 34 arranged in columns, and sequentially supplies data signals to 3 columns constituting each group.
Here, the input terminals of the transfer gates 34 corresponding to the (3 j-2), (3 j-1), and (3j) columns belonging to the j-th group are commonly connected to each other, and the data signals vd (j) are supplied to the common terminals, respectively.
When the control signal Sel (1) is at the H level (when the control signal/Sel (1) is at the L level), the transmission gates 34 provided in the (3 j-2) column as the left-end column in the j-th group are turned on (on). Similarly, when the control signal Sel (2) is at the H level (when the control signal/Sel (2) is at the L level), the transfer gates 34 provided at the (3 j-1) column as the center column in the j-th group are turned on, and when the control signal Sel (3) is at the H level (when the control signal/Sel (3) is at the L level), the transfer gates 34 provided at the (3j) column as the right-end column in the j-th group are turned on.
The level shift circuit 40 includes a group of a holding capacitor 44, a P-channel MOS transistor 45, and an N-channel MOS transistor 46 for each column, and shifts the potential of the data signal output from the output terminal of the transfer gate 34 for each column. Here, one end of the holding capacitor 44 is connected to the data line 14 of the corresponding column and the drain node of the transistor 45, and the other end of the holding capacitor 44 is connected to the output end of the transmission gate 34 and the drain node of the transistor 46. Therefore, the storage capacitor 44 functions as the 1 st storage capacitor having one end connected to the data line 14. Note that, although not shown in fig. 2, the capacitance of the storage capacitor 44 is Crf 1.
The initial potential Vini is supplied to the source node of the transistor 45 in common to each column in each column, and the control signal/Gini is supplied to the gate node in common to each column. The potential Vref is supplied to the source node of the transistor 46 in each column in common, and the NOT circuit 18 supplies a signal obtained by logically inverting the control signal/Gini to the gate node in common in each column.
Therefore, in the present embodiment, the transistors 45 and 46 in each column are configured to be turned on at a time when the control signal/Gini is at the L level, and to be turned off at a time when the control signal/Gini is at the H level.
The holding capacitance 50 is provided for each data line 14. Specifically, one end of the holding capacitor 50 is connected to the data line 14, and the other end is grounded to the common potential Vss, for example, in each column. Therefore, the storage capacitor 50 functions as a 2 nd storage capacitor for storing the potential of the data line 14.
Note that although the storage capacitor 50 is provided outside the display unit 100 in fig. 2, this is merely an equivalent circuit, and may be provided inside the display unit 100 or may be provided from the inside to the outside. Note that, although omitted in fig. 2, the capacitance of the storage capacitor 50 is Cdt. The potential Vss corresponds to the L level of a scanning signal or a control signal which is a logic signal.
In this embodiment, the scanning line driving circuit 20, the demultiplexer 30, and the level shift circuit 40 are divided for convenience, but these can be collectively summarized as a driving circuit for driving the pixel circuit 110.
Referring to fig. 3, the pixel circuit 110 is explained. Since the pixel circuits 110 have the same configuration in electrical terms, the description will be given here by taking as an example the pixel circuit 110 in the i-th row (3 j-2) column of the (3 j-2) th column located at the left end column in the j-th group of the i-th row.
Here, i is a symbol generally indicating a row in which the pixel circuits 110 are arranged, and is an integer of 1 to m.
As shown in fig. 3, the pixel circuit 110 includes transistors 121, 122, 124 of a P-channel MOS type, an OLED130, and a holding capacitance 132.
The pixel circuit 110 is supplied with a scanning signal gwr (i) and a control signal gel (i). Here, the scanning signal gwr (i) and the control signal gel (i) are supplied through the scanning line driving circuit 20 in correspondence with the ith row. Therefore, in the ith row, the scanning signal gwr (i) and the control signal gel (i) are supplied in common to the pixel circuits in the columns other than the (3 j-2) column to be observed.
The gate node of the transistor 122 in the pixel circuit 110 in the i-row (3 j-2) -column is connected to the scanning line 12 in the i-th row, one of the drain or source nodes is connected to the data line 14 in the (3 j-2) -th column, and the other is connected to the gate node of the transistor 121 and one end of the holding capacitor 132. Here, the gate node of the transistor 121 is denoted by g for distinguishing from other nodes.
The source node of transistor 121 is connected to power supply line 116, and the drain node is connected to the source node of transistor 124. Here, the power supply line 116 is supplied with a potential Vel on the high-order side which becomes a power supply in the pixel circuit 110.
The gate node of the transistor 124 is supplied with a control signal gel (i) corresponding to the ith row, and the drain node is connected to the anode of the OLED 130.
Here, the transistor 121 corresponds to a 1 st transistor, the transistor 122 corresponds to a 2 nd transistor, and the transistor 124 corresponds to a 3 rd transistor.
The other end of the holding capacitor 132 is connected to the power supply line 116. Therefore, the storage capacitor 132 functions as a 3 rd storage capacitor for storing the source-drain voltage of the transistor 121. Here, when the capacitance of the storage capacitor 132 is denoted as Cpix, the capacitance Cdt of the storage capacitor 50, the capacitance Crf1 of the storage capacitor 44, and the capacitance Cpix of the storage capacitor 132 are Cdt > Crf1 > Cpix.
That is, Cdt is set to be larger than Crf1, and Cpix is set to be sufficiently smaller than Cdt and Crf 1.
As the storage capacitor 132, a capacitor parasitic on the gate node g of the transistor 121 or a capacitor formed by sandwiching an insulating layer between conductive layers different from each other in a silicon substrate may be used.
In the present embodiment, since the electro-optical device 10 is formed on a silicon substrate, the substrate potential of the transistors 121, 122, and 124 is the potential Vel.
The anode of the OLED130 is a pixel electrode provided independently for each pixel circuit 110. On the other hand, the cathode of the OLED130 is the common electrode 118 shared by all the pixel circuits 110, and is held at the potential Vct on the low-order side serving as the power supply in the pixel circuits 110.
The OLED130 is an element formed by sandwiching a white organic EL layer between an anode and a cathode having light transmittance in the silicon substrate. Then, a color filter corresponding to any of RGB is superimposed on the emission side (cathode side) of the OLED 130.
In the OLED130, when a current flows from the anode to the cathode, holes injected from the anode and electrons injected from the cathode are recombined in the organic EL layer to generate excitons, thereby generating white light. The white light generated at this time is transmitted through the cathode on the side opposite to the silicon substrate (anode), and is visually confirmed on the observer side by coloring with a color filter.
< operation of embodiment 1 >
The operation of the electro-optical device 10 will be described with reference to fig. 4. Fig. 4 is a timing chart for explaining the operation of each part in the electro-optical device 10. For convenience of explanation, the vertical scale indicating the voltage amplitude is not necessarily the same in the figure (the same applies to fig. 13 and 20 below).
As shown in the figure, the scanning signals Gwr (1) to Gwr (m) are sequentially switched to the L level, and the scanning lines 12 in the 1 st to mth rows are sequentially scanned every 1 horizontal scanning period (H) in a period of 1 frame.
The operation in 1 horizontal scanning period (H) is common to the pixel circuits 110 in each row. In view of this, the following description will focus on the pixel circuits 110 in the i row (3 j-2) column in the scanning period for horizontally scanning the i-th row.
In the present embodiment, the scanning period of the i-th row is roughly divided into an initialization period shown in fig. 4 (b) and a writing period shown in fig. 4 (d). After the writing period of (d), the light emission period shown in (a) is set at an interval, and after a period of 1 frame elapses, the scanning period of the i-th row is reached again. Therefore, the repetition of a period of (light-emitting period) → initialization period → writing period → (light-emitting period) is performed in chronological order.
In fig. 4, each of the scanning signal Gwr (i-1) and the control signal Gel (i-1) corresponding to the (i-1) th line of the first 1 th line of the ith line has a waveform that temporally precedes the scanning signal Gwr (i) and the control signal Gel (i) corresponding to the ith line by 1 horizontal scanning period (H).
< light emission period >
For convenience of explanation, the light emission period which is a precondition of the initialization period will be described. As shown in fig. 4, in the light-emitting period of the ith row, the scanning signal gwr (i) is at the H level, and the control signal gel (i) is at the L level.
Therefore, as shown in fig. 5, in the pixel circuit 110 of i row (3 j-2) column, the transistor 124 is turned on, and the transistor 122 is turned off. Therefore, the transistor 121 supplies the OLED130 with a current Ids corresponding to the voltage held by the holding capacitor 132, that is, the gate-source voltage Vgs. As described later, since the potential of the gate node g in the light-emitting period is a value obtained by level-shifting the data signal having the potential corresponding to the gradation level in accordance with the capacitance ratio of the holding capacitors 44 and 50, the voltage Vgs becomes a voltage corresponding to the gradation level. Accordingly, since the transistor 121 supplies a current corresponding to a gray scale, the OLED130 emits light with a luminance corresponding to the current.
Here, since the light emission period of the ith row is a period in which horizontal scanning is performed other than the ith row, the potential of the data line 14 appropriately varies. However, in the pixel circuit 110 in the ith row, since the transistor 122 is off, the potential variation of the data line 14 is not considered here.
In fig. 5, paths important for the operation description are indicated by thick lines (the same applies to fig. 6 to 9, 14 to 17, and 21 to 24 below).
< initialization period >
Next, when the scanning period of the i-th row is reached, the initialization period of (b) is first started. In the initialization period, the control signal gel (i) is at H level compared to the light emission period.
Therefore, as shown in fig. 6, in the pixel circuit 110 of i row (3 j-2) column, the transistor 124 is turned off. Thus, the OLED130 is in an off (non-light-emitting) state because the path of the current supplied to the OLED130 is cut off.
On the other hand, since the control signal/Gini becomes L level in the initialization period, the transistors 45 and 46 are turned on in the level shift circuit 40 as shown in fig. 6. Therefore, the data line 14 as one end of the holding capacitance 44 is initialized to the potential Vini, and the node h as the other end of the holding capacitance 44 is initialized to the potential Vref.
In the initialization period, the scanning signal gwr (i) is kept at the L level in a state where the control signal Gini is at the L level (1 st period). Therefore, as shown in fig. 7, in the pixel circuit 110 in i row (3 j-2), the transistor 122 is turned on, and therefore the gate node g is electrically connected to the data line 14. Therefore, since the gate node g also becomes the potential Vini, the holding voltage of the holding capacitor 132 is initialized from the voltage held during light emission to (Vel-Vini).
< writing period >
After the initialization period, the writing period of (d) is reached as the 2 nd period. In the write period, since the scanning signal/Gini is at the H level in a state where the scanning signal gwr (i) is at the L level, the transistors 45 and 46 are turned off in the level shift circuit 40.
Therefore, as shown in fig. 8, although the path from the data line 14 in the (3 j-2) th column to the gate node g in the pixel circuit 110 in the (3 j-2) row is in a floating state, the other end of the holding capacitor 50 is grounded to the potential Vss and the other end of the holding capacitor 132 is connected to the power feeding line 116, so that the potential Vini is maintained until the data signal is supplied by the conduction of the transfer gate 34.
The control circuit 5 outputs the following data signal in the writing period of the ith row. That is, if the group j is used, the control circuit 5 sequentially switches the data signal vd (j) to the potential corresponding to the gray scale of the pixel in the (3 j-2) column belonging to the left end column, the (3 j-1) column in the center column, and the (3j) column in the right end column of the i-th row. The control circuit 5 sequentially switches the potentials for the data signals to be output to the other groups as well.
On the other hand, the control circuit 5 exclusively sets the control signals Sel (1), Sel (2), Sel (3) to the H level in order in accordance with the switching of the potential of the data signal. Although not shown in fig. 4, the control circuit 5 also outputs control signals/Sel (1),/Sel (2), and/Sel (3) that are logically inverted with respect to the control signals Sel (1), Sel (2), and Sel (3). Thus, the demultiplexer 30 turns on the transfer gates 34 in each group in the order of the left end column, the center column, and the right end column.
Here, when the transfer gate 34 belonging to the left end column of the j-th group is turned on by the control signals Sel (1) and/Sel (1), the node h as the other end of the holding capacitance 44 changes from the potential Vref after initialization to the potential of the data signal vd (j), that is, the potential corresponding to the gradation of the pixel in the i row (3 j-2) column, as shown in fig. 9. The potential change amount of the node h at this time is represented by Δ V, and the potential after the change is represented by (Vref + Δ V).
On the other hand, since the gate node g is electrically connected to one end of the holding capacitor 44 via the data line 14, the potential Vini is shifted in the direction of change of the node h by a value obtained by multiplying the potential change amount Δ V of the node h by the capacitance ratio k 1.
The capacitance ratio k1 is Crf1/(Cdt + Crf 1). Strictly speaking, the capacitance Cpix of the holding capacitor 132 must be considered, but since the capacitance Cpix is set to be sufficiently small compared with the capacitances Crf1 and Cdt, it is ignored.
Fig. 10 is a diagram showing a relationship between the potential of the data signal and the potential of the gate node g in the writing period. As described above, the data signal supplied from the control circuit 5 can take a potential range from the minimum value Vmin to the maximum value Vmax according to the gradation of the pixel. In this embodiment, the data signal is not directly written to the gate node g, but is level-shifted as shown in the figure and then written to the gate node g.
At this time, the potential range Δ Vgate of the gate node g is compressed to a value obtained by multiplying the potential range Δ Vdata (Vmax-Vmin) of the data signal by the capacitance ratio k 1. For example, when Crf 1: cdt ═ 1: when the capacitances of the holding capacitances 44 and 50 are set in the mode of 9, the potential range Δ Vgate of the gate node g can be compressed to 1/10 of the potential range Δ Vdata of the data signal.
The potential Vini and Vref can be used to determine how much the potential range Δ Vgate of the gate node g is shifted in any direction with respect to the potential range Δ Vdata of the data signal. This is because the potential range Δ Vdata of the data signal is compressed by the capacitance ratio k1 with reference to the potential Vref, and a range shifted by the compression range with reference to the potential Vini becomes the potential range Δ Vgate of the gate node g.
In this way, in the writing period in the ith row, a potential obtained by level-shifting the data signal of the potential corresponding to the gradation in accordance with the capacitance ratio of the holding capacitances 44 and 50 is written into the gate node g of the pixel circuit 110 in the ith row.
After that, the scanning signal gwr (i) becomes H level, and the transistor 122 is turned off. Thus, the writing period ends, and the potential of the gate node g is determined to be a shifted value.
< light emission period >
After the writing period of the ith row is completed, the light-emitting period as the 3 rd period is reached at intervals. In this light emission period, since the control signal gel (i) is at the L level as described above, the transistor 124 is turned on in the pixel circuit 110 in the i row (3 j-2) column. Therefore, as shown in fig. 5, since the current Ids corresponding to the gate-source voltage Vgs is supplied to the OLED130 through the transistor 121, the OLED130 emits light with a luminance corresponding to the current.
Such an operation is also performed in parallel with time in the pixel circuit 110 in the ith row other than the pixel circuit 110 in the (3 j-2) th column concerned in the scanning period of the ith row. In practice, the operation of the ith line is performed in the order of the 1 st, 2 nd, 3 rd, … th, (m-1) th, and mth lines in the period of 1 frame, and is repeated for each frame.
Fig. 4 shows a point where the gate node g of the pixel circuit 110 in the i row (3 j-2) column is level-shifted from the potential Vini when the control signal Sel (1) is at the H level, and a point where the gate node g of the (i-1) row (3 j-2) column in the first 1 row in the same column as the i row (3 j-2) column is level-shifted from the potential Vini.
According to this embodiment, since the potential range Δ Vgate at the gate node g is narrowed with respect to the potential range Δ Vdata of the data signal, a voltage reflecting the gradation can be applied between the gate and the source of the transistor 121 without describing the data signal with high accuracy. Therefore, even in the case where a minute current flowing through the OLED130 in the minute pixel circuit 110 relatively largely changes with respect to the change in the gate-source voltage Vgs of the transistor 121, the current supplied to the OLED130 can be accurately controlled.
In addition, as shown by a dotted line in fig. 3, a capacitance Cprs is actually parasitic between the data line 14 and the gate node g in the pixel circuit 110. Therefore, if the potential variation range of the data line 14 is large, the potential propagates to the gate node g through the capacitor Cprs, so-called crosstalk, unevenness, and the like occur, and the display quality is lowered. The influence of the capacitor Cprs is conspicuously exhibited when the pixel circuit 110 is miniaturized.
In contrast, in the present embodiment, since the potential variation range of the data line 14 is also narrowed with respect to the potential range Δ Vdata of the data signal, the influence of the capacitor Cprs can be suppressed.
< embodiment 2 >
In embodiment 1, if the threshold voltage of the transistor 121 varies for each pixel circuit 110, display unevenness occurs which impairs the uniformity of the display screen. In view of this, embodiment 2 in which the variation in the threshold voltage of the transistor 121 is compensated for will be described below. In the following, in order to avoid redundancy of description, the description will be focused on a portion different from embodiment 1.
Fig. 11 is a diagram showing a configuration of the electro-optical device 10 according to embodiment 2.
The difference between the embodiment 2 shown in the figure and the embodiment 1 (see fig. 2) is that the embodiment 1: a power supply line 16 is provided, 2 nd: a part of the level shift circuit 40 is different, and 3 rd: the pixel circuit 110 differs in configuration and operation.
First, regarding the 1 st difference, the power supply lines 16 are provided along the data lines 14 in each column of the display unit 100. The potential Vorst is supplied in common to the power feed lines 16. The other end of the holding capacitor 50 of each column is connected to the power supply line 16 of the corresponding column.
Regarding the difference of point 2, the transistor 46 (see fig. 2) in embodiment 1 is replaced with the transistor 43 in fig. 11. The control circuit 5 commonly supplies a control signal Gref to the gates of the transistors 43 in each column.
The difference in the 3 rd point will be described with reference to fig. 12. Fig. 12 is a diagram showing a configuration of a pixel circuit 110 of the electro-optical device 10 according to embodiment 2. The pixel circuit 110 shown in the figure is different from the circuit configuration shown in fig. 4 in that P- channel MOS transistors 123 and 125 are added.
A control signal gcmp (i) corresponding to the ith row is supplied to the gate node of the transistor 123, and the source node thereof is connected to the drain node of the transistor 121. In addition, the drain node of the transistor 123 is connected to the gate node g of the transistor 121.
On the other hand, the gate node of the transistor 125 is supplied with a control signal gorst (i) corresponding to the ith row, and the source node thereof is connected to the anode of the OLED 130. In addition, the drain node of the transistor 125 is connected to the power supply line 16 of the corresponding column.
The substrate potential of the transistors 123 and 125 is also set to the potential Vel in the same manner as the transistors 121, 122, and 14.
< operation of embodiment 2 >
The operation of the electro-optical device 10 according to embodiment 2 will be described with reference to fig. 13. Fig. 13 is a timing chart for explaining the operation in embodiment 2.
As shown in the figure, the following points are the same as those of embodiment 1: the scanning signals Gwr (1) to Gwr (m) are sequentially switched to the L level, and the scanning lines 12 in the 1 st to mth rows are sequentially scanned every 1 horizontal scanning period (H) in a period of 1 frame. However, in embodiment 2, the scanning period of the i-th row is compared with embodiment 1 in that the compensation period shown in (c) is inserted between the initialization period shown in (b) and the writing period shown in (d). Therefore, in embodiment 2, if the time sequence is such that the period is repeated, the period is (light emission period) → initialization period → compensation period → writing period → (light emission period).
< light emission period >
In embodiment 2, as shown in fig. 13, the scanning signal gwr (i) is at the H level in the light emission period of the i-th row. Among the logic signals, the control signals gel (i), gcmp (i), and gorst (i) are at the L level, and the control signals gcmp (i) and gorst (i) are at the H level.
Therefore, as shown in fig. 14, in the pixel circuit 110 of i row (3 j-2) column, the transistor 124 is turned on, and the transistors 122, 123, 125 are turned off. Accordingly, the transistor 121 supplies a current Ids corresponding to the gate-source voltage Vgs to the OLED 130.
As described later, in embodiment 2, the voltage Vgs in the light emission period is a value level-shifted from the threshold voltage of the transistor 121 in accordance with the potential of the data signal. Accordingly, a current corresponding to a gray scale is supplied to the OLED130 in a state where the threshold voltage of the transistor 121 is compensated.
< initialization period >
When the scanning period of the ith row is reached, the initialization period of (a) is first started. In the initialization period, the control signal gel (i) changes to the H level and the control signal gorst (i) changes to the L level, compared to the light emission period.
Therefore, as shown in fig. 15, in the pixel circuit 110 of i row (3 j-2) column, the transistor 124 is turned off, and the transistor 125 is turned on. Thereby, the path of the current supplied to the OLED130 is cut off, and the anode of the OLED130 is reset to the potential Vorst.
As described above, since the OLED130 is configured such that the organic EL layer is sandwiched between the anode and the cathode, a capacitance Coled is actually parasitic in parallel between the anode and the cathode as shown by a dotted line in the figure. When a current flows through the OLED130 during light emission, a voltage across the anode and the cathode of the OLED130 is held by the capacitor Coled, but the held voltage is reset by the conduction of the transistor 125. Therefore, in embodiment 2, when a current flows through the OLED130 again in the following light emission period, the voltage held by the capacitor Coled is less likely to be affected.
Specifically, for example, when the display state is changed from the high-luminance display state to the low-luminance display state, if the configuration is not reset, since the high voltage at the time of high luminance (large current flows) is maintained, an excessive current flows even if a small current is to be flown next, and the display state with low luminance cannot be achieved. In contrast, in embodiment 2, the potential of the anode of the OLED130 is reset by turning on the transistor 125, and therefore, the reproducibility on the low luminance side can be improved.
In embodiment 2, the potential Vorst is set such that the difference between the potential Vorst and the potential Vct of the common electrode 118 is lower than the emission threshold voltage of the OLED 130. Therefore, in the initialization period (the compensation period and the writing period to be described later), the OLED130 is in an off (non-light-emitting) state.
On the other hand, in the initialization period, since the control signal/Gini becomes L level and the control signal Gref becomes H level, the transistors 45 and 43 are turned on in the level shift circuit 40 as shown in fig. 15. Therefore, the data line 14 as one end of the holding capacitance 44 is initialized to the potential Vini, and the node h as the other end of the holding capacitance 44 is initialized to the potential Vref.
In embodiment 2, the potential Vini is set to (Vel-Vini) larger than the threshold voltage | Vth | of the transistor 121. Here, since the transistor 121 is of a P-channel type, the threshold voltage Vth with reference to the potential of the source node is negative. In order to prevent the description of the high-low relationship from being confused, the threshold voltage is expressed by | Vth | of an absolute value, and the threshold voltage is defined in a magnitude relationship.
In embodiment 2, the potential Vref is set to a value that can be obtained with respect to the data signals Vd (1) to Vd (n), which is lower than the lowest value Vmin, for example, at which the potential of the node h changes in an increasing manner in the subsequent writing period.
< period of Compensation >
The scanning period of the i-th row is followed by the compensation period of (c). In the compensation period, the scanning signal gwr (i) and the control signal gcmp (i) are at L level compared to the initialization period. On the other hand, in the compensation period, the control signal/Gini becomes H level in a state where the control signal Gref is maintained at H level.
Therefore, as shown in fig. 16, in the level shift circuit 40, the node h is fixed to the potential Vref by turning off the transistor 45 in a state where the transistor 43 is turned on. On the other hand, in the pixel circuits 110 in i rows (3 j-2) and columns, the gate node g is electrically connected to the data line 14 by turning on the transistor 122, and therefore the gate node g becomes the potential Vini at the beginning of the compensation period.
Since the transistor 123 is turned on during compensation, the transistor 121 becomes diode-connected. Therefore, a drain current flows through the transistor 121, and the gate node g and the data line 14 are charged. Specifically, a current flows through a path of the power supply line 116 → the transistor 121 → the transistor 123 → the data line 14 in the column 122 → (3 j-2) of the transistor. Therefore, the data line 14 and the gate node g which are connected to each other by the transistor 121 being turned on rise from the potential Vini.
However, since the current flowing through the path becomes difficult to flow as the gate node g approaches the potential (Vel- | Vth |), the data line 14 and the gate node g are saturated with the potential (Vel- | Vth |) until the end of the compensation period. Therefore, the holding capacitance 132 holds the threshold voltage | Vth | of the transistor 121 until the end of the compensation period.
< writing period >
When the compensation period is completed, the control signal gcmp (i) becomes H level, so that the diode connection of the transistor 121 is released, and the control signal Gref becomes L level, so that the transistor 43 is turned off. Therefore, although the path from the data line 14 in the (3 j-2) th column to the gate node g in the pixel circuit 110 in the (3 j-2) i row and the (3 j-2) column is in a floating state, the potential in the path is maintained at (Vel- | Vth |) by the holding capacitances 50 and 132.
In the writing period of the ith row, if the group is jth, the control circuit 5 sequentially switches the data signal vd (j) to potentials corresponding to the gray scales of the pixels in the ith row (3 j-2), ith row (3 j-1), and ith row (3 j). On the other hand, the control circuit 5 sequentially and exclusively sets the control signals Sel (1), Sel (2), Sel (3) to the H level in accordance with the switching of the potential of the data signal. Although not shown in fig. 13, the control circuit 5 also outputs control signals/Sel (1), (2), and/Sel (3) in a logically inverted relationship with the control signals Sel (1), (2), and Sel (3). Thus, the demultiplexer 30 turns on the transfer gates 34 in each group in the order of the left end column, the center column, and the right end column.
Here, when the transfer gate 34 of the left-end column is turned on based on the control signals Sel (1) and Sel (1), the node h as the other end of the holding capacitance 44 changes from the potential Vref in the compensation period to the potential of the data signal vd (j), that is, the potential (Vref + Δ V) corresponding to the gradation level of the pixel in the i row (3 j-2) as shown in fig. 17.
On the other hand, since the gate node g is connected to one end of the holding capacitor 44 via the data line 14, the potential in the compensation period (Vel- | Vth |) is shifted in the rising direction by a value obtained by multiplying the potential change amount Δ V to the node h by the capacitance ratio k 1.
Therefore, the potential of the gate node g is shifted in the rising direction from the potential (Vel- | Vth |) in the compensation period by a value obtained by multiplying the potential change amount Δ V for the node h by the capacitance ratio k1 (Vel- | Vth | + k1 · Δ V). At this time, when the voltage Vgs of the transistor 121 is expressed as an absolute value, the voltage becomes a value (| Vth | -k 1 · Δ V) obtained by subtracting the shift amount of the potential increase of the gate node g from the threshold voltage | Vth |.
< light emission period >
In embodiment 2, after the writing period of the ith row is completed, the light-emitting period is reached at intervals of 1 horizontal scanning period. In this light-emission period, as described above, since the control signal gel (i) is at the L level, the transistor 124 is turned on in the pixel circuit 110 in the i row (3 j-2) column. Since the gate-source voltage Vgs is (| Vth | -k 1 · Δ V), the OLED130 is supplied with a current corresponding to the gray scale while compensating the threshold voltage of the transistor 121, as shown in fig. 14.
Such an operation is also performed in parallel with time in the pixel circuits 110 in the ith row other than the pixel circuit 110 in the (3 j-2) th column in the scanning period of the ith row. In practice, the operation of the ith line is executed in the order of the 1 st, 2 nd, 3 rd, … th, (m-1) th, and mth lines in a period of 1 frame, and is repeated for each frame.
According to embodiment 2, as in embodiment 1, since the potential range Δ Vgate of the gate node g is narrowed with respect to the potential range Δ Vdata of the data signal, a voltage reflecting the gradation can be applied between the gate and the source of the transistor 121 without accurately describing the data signal. Therefore, even in the case where a minute current flowing through the OLED130 in the minute pixel circuit 110 relatively largely changes with respect to the gate-source voltage Vgs of the transistor 121, the current supplied to the OLED130 can be accurately controlled.
Further, according to embodiment 2, since a period longer than the scanning period, for example, 2 horizontal scanning periods in embodiment 2 can be secured as a period for turning on the transistor 125, that is, a reset period of the OLED130, it is possible to sufficiently initialize the voltage held by the parasitic capacitance of the OLED130 during the light emission period.
In addition, according to embodiment 2, the current Ids supplied to the OLED130 through the transistor 121 may cancel the influence of the threshold voltage. Therefore, according to embodiment 2, even if the threshold voltage of the transistor 121 varies for each pixel circuit 110, the variation is compensated for, and a current corresponding to the gray scale is supplied to the OLED130, so that it is possible to suppress the occurrence of display unevenness that impairs the uniformity of the display screen, and as a result, it is possible to perform high-quality display.
This cancellation will be described with reference to fig. 18. As shown in the figure, the transistor 121 operates in a weak inversion region (sub-threshold region) to control a minute current supplied to the OLED 130.
In the figure, a denotes a transistor having a large threshold voltage | Vth |, and B denotes a transistor having a small threshold voltage | Vth |. In fig. 18, the gate-source voltage Vgs is the difference between the characteristic indicated by the solid line and the potential Vel. In fig. 18, the current on the vertical scale is represented by the positive (upper) logarithm in the direction from the source to the drain.
During the compensation period, the gate node g changes from the potential Vini to the potential (Vel- | Vth |). Therefore, the operating point of the transistor a having a large threshold voltage | Vth | moves from S to Aa, and the operating point of the transistor B having a small threshold voltage | Vth | moves from S to Ba.
Next, when the potentials of the data signals input to the pixel circuits 110 to which the 2 transistors belong are the same, that is, when the same gray scale is specified, the amounts of potential shift from the operating points Aa and Ba in the writing period are the same k1 · Δ V. Therefore, the operating point of the transistor a moves from Aa to Ab, and the operating point of the transistor B moves from Ba to Bb, and the transistors A, B are aligned with the same Ids for the current at the operating point after the potential shift.
< embodiment 3 >
In embodiment 2, the demultiplexer 30 directly supplies a data signal to the other end of the holding capacitor 44 of each column, that is, the node h. Therefore, in the scanning period of each row, since the period in which the data signal is supplied from the control circuit 5 is equal to the writing period, the time restriction is large.
In view of this, embodiment 3 capable of alleviating such temporal constraints will be described below. In the following, in order to avoid redundancy of description, the description will be focused on the differences from embodiment 2.
Fig. 19 is a diagram showing a configuration of the electro-optical device 10 according to embodiment 3.
The 3 rd embodiment shown in the figure is different from the 2 nd embodiment shown in fig. 11 mainly in that: a holding capacitor 41 and a transmission gate 42 are provided in each column of the level shift circuit 40.
In detail, in each column, the transfer gate 42 is electrically sandwiched between the output terminal of the transfer gate 34 and the other end of the holding capacitor 44. That is, the input terminal of the transmission gate 42 is connected to the output terminal of the transmission gate 34, and the output terminal of the transmission gate 42 is connected to the other terminal of the holding capacitor 44.
When the control signal Gcpl supplied from the control circuit 5 is at the H level (when the control signal Gcpl is at the L level), the transfer gates 42 of the respective columns are turned on at the same time.
In each column, one end of the holding capacitor 41 is connected to the output terminal of the transfer gate 34 (input terminal of the transfer gate 42), and the other end of the holding capacitor 41 is commonly grounded to a fixed potential, for example, Vss. Although not shown in fig. 19, the capacitance of the storage capacitor 41 is Crf 2.
< operation of embodiment 3 >
The operation of the electro-optical device 10 according to embodiment 3 will be described with reference to fig. 20. Fig. 20 is a timing chart for explaining the operation in embodiment 3.
As shown in the drawing, the scanning signals Gwr (1) to Gwr (m) are sequentially switched to the L level, and the scanning lines 12 in the 1 st to mth rows are sequentially scanned every 1 horizontal scanning period (H) in a period of 1 frame, which is the same as that in embodiment 2. In embodiment 3, the scanning period of the i-th row is the same as that of embodiment 2 in the order of the initialization period shown in (b), the compensation period shown in (c), and the writing period shown in (d). In embodiment 3, the writing period (d) is a period from when the control signal Gcpl changes from L to H level (when the control signal/Gcpl changes to L level) to when the scan signal changes from L to H level.
In embodiment 3, as in embodiment 2, a period of (light-emitting period) → initialization period → compensation period → writing period → (light-emitting period) repeats in chronological order. However, in embodiment 3, the supply period of the data signal is not equal to the write period, but is different from embodiment 2 in that the supply period of the data signal precedes the write period. Specifically, embodiment 3 is different from embodiment 2 in that the data signal can be supplied over the initialization period of (a) and the compensation period of (b).
< light emission period >
In embodiment 3, as shown in fig. 20, the scanning signal gwr (i) is at the H level, the control signal gel (i) is at the L level, and the control signals gcmp (i) and gorst (i) are at the H level in the light emission period of the i-th row.
Therefore, as shown in fig. 21, in the pixel circuit 110 in i row (3 j-2) column, the transistor 124 is turned on, and the transistors 122, 123, and 125 are turned off, so that the operation in the pixel circuit 110 is basically the same as that in embodiment 2. That is, the transistor 121 supplies a current Ids corresponding to the gate-source voltage Vgs to the OLED 130.
< initialization period >
When the scanning period of the ith row is reached, the initialization period of (b) is first started.
In embodiment 3, in the initialization period, the control signal gel (i) is changed to the H level and the control signal gorst (i) is changed to the L level, compared to the light emission period.
Therefore, as shown in fig. 22, in the pixel circuit 110 in the i row (3 j-2) column, the transistor 124 is turned off and the transistor 125 is turned on. Thus, the path of the current supplied to the OLED130 is cut off, and the anode of the OLED130 is reset to the potential Vorst by turning on the transistor 124, so that the operation of the pixel circuit 110 is basically the same as that of embodiment 2.
On the other hand, in embodiment 3, during the initialization period, the control signal/Gini becomes L level, the control signal Gref becomes H level, and the control signal Gcpl becomes L level. Therefore, as shown in fig. 22, in the level shift circuit 40, the transistors 45, 43 are turned on, respectively, and the transmission gate 42 is turned off. Therefore, the data line 14 as one end of the holding capacitance 44 is initialized to the potential Vini, and the node h as the other end of the holding capacitance 44 is initialized to the potential Vref.
In embodiment 3, as in embodiment 2, the potential Vref is set to a value such that the potential at the node h changes in an increasing manner with respect to the potential that can be obtained by the data signals Vd (1) to Vd (n) in the subsequent writing period.
As described above, in embodiment 3, the control circuit 5 supplies the data signal throughout the initialization period and the compensation period. That is, if the j-th group is used, the control circuit 5 sequentially switches the data signal vd (j) to the potential corresponding to the gray scale of the pixels in the i row (3 j-2), i row (3 j-1), and i row (3j), and sequentially and exclusively sets the control signals Sel (1), Sel (2), and Sel (3) to the H level in accordance with the switching of the potential of the data signal. Thus, the demultiplexer 30 turns on the transfer gates 34 in each group in the order of the left end column, the center column, and the right end column.
Here, in the initialization period, when the transfer gate 34 belonging to the left end column of the j-th group is turned on based on the control signal Sel (1), as shown in fig. 22, the data signal vd (j) is supplied to one end of the holding capacitor 41, and thus the data signal is held by the holding capacitor 41.
< period of Compensation >
The scanning period of the i-th row is followed by the compensation period of (c). In embodiment 3, in the compensation period, the scanning signal gwr (i) changes to the L level and the control signal gcmp (i) changes to the L level, as compared with the initialization period.
Therefore, as shown in fig. 23, in the pixel circuit 110 in the i row (3 j-2) column, the transistor 122 is turned on, the gate node g is electrically connected to the data line 14, and the transistor 121 is diode-connected by the on state of the transistor 123.
Therefore, since a current flows through a path of the power supply line 116 → the transistor 121 → the transistor 123 → the transistor 122 → the data line 14 of the (3 j-2) th column, the gate node g rises from the potential Vini and is saturated with (Vel- | Vth |) in the near future. Therefore, in embodiment 3, the storage capacitor 132 also holds the threshold voltage | Vth | of the transistor 121 until the compensation period ends.
In embodiment 3, since the state control signal/Gini that maintains the H level with the control signal Gref becomes the H level in the compensation period, the node H is fixed to the potential Vref in the level shift circuit 40.
In addition, when the transfer gate 34 belonging to the left end column of the j-th group is turned on in the compensation period based on the control signal Sel (1), the data signal vd (j) is held by the holding capacitor 41 as shown in fig. 23.
Further, when the transfer gate 34 belonging to the left end column of the j-th group has been turned on based on the control signal Sel (1) during the initialization, the transfer gate 34 is not turned on during the compensation, but the point at which the holding capacitance 41 holds the data signal vd (j) is not changed.
When the compensation period is completed, the control signal gcmp (i) becomes H level, and therefore the diode connection of the transistor 121 is released.
In embodiment 3, the control signal Gref becomes L level after the compensation period ends until the next write period starts, and therefore the transistor 43 is turned off. Therefore, although the path from the data line 14 in the (3 j-2) th column to the gate node g in the pixel circuit 110 in the (3 j-2) i row and the (3 j-2) column is in a floating state, the potential of the path is maintained at (Vel- | Vth |) by the holding capacitances 50 and 132.
< writing period >
In embodiment 3, the control signal Gcpl becomes H level (control signal/Gcpl becomes L level) during the write period. Therefore, as shown in fig. 24, since the transmission gate 42 is turned on in the level shift circuit 40, the data signal held in the holding capacitor 41 is supplied to the node h which is the other end of the holding capacitor 44. Therefore, the node h changes from the potential Vref in the compensation period to the potential (Vref + Δ V).
On the other hand, since the gate node g is connected to one end of the holding capacitor 44 via the data line 14, the potential in the compensation period (Vel- | Vth |) is shifted in the rising direction by a value obtained by multiplying the potential change amount Δ V to the node h by the capacitance ratio k 2. That is, the potential of the gate node g is shifted in the rising direction from the potential (Vel- | Vth |) in the compensation period by a value obtained by multiplying the potential change amount Δ V for the node h by the capacitance ratio k2 (Vel- | Vth | + k2 · Δ V).
The capacitance ratio k2 is the capacitance ratio of Cdt, Crf1, and Crf 2. As described above, the capacitance Cpix of the holding capacitance 132 is ignored.
In embodiment 3, the potential Vref is set to be lower than a potential that can be obtained with respect to, for example, the data signals Vd (1) to Vd (n), for example, than a value at which the potential of the node h changes in an increasing manner in the subsequent writing period, for example, the lowest value Vmin.
At this time, when the voltage Vgs of the transistor 121 is expressed as an absolute value, the voltage is obtained by subtracting the shift amount of the potential increase of the gate node g from the threshold voltage | Vth | -k 2 · Δ V (| Vth | -k 2 · Δ V).
< light emission period >
In embodiment 3, after the writing period for the ith row ends, the light-emitting period is reached at intervals of 1 horizontal scanning period. In this light emission period, since the control signal gel (i) is at the L level as described above, the transistor 124 is turned on in the pixel circuit 110 in the i row (3 j-2) column.
The gate-source voltage Vgs is (| Vth | -k 2 · Δ V), and is a value level-shifted from the threshold voltage of the transistor 121 in accordance with the potential of the data signal. Therefore, as shown in fig. 21, a current corresponding to the gray scale is supplied to the OLED130 while the threshold voltage of the transistor 121 is compensated.
Such an operation is also performed in parallel with time in the pixel circuits 110 in the ith row other than the pixel circuit 110 in the (3 j-2) th column in the scanning period of the ith row. Such an operation of the ith line is actually executed in the order of the 1 st, 2 nd, 3 rd, … th, (m-1) th, and mth lines during 1 frame, and is repeated for each frame.
According to embodiment 3, as in embodiments 1 and 2, even when a minute current flowing through the OLED130 in the minute pixel circuit 110 changes greatly with respect to the voltage Vgs between the gate and the source of the transistor 121, the current supplied to the OLED130 can be controlled accurately.
According to embodiment 3, in addition to sufficiently initializing the voltage held by the parasitic capacitance of the OLED130 during the light emission period as in embodiment 2, even if the threshold voltage of the transistor 121 varies for each pixel circuit 110, the occurrence of display unevenness that impairs the uniformity of the display screen can be suppressed, and as a result, high-quality display can be performed.
According to embodiment 3, the operation of holding the data signal supplied from the control circuit 5 via the demultiplexer 30 by the holding capacitor 41 is performed from the initialization period to the compensation period. Therefore, temporal constraints can be relaxed for the operations to be executed during 1 horizontal scanning period.
For example, in the compensation period, as the gate-source voltage Vgs approaches the threshold voltage, the current flowing through the transistor 121 decreases, and therefore it takes time to converge the gate node g to the potential (Vel- | Vth |), but in embodiment 3, the compensation period can be secured longer than in embodiment 2, as shown in fig. 20. Therefore, according to embodiment 3, the deviation of the threshold voltage of the transistor 121 can be accurately compensated compared to embodiment 2.
In addition, the data signal supply operation can be slowed down.
< application/modification example >
The present invention is not limited to the above-described embodiments, application examples, and other embodiments, and various modifications can be made as described below. In addition, one or more arbitrarily selected modifications can be combined as appropriate with the following modifications.
< control Circuit >
In the embodiment, the control circuit 5 for supplying the data signal is provided separately from the electro-optical device 10, but the control circuit 5 may be integrated with the scanning line driving circuit 20, the demultiplexer 30, and the level shift circuit 40 on the silicon substrate.
< substrate >
In the embodiment, the electro-optical device 10 is integrated on a silicon substrate, but may be integrated on another semiconductor substrate. Alternatively, the polycrystalline silicon process may be applied to form the polycrystalline silicon layer on a glass substrate or the like. In short, it is effective to miniaturize the pixel circuit 110, and to configure the transistor 121 so that the drain current significantly changes exponentially with respect to the change in the gate voltage Vgs.
< demultiplexer >
In the embodiment and the like, the data lines 14 are grouped in 3 columns, and the data lines 14 are sequentially selected in each group to supply the data signal, but the number of data lines constituting a group may be "2" or "4" or more.
Further, the data signals may be supplied to the data lines 14 of each column at once in a line order without grouping, that is, without using the demultiplexer 30. In embodiment 1, when the data lines 14 of the respective columns are supplied with data signals in line order at once without using the demultiplexer 30, the node h as the other end of the holding capacitor 44 is connected to the output terminal of the data signal output circuit (control circuit 5). When the output resistance of the data signal output circuit is low, since the node h becomes the ground level during a period in which the data signal is not output, this can be used as the initial potential.
< channel type of transistor >
In the above-described embodiments and the like, the transistors 121 to 125 in the pixel circuit 110 are unified into a P-channel type, but may be unified into an N-channel type. In addition, P channel type and N channel type may be appropriately combined.
< others >
In the embodiments and the like, the OLED as the Light Emitting element is exemplified as the electro-optical element, but any element may be used as long as it emits Light with a luminance corresponding to a current, such as an inorganic Light Emitting Diode or an LED (Light Emitting Diode).
< electronic apparatus >
Next, an electronic apparatus to which the electro-optical device 10 according to the embodiment and the like or the application example is applied will be described. The electro-optical device 10 is suitable for use in a small-sized and high-definition display. In view of this, a head-mounted display will be described as an example of the electronic apparatus.
Fig. 25 is a diagram showing an external appearance of the head-mounted display, and fig. 26 is a diagram showing an optical configuration thereof.
First, as shown in fig. 25, the head-mounted display 300 has arms 310, a nose piece 320, and lenses 301L and 301R, similar in appearance to general eyeglasses. As shown in fig. 26, the head-mounted display 300 includes the left-eye electro-optical device 10L and the right-eye electro-optical device 10R on the back side (lower side in the drawing) of the lenses 301L and 301R near the nose bridge 320.
In fig. 26, the image display surface of the electro-optical device 10L is disposed to the left. Thereby, the display image of the electro-optical device 10L is emitted in the 9 o' clock direction in the figure via the optical lens 302L. The half mirror 303L reflects the display image of the electro-optical device 10L in the 6 o 'clock direction, and transmits light incident from the 12 o' clock direction.
The image display surface of the electro-optical device 10R is disposed on the right side opposite to the electro-optical device 10L. Thereby, the display image of the electro-optical device 10R is emitted in the 3 o' clock direction in the figure via the optical lens 302R. The half mirror 303R reflects the display image of the electro-optical device 10R in the 6 o 'clock direction, and transmits light incident from the 12 o' clock direction.
In this configuration, the wearer of the head-mounted display 300 can observe the display images of the electro- optical devices 10L and 10R in a see-through state overlapping the appearance of the outside.
In the head-mounted display 300, when the left-eye image and the right-eye image are displayed on the electro-optical device 10L and the right-eye image, respectively, out of the binocular images with parallax, the wearer can feel as if the displayed images have a sense of depth and a three-dimensional effect (3D display).
In addition to the head-mounted display 300, the electro-optical device 10 can be applied to an electronic viewfinder in a video camera, a lens-interchangeable digital camera, or the like.
Description of the symbols: 10 … electro-optical device, 12 … scan line, 14 … data line, 20 … scan line driving circuit, 30 … demultiplexer, 40 … level shift circuit, 41, 44, 50 … holding capacitance, 100 … display unit, 110 … pixel circuit, 116 … power supply line, 118 … common electrode, 121 to 125 … transistor, 130 … OLED, 132 … holding capacitance, 300 … head mounted display.

Claims (7)

1. An electro-optical device comprising:
a 1 st capacitor having a 1 st electrode and a 2 nd electrode;
a control circuit for supplying a data signal to the 1 st electrode of the 1 st capacitor;
a 1 st wiring electrically connected to the 2 nd electrode of the 1 st capacitor;
a 2 nd wiring to which a fixed potential is supplied;
a 2 nd capacitor in which a 3 rd electrode is electrically connected to the 1 st wiring and a 4 th electrode is electrically connected to the 2 nd wiring; and
a pixel circuit electrically connected to the 1 st wiring and including a pixel capacitor for holding a 1 st potential corresponding to the data signal,
the 1 st potential is a potential corresponding to the data signal, the 1 st capacitance, and the 2 nd capacitance,
the 2 nd wiring is provided along the 1 st wiring in each column of the electro-optical device, and the pixel circuit is electrically connected to the 1 st wiring and the 2 nd wiring, respectively.
2. The electro-optical device of claim 1,
the pixel circuit has:
a light emitting element;
a 1 st transistor which controls a current supplied to the light emitting element when the transistor is electrically connected to the light emitting element; and
a 2 nd transistor connected between the 1 st wiring and a gate of the 1 st transistor, and turned on or off;
the pixel capacitor is electrically connected with the gate of the 1 st transistor,
the pixel circuit includes a 3 rd transistor, and the 3 rd transistor is connected between the 1 st transistor and the light emitting element and turned on or off.
3. The electro-optical device of claim 2,
the pixel circuit includes a 4 th transistor, and the 4 th transistor is connected between the 2 nd wiring and the light-emitting element and turned on or off.
4. An electro-optical device comprising:
a 1 st capacitor having a 1 st electrode and a 2 nd electrode;
a control circuit for supplying a data signal;
a 1 st wiring electrically connected to the 2 nd electrode of the 1 st capacitor;
a 2 nd wiring to which a fixed potential is supplied;
a 2 nd capacitor in which a 3 rd electrode is electrically connected to the 1 st wiring and a 4 th electrode is electrically connected to the 2 nd wiring;
a pixel circuit electrically connected to the 1 st wiring and including a pixel capacitor for holding a 1 st potential corresponding to the data signal;
a 3 rd capacitor for holding a 2 nd potential supplied in accordance with the data signal; and
a switch connected between the 1 st electrode of the 1 st capacitor and a 3 rd capacitor,
the 1 st potential is a potential corresponding to the 2 nd potential, the 1 st capacitance, the 2 nd capacitance, and the 3 rd capacitance,
the 2 nd wiring is provided along the 1 st wiring in each column of the electro-optical device, and the pixel circuit is electrically connected to the 1 st wiring and the 2 nd wiring, respectively.
5. Electro-optical device as claimed in claim 4,
the pixel circuit has:
a light emitting element;
a 1 st transistor which controls a current supplied to the light emitting element when the transistor is electrically connected to the light emitting element; and
a 2 nd transistor connected between the 1 st wiring and a gate of the 1 st transistor and turned on or off,
the pixel capacitor is electrically connected with the gate of the 1 st transistor,
the pixel circuit includes a 3 rd transistor, and the 3 rd transistor is connected between the 1 st transistor and the light emitting element and turned on or off.
6. The electro-optical device of claim 5,
the pixel circuit includes a 4 th transistor, and the 4 th transistor is connected between the 2 nd wiring and the light-emitting element and turned on or off.
7. An electronic device, characterized in that,
an electro-optical device according to any one of claims 1 to 6.
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US11087683B2 (en) 2021-08-10
US20130093737A1 (en) 2013-04-18
CN103065581B (en) 2017-05-10
JP2013088611A (en) 2013-05-13
CN107248395B (en) 2019-10-01

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