JP2013088638A - Electro-optical device and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accurately control luminance of an electro-optical element without the need of a data signal with high accuracy.SOLUTION: An electro-optical device includes: pixel circuits 110 provided corresponding to intersections between a plurality of scan lines 12 and a plurality of data lines 14; storage capacitors 44 of which one ends are connected to the plurality of data lines 14; storage capacitors 50 individually holding each potential of the data lines 14; transistors 45 which are turned ON/OFF among the data lines 14 and a power feeding line 61 for power feeding an initial potential; and transistors 46 which are turned ON/OFF among other ends of the storage capacitors 44 and a power feeding line 62 for power feeding a predetermined potential. The transistors 45 and 46 have conductivity types different from each other. Each pixel circuit 110 includes: a circuit for holding each potential of the data lines 14 in response to each scan signal supplied to the scan lines 12; and an electro-optical element having luminance in response to the potential held. After the transistors 45 and 46 are switched from ON to OFF, a data signal of a potential in response to gradation is supplied to each other end of the storage capacitors 44.

Description

  The present invention relates to an electro-optical device and an electronic apparatus that are effective when a pixel circuit is miniaturized, for example.

In recent years, various electro-optical devices using electro-optical elements such as organic light emitting diode elements (hereinafter referred to as “OLED”) have been proposed. In this electro-optical device, a configuration in which a pixel circuit including the electro-optical element is provided corresponding to a pixel of an image to be displayed is common. In such a configuration, when a data signal having a potential corresponding to the gray level of the pixel is supplied to the data line, the potential of the data line is changed according to the scanning signal supplied to the scanning line in the pixel circuit. The electro-optical element is held and has a luminance corresponding to the holding potential (see, for example, Patent Document 1).
On the other hand, electro-optical devices are often required to have a smaller display size and higher display definition. In order to achieve both a reduction in display size and a higher definition of display, it is necessary to miniaturize the pixel circuit. Therefore, a technique for integrating an electro-optical device in, for example, a silicon integrated circuit has been proposed (for example, a patent) Reference 2).

JP 2007-316462 A JP 2009-288435 A

By the way, when the pixel circuit is fine, the luminance of the pixel circuit may greatly change with a slight voltage change of the data line. In this case, it is necessary to supply the potential of the data signal supplied to the data line with very fine accuracy.
On the other hand, a circuit that outputs a data signal has a high driving capability in order to charge the data line in a short time. In a circuit having such a high driving capability, it is difficult to output a data signal with very fine accuracy.
The present invention has been made in view of the above-described circumstances, and one of its purposes is an electro-optical device that does not require a finely-accurate data signal and can accurately control the luminance of the electro-optical element. It is to provide an apparatus and an electronic device.

In order to achieve the above object, the electro-optical device according to the present invention is provided corresponding to a plurality of scanning lines, a plurality of data lines, and an intersection of the plurality of scanning lines and the plurality of data lines. A pixel circuit including a circuit for holding the potential of the data line in accordance with a scanning signal supplied to the scanning line, an electro-optical element having a luminance corresponding to the holding potential, and one end of the data line A first storage capacitor electrically connected to the line, a second storage capacitor that stores the potential of each of the plurality of data lines, and a first power supply line that supplies the initial potential to the data line. A first switch that is turned on or off; and a second switch that is turned on or off between the other end of the first storage capacitor and a second feeder that feeds a predetermined potential. The second switches have different conductivity types. A lunge star, the first switch and the second switch is on after turned from ON to OFF, the data signal potential corresponding to the gradation to the other end of the first storage capacitor, characterized in that it is supplied.
In the present invention, when the first switch and the second switch are turned on, one end of the data line and the first storage capacitor becomes an initial potential, and the other end of the first storage capacitor becomes a predetermined potential. After the first switch and the second switch are turned off, when a data signal having a potential corresponding to the gradation level is supplied to the other end of the first storage capacitor, the potential of the data line is the other end of the first storage capacitor. The potential fluctuation at is shifted by the amount divided by the capacitance ratio of the first storage capacitor and the second storage capacitor. Therefore, according to the present invention, the potential range at the gate of the first transistor is narrowed relative to the potential range of the data signal. Here, since the first switch and the second switch are transistors having different conductivity types, the influence of feedthrough when the first switch and the second switch are turned off is offset. For this reason, fluctuations until the data signal is supplied are suppressed, so that no adverse effect is exerted when the potential of the data line is shifted. Therefore, according to the present invention, it is possible to accurately control the luminance even when the luminance of the pixel circuit greatly changes with respect to the potential change of the data line.

  In the present invention, the pixel circuit includes a first transistor that supplies a current corresponding to a voltage between a gate and a source, and the pixel circuit is turned on or off between the data line and the gate of the first transistor. The electro-optic element is a light emitting element that emits light with a luminance corresponding to the current supplied by the first transistor, and the driving circuit includes the first switch, Turning on the second switch and the second transistor; turning off the first switch and the second switch in a state where the second transistor is turned on in a second period following the first period; It is preferable that a data signal is supplied to the other end of the first storage capacitor and the second transistor is turned off at the end of the second period. According to this configuration, in the first period, the gate of the first transistor as well as the data line becomes the initial potential when the first switch is turned on. In the second period, after the first switch and the second switch are turned off with the second transistor turned on, a data signal having a potential corresponding to the gradation level is supplied to the other end of the first storage capacitor. In this case, the potential of the gate of the data line and the first transistor is shifted by an amount obtained by dividing the potential fluctuation at the other end of the first storage capacitor by the capacitance ratio of the first storage capacitor and the second storage capacitor. For this reason, since the potential range at the gate of the first transistor is narrowed relative to the potential range of the data signal, the current is accurately controlled even when the current change with respect to the voltage change between the gate and source of the first transistor is large. be able to.

In the present invention, the transistor constituting the first switch preferably has a conductivity type that is the conductivity type of the first transistor. According to this configuration, writing on the black side can be improved as compared with a configuration in which the conductivity type of the transistor constituting the first switch is different from that of the first transistor.
In the present invention, it is preferable that the size of the transistor constituting the first switch and the size of the transistor constituting the second switch are aligned. According to this configuration, the potential fluctuation of the data line when the first switch and the second switch are turned off can be made substantially zero.
In addition to the electro-optical device, the present invention can be conceptualized as an electronic apparatus having the electro-optical device. Typically, the electronic device includes a display device such as a head mounted display (HMD) or an electronic viewfinder.

1 is a perspective view illustrating a configuration of an electro-optical device according to an embodiment of the invention. It is a figure which shows the structure of the same electro-optical apparatus. It is a figure which shows the pixel circuit in the same electro-optical apparatus. 6 is a timing chart showing the operation of the electro-optical device. FIG. 6 is an operation explanatory diagram of the same electro-optical device. FIG. 6 is an operation explanatory diagram of the same electro-optical device. FIG. 6 is an operation explanatory diagram of the same electro-optical device. FIG. 6 is an operation explanatory diagram of the same electro-optical device. FIG. 6 is an operation explanatory diagram of the same electro-optical device. It is a figure which shows the amplitude compression of the data signal in the same electro-optical apparatus. It is a figure which shows the principal part equivalent circuit of the level shift circuit of the same electro-optical apparatus. It is a perspective view which shows HMD using the electro-optical apparatus which concerns on embodiment etc. FIG. It is a figure which shows the optical structure of HMD.

  Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.

<Overall configuration>
FIG. 1 is a perspective view illustrating a configuration of an electro-optical device 10 according to the embodiment. The electro-optical device 10 is a micro display that displays an image on a head-mounted display, for example. Although details of the electro-optical device 10 will be described later, a plurality of pixel circuits, a driving circuit for driving the pixel circuits, and the like are organic EL devices formed on, for example, a silicon substrate, and the pixel circuit includes an example of an electro-optical element. OLED is used.
The electro-optical device 10 is housed in a frame-like case 72 that opens at a display unit, and one end of an FPC (Flexible Printed Circuits) substrate 74 is connected. A semiconductor chip control circuit 5 is mounted on the FPC board 74 by a COF (Chip On Film) technique, and a plurality of terminals 76 are provided to be connected to an upper circuit (not shown). Image data is supplied from the upper circuit via a plurality of terminals 76 in synchronization with the synchronization signal. The synchronization signal includes a vertical synchronization signal, a horizontal synchronization signal, and a dot clock signal. Further, the image data defines the gradation level of the pixel of the image to be displayed by, for example, 8 bits.
The control circuit 5 combines the functions of the power supply circuit and the data signal output circuit of the electro-optical device 10. That is, the control circuit 5 supplies various control signals and various potentials generated according to the synchronization signal to the electro-optical device 10, converts digital image data into an analog data signal, and supplies the analog data signal to the electro-optical device 10. To do.

<Electrical configuration>
FIG. 2 is a diagram illustrating a configuration of the electro-optical device 10 according to the first embodiment. As shown in this figure, the electro-optical device 10 is roughly divided into a scanning line driving circuit 20, a demultiplexer 30, a level shift circuit 40, and a display unit 100.
Among these, in the display unit 100, pixel circuits 110 corresponding to pixels of an image to be displayed are arranged in a matrix. Specifically, in the display unit 100, m rows of scanning lines 12 are provided so as to extend in the horizontal direction in the figure, and (3n) columns of data lines 14 grouped every three columns are vertically arranged in the figure. The scanning lines 12 extend in the direction and are electrically insulated from each other. A pixel circuit 110 is provided corresponding to the intersection of the m rows of scanning lines 12 and the (3n) columns of data lines 14. For this reason, in the present embodiment, the pixel circuits 110 are arranged in a matrix form of vertical m rows × horizontal (3n) columns.

Here, m and n are both natural numbers. In order to distinguish rows (rows) in the matrix of the scanning lines 12 and the pixel circuits 110, they may be referred to as 1, 2, 3,..., (M−1), m rows in order from the top in the drawing. Similarly, in order to distinguish the columns of the data line 14 and the matrix of the pixel circuit 110, they may be referred to as 1, 2, 3, ..., (3n-1), (3n) columns in order from the left in the figure. . Further, in order to generalize and describe the group of data lines 14, when an integer j of 1 to n is used, the j-th group counted from the left includes the (3j-2) th column, (3j-1). ) And (3j) th column data lines 14 belong.
Note that the three pixel circuits 110 corresponding to the intersection of the scanning lines 12 in the same row and the three columns of data lines 14 belonging to the same group respectively have R (red), G (green), and B (blue) pixels. Correspondingly, these three pixels represent one dot of a color image to be displayed. That is, in the present embodiment, one dot color is expressed by additive color mixing by light emission of an OLED corresponding to RGB.

The following control signals are supplied from the control circuit 5 to the electro-optical device 10. Specifically, the electro-optical device 10 includes a control signal Ctr for controlling the scanning line driving circuit 20 and control signals Sel (1), Sel (2), Sel for controlling selection in the demultiplexer 30. (3), and control signals / Sel (1), / Sel (2), / Sel (3) that are in a logically inverted relationship with these signals, and a negative logic for controlling the level shift circuit 40. A control signal / Gini is supplied. Note that the control signal Ctr actually includes a plurality of signals such as a pulse signal, a clock signal, and an enable signal.
In addition, in the electro-optical device 10, the data signals Vd (1), Vd (2),..., Vd (n) are assigned to the first, second,. Correspondingly, it is supplied by the control circuit 5. Note that the maximum potential of the data signals Vd (1) to Vd (n) is Vmax, and the minimum value is Vmin.

The scanning line driving circuit 20 generates a scanning signal for sequentially scanning the scanning lines 12 for each row over a frame period in accordance with the control signal Ctr. Here, the scanning signals supplied to the scanning lines 12 of 1, 2, 3,..., (M−1) and the m-th row are Gwr (1), Gwr (2), Gwr (3),. It is written as Gwr (m-1) and Gwr (m).
In addition to the scanning signals Gwr (1) to Gwr (m), the scanning line driving circuit 20 generates various control signals synchronized with the scanning signals for each row and supplies them to the display unit 100. Illustration is omitted in FIG. The frame period is a period required for the electro-optical device 10 to display an image for one cut (frame). For example, if the frequency of the vertical synchronization signal included in the synchronization signal is 120 Hz, the first period is 1. This is a period of 8.3 milliseconds corresponding to the period.

The demultiplexer 30 is an aggregate of transmission gates 34 provided for each column, and sequentially supplies data signals to three columns constituting each group.
Here, the input terminals of the transmission gates 34 corresponding to the (3j-2), (3j-1), and (3j) columns belonging to the jth group are commonly connected to each other, and the data signal Vd ( j) is supplied.
The transmission gate 34 provided in the leftmost column (3j-2) in the j-th group has the control signal Sel (1) at the H level (when the control signal / Sel (1) is at the L level. ) Is turned on (conductive). Similarly, in the j-th group, the transmission gate 34 provided in the (3j−1) column which is the central column has the control signal Sel (2) at the H level (the control signal / Sel (2) is at the L level. The transmission gate 34 provided in the (3j) column which is the rightmost column in the j-th group when the control signal Sel (3) is at the H level (control signal / Sel (3) Is on).

  The level shift circuit 40 includes a set of a storage capacitor 44, a P-channel MOS transistor 45, and an N-channel MOS transistor 46 for each column, and data output from the output terminal of the transmission gate 34 in each column. It shifts the potential of the signal. Here, one end of the storage capacitor 44 is connected to the data line 14 of the corresponding column and the source node of the transistor 45, while the other end of the storage capacitor 44 is the output end of the transmission gate 34 and the drain node of the transistor 46. And connected to. For this reason, the storage capacitor 44 functions as a first storage capacitor having one end connected to the data line 14. Although omitted in FIG. 2, the capacity of the storage capacitor 44 is Crf1.

The drain nodes of the transistors 45 in each column are commonly connected across the columns to the power supply line 61 that supplies the potential Vini as an initial potential, and the control signal / Gini is commonly supplied across the columns to the gate node. For this reason, the transistor 45 is electrically connected to the data line 14 and the power supply line 61 when the control signal / Gini is at L level, and is electrically disconnected when the control signal / Gini is at H level. It functions as a first switch.
The source node of the transistor 46 in each column is connected in common across the columns to a power supply line 62 that supplies a potential Vref as a predetermined potential, and a signal obtained by logically inverting the control signal / Gini by the NOT circuit 18 is applied to the gate node. Gini is commonly supplied across each column. Therefore, the transistor 46 electrically connects the other end of the storage capacitor 44 and the power supply line 62 when the control signal / Gini is at L level (the control signal Gini is at H level), and the control signal / Gini is at H level. It functions as a second switch that is electrically disconnected when the level (the control signal Gini is at the L level).

The storage capacitor 50 is provided for each data line 14. Specifically, one end of the storage capacitor 50 is connected to the data line 14 and the other end is grounded to a common potential Vss, for example, across each column. Therefore, the storage capacitor 50 functions as a second storage capacitor that holds the potential of the data line 14.
Note that the storage capacitor 50 is provided outside the display unit 100 in FIG. 2, but this is only an equivalent circuit and may be provided inside the display unit 100 or from the inside to the outside. It is. Although omitted in FIG. 2, the capacity of the storage capacitor 50 is Cdt. The potential Vss corresponds to an L level of a scanning signal or a control signal that is a logic signal.

  In the present embodiment, the scanning line driving circuit 20, the demultiplexer 30 and the level shift circuit 40 are divided for convenience, but these can be collectively considered as a driving circuit for driving the pixel circuit 110. .

<Pixel circuit>
The pixel circuit 110 will be described with reference to FIG. Since each pixel circuit 110 has the same configuration when viewed electrically, here, the i-th row (3j−) located in the (3j-2) th column of the leftmost column in the j-th group is the i-th row. 2) The pixel circuit 110 in the column will be described as an example.
Note that i is a symbol for generally indicating a row in which the pixel circuits 110 are arranged, and is an integer of 1 to m.

As shown in FIG. 3, the pixel circuit 110 includes P-channel MOS transistors 121, 122, and 124, an OLED 130, and a storage capacitor 132.
The pixel circuit 110 is supplied with a scanning signal Gwr (i) and a control signal Gel (i). Here, the scanning signal Gwr (i) and the control signal Gel (i) are respectively supplied by the scanning line driving circuit 20 corresponding to the i-th row. For this reason, the scanning signal Gwr (i) and the control signal Gel (i) are commonly supplied to pixel circuits in columns other than the focused (3j-2) column as long as the i-th row. .

In the transistor 122 in the pixel circuit 110 in the i-th row (3j-2) column, the gate node is connected to the scanning line 12 in the i-th row, and either the drain or the source node is the data in the (3j-2) -th column. The other is connected to the line 14, and the other is connected to the gate node of the transistor 121 and one end of the storage capacitor 132. Here, the gate node of the transistor 121 is denoted by g to distinguish it from other nodes.
In the transistor 121, the source node is connected to the power supply line 116, and the drain node is connected to the source node of the transistor 124. Here, the power supply line 116 is supplied with a potential Vel that is higher in the power supply in the pixel circuit 110.
In the transistor 124, a control signal Gel (i) corresponding to the i-th row is supplied to the gate node, and the drain node is connected to the anode of the OLED 130.
Here, the transistor 121 corresponds to the first transistor, and the transistor 122 corresponds to the second transistor.

The other end of the storage capacitor 132 is connected to the power supply line 116. For this reason, the storage capacitor 132 holds the voltage between the source and the drain of the transistor 121. Here, when the capacity of the storage capacitor 132 is expressed as Cpix, the capacity Cdt of the storage capacitor 50, the capacity Crf1 of the storage capacitor 44, and the capacity Cpix of the storage capacitor 132 are:
Cdt >> Crf1 >> Cpix
Is set to be
That is, Cdt is set to be larger than Crf1, and Cpix is set to be sufficiently smaller than Cdt and Crf1.
Note that as the storage capacitor 132, a capacitor parasitic to the gate node g of the transistor 121 may be used, or a capacitor formed by sandwiching an insulating layer between different conductive layers in a silicon substrate may be used.

  In this embodiment, since the electro-optical device 10 is formed on a silicon substrate, the substrate potential of the transistors 121, 122, and 124 is set to the potential Vel.

The anode of the OLED 130 is a pixel electrode provided individually for each pixel circuit 110. On the other hand, the cathode of the OLED 130 is a common electrode 118 that is common to all the pixel circuits 110, and is kept at a potential Vct that is the lower side of the power supply in the pixel circuit 110.
The OLED 130 is an element in which a white organic EL layer is sandwiched between an anode and a light-transmitting cathode on the silicon substrate. A color filter corresponding to any of RGB is superimposed on the emission side (cathode side) of the OLED 130.
In such an OLED 130, when current flows from the anode to the cathode, holes injected from the anode and electrons injected from the cathode are recombined in the organic EL layer to generate excitons, and white light is generated. . The white light generated at this time passes through the cathode opposite to the silicon substrate (anode), and is colored by a color filter so as to be visually recognized by the viewer.

<Operation>
The operation of the electro-optical device 10 will be described with reference to FIG. FIG. 4 is a timing chart for explaining the operation of each part in the electro-optical device 10. In this figure, the vertical scale indicating the potential is different between the scanning signal and the control signal, the data signal and the gate for convenience of explanation.

As shown in this figure, the scanning signals Gwr (1) to Gwr (m) are sequentially switched to the L level, and the scanning lines 12 in the 1st to m-th rows in one frame period are in one horizontal scanning period (H). Scanned sequentially.
The operation in one horizontal scanning period (H) is common to the pixel circuits 110 in each row. Therefore, in the following, the operation will be described focusing on the pixel circuit 110 in the i-th row (3j-2) column in the scanning period in which the i-th row is horizontally scanned.

In the present embodiment, the i-th scanning period is roughly divided into an initialization period shown in FIG. 4B and a writing period shown in FIG. Then, after the writing period of (c), the light emission period indicated by (a) is reached, and the scanning period of the i-th row is reached again after the elapse of one frame period. Therefore, in the order of time, a cycle of (light emission period) → initialization period → writing period → (light emission period) is repeated.
In FIG. 4, for each of the scanning signal Gwr (i-1) and the control signal Gel (i-1) corresponding to the (i-1) th row before the ith row, the ith row The waveform is temporally preceded by one horizontal scanning period (H), respectively, with respect to the scanning signal Gwr (i) and the control signal Gel (i) corresponding to.

<Light emission period>
For convenience of explanation, the light emission period which is the premise of the initialization period will be described. As shown in FIG. 4, in the light emission period of the i-th row, the scanning signal Gwr (i) is at the H level and the control signal Gel (i) is at the L level.
For this reason, as shown in FIG. 5, in the pixel circuit 110 in the i row (3j-2) column, the transistor 124 is turned on while the transistor 122 is turned off. Therefore, the transistor 121 supplies the OLED 130 with the current Ids corresponding to the voltage held by the holding capacitor 132, that is, the gate-source voltage Vgs. As will be described later, the potential of the gate node g in the light emission period is a value obtained by level-shifting the potential change from the initial potential Vini to the data signal of the potential corresponding to the gradation level according to the capacitance ratio of the holding capacitors 44 and 50. Therefore, the voltage Vgs is a voltage corresponding to the gradation. For this reason, since the transistor 121 supplies a current corresponding to the gradation level, the OLED 130 emits light with a luminance corresponding to the current.

Note that since the light emission period of the i-th row is a period during which horizontal scanning is performed except for the i-th row, the potential of the data line 14 varies appropriately. However, in the pixel circuit 110 in the i-th row, since the transistor 122 is off, the potential fluctuation of the data line 14 is not considered here.
Further, in FIG. 5, paths that are important in the explanation of operations are indicated by bold lines (the same applies to FIGS. 6 to 9 below).

<Initialization period>
Next, when the scanning period of the i-th row is reached, the initialization period starts. In the initialization period, first, the control signal Gel (i) becomes H level compared to the light emission period.
For this reason, as shown in FIG. 6, the transistor 124 is turned off in the pixel circuit 110 in the i row (3j−2) column. As a result, the path of the current supplied to the OLED 130 is interrupted, so that the OLED 130 enters an off (non-light emitting) state.
On the other hand, since the control signal / Gini becomes L level during the initialization period, the transistors 45 and 46 are turned on in the level shift circuit 40 as shown in FIG. Therefore, the node Na (data line 14) which is one end of the storage capacitor 44 is initialized to the potential Vini, and the node Nb which is the other end of the storage capacitor 44 is initialized to the potential Vref.

  In the initialization period, there is a period in which the scanning signal Gwr (i) is at the L level while the control signal / Gini is at the L level. This period is the first period. In this first period, as shown in FIG. 7, the transistor 122 is turned on in the pixel circuit 110 in the i row (3j−2) column, so that the gate node g is electrically connected to the data line 14. Become. Accordingly, since the gate node g is also at the potential Vini, the holding voltage of the holding capacitor 132 is initialized to (Vel−Vini) from the voltage held in the light emission period.

<Writing period>
After the initialization period, the writing period (c) is reached as the second period. First, in the writing period, since the control signal / Gini becomes H level while the scanning signal Gwr (i) is at L level, the transistors 45 and 46 are turned off in the level shift circuit 40, respectively. At this time, in the present embodiment, the influence of feedthrough is canceled as follows.
Specifically, the feedthrough when the P-channel transistor 45 is turned off is a function of causing the node Na to change in the upward direction indicated by “↑” from the potential Vini at the time of turning on in FIG. Here, the feedthrough due to the turning off of the transistor 45 does not stop at the node Na but attempts to change the node Nb in the upward direction indicated by “Δ” in FIG.
On the other hand, the feedthrough when the N-channel type transistor 46 is turned off is a function of changing the node Nb in the downward direction indicated by “↓” from the potential Vref in the on state in FIG. Here, the feedthrough due to the turning off of the transistor 46 does not stop at the node Nb but attempts to change the node Na in the downward direction indicated by “▽” via the storage capacitor 44.
Therefore, at the node Na, the potential increase “↑” due to the transistor 45 being off and the potential decrease ▽ due to the transistor 46 being off cancel each other, and even at the node Nb, the potential decrease “↓” due to the transistor 46 being off is The potential increase Δ caused by turning off 45 cancels each other.
When the transistors 45 and 46 are turned off, the path from the node Na to the gate node g via the data line 14 becomes floating as shown in FIG. The node Na is maintained at the potential Vini, and the node Nb is maintained at the potential Vref.

Next, the control circuit 5 outputs the following data signal in the writing period of the i-th row. That is, in the j-th group, the control circuit 5 sequentially outputs the data signal Vd (j) in the i-th row and the leftmost column (3j-2) column and the central column (3j) belonging to the group. -1) The potential is switched in order to the potential corresponding to the gradation level of the pixel in the column and the (3j) column in the rightmost column. The control circuit 5 similarly switches the potential in order for data signals to other groups.
Further, the control circuit 5 exclusively sets the control signals Sel (1), Sel (2), and Sel (3) to the H level in order in accordance with the switching of the potential of the data signal. Although not shown in FIG. 4, the control circuit 5 controls the control signals Sel (1), Sel (2), and Sel (3) that are in a logically inverted relationship with the control signals Sel (1), Sel (2), and Sel (3). (2) and / Sel (3) are also output. As a result, in the demultiplexer 30, the transmission gates 34 are turned on in the order of the left end column, the center column, and the right end column in each group.

Here, when the leftmost transmission gate 34 belonging to the jth group is turned on by the control signals Sel (1), / Sel (1), as shown in FIG. Nb changes from the initialized potential Vref to the potential of the data signal Vd (j), that is, the potential corresponding to the gradation level of the pixel in the i row (3j-2) column. The potential change of the node Nb at this time is represented as ΔV, and the potential after the change is represented as (Vref + ΔV).
On the other hand, since the gate node g is electrically connected to the node Na which is one end of the storage capacitor 44 via the data line 14, the capacitance ratio k1 is changed from the potential Vini to the potential change ΔV of the node Nb. Only the multiplied value is a value shifted in the changing direction of the node Nb. Here, the capacitance ratio k1 is Crf1 / (Cdt + Crf1). Strictly speaking, the capacitance Cpix of the storage capacitor 132 must be taken into consideration, but the capacitance Cpix is ignored because it is set to be sufficiently smaller than the capacitances Crf1 and Cdt.

FIG. 10 is a diagram showing the relationship between the potential of the data signal and the potential of the gate node g in the writing period. As described above, the data signal supplied from the control circuit 5 can take a potential range from the minimum value Vmin to the maximum value Vmax according to the gradation level of the pixel. In this embodiment, the data signal is not directly written to the gate node g, but is level-shifted and written to the gate notebook g as shown in the figure.
At this time, the potential range ΔVgate of the gate node g is compressed to a value obtained by multiplying the potential range ΔVdata (= Vmax−Vmin) of the data signal by the capacitance ratio k1. For example, when the storage capacitors 44 and 50 are set so that Crf1: Cdt = 1: 9, the potential range ΔVgate of the gate node g is compressed to 1/10 of the potential range ΔVdata of the data signal.
Further, how much the potential range ΔVgate of the gate node g is shifted in which direction with respect to the potential range ΔVdata of the data signal can be determined by the potentials Vini and Vref. This is because the potential range ΔVdata of the data signal is compressed with the capacitance ratio k1 with respect to the potential Vref, and the compression range shifted with reference to the potential Vini becomes the potential range ΔVgate of the gate node g. Because.
Therefore, if the node Na fluctuates from the potential Vini due to feedthrough when the transistors 45 and 46 are turned off, the premise of potential shift is lost. However, in this embodiment, the feedthrough is canceled as described above. Thus, the node Na is prevented from changing from the potential Vini.

In this manner, in the writing period of the i-th row, the data signal of the potential corresponding to the gradation level is level-shifted to the gate node g of the pixel circuit 110 of the i-th row according to the capacitance ratio of the holding capacitors 44 and 50 The written potential is written.
Eventually, the scanning signal Gwr (i) becomes H level, and the transistor 122 is turned off. Thus, the writing period ends, and the potential of the gate node g is fixed to the shifted value.

<Light emission period>
After the end of the writing period of the i-th row, a light emission period is reached after a while. In this light emission period, the control signal Gel (i) is at the L level as described above, so that the transistor 124 is turned on in the pixel circuit 110 in the i row (3j-2) column. For this reason, as shown in FIG. 5, the current Ids corresponding to the gate-source voltage Vgs is supplied to the OLED 130 by the transistor 121, so that the OLED 130 emits light with the luminance corresponding to the current. become.

  Such an operation is also executed in parallel in time in the i-th pixel circuit 110 other than the pixel circuit 110 in the (3j-2) th column of interest in the i-th scanning period. Further, such an operation on the i-th row is actually executed in the order of 1, 2, 3,..., (M−1), m-th row in the period of one frame, and is repeated for each frame. It is.

Note that FIG. 4 shows that the gate node g in the pixel circuit 110 in the i-th row (3j-2) column is level-shifted from the potential Vini due to the control signal Sel (1) becoming the H level. ing.
Here, when the data signal corresponding to the pixel in the i row (3j-2) column is the potential V (i, 3j-2), the potential of the gate node of the pixel after the level shift is shown in FIG. Vini + k1 {V (i, 3j-2) -Vref}.
In the same figure, the gate node of the (i-1) row (3j-2) column, which is the same column as the i row (3j-2) column and one row before, is level-shifted from the potential Vini. Is also shown.
Here, when the data signal corresponding to the pixel in the i row (3j-2) column is the potential V (i-1, 3j-2), the potential of the gate node of the pixel after the level shift is shown in FIG. As shown, Vini + k1 {V (i-1,3j-2) -Vref}.

  According to the present embodiment, the potential range ΔVgate at the gate node g is narrowed with respect to the potential range ΔVdata of the data signal, so that the voltage reflecting the gradation level can be applied to the transistor 121 without engraving the data signal with fine accuracy. Can be applied between the gate and the source. Therefore, even in the case where the minute current flowing through the OLED 130 changes relatively greatly with respect to the change in the gate-source voltage Vgs of the transistor 121 in the fine pixel circuit 110, the current supplied to the OLED 130 is accurately controlled. It becomes possible to do.

Further, as indicated by a broken line in FIG. 3, a capacitance Cprs is actually parasitic between the data line 14 and the gate node g in the pixel circuit 110. For this reason, if the potential change width of the data line 14 is large, it propagates to the gate node g via the capacitor Cprs, and so-called crosstalk or unevenness occurs, thereby degrading the display quality. The influence of the capacitance Cprs is noticeable when the pixel circuit 110 is miniaturized.
On the other hand, in the present embodiment, the potential change range of the data line 14 is also narrowed with respect to the potential range ΔVdata of the data signal, so that the influence via the capacitor Cprs can be suppressed.

Here, consider once again the cancellation of the feedthrough by turning off the transistors 45 and 46. The cause of the feedthrough is that the charge accumulated in the parasitic capacitance between each node of the transistor is redistributed to each capacitance due to the potential change of the gate node when turning from on to off.
The periphery of the transistors 45 and 46 can be represented by an equivalent circuit as shown in FIG. Note that the capacitance Cini is a parasitic capacitance between the gate node of the transistor 45 and one of the source node or the drain node, and the capacitance Cref is between the gate node of the transistor 46 and one of the source node or the drain node. Of parasitic capacitance.

The potential change ΔVa_ini generated at the node Na when the transistor 45 is turned off is expressed by the following equation when the potential change from L to H level of the gate node in the transistor 45 is ΔVsw_ini. That is,
ΔVa_ini
= ΔVsw_ini · Cini / {Cdt + (Crf1 · Cref) / (Crf1 + Cref) + Cini}
Since the capacitors Cini and Cref are sufficiently smaller than the capacitor Cdt added to the data line 14 and the capacitor Crf1 used for level shift, it can be approximated by the following equation.
ΔVa_ini≈ΔVsw_ini · Cini / Cdt (1)
Note that the potential change is positive in the direction of change in the upward direction.

On the other hand, when the transistor 46 is turned off, the potential change ΔVa_ref applied to the node Na via the storage capacitor 44 is expressed by the following equation when the potential change from the H level to the L level of the gate node in the transistor 46 is ΔVsw_ref. Represented by That is,
ΔVa_ref
= ΔVsw_ref · 1 // (Cdt + Cini) · {1 / (Cdt + Cini) + 1 / Crf1 + 1 / Cref} ⁻¹
Since the capacitors Cini and Cref are sufficiently smaller than the capacitors Cdt and Crf1, they can be approximated as follows.
ΔVa_ref≈ΔVsw_ref · Cref / Cdt (2)

Since the potential fluctuation of the node Na is the sum of the potential changes ΔVa_ini and ΔVa_ref, it can be expressed by the following equation (3) from the equations (1) and (2).
ΔVa_ini + ΔVa_ref = (ΔVsw_ini · Cini + ΔVsw_ref · Cref) / Cdt (3)
Therefore, the following conditions (A) and (B) are derived to make the potential fluctuation of the node Na zero.

That is,
(A) ΔVsw_ini and ΔVsw_ref are positive and negative, and their absolute values are equal.
For this purpose, the channel types (conductivity types) of the transistors 45 and 46 may be different from each other as in the embodiment, and the amplitudes of the logic signals to the transistors 45 and 36 may be the same.
(B) Cini and Cref are equal to each other.
For this purpose, the sizes of the transistors 45 and 46 may be equalized.

In order to tighten the display on the black side in the display image by the electro-optical device 10, it is preferable that the potential Vini applied to the gate node g at the time of initialization is in the vicinity of (Vel + Vth) with respect to the threshold voltage Vth of the transistor 121. . Note that in the case where the transistor 121 is a P-channel type, the threshold voltage Vth is negative, and is, for example, about “−1 V” when miniaturized.
In order to simplify the electro-optical device 10, the number of potentials to be used should be reduced as much as possible. For this purpose, the H level that is the higher level of the logic signal is shared with the potential Vel that is the higher level of the power supply in the pixel circuit 110.
On the other hand, since the shift reference of the compression range of the data signal is the potential Vini, when the transistor 121 is a P-channel type, the potential Vini is preferably higher than half of the higher potential Vel. .
For this reason, since the potential Vini is set in a range of Vel>Vini> Vel / 2, the transistor 45 that supplies such a potential Vini to the gate node g via the data line 14 is the channel type of the transistor 121. The same P channel type configuration is desirable.

In the embodiment, the transistor 121 is described as a P-channel type. However, when the transistor 121 is an N-channel type, the transistor 45 may be an N-channel type and the transistor 46 may be a P-channel type.
Further, although the control signal Gini to the transistor 46 is logically inverted by the NOT circuit 18 from the control signal / Gini to the transistor 45, it is needless to say that the control signal Gini is not limited to this.

  In the present embodiment, a P-channel transistor 45 is used as a first switch that connects one end of the storage capacitor 44 to the power supply line 61, and an N channel is used as a second switch that connects the other end of the storage capacitor 44 to the power supply line 62. A type transistor 46 is used. For this reason, compared with a configuration using transmission gates as the first switch and the second switch, the configuration is simplified, so that space can be saved, and a so-called frame that is outside the display unit 100 correspondingly. Can be narrowed.

<Application and modification>
The present invention is not limited to the above-described embodiments and application examples, and various modifications as described below are possible. Moreover, the aspect of the deformation | transformation described below can also combine suitably arbitrarily selected 1 or several.

<Application to other electro-optical devices>
In the embodiments and the like, the OLED 130 that is a light emitting element is illustrated as an electro-optical element, but a type that emits light with luminance according to current, such as an inorganic light emitting diode or LED (Light Emitting Diode), is applicable. Further, the present invention is not limited to a light-emitting element that emits light with luminance corresponding to a current, and can be applied to a liquid crystal element or an electrophoretic element. In short, in the configuration in which the data signal is supplied to the data line 14 through the coupling of the storage capacitor 44, the potential of the data line is held in accordance with the scanning signal supplied to the scanning line, and the holding potential is set to the holding potential. An electro-optical element having a corresponding luminance (reflectance, transmittance) can be applied.

<Control circuit>
In the embodiment, the control circuit 5 that supplies the data signal is separated from the electro-optical device 10. However, the control circuit 5 also includes a silicon substrate along with the scanning line driving circuit 20, the demultiplexer 30, and the level shift circuit 40. It may be integrated in.

<Board>
In the embodiment, the electro-optical device 10 is integrated on the silicon substrate. However, the electro-optical device 10 may be integrated on another semiconductor substrate. Further, it may be formed on a glass substrate or the like by applying a polysilicon process. In any case, the pixel circuit 110 is miniaturized, and the transistor 121 is effective in a configuration in which the drain current greatly changes exponentially with respect to the change in the gate voltage Vgs.

<Demultiplexer>
In the embodiment and the like, the data lines 14 are grouped every three columns, and the data lines 14 are sequentially selected in each group to supply data signals. However, the number of data lines constituting the group is as follows. "2" may be sufficient and "4" or more may be sufficient.
Further, a configuration may be adopted in which data signals are supplied to the data lines 14 of each column all at once without grouping, that is, without using the demultiplexer 30.

<Transistor channel type>
In the above-described embodiments and the like, the transistors 121, 122, and 124 in the pixel circuit 110 are unified with the P-channel type, but may be unified with the N-channel type. Further, the P channel type and the N channel type may be appropriately combined.

<Electronic equipment>
Next, an electronic apparatus to which the electro-optical device 10 according to the embodiment and the application example is applied will be described. The electro-optical device 10 is suitable for high-definition display with small pixels. Therefore, a head mounted display will be described as an example of an electronic device.

FIG. 12 is a diagram showing the external appearance of the head-mounted display, and FIG. 13 is a diagram showing its optical configuration.
First, as shown in FIG. 12, the head mounted display 300 has a temple 310, a bridge 320, and lenses 301L and 301R in the same manner as general glasses. Further, as shown in FIG. 13, the head mounted display 300 is in the vicinity of the bridge 320 and on the back side (lower side in the drawing) of the lenses 301L and 301R, the electro-optical device 10L for the left eye and the right eye. Electro-optical device 10R.
The image display surface of the electro-optical device 10L is arranged on the left side in FIG. Accordingly, the display image by the electro-optical device 10L is emitted in the direction of 9 o'clock in the drawing through the optical lens 302L. The half mirror 303L reflects the display image from the electro-optical device 10L in the 6 o'clock direction, and transmits light incident from the 12 o'clock direction.
The image display surface of the electro-optical device 10R is disposed on the right side opposite to the electro-optical device 10L. As a result, the display image by the electro-optical device 10R is emitted in the direction of 3 o'clock in the drawing through the optical lens 302R. The half mirror 303R reflects the display image by the electro-optical device 10R in the 6 o'clock direction, and transmits light incident from the 12 o'clock direction.

In this configuration, the wearer of the head mounted display 300 can observe the display image by the electro-optical devices 10L and 10R in a see-through state superimposed on the outside.
In the head-mounted display 300, when a left-eye image is displayed on the electro-optical device 10L and a right-eye image is displayed on the electro-optical device 10R among binocular images with parallax, The displayed image can be perceived as if it had a depth or a stereoscopic effect (3D display).

  The electro-optical device 10 can be applied to an electronic viewfinder in a video camera, an interchangeable lens digital camera, etc. in addition to the head mounted display 300.

DESCRIPTION OF SYMBOLS 10 ... Electro-optical apparatus, 12 ... Scan line, 14 ... Data line, 20 ... Scan line drive circuit, 30 ... Demultiplexer, 40 ... Level shift circuit, 44 ... Retention capacity, 45, 46 ... Transistor, 50 ... Retention capacity, DESCRIPTION OF SYMBOLS 100 ... Display part, 110 ... Pixel circuit, 116 ... Feeding line, 118 ... Common electrode, 121, 122, 124 ... Transistor, 130 ... OLED, 132 ... Retention capacity, 300 ... Head mounted display.

Claims (5)

A plurality of scan lines;
Multiple data lines,
A circuit that is provided corresponding to the intersection of the plurality of scanning lines and the plurality of data lines and holds the potential of the data line in accordance with a scanning signal supplied to the scanning line; A pixel circuit including an electro-optical element having a corresponding luminance;
A first storage capacitor having one end electrically connected to the data line;
A second holding capacitor for holding the potential of each of the plurality of data lines;
A first switch that is turned on or off between the data line and a first feed line that feeds an initial potential;
A second switch that is turned on or off between the other end of the first storage capacitor and a second feeder that feeds a predetermined potential;
Have
The first switch and the second switch are transistors having different conductivity types,
An electro-optical device, wherein after the first switch and the second switch are turned from on to off, a data signal having a potential corresponding to a gradation is supplied to the other end of the first storage capacitor. Having a drive circuit,
The pixel circuit includes:
A first transistor for supplying a current according to a voltage between the gate and the source;
A second transistor that is turned on or off between the data line and the gate of the first transistor;
Including
The electro-optic element is a light emitting element that emits light with a luminance according to the current supplied by the first transistor,
The drive circuit is
In the first period, the first switch, the second switch, and the second transistor are turned on,
In a second period following the first period,
With the second transistor turned on, the first switch and the second switch are turned off to supply the data signal to the other end of the first storage capacitor,
The electro-optical device according to claim 1, wherein the second transistor is turned off at the end of the second period. The electro-optical device according to claim 1, wherein a conductivity type of a transistor constituting the first switch is a conductivity type of the first transistor. 4. The electro-optical device according to claim 1, wherein a size of a transistor configuring the first switch is equal to a size of a transistor configuring the second switch. 5. An electronic apparatus comprising the electro-optical device according to claim 1.

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