CN113508430A

CN113508430A - Pixel circuit, display substrate and display device

Info

Publication number: CN113508430A
Application number: CN202080000102.7A
Authority: CN
Inventors: 黄耀; 邱远游; 黄炜赟; 肖星亮
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Priority date: 2020-01-23
Filing date: 2020-01-23
Publication date: 2021-10-15
Anticipated expiration: 2040-01-23
Also published as: CN113508430B; WO2021147083A1

Abstract

A pixel circuit (100), a display substrate (10) and a display device (20), the pixel circuit (100) includes a first drive circuit (101), a second drive circuit (102), a data write circuit (103) and a signal storage circuit (104); a data write circuit (103) configured to receive a data signal; the first drive circuit (101) is connected with the data write circuit (103) and is configured to receive a data signal from the data write circuit (103) and allow the data signal to be written to a control terminal of the first drive circuit (101); the control terminal of the second drive circuit (102) is configured to receive a data signal written to the control terminal of the first drive circuit (101); the signal storage circuit (104) is configured to store, at a control terminal of the first drive circuit (101), a data signal written to the control terminal of the first drive circuit (101); a first terminal of the first driving circuit (101) and a first terminal of the second driving circuit (102) are each configured to receive a first power supply voltage from a first power supply voltage terminal (VDD), and a second terminal of the first driving circuit (101) and a second terminal of the second driving circuit (102) are each configured to be electrically connected to a first terminal of the light emitting element (116); the first drive circuit (101) and the second drive circuit (102) are configured to control drive currents for driving the light emitting element (116) from a first power supply voltage terminal (VDD) to the light emitting element (116) respectively flowing through the first drive circuit (101) and the second drive circuit (102) based on the data signal stored in the signal storage circuit (104) and the received first power supply voltage; the luminance of a light emitting element (116) electrically connected to the pixel circuit (100) can be improved.

Description

Pixel circuit, display substrate and display device

Technical Field

Embodiments of the present disclosure relate to a pixel circuit, a display substrate, and a display device.

Background

An Organic Light Emitting Diode (OLED) display device has the characteristics of wide viewing angle, high contrast, high response speed and the like. Also, the organic light emitting diode display device has advantages of higher light emitting luminance, lower driving voltage, and the like, compared to the inorganic light emitting display device. Due to the above features and advantages, Organic Light Emitting Diode (OLED) display devices are receiving wide attention from people and may be applied to devices having display functions, such as mobile phones, displays, notebook computers, digital cameras, instruments and meters.

Disclosure of Invention

At least one embodiment of the present disclosure provides a pixel circuit including: the driving circuit comprises a first driving circuit, a second driving circuit, a data writing circuit and a signal storage circuit. The data write circuit is configured to receive a data signal; the first drive circuit is connected with the data writing circuit and is configured to receive the data signal from the data writing circuit and allow the data signal to be written into a control end of the first drive circuit; the control terminal of the second drive circuit is configured to receive the data signal written to the control terminal of the first drive circuit; the signal storage circuit is configured to store the data signal written to the control terminal of the first drive circuit at the control terminal of the first drive circuit; a first terminal of the first driving circuit and a first terminal of the second driving circuit are each configured to receive a first power supply voltage from a first power supply voltage terminal, and a second terminal of the first driving circuit and a second terminal of the second driving circuit are each configured to be electrically connected to a first terminal of a light emitting element; and the first drive circuit and the second drive circuit are configured to control drive currents for driving the light emitting elements, which flow through the first drive circuit and the second drive circuit, respectively, and from the first power supply voltage terminal to the light emitting elements, based on the data signal stored in the signal storage circuit and the received first power supply voltage.

For example, in at least one example of the pixel circuit, the control terminal of the first drive circuit and the control terminal of the second drive circuit are electrically connected to each other.

For example, in at least one example of the pixel circuit, the pixel circuit further includes a compensation connection circuit. The data writing circuit writes the data signal into a first end of the first driving circuit; and the compensation connection circuit is connected between the second terminal of the first drive circuit and the control terminal of the first drive circuit, and is configured to write the data signal written to the first terminal of the first drive circuit to the control terminal of the first drive circuit via the first drive circuit.

For example, in at least one example of the pixel circuit, the control terminal of the compensation connection circuit and the control terminal of the data writing circuit are connected to the same scanning signal line.

For example, in at least one example of the pixel circuit, the pixel circuit further includes a first reset circuit. The first reset circuit is connected with the signal storage circuit; and the first reset circuit is configured to receive a first reset signal and write the first reset signal to the signal storage circuit to reset the signal storage circuit.

For example, in at least one example of the pixel circuit, the pixel circuit further includes a first control circuit and a second control circuit. The first control circuit is connected between a first terminal of the first drive circuit and the first power supply voltage terminal, and is configured to control whether the first drive circuit is electrically connected to the first power supply terminal; and the second control circuit is connected between the first terminal of the second drive circuit and the first power supply voltage terminal, and is configured to control whether or not the second drive circuit is electrically connected to the first power supply terminal.

For example, in at least one example of the pixel circuit, the control terminal of the first control circuit and the control terminal of the second control circuit are connected to the same emission control line.

For example, in at least one example of the pixel circuit, the pixel circuit further includes a second reset circuit. The second reset circuit is configured to receive a second reset signal and write the second reset signal to the first terminal of the light emitting element to reset the first terminal of the light emitting element.

For example, in at least one example of the pixel circuit, the pixel circuit further includes a third control circuit and a fourth control circuit. The third control circuit is connected between the second end of the first driving circuit and the first end of the light emitting element, and is configured to control whether the first driving circuit is electrically connected to the first end of the light emitting element; and the fourth control circuit is connected between the second end of the second driving circuit and the first end of the light emitting element, and is configured to control whether the second driving circuit is electrically connected to the first end of the light emitting element.

For example, in at least one example of the pixel circuit, the control terminal of the third control circuit and the control terminal of the fourth control circuit are connected to the same emission control line.

For example, in at least one example of the pixel circuit, the first drive circuit includes a first transistor, and the second drive circuit includes a second transistor; and the threshold voltage of the first transistor and the threshold voltage of the second transistor are equal.

At least one embodiment of the present disclosure also provides a display substrate including any one of the pixel circuits provided by at least one embodiment of the present disclosure.

For example, in at least one example of the display substrate, the at least one pixel circuit includes a plurality of pixel circuits; the display substrate is provided with a display area, and the display area comprises a first display area and a second display area; the first display area comprises a plurality of first pixel units arranged in an array, and the second display area comprises a plurality of second pixel units arranged in an array; the unit area distribution density of the plurality of first pixel units in the first display area is smaller than the unit area distribution density of the plurality of second pixel units in the second display area; each of the plurality of first pixel units includes the light emitting element; and the pixel circuits are electrically connected with the light-emitting elements in a one-to-one correspondence manner.

For example, in at least one example of the display substrate, the first display region further includes a first sub-display region and a second sub-display region that do not overlap with each other; the first sub-display area comprises a first group of the plurality of first pixel units, the second sub-display area comprises a second group of the plurality of first pixel units, and the first group and the second group are not overlapped with each other; and pixel circuits connected in one-to-one correspondence with the light emitting elements of the second group of the plurality of first pixel units are disposed in the first sub-display region.

For example, in at least one example of the display substrate, the display substrate further includes a plurality of transparent traces. The plurality of transparent wires electrically connect the light emitting elements of the second group of the plurality of first pixel units with the pixel circuits which are connected with the light emitting elements of the second group of the plurality of first pixel units in a one-to-one correspondence manner.

For example, in at least one example of the display substrate, the display substrate further has a peripheral region at least partially surrounding the display region, and the plurality of pixel circuits are at least partially disposed in the peripheral region.

For example, in at least one example of the display substrate, the display substrate further comprises a sensor. The sensor is disposed on a non-display side of the display substrate, overlaps the first display region in a normal direction of a display surface of the display substrate, and is configured to receive and process an optical signal passing through the first display region.

At least one embodiment of the present disclosure also provides a display device including any one of the pixel circuits or any one of the display substrates provided by at least one embodiment of the present disclosure.

Drawings

To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure and are not limiting to the present disclosure.

FIG. 1A is a schematic cross-sectional view of a display substrate;

FIG. 1B is a schematic plan view of the display substrate shown in FIG. 1A;

FIG. 1C is a schematic view of a portion of the area of the display substrate shown in FIG. 1B;

fig. 2A is a schematic structural diagram of a 7T1C pixel circuit;

FIG. 2B is a driving timing diagram of the 7T1C pixel circuit shown in FIG. 2A;

fig. 3 is a schematic diagram of a pixel circuit provided by at least one embodiment of the present disclosure;

FIG. 4A is an example of the pixel circuit shown in FIG. 3;

fig. 4B is a driving timing chart of the pixel circuit shown in fig. 4A;

fig. 5A is an exemplary block diagram of a display substrate provided by at least one embodiment of the present disclosure;

FIG. 5B is a schematic cross-sectional view of the display substrate shown in FIG. 5A;

FIG. 6 is a schematic plan view of one example of the display substrate shown in FIG. 5B;

fig. 7A is a schematic view of a partial area of a first display region of the display substrate shown in fig. 6;

FIG. 7B shows a schematic diagram of a first group of the plurality of first pixel cells shown in FIG. 7A;

FIG. 7C shows a schematic diagram of a second group of the plurality of first pixel cells shown in FIG. 7A;

fig. 8A is a schematic view of a partial region of a second display region of the display substrate shown in fig. 6;

FIG. 8B illustrates an example of the first pixel cell shown in FIG. 7A;

FIG. 8C illustrates another example of the first pixel cell shown in FIG. 7A;

FIG. 8D shows a schematic diagram of the second pixel cell shown in FIG. 8A;

FIG. 8E shows a schematic diagram of the redundant pixel cell shown in FIG. 7A;

FIG. 9 is a schematic plan view of another example of the display substrate shown in FIG. 5B;

FIG. 10 is a schematic plan view of still another example of the display substrate shown in FIG. 5B; and

fig. 11 is an exemplary block diagram of a display device provided by at least one embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the drawings of the embodiments of the present invention. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the invention without any inventive step, are within the scope of protection of the invention.

Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

The inventors of the present disclosure have noted that the current display substrate with an off-screen sensor (camera) has a low emission luminance of a display area corresponding to the off-screen sensor (camera), thereby affecting the quality of an image displayed by the display substrate. The following is an exemplary description with reference to fig. 1A, 1B, 2A, and 2B.

Fig. 1A is a schematic cross-sectional view of a display substrate 500, fig. 1B is a schematic plan view of the display substrate 500 shown in fig. 1A, and fig. 1C is a schematic partial area 513 of the display substrate 500 shown in fig. 1B. The display substrate 500 shown in fig. 1B corresponds to the BB' line of the display substrate 10 shown in fig. 1A.

As shown in fig. 1A, the display substrate 500 includes a display layer 510 and a sensing layer 520, and the sensing layer 520 is disposed on a non-display side of the display substrate 500. As shown in fig. 1A to 1C, the display layer 510 includes a first display region 511 and a second display region 512; the first display region 511 includes a plurality of first light emitting elements 531 arranged in an array, and the second display region 512 includes a plurality of second light emitting elements 532 arranged in an array. For example, the plurality of first light emitting elements 531 and the plurality of second light emitting elements 532 have the same structure and performance characteristics.

As shown in fig. 1A, the sensing layer 520 includes a sensor 521, the sensor 521 overlaps the first display region 511 in a normal direction of the display surface of the display substrate 500, and is configured to receive and process an optical signal passing through the first display region 511.

As shown in fig. 1C, in order to reduce the blocking of the light signal incident to the first display region 511 and transmitted toward the sensor 521 by the elements in the first display region 511, the distribution density per unit area of the plurality of first light emitting elements 531 in the first display region 511 is smaller than the distribution density per unit area of the plurality of second light emitting elements 532 in the second display region 512. However, this makes the effective light emitting area of the first display region 511 smaller than that of the second display region 512, and makes the difference between the luminance of the image region corresponding to the first display region 511 and the luminance of the image region corresponding to the second display region 512 in the image displayed on the display substrate 500 relatively large.

For example, the display layer 510 further includes a plurality of first pixel circuits and a plurality of second pixel circuits (not shown in fig. 1A to 1C, see fig. 2A); the plurality of first pixel circuits are configured to drive the plurality of first light emitting elements 531 in one-to-one correspondence, and the plurality of second pixel circuits are configured to drive the plurality of second light emitting elements 532 in one-to-one correspondence. For example, the plurality of first pixel circuits and the plurality of second pixel circuits have the same circuit structure.

For example, in the case where the data signal (e.g., data voltage) received by the plurality of first pixel circuits that drive the plurality of first light emitting elements is equal to the data signal (e.g., data voltage) received by the plurality of second pixel circuits that drive the plurality of second light emitting elements, the light emission luminance of the plurality of first light emitting elements is smaller than the light emission luminance of the plurality of second light emitting elements, and thus the luminance of an image region corresponding to the first display region 511 in an image displayed by the display substrate may be made lower than a predetermined luminance.

The circuit structures of the plurality of first pixel circuits and the plurality of second pixel circuits can be set according to the actual application requirements. For example, each of the plurality of first pixel circuits and the plurality of second pixel circuits may be implemented as a 2T1C pixel circuit, a 3T1C pixel circuit, a 5T1C pixel circuit, a 7T1C pixel circuit, or other suitable pixel circuits. It should be noted that the 2T1C pixel circuit is a pixel circuit including two transistors and one storage capacitor Cst, and the 7T1C pixel circuit is a pixel circuit including seven transistors and one storage capacitor Cst.

The display substrate 500 shown in fig. 1A and 1B is exemplarily illustrated below with each of the plurality of first pixel circuits and the plurality of second pixel circuits implemented as a 7T1C pixel circuit 580.

Fig. 2A is a schematic structural diagram of a 7T1C pixel circuit 580. As shown in fig. 2A, the 7T1C pixel circuit 580 includes a first transistor CT1, a second transistor CT2, a third transistor CT3, a fourth transistor CT4, a fifth transistor CT5, a sixth transistor CT6, a seventh transistor CT7, and a storage capacitor Cst. For example, the first transistor CT1 to the seventh transistor CT7 are all P-type transistors.

As shown in fig. 2A, a first terminal of the storage capacitor Cst is connected to the first power voltage terminal VDD to receive the first power voltage V1; a second terminal of the storage capacitor Cst is connected to the first node N1; a first terminal of the light emitting element EL is connected to the fourth node N4, and a second terminal of the light emitting element EL is connected to the second power voltage terminal VSS to receive the second power voltage V2; a control terminal of the first transistor CT1 is connected to a first node N1; a first terminal of the first transistor CT1 is connected to the second node N2, and a second terminal of the first transistor CT1 is connected to the third node N3; a first terminal of the second transistor CT2 is connected to the second node N2, and a second terminal of the second transistor CT2 is connected to the data signal terminal DAT to receive a data signal (e.g., data voltage) Vdata; a first terminal of the third transistor CT3 is coupled to the first node N1, and a second terminal of the third transistor CT3 is coupled to the third node N3; a first terminal of the fourth transistor CT4 is connected to the first node N1; a second terminal of the fourth transistor CT4 is connected to the first reset signal terminal Init1 to receive the first reset signal Vinit1 provided by the first reset signal terminal Init 1; a first terminal of the fifth transistor CT5 is connected to the first power voltage terminal VDD, and a first terminal of the fifth transistor CT5 is connected to the second node N2; a first terminal of the sixth transistor CT6 is connected to the fourth node N4; a second terminal of the sixth transistor CT6 is connected to the second reset signal terminal Init2 to receive a second reset signal Vinit 2; a first terminal of the seventh transistor CT7 is connected to the third node N3, and a second terminal of the seventh transistor CT7 is connected to the fourth node N4. For example, the control terminal GAT1 of the second transistor CT2 and the control terminal GAT2 of the third transistor CT3 are both connected to the scan signal terminal GAT (not shown); a control terminal EM1 of the fifth transistor CT5 and a control terminal EM2 of the seventh transistor CT7 are both connected to a light emission control terminal EM (not shown in the figure); a control terminal of the fourth transistor CT4 is configured as a first reset control terminal RST 1; the control terminal of the sixth transistor CT6 is configured as a second reset control terminal RST 2.

For convenience of description, fig. 2A also shows a first node N1, a second node N2, a third node N3, a fourth node N4, and a light emitting element EL.

Fig. 2B is a driving timing diagram of the 7T1C pixel circuit 580 shown in fig. 2A. As shown in fig. 2B, each driving period of the 7T1C pixel circuit 580 includes a first phase T1, a second phase T2, and a third phase T3.

As shown in fig. 2A and 2B, in the first phase t1, the first reset control terminal RST1 receives an active level, and the scan signal terminal GAT, the second reset control terminal RST2 and the emission control terminal EM all receive an inactive level; in this case, the fourth transistor CT4 is turned on, and the second transistor CT2, the third transistor CT3, the fifth transistor CT5, the sixth transistor CT6, and the seventh transistor CT7 are turned off; the fourth transistor CT4 is configured to receive a first reset signal (e.g., a reset voltage) Vinit1 and write the first reset signal Vinit1 to the storage capacitor Cst to reset the storage capacitor Cst; the voltage at the first node N1 is Vinit1, and Vinit1 is, for example, a negative value. For example, after resetting the storage capacitor Cst, the first transistor CT1 is turned on.

As shown in fig. 2A and 2B, in the second phase t2, the scan signal terminal GAT and the second reset control terminal RST2 receive an active level, and the first reset control terminal RST1 and the emission control terminal EM receive an inactive level; in this case, the first transistor CT1, the third transistor CT3 and the sixth transistor CT6 are turned on, and the fourth transistor CT4, the fifth transistor CT5 and the seventh transistor CT7 are turned off; the second transistor CT2 receives the data signal Vdata, and the data signal Vdata is written into the control terminal of the first transistor CT1 through the turned-on first transistor CT1 and the turned-on third transistor CT3, the storage capacitor Cst stores the data signal Vdata written into the control terminal of the first transistor CT1 at the control terminal of the first transistor CT1, and the voltage of the first node N1 is Vdata + Vth; the sixth transistor CT6 is configured to receive a second reset signal (e.g., a reset voltage) Vinit2 and write the second reset signal Vinit2 to the first terminal of the light emitting element EL to reset the first terminal of the light emitting element EL, the voltage of the fourth node N4 is Vinit2, and Vinit2 is, for example, a negative value.

As shown in fig. 2A and 2B, in the third stage t3, the emission control terminal EM receives an active level, and the first reset control terminal RST1, the scan signal terminal GAT, and the second reset control terminal RST2 receive an inactive level; in this case, the first transistor CT1, the fifth transistor CT5, and the seventh transistor CT7 are turned on, and the second transistor CT2, the third transistor CT3, the fourth transistor CT4, and the sixth transistor CT6 are turned off; the first transistor CT1 is configured to control a driving current flowing through the first transistor CT1 and from the first power voltage terminal VDD to the light emitting element EL for driving the light emitting element EL, based on the data signal (e.g., data voltage) Vdata stored in the storage capacitor Cst and the received first power voltage V1; the voltage of the first node N1 is Vdata + Vth, and the voltage of the second node N2 is VDD; the drive current Id can be expressed by the following equation.

Here, k ═ μ × Cox × W/L; μ is the mobility of carriers in the first transistor CT1, Cox is the capacitance of the gate oxide layer of the first transistor CT1, W/L is the width-to-length ratio of the channel of the first transistor CT1, Vth is the threshold voltage of the first transistor CT1, Vth is the gate-source voltage of the first transistor CT1, Vg is the gate voltage of the first transistor CT1, and Vs is the source voltage of the first transistor CT 1.

As can be seen from the above formula, the driving current Id generated by the first transistor CT1 is independent of the threshold voltage of the first transistor CT1, and therefore, the 7T1C pixel circuit 580 shown in fig. 2A and 2B has a threshold compensation function.

At least one embodiment of the present disclosure provides a pixel circuit, a display substrate, and a display device. The pixel circuit includes: the driving circuit comprises a first driving circuit, a second driving circuit, a data writing circuit and a signal storage circuit. The data writing circuit is configured to receive a data signal; the first drive circuit is connected with the data writing circuit and is configured to receive the data signal from the data writing circuit and allow the data signal to be written into the control end of the first drive circuit; the control terminal of the second drive circuit is configured to receive a data signal written to the control terminal of the first drive circuit; the signal storage circuit is configured to store, at the control terminal of the first drive circuit, the data signal written to the control terminal of the first drive circuit; a first terminal of the first driving circuit and a first terminal of the second driving circuit are each configured to receive a first power supply voltage from a first power supply voltage terminal, and a second terminal of the first driving circuit and a second terminal of the second driving circuit are each configured to be electrically connected to a first terminal of the light emitting element; and the first drive circuit and the second drive circuit are configured to control drive currents for driving the light emitting element, which flow through the first drive circuit and the second drive circuit, respectively, and from the first power supply voltage terminal to the light emitting element, based on the data signal stored in the signal storage circuit and the received first power supply voltage.

For example, by providing the second drive circuit in parallel with the first drive circuit, the pixel circuit can increase the value of the drive current flowing through the light emitting element electrically connected to the pixel circuit and the luminance of the light emitting element electrically connected to the pixel circuit.

In the following, a pixel circuit provided according to at least one embodiment of the present disclosure is illustrated in a non-limiting manner by several examples or embodiments, and as described below, different features of these specific examples or embodiments may be combined with each other without mutual conflict, so as to obtain new examples or embodiments, which also belong to the protection scope of the present disclosure.

Fig. 3 is a schematic diagram of a pixel circuit 100 provided by at least one embodiment of the present disclosure. As shown in fig. 3, the pixel circuit 100 includes a first driver circuit 101, a second driver circuit 102, a data write circuit 103, and a signal storage circuit 104.

As shown in fig. 3, the data writing circuit 103 is configured to receive a data signal, for example, the data writing circuit 103 is configured to be connected to the data signal terminal DAT to receive the data signal provided by the data signal terminal DAT. For example, the data signal is a voltage signal.

As shown in fig. 3, the first driving circuit 101 is connected to the data writing circuit 103, and configured to receive a data signal from the data writing circuit 103 and allow the data signal to be written to the control terminal of the first driving circuit 101; the control terminal of the second drive circuit 102 is configured to receive the data signal written to the control terminal of the first drive circuit 101;

as shown in fig. 3, the signal storage circuit 104 is configured to store the data signal written to the control terminal of the first drive circuit 101 at the control terminal of the first drive circuit 101. For example, the signal storage circuit 104 is connected between the first power supply voltage terminal VDD and the control terminal of the first drive circuit 101.

As shown in fig. 3, the first terminal of the first driving circuit 101 and the first terminal of the second driving circuit 102 are each configured to receive a first power supply voltage from a first power supply voltage terminal VDD, and the second terminal of the first driving circuit 101 and the second terminal of the second driving circuit 102 are each configured to be electrically connected to the first terminal of the light emitting element 116; the first drive circuit 101 and the second drive circuit 102 are configured to control drive currents for driving the light emitting element 116, which flow through the first drive circuit 101 and the second drive circuit 102, respectively, and from the first power supply voltage terminal VDD to the light emitting element 116, based on the data signal stored in the signal storage circuit 104 and the received first power supply voltage.

For example, by providing the second driving circuit 102 in parallel with the first driving circuit 101, the first driving circuit 101 and the second driving circuit 102 generate driving currents for driving the light emitting element 116 from the first power supply voltage terminal VDD to the light emitting element 116 through the first driving circuit 101 and the second driving circuit 102, respectively, in a light emitting stage of the pixel circuit 100, whereby the pixel circuit 100 can increase a value of the driving current flowing through the light emitting element 116 electrically connected to the pixel circuit 100 and luminance of the light emitting element 116 electrically connected to the pixel circuit 100.

For example, at least one embodiment of the present disclosure may increase the luminance of the light emitting element 116 electrically connected to the pixel circuit 100 by connecting a simple first driving circuit 101 in parallel to the pixel circuit 100 shown in fig. 2A, so that the luminance of the light emitting element 116 electrically connected to the pixel circuit 100 may be increased while the structure of the pixel circuit 100 is simplified as much as possible.

For example, as shown in fig. 3, the control terminal of the first drive circuit 101 and the control terminal of the second drive circuit 102 are electrically connected to each other, thereby making it possible for the control terminal of the second drive circuit 102 to receive a data signal written to the control terminal of the first drive circuit 101. For example, the control terminal of the first drive circuit 101 and the control terminal of the second drive circuit 102 are directly connected.

For example, as shown in fig. 3, the pixel circuit 100 further includes a compensation connection circuit 105. For example, the data writing circuit 103 writes a data signal to a first terminal of the first drive circuit 101; the compensation connection circuit 105 is connected between the second terminal of the first drive circuit 101 and the control terminal of the first drive circuit 101, and is configured to write the data signal written to the first terminal of the first drive circuit 101 to the control terminal of the first drive circuit 101 via the first drive circuit 101.

For example, by causing the compensation connection circuit 105 to be configured to write the data signal written to the first terminal of the first drive circuit 101 to the control terminal of the first drive circuit 101 via the first drive circuit 101, the threshold characteristic of the first drive circuit 101 may be written to the control terminal of the first drive circuit 101 and stored in the signal storage circuit 104, whereby an adverse effect of the threshold characteristic of the first drive circuit 101 on the drive current generated by the first drive circuit 101, which flows through the first drive circuit 101 and from the first power supply voltage terminal VDD to the light emitting element 116 for driving the light emitting element 116, may be eliminated, that is, by providing the compensation connection circuit 105, the pixel circuit 100 provided by at least one embodiment of the present disclosure may be caused to have a threshold compensation function.

For example, the threshold characteristic of the first driving circuit 101 and the threshold characteristic of the second driving circuit 102 are close, thereby making it possible for the compensation connection circuit 105 to also alleviate the adverse effect of the threshold characteristic of the second driving circuit 102 on the driving current generated by the second driving circuit 102, which flows through the second driving circuit 102 and from the first power supply voltage terminal VDD to the light emitting element 116. For example, the threshold characteristics of the first driving circuit 101 and the second driving circuit 102 being similar means that the ratio of the difference between the threshold of the first driving circuit 101 and the threshold of the second driving circuit 102 to the threshold of the first driving circuit 101 is less than 10% (e.g., less than 5%, 3%, or 1%).

For example, the first drive circuit 101 and the second drive circuit 102 have the same threshold characteristics; in this case, the compensation connection circuit 105 can also eliminate the adverse effect of the threshold characteristic of the second driving circuit 102 on the driving current generated by the second driving circuit 102 and flowing through the second driving circuit 102 from the first power supply voltage terminal VDD to the light emitting element 116, thereby further improving the threshold compensation function of the pixel circuit 100 provided by at least one embodiment of the present disclosure.

For example, as shown in fig. 3, the control terminal GAT1 of the data writing circuit 103 and the control terminal GAT2 of the compensation connection circuit 105 are configured to receive the same scan signal, thereby enabling the data signal written to the first terminal of the first driving circuit 101 to be written to the control terminal of the first driving circuit 101 via turning on the first driving circuit 101 and the compensation connection circuit 105 in the data writing phase of the pixel circuit 100, in which case the data writing phase is also referred to as the data writing and compensation phase of the pixel circuit 100. For example, the control terminal of the compensation connection circuit 105 and the control terminal of the data writing circuit 103 are connected to the same scanning signal terminal GAT or scanning signal line (not shown), whereby the structure of a display substrate including the pixel circuit 100 can be simplified.

For example, as shown in fig. 3, the pixel circuit 100 further includes a first reset circuit 106. The first reset circuit 106 is connected to the signal storage circuit 104; the first reset circuit 106 is configured to receive a first reset signal and write the first reset signal to the signal storage circuit 104 to reset the signal storage circuit 104. For example, the first reset signal may be a first reset voltage. For example, the first reset voltage is a negative value (e.g., -3V) so that the first driving circuit 101 can still be turned on after the memory circuit is reset in the presence of process variations. For example, the first reset circuit 106 may reset the signal storage circuit 104 during a reset phase of the pixel circuit 100.

For example, a first terminal of the first reset circuit 106 is connected to the signal storage circuit 104; a second terminal of the first reset circuit 106 is connected to the first reset signal terminal Init1 for receiving a first reset signal provided by the first reset signal terminal Init 1; the control terminal of the first reset circuit 106 is configured as a first reset control terminal RST 1.

For example, as shown in fig. 3, the pixel circuit 100 further includes a first control circuit 111; the first control circuit 111 is connected between the first terminal of the first drive circuit 101 and the first power supply voltage terminal VDD, and is configured to control whether or not the first drive circuit 101 is electrically connected to the first power supply voltage terminal VDD. For example, by providing the first control circuit 111, the first power supply voltage provided by the first power supply voltage terminal VDD can be prevented from adversely affecting the data signal written to the first terminal of the first driving circuit 101 during the data writing and compensation stages.

For example, as shown in fig. 3, the pixel circuit 100 further includes a second reset circuit 115. The second reset circuit 115 is configured to receive a second reset signal and write the second reset signal to the first terminal of the light emitting element 116 to reset the first terminal of the light emitting element 116. For example, a first terminal of the second reset circuit 115 is connected to a first terminal of the light emitting element 116; a second terminal of the second reset circuit 115 is connected to the second reset signal terminal Init2 to receive a second reset signal provided by the second reset signal terminal Init 2; the control terminal of the second reset circuit 115 is configured as a second reset control terminal RST 2.

For example, the second reset circuit 115 is configured to eliminate the electric charges that may remain on the light emitting element 116. For example, the first terminal of the light emitting element 116 may be reset before the light emitting phase to improve the accuracy of the brightness of the light emitting element 116 and the contrast of the display substrate including the pixel circuit 100. For example, the first terminal of the light emitting element 116 may be reset in a data writing and compensation phase or a reset phase of the pixel circuit 100.

For example, the second reset signal may be a second reset voltage. For example, the second terminal of the light emitting element 116 is connected to the second power voltage terminal VSS to receive the second power voltage provided by the second power voltage terminal VSS. For example, the second reset voltage is equal to the second power supply voltage to prevent the light emitting element 116 from emitting light during the process of resetting the first terminal of the light emitting element 116. For example, the second reset voltage and the second power supply voltage are both negative values (e.g., -3V). For example, the second supply voltage is less than the first supply voltage.

For example, the pixel circuit 100 further includes a third control circuit 113. The third control circuit 113 is connected between the second terminal of the first driving circuit 101 and the first terminal of the light emitting element 116, and is configured to control whether the first driving circuit 101 is electrically connected to the first terminal of the light emitting element 116. For example, by providing the third control circuit 113, the voltage at the second terminal of the first driving circuit 101 and the voltage at the first terminal of the light emitting element 116 can be prevented from interfering with each other in the data writing and compensation stages. For example, by providing the third control circuit 113, it is possible to prevent the voltage at the second terminal of the first drive circuit 101 from adversely affecting the reset of the first terminal of the light emitting element 116 and prevent the light emitting element 116 from emitting light during the data writing and compensation stages. For another example, by providing the third control circuit 113, the voltage at the first terminal of the light emitting element 116 can be prevented from adversely affecting the voltage at the second terminal of the first driving circuit 101 and threshold compensation during the data writing and compensation stages.

For example, as shown in fig. 3, the pixel circuit 100 further includes a second control circuit 112; the second control circuit 112 is connected between the first terminal of the second drive circuit 102 and the first power supply voltage terminal VDD, and is configured to control whether or not the second drive circuit 102 is electrically connected to the first power supply voltage terminal VDD. For example, by providing the second control circuit 112, the second driving circuit 102 can be prevented from driving the light emitting element 116 to emit light in a stage other than the light emitting stage.

For example, as shown in fig. 3, the pixel circuit 100 further includes a fourth control circuit 114; the fourth control circuit 114 is connected between the second terminal of the second driving circuit 102 and the first terminal of the light emitting element 116, and is configured to control whether the second driving circuit 102 is electrically connected to the first terminal of the light emitting element 116. For example, by providing the fourth control circuit 114, the electrical environment experienced by the driving current generated by the first driving circuit 101, which flows through the first driving circuit 101 and from the first power supply voltage terminal VDD to the light emitting element 116, and the driving current generated by the second driving circuit 102, which flows through the second driving circuit 102 and from the first power supply voltage terminal VDD to the light emitting element 116, can be made similar.

For example, the control terminal EM1 of the first control circuit 111, the control terminal EM2 of the second control circuit 112, the control terminal EM3 of the third control circuit 113, and the control terminal EM4 of the fourth control circuit 114 are configured to receive the same light emission control signal, thereby causing the first control circuit 111, the second control circuit 112, the third control circuit 113, and the fourth control circuit 114 to be simultaneously turned on, and causing the first drive circuit 101 and the second drive circuit 102 to synchronously drive the light emitting element 116.

For example, the control terminal EM1 of the first control circuit 111, the control terminal EM2 of the second control circuit 112, the control terminal EM3 of the third control circuit 113, and the control terminal EM4 of the fourth control circuit 114 are connected to the same emission control terminal EM or emission control line (not shown in the drawings), whereby the structure of a display substrate including the pixel circuit 100 can be simplified.

It should be noted that the pixel circuit 100 provided by at least one embodiment of the present disclosure is not limited to include both the second control circuit 112 and the fourth control circuit 114; the pixel circuit 100 provided by at least one embodiment of the present disclosure may further include only one of the second control circuit 112 and the fourth control circuit 114 according to the practical application requirement.

It should be noted that, the embodiment shown in fig. 3 exemplifies at least one embodiment of the present disclosure by taking the pixel circuit having the compensation function, the reset function and the light emission control function at the same time, but at least one embodiment of the present disclosure is not limited thereto, for example, according to the practical application requirement, at least one embodiment of the present disclosure may provide a pixel circuit without the above three functions or with partial functions (i.e., less than three functions) of the above three functions as long as the pixel circuit has the first driving circuit and the second driving circuit connected in parallel.

Fig. 4A is an example of the pixel circuit 100 shown in fig. 3, and fig. 4B is a driving timing chart of the pixel circuit 100 shown in fig. 4A. The pixel circuit 100 shown in fig. 3 is exemplarily described below with reference to fig. 4A and 4B.

As shown in fig. 3 and 4A, the first driving circuit 101 includes a first transistor T1, a control terminal of the first transistor T1 is connected to the first node N1, a first terminal of the first transistor T1 is connected to the second node N2, and a second terminal of the first transistor T1 is connected to the third node N3; the second driving circuit 102 includes a second transistor T2, and a control terminal of the second transistor T2 is connected to the first node N1.

For example, the threshold voltage of the first transistor T1 and the threshold voltage of the second transistor T2 are equal. For example, the width and length of the channel of the first transistor T1 are substantially the same as those of the channel of the second transistor T2, respectively. For example, the width-to-length ratio of the channel (i.e., the ratio of the width to the length of the channel) of the first transistor T1 is substantially the same as the width-to-length ratio of the channel of the second transistor T2; the capacitance of the gate oxide layer of the first transistor T1 is substantially the same as the capacitance of the gate oxide layer of the second transistor T2; the mobility of carriers in the first transistor T1 is substantially the same as the mobility of carriers in the second transistor T2. In some examples, the value of the a parameter and the value of the B parameter being substantially equal means that: the ratio of the difference between the value of the a parameter and the value of the B parameter to the value of the a parameter is less than 3% (e.g., less than 1%). For example, the first transistor T1 and the second transistor T2 may be fabricated in a symmetrical manner.

As shown in fig. 3 and 4A, the data writing circuit 103 includes a third transistor T3, and the signal storage circuit 104 includes a storage capacitor Cst; a first terminal of the third transistor T3 is connected to the second node N2; a second terminal of the third transistor T3 is connected to the data signal terminal DAT to receive the data signal Vdata provided by the data signal terminal DAT; a first terminal of the storage capacitor Cst is connected to the first power voltage terminal VDD, and a second terminal of the storage capacitor Cst is connected to the first node N1.

As shown in fig. 3 and 4A, the compensation connection circuit 105 includes a fourth transistor T4; a first terminal of the fourth transistor T4 is connected to the first node N1, and a second terminal of the fourth transistor T4 is connected to the third node N3.

For example, the control terminal GAT1 of the third transistor T3 and the control terminal GAT2 of the fourth transistor T4 are both connected to the same scan signal terminal GAT or the same scan signal line (not shown).

For example, as shown in fig. 3 and 4A, the light emitting element 116 may be an organic light emitting element EL, and the organic light emitting element EL may be, for example, an organic light emitting diode, but the embodiment of the present disclosure is not limited thereto. For example, the light-emitting element 116 may be an inorganic light-emitting element.

As shown in fig. 3 and 4A, the first reset circuit 106 includes a fifth transistor T5, a control terminal of the fifth transistor T5 is configured as a first reset control terminal RST1, a first terminal of the fifth transistor T5 is connected to the first node N1, and a second terminal of the fifth transistor T5 is connected to the first reset signal terminal Init1 to receive the first reset signal Vinit1 provided by the first reset signal terminal Init 1;

as shown in fig. 3 and 4A, the first control circuit 111 includes a sixth transistor T6, and the second control circuit 112 includes a seventh transistor T7; a first terminal of the sixth transistor T6 is connected to the first power voltage terminal VDD to receive the first power voltage, and a second terminal of the sixth transistor T6 is connected to the second node N2; a first terminal of the seventh transistor T7 is connected to the first power voltage terminal VDD to receive the first power voltage, and a second terminal of the seventh transistor T7 is connected to the first terminal of the second transistor T2.

As shown in fig. 3 and 4A, the second reset circuit 115 includes an eighth transistor T8, the third control circuit 113 includes a ninth transistor T9, and the fourth control circuit 114 includes a tenth transistor T10; a control terminal of the eighth transistor T8 is configured as a second reset control terminal RST2, a first terminal of the eighth transistor T8 is connected to the fourth node N4, and a second terminal of the eighth transistor T8 is connected to the second reset signal terminal Init2 to receive a second reset signal Vinit2 provided by the second reset signal terminal Init 2; a first terminal of the ninth transistor T9 is connected to the third node N3, and a second terminal of the ninth transistor T9 is connected to the fourth node N4; a first terminal of the tenth transistor T10 is connected to the second terminal of the second transistor T2, and a second terminal of the tenth transistor T10 is connected to the fourth node N4; a first terminal of the organic light emitting element EL is connected to the fourth node N4, and a second terminal of the organic light emitting element EL is connected to the second power voltage terminal VSS to receive the second power voltage.

For example, the control terminal EM1 of the sixth transistor T6, the control terminal EM2 of the seventh transistor T7, the control terminal EM3 of the ninth transistor T9, and the control terminal EM4 of the tenth transistor T10 are connected to the same emission control terminal EM or the same emission control line (not shown in the drawings).

For example, the first transistor T1 to the tenth transistor T10 may be all P-type transistors (for example, PMOS transistors, i.e., n-type substrate, P-channel, MOS transistors that carry current by the flow of holes), in which case, the first transistor T1 to the tenth transistor T10 are turned off when receiving a high level (first level) and turned on when receiving a low level (second level, which is smaller than the first level), i.e., the high level (first level) is an inactive level (i.e., a level that turns off the transistors) and the low level (second level) is an active level (i.e., a level that turns on the transistors). It should be noted that the first transistor T1-the tenth transistor T10 are not limited to be implemented as P-type transistors, and one or more of the first transistor T1-the tenth transistor T10 may also be implemented as N-type transistors according to practical application requirements.

It should be noted that the introduction of the first node N1-the fourth node N4 is intended to more conveniently describe the connection relationship between the elements, and it is not necessary to provide, for example, a pad or a pad as an actual node in the pixel circuit 100.

For example, as shown in fig. 4B, each driving period of the pixel circuit 100 shown in fig. 4A includes a reset phase S _ re, a data writing and compensating phase S _ wc, and an emission phase S _ EM.

As shown in fig. 4A and 4B, in the reset phase S _ re, the first reset control terminal RST1 receives an active level, and the scan signal terminal GAT (corresponding to the control terminal GAT1 of the second transistor CT2 and the control terminal GAT2 of the third transistor CT 3), the second reset control terminal RST2, and the emission control terminal EM (corresponding to the control terminal EM1 of the fifth transistor CT5 and the control terminal EM2 of the seventh transistor CT 7) receive an inactive level; in this case, the fifth transistor T5 is turned on, and the third transistor T3, the fourth transistor T4, and the sixth to tenth transistors T6 to T10 are turned off; the fifth transistor T5 is configured to receive the first reset signal Vinit1 and write the first reset signal Vinit1 to the storage capacitor Cst to reset the storage capacitor Cst; the voltage at the first node N1 is Vinit1, and Vinit1 is, for example, a negative value (e.g., -3V). For example, after the first reset signal Vinit1 is written to the storage capacitor Cst, the first transistor T1 and the second transistor T2 are turned on.

As shown in fig. 4A and 4B, in the data writing and compensating phase S _ wc, the scan signal terminal GAT and the second reset control terminal RST2 receive an active level, and the first reset control terminal RST1 and the emission control terminal EM receive an inactive level; in this case, the first to eighth transistors T1 to T4 and T8 are turned on (the first to second transistors T1 and T2 are turned on by the first reset signal Vinit1 written to the storage capacitor Cst), and the fifth to seventh transistors T5 to T7 and T9 and the tenth transistor T10 are turned off; the third transistor T3 receives the data signal Vdata, and the data signal Vdata is written to the control terminal of the first transistor T1 via the turned-on first transistor T1 and fourth transistor T4, the storage capacitor Cst stores the data signal Vdata written to the control terminal of the first transistor T1 at the control terminal of the first transistor T1, the voltage of the first node N1 is Vdata + Vth, where Vth is the threshold voltage of the first transistor; the eighth transistor T8 is configured to receive the second reset signal Vinit2 and write the second reset signal Vinit2 to the first terminal of the organic light emitting element EL to reset the first terminal of the organic light emitting element EL, and the voltage of the fourth node N4 is Vinit2 and Vinit2 is, for example, a negative value (e.g., -3V).

As shown in fig. 4A and 4B, in the emission phase S _ EM, the emission control terminal EM receives an active level, and the first reset control terminal RST1, the scan signal terminal GAT, and the second reset control terminal RST2 receive an inactive level; in this case, the first transistor T1, the second transistor T2, the sixth transistor T6, the seventh transistor T7, the ninth transistor T9, and the tenth transistor T10 are turned on, and the third transistor T3 to the fifth transistor T5, and the eighth transistor T8 are turned off; the first transistor T1 is configured to control a driving current for driving the organic light emitting element EL, which flows through the first transistor T1 and from the first power voltage terminal VDD to the organic light emitting element EL, based on the data signal Vdata stored in the storage capacitor Cst and the received first power voltage VDD, and the second transistor T2 is configured to control a driving current for driving the organic light emitting element EL, which flows through the second transistor T2 and from the first power voltage terminal VDD to the organic light emitting element EL, based on the data signal Vdata stored in the storage capacitor Cst and the received first power voltage VDD; the voltage of the first node N1 is Vdata + Vth, and the voltage of the second node N2 is VDD.

For example, the inventors of the present disclosure determined that the pixel circuit 100 shown in fig. 4A can boost the luminance of the organic light emitting element EL driven by the pixel circuit 100 shown in fig. 4A (compared to the pixel circuit 580 shown in fig. 2A) by performing simulation calculation on a display substrate including the pixel circuit 100 shown in fig. 4A. This is illustrated below in connection with a simulation example.

For example, for an example in which the display substrate includes a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B, each of the red sub-pixel R, the green sub-pixel G, and the blue sub-pixel B includes the pixel circuit 100 shown in fig. 4A, the first power voltage VDD is 4.6V, the voltages Vdata of the data signals received by the red sub-pixel R, the green sub-pixel G, and the blue sub-pixel B are 2.7V, 3.3V, and 2.28V, respectively, and the calculated voltage values of the first node N1-the fourth node N4 and the value of the driving current Id of the pixel circuit of each of the red sub-pixel R, the green sub-pixel G, and the blue sub-pixel B may be referred to table 1.

TABLE 1

As shown in table 1, the ratio of the drive current of the red subpixel R including the pixel circuit 100 shown in fig. 4B to the drive current of the red subpixel R including the pixel circuit 580 shown in fig. 2A is 229.0%, the ratio of the drive current of the green subpixel G including the pixel circuit 100 shown in fig. 4B to the drive current of the green subpixel G including the pixel circuit 580 shown in fig. 2A is 277.1%, and the ratio of the drive current of the blue subpixel B including the pixel circuit 100 shown in fig. 4B to the drive current of the blue subpixel B including the pixel circuit 580 shown in fig. 2A is 252.2%, that is, for the above example, the drive current of the pixel circuit 100 is at least 2.2 times the drive current of the pixel circuit 580.

For example, the inventors of the present disclosure also found through simulation that by increasing (e.g., from 6.5V to 7.0V) the voltage value of the data signal of the pixel circuit 100 (compared to the pixel circuit 580 shown in fig. 2A), the driving current of the pixel circuit 100 can be made to correspond to the driving current of the zero gray scale. For example, the drive current corresponding to the zero gray level is less than 1 picoampere (pA).

It should be noted that, in some examples, in the data writing and compensating phase S _ wc, the eighth transistor T8 receives an inactive level, and in the reset phase S _ re, the eighth transistor T8 receives an active level, that is, the eighth transistor T8 resets the first terminal of the organic light emitting element EL in the reset phase S _ re, instead of resetting the first terminal of the organic light emitting element EL in the data writing and compensating phase S _ wc.

At least one embodiment of the present disclosure also provides a display substrate including any one of the pixel circuits provided by at least one embodiment of the present disclosure. For example, the display substrate may be an organic light emitting diode display panel.

Fig. 5A is an exemplary block diagram of a display substrate 10 provided by at least one embodiment of the present disclosure. As shown in fig. 5A, the display substrate 10 includes at least one pixel circuit 100 provided by at least one embodiment of the present disclosure.

For example, the display substrate 10 includes a display side and a non-display side, and a displayed screen of the display substrate 10 is configured to be displayed on the display side of the display substrate 10, that is, the display side of the display substrate 10 is a light emitting side of the display substrate 10. The display side and the non-display side face each other in a normal direction of the display surface of the display substrate 10 (for example, a direction perpendicular to the display substrate 10).

Fig. 5B is a schematic cross-sectional view of the display substrate 10 shown in fig. 5A. For example, as shown in fig. 5B, the display substrate 10 includes a display layer 260 and a sensing layer 250, the sensing layer 250 being disposed on the non-display side of the display substrate 10; the display layer 260 includes a display area 201, and the display area 201 includes a first display area 210 and a second display area 220; the sensing layer 250 includes a sensor 251, the sensor 251 being overlapped with the first display region 210 in a normal direction of the display surface of the display substrate 10, and configured to receive and process an optical signal passing through the first display region 210.

For example, the sensor 251 may be an image sensor and may be used to capture images of the external environment to which the light collecting surface of the sensor 251 is facing. For example, in the case where the display device 20 including the display substrate 10 is a mobile terminal such as a mobile phone or a notebook, the sensor 251 may be used to implement a camera of the mobile terminal such as a mobile phone or a notebook. For example, the sensor 251 may include an array arrangement of sensing pixels. For example, each light-sensitive pixel may include a light-sensitive detector (e.g., a photodiode, a phototransistor) and a switching transistor (e.g., a switching transistor). The photodiode may convert an optical signal irradiated thereto into an electrical signal, and the switching transistor may be electrically connected to the photodiode to control whether or not the photodiode is in a state of collecting the optical signal and a time of collecting the optical signal.

Fig. 6 is a schematic plan view of an example of the display substrate 10 shown in fig. 5B, and the display substrate 10 shown in fig. 5B corresponds to the AA' line of the display substrate 10 shown in fig. 6.

For example, as shown in fig. 6, the display substrate 10 (e.g., the display layer 260 of the display substrate 10) includes a display area 201 and a peripheral area 202 at least partially surrounding the display area 201; the display area 201 includes a first display area 210 and a second display area 220. For example, as shown in FIG. 6, the second display area 220 at least partially surrounds the first display area 210.

Fig. 7A is a schematic diagram of the partial region REG1 of the first display region 210 of the display substrate 10 shown in fig. 6, and fig. 8A is a schematic diagram of the partial region REG2 of the second display region 220 of the display substrate 10 shown in fig. 6. As shown in fig. 7A, the first display region 210 includes a plurality of first pixel units 270 arranged in an array; as shown in fig. 8A, the second display region 220 includes a plurality of second pixel units 290 arranged in an array.

For example, the plurality of pixel units included in the display region 201 of the display substrate 10 may include pixel units of different colors (e.g., a red pixel unit, a green pixel unit, and a blue pixel unit), and the light emitting areas of the light emitting elements in the pixel units of different colors may be the same or not completely the same. For example, the light emitting area of the light emitting element in the red pixel unit, the light emitting area of the light emitting element in the green pixel unit, and the light emitting area of the light emitting element in the blue pixel unit are different from each other.

Fig. 8B illustrates an example of the first pixel unit 270 illustrated in fig. 7A, fig. 8C illustrates another example of the first pixel unit 270 illustrated in fig. 7A, and fig. 8D illustrates a schematic diagram of the second pixel unit 290 illustrated in fig. 8A.

For example, as shown in fig. 8B and 8C, each of the plurality of first pixel units 270 includes a light emitting element 301; each of the plurality of second pixel units 290 includes a second light emitting element 302. For example, the light emitting element 301 and the second light emitting element 302 may both be organic light emitting elements, and the organic light emitting elements may be, for example, organic light emitting diodes, but the embodiments of the present disclosure are not limited thereto. For example, the light-emitting element 301 and the second light-emitting element 302 may be both inorganic light-emitting elements. For example, the light emitting element 301 and the second light emitting element 302 may be implemented to have the same structure and performance characteristics. For example, each of the plurality of first pixel units 270 includes the number of light emitting elements 301 equal to the number of second light emitting elements 302 (e.g., equal to one) included in each of the plurality of second pixel units 290.

For example, the light emitting area of the light emitting element 301 included in the first pixel unit 270 of the first display region 210 displaying the first color and the light emitting area of the light emitting element 302 included in the second pixel unit 290 of the second display region 220 displaying the first color are different from each other. For example, the first color may be red, green, blue, or other suitable colors.

For example, the unit area distribution density of the plurality of first pixel units 270 in the first display region 210 is less than the unit area distribution density of the plurality of second pixel units 290 in the second display region 220. For example, the distribution density per unit area of the plurality of light emitting elements 301 in the first display region 210 is smaller than the distribution density per unit area of the plurality of second light emitting elements 302 in the second display region 220. For example, since the unit area distribution density of the plurality of first pixel cells 270 in the first display region 210 is less than the unit area distribution density of the plurality of second pixel cells 290 in the second display region 220, the display resolution of the first display region 210 is lower than that of the second display region 220, and thus, the first display region 210 may be referred to as a low resolution region of the display substrate 10.

For example, as shown in fig. 7A, the pitch of two adjacent first pixel units 270 in the first direction D1 is greater than the size of the first pixel unit 270 in the first direction D1, and the pitch of two adjacent first pixel units 270 in the second direction D2 is greater than or equal to the size of the first pixel unit 270 in the second direction D2. For example, the pitch of two adjacent first pixel cells 270 in the first direction D1 is equal to three times the size of the first pixel cell 270 in the first direction D1; the pitch of two adjacent first pixel units 270 in the second direction D2 is equal to the size of the first pixel unit 270 in the second direction D2. For example, the pitch of two adjacent first pixel cells 270 in the first direction D1 is within a range of 280-. In some examples, the pitch of two cells refers to the pitch of the centers of two cells.

For example, as shown in fig. 8A, the pitch of two adjacent second pixel units 290 in the first direction D1 is smaller than the size of the second pixel unit 290 in the first direction D1, and the pitch of two adjacent second pixel units 290 in the second direction D2 is smaller than the size of the second pixel unit 290 in the second direction D2. For example, as shown in fig. 8A, the pitch of two adjacent second pixel units 290 in the first direction D1 is less than one fifth of the size of the second pixel unit 290 in the first direction D1, and the pitch of two adjacent second pixel units 290 in the second direction D2 is less than one fifth of the size of the second pixel unit 290 in the second direction D2.

For example, the display substrate 10 includes a plurality of pixel circuits 100, and the plurality of pixel circuits 100 are electrically connected to the plurality of light emitting elements 301 included in the plurality of first pixel units 270 in a one-to-one correspondence. For example, the display substrate 10 further includes a plurality of pixel circuits 580, and the plurality of pixel circuits 580 are electrically connected to the plurality of second light emitting elements 302 included in the plurality of second pixel units 290 in a one-to-one correspondence manner. As shown in fig. 8D, each second pixel unit 290 includes a second light emitting element 302 and a pixel circuit 580 for driving the second light emitting element 302.

It should be noted that fig. 8B is only used to illustrate that the pixel unit 273 includes the light-emitting element 301 and the pixel circuit 100, fig. 8C is only used to illustrate that the pixel circuit 100 included in the pixel driving unit 281 and the light-emitting element 301 included in the pixel unit 274 are electrically connected to each other, fig. 8D is only used to illustrate that the second pixel unit 290 includes the second light-emitting element 302 and the pixel circuit 580, and the specific shapes and relative positional relationships of the light-emitting element 301, the second light-emitting element 302, the pixel circuit 100 and the pixel circuit 580 are not limited, and the specific shapes and relative positional relationships of the light-emitting element 301, the second light-emitting element 302, the pixel circuit 100 and the pixel circuit 580 may be set according to actual application requirements.

For example, by making the pixel circuits connected to the light emitting elements of the plurality of first pixel units 270 in one-to-one correspondence to be any one of the pixel circuits 100 provided in at least one embodiment of the present disclosure, the light emitting luminance of the light emitting elements of the plurality of first pixel units 270 may be improved, and thus the luminance of the first display region 210 of the display substrate 10 including the plurality of first pixel units 270 may be improved (i.e., the luminance of the low resolution region of the display substrate 10 may be improved).

For example, as shown in fig. 6 and 7A, the first display region 210 includes a first sub display region 211 and a second sub display region 212, which are not overlapped with each other. For example, as shown in fig. 6 and 7A, the first sub-display area 211 at least partially surrounds (e.g., completely surrounds) the second sub-display area 212.

For example, as shown in fig. 7A to 7C, the first sub display region 211 includes a first group 271 of a plurality of first pixel units, and the second sub display region 212 includes a second group 272 of a plurality of first pixel units, the first and second groups being not overlapped with each other. As shown in fig. 7A-7C, a first group 271 of the plurality of first pixel cells 270 includes a first number of first pixel cells 270 (i.e., a first number of pixel cells 273); the second group 272 of the plurality of first pixel cells includes a second number of first pixel cells 270 (i.e., a second number of pixel cells 274).

For example, as shown in fig. 8C, the second group 272 includes pixel cells 274 including only the light emitting elements 301, and not the pixel circuits 100; as shown in fig. 8C and 7A, the pixel circuit 100 for driving the light emitting element 301 included in the pixel unit 274 is provided in the pixel driving unit 281 included in the first sub-display region 211. Correspondingly, the pixel circuits 100 connected in one-to-one correspondence with the light emitting elements of the second group 272 of the plurality of first pixel units are disposed in the first sub-display region 211 (respectively disposed in the plurality of pixel driving units 281 included in the first sub-display region 211). For example, the pixel driving unit 281 does not include a light emitting element.

For example, by causing the pixel circuits 100 connected in one-to-one correspondence with the light emitting elements of the second group 272 of the plurality of first pixel units to be disposed in the first sub-display region 211, it is possible to dispense with disposing the pixel circuits in the second sub-display region 212, whereby the transmittance of the second sub-display region 212 and the aperture ratio of the first pixel units 270 included in the second sub-display region 212 can be improved; in this case, the sensor 251 and the second sub display region 212 may be overlapped in a normal direction of the display surface of the display substrate 10 (see fig. 5B) to reduce the shielding of the elements in the second sub display region 212 from the optical signal incident to the second sub display region 212 and transmitted toward the sensor 251, whereby the signal-to-noise ratio of the image output by the sensor 251 may be improved. For example, the second sub-display region 212 may be referred to as a high light transmission region of a low resolution region of the display substrate 10.

For example, the display substrate 10 further includes a plurality of traces 213. The plurality of wires 213 electrically connect the light emitting elements of the second group 272 of the plurality of first pixel units and the pixel circuits 100 (pixel driving units 281) connected to the light emitting elements of the second group 272 of the plurality of first pixel units in a one-to-one correspondence. For example, each of the plurality of wires 213 may be implemented as a transparent wire, so that the transmittance of the second sub-display region 212 and the signal-to-noise ratio of the image output by the sensor 251 may be further improved.

It should be noted that the pixels connected to the light emitting elements of the second group 272 of the plurality of first pixel units in a one-to-one correspondence are not limited to be disposed in the first sub display region 211, and in some examples, at least a portion (e.g., all) of the pixels connected to the light emitting elements of the second group 272 of the plurality of first pixel units in a one-to-one correspondence may also be disposed in the second sub display region 212 without considering the transmittance of the second sub display region 212 and the aperture ratio of the first pixel units 270 included in the second sub display region 212.

For example, as shown in fig. 8B, the pixel cell 273 included in the first group 271 includes both the light emitting element 301 and the pixel circuit 100. Correspondingly, the pixel circuits 100 in which the light emitting elements of the first group 271 of the plurality of first pixel units are connected in one-to-one correspondence are also disposed in the first sub-display region 211. For example, the pixel circuits 100, in which the light emitting elements of the first group 271 of the plurality of first pixel units are connected in a one-to-one correspondence, are respectively disposed in the corresponding first pixel units 270 of the first group 271 of the plurality of first pixel units, that is, each first pixel unit 270 of the first group 271 of the plurality of first pixel units further includes a pixel circuit for driving the light emitting element. For example, each first pixel unit 270 of the first group 271 of the plurality of first pixel units includes a pixel circuit and a light emitting element as shown in fig. 4A.

For example, as shown in fig. 7A, the first sub-display region 211 may further include a redundant pixel unit 282, as shown in fig. 8E, the redundant pixel unit 282 including a pixel circuit (e.g., the pixel circuit 100) but not including a light emitting element. For example, by providing the redundant pixel unit 282, the electrical environment of the first sub-display region 211 may be made uniform (e.g., the load of resistance and capacitance is made uniform).

For example, the display substrate 10 may further include a plurality of scan signal lines (e.g., gate lines) and a plurality of data lines disposed to cross (e.g., vertically) each other, and a plurality of voltage control lines disposed in parallel with the scan signal lines. For example, each pixel circuit may be connected to a corresponding scan signal line and a corresponding data line, for example, a corresponding scan signal terminal of each pixel circuit may be connected to a corresponding scan signal line, a corresponding data signal terminal of each pixel circuit may be connected to a corresponding data line, and a corresponding first power supply voltage terminal and a corresponding second power supply voltage terminal of each pixel circuit may be connected to a corresponding voltage control line. For example, the plurality of scan signal lines respectively extend in a row direction (e.g., the first direction D1) of the display substrate 10, and the plurality of scan data lines respectively have portions extending in a column direction (e.g., the second direction D2) of the display substrate 10. For example, the first direction D1 intersects (e.g., is perpendicular to) the second direction D2.

For example, as shown in fig. 7A, the data line DL electrically connected to the pixel driving unit 281 for driving the light emitting element is routed from the region between the first sub-display region 211 and the second sub-display region 212 to the first sub-display region 211, and thus, the data line DL further includes a portion extending in the first direction D1.

For example, as shown in fig. 6, the peripheral region 202 includes a driving chip 230. For example, the driving chip 230 may include a data driver, and the data driver of the driving chip 230 may be bonded on the display substrate 10 via a flexible circuit board, and provide a data signal for display to the plurality of data lines via the flexible circuit board, so as to drive the display substrate 10 to implement a display function. For example, the peripheral region 202 may further include a gate driver assembly (GOA) on the array substrate, wherein a plurality of output terminals of the GOA are respectively connected to the plurality of gate lines GL to provide gate scan signals to the plurality of gate lines GL.

Fig. 9 is a schematic plan view of another example of the display substrate 10 shown in fig. 5B, and the display substrate 10 shown in fig. 5B corresponds to an AA' line of the display substrate 10 shown in fig. 9.

The display substrate 10 shown in fig. 9 is similar to the display substrate 10 shown in fig. 6, and therefore, only the differences between the display substrate 10 shown in fig. 9 and the display substrate 10 shown in fig. 6 will be described here, and the descriptions of the same parts will be omitted. The difference between the display substrate 10 shown in fig. 9 and the display substrate 10 shown in fig. 6 includes: the peripheral region 202 of the display substrate 10 shown in fig. 9 includes a pixel driving region 240, and a plurality of pixel circuits electrically connected to the plurality of light emitting elements in a one-to-one correspondence are at least partially (e.g., entirely) disposed in the pixel driving region 240; in this case, the first display region 210 of the display substrate 10 shown in fig. 9 does not need to be provided with the first sub-display region 211 (only the second sub-display region 212 or the high light transmission region of the low resolution region of the display substrate 10 is provided), so that the size of the first display region 210 can be reduced, that is, the size of the low resolution region of the display substrate 10 can be reduced, thereby improving the quality of the image displayed by the display substrate 10.

For example, as shown in fig. 9, the second display area 220 surrounds the first display area 210. For example, as shown in fig. 9, the pixel driving region 240 is juxtaposed with the first display region 210 in a row direction of the display substrate 10 (e.g., corresponding to the first direction D1 of fig. 7A and 8A), the pixel driving region 240 and the first display region 210 being spaced apart by the second display region 220. In this case, the plurality of traces 213 extend in the row direction of the display substrate 10.

It should be noted that the pixel driving region 240 and the first display region 210 are not limited to be arranged in parallel in the row direction of the display substrate 10, and according to the practical application requirement, as shown in fig. 10, the pixel driving region 240 and the first display region 210 may be arranged in parallel in the column direction of the display substrate 10 (for example, corresponding to the second direction D2 in fig. 7A and fig. 8A), in which case, the plurality of routing lines 213 respectively extend along the column direction of the display substrate 10.

For example, in order to make the luminance of the second display region 220 more consistent with the luminance of the first display region 210, the data signal provided to the pixel circuit 100 of the first display region 210 may be additionally compensated on the basis that the pixel circuit 100 provided by at least one embodiment of the present disclosure is adopted in the first display region 210. For example, the timing controller may be used to compensate the data signal supplied to the pixel circuit 100 of the first display region 210.

For example, as shown in fig. 9, the first display region 210 has a circular shape, but embodiments of the present disclosure are not limited thereto. The shape of the first display area 210 can also be implemented as a rectangle or other suitable shapes according to the requirements of the actual application.

Fig. 11 is an exemplary block diagram of a display device 20 provided by at least one embodiment of the present disclosure. As shown in fig. 11, the display device 20 includes any one of the pixel circuits 100 or any one of the display substrates 10 provided in at least one embodiment of the present disclosure.

It should be noted that, for the display substrate and other components of the display device (for example, the image data encoding/decoding device, the clock circuit, etc.), suitable components may be adopted, which are understood by those skilled in the art, and are not described herein again, nor should be taken as a limitation to the present disclosure. The display substrate and the display device can improve the brightness (e.g., the overall brightness) of the low resolution area (i.e., the first display area) of the display substrate and the display device.

Although the present disclosure has been described in detail hereinabove with respect to general illustrations and specific embodiments, it will be apparent to those skilled in the art that modifications or improvements may be made thereto based on the embodiments of the disclosure. Accordingly, such modifications and improvements are intended to be within the scope of this disclosure, as claimed.

The above description is intended to be exemplary of the present disclosure, and not to limit the scope of the present disclosure, which is defined by the claims appended hereto.

Claims

A pixel circuit, comprising: a first drive circuit, a second drive circuit, a data write circuit, and a signal storage circuit,

wherein the data write circuit is configured to receive a data signal;

the first drive circuit is connected with the data writing circuit and is configured to receive the data signal from the data writing circuit and allow the data signal to be written into a control end of the first drive circuit;

the control terminal of the second drive circuit is configured to receive the data signal written to the control terminal of the first drive circuit;

the signal storage circuit is configured to store the data signal written to the control terminal of the first drive circuit at the control terminal of the first drive circuit;

a first terminal of the first driving circuit and a first terminal of the second driving circuit are each configured to receive a first power supply voltage from a first power supply voltage terminal, and a second terminal of the first driving circuit and a second terminal of the second driving circuit are each configured to be electrically connected to a first terminal of a light emitting element; and

the first and second drive circuits are configured to control drive currents for driving the light emitting elements, which respectively flow through the first and second drive circuits and from the first power supply voltage terminal to the light emitting elements, based on the data signal stored in the signal storage circuit and the received first power supply voltage.
The pixel circuit according to claim 1, wherein the control terminal of the first drive circuit and the control terminal of the second drive circuit are electrically connected to each other.
The pixel circuit according to claim 1 or 2, further comprising a compensation connection circuit,

wherein the data writing circuit writes the data signal to a first terminal of the first driving circuit; and

the compensation connection circuit is connected between the second terminal of the first drive circuit and the control terminal of the first drive circuit, and is configured to write the data signal written to the first terminal of the first drive circuit to the control terminal of the first drive circuit via the first drive circuit.
The pixel circuit according to claim 3, wherein a control terminal of the compensation connection circuit and a control terminal of the data write circuit are connected to the same scan signal line.
A pixel circuit according to any one of claims 1-4, further comprising a first reset circuit,

the first reset circuit is connected with the signal storage circuit; and

the first reset circuit is configured to receive a first reset signal and write the first reset signal to the signal storage circuit to reset the signal storage circuit.
A pixel circuit according to any one of claims 1-5, further comprising a first control circuit and a second control circuit,

wherein the first control circuit is connected between a first terminal of the first drive circuit and the first power supply voltage terminal, and is configured to control whether the first drive circuit is electrically connected to the first power supply terminal; and

the second control circuit is connected between the first terminal of the second drive circuit and the first power supply voltage terminal, and is configured to control whether or not the second drive circuit is electrically connected to the first power supply terminal.
The pixel circuit according to claim 6, wherein the control terminal of the first control circuit and the control terminal of the second control circuit are connected to the same emission control line.
A pixel circuit according to any one of claims 1-7, further comprising a second reset circuit,

wherein the second reset circuit is configured to receive a second reset signal and write the second reset signal to the first terminal of the light emitting element to reset the first terminal of the light emitting element.
A pixel circuit according to any one of claims 1-8, further comprising a third control circuit and a fourth control circuit,

wherein the third control circuit is connected between the second terminal of the first driving circuit and the first terminal of the light emitting element, and configured to control whether the first driving circuit is electrically connected to the first terminal of the light emitting element; and

the fourth control circuit is connected between the second terminal of the second driving circuit and the first terminal of the light emitting element, and is configured to control whether the second driving circuit is electrically connected to the first terminal of the light emitting element.
The pixel circuit according to claim 9, wherein the control terminal of the third control circuit and the control terminal of the fourth control circuit are connected to the same emission control line.
A pixel circuit according to any one of claims 1-10, wherein the first driver circuit comprises a first transistor and the second driver circuit comprises a second transistor; and

the threshold voltage of the first transistor and the threshold voltage of the second transistor are equal.
A display substrate comprising at least one pixel circuit as claimed in any one of claims 1 to 11.
The display substrate of claim 12, wherein the at least one pixel circuit comprises a plurality of pixel circuits;

the display substrate is provided with a display area, and the display area comprises a first display area and a second display area;

the first display area comprises a plurality of first pixel units arranged in an array, and the second display area comprises a plurality of second pixel units arranged in an array;

the unit area distribution density of the plurality of first pixel units in the first display area is smaller than the unit area distribution density of the plurality of second pixel units in the second display area;

each of the plurality of first pixel units includes the light emitting element; and

the pixel circuits are electrically connected with the light-emitting elements in a one-to-one correspondence manner.
The display substrate of claim 13, wherein the first display region further comprises a first sub-display region and a second sub-display region that do not overlap with each other;

the first sub-display area comprises a first group of the plurality of first pixel units, the second sub-display area comprises a second group of the plurality of first pixel units, and the first group and the second group are not overlapped with each other; and

pixel circuits connected in one-to-one correspondence with the light emitting elements of the second group of the plurality of first pixel units are disposed in the first sub-display region.
The display substrate according to claim 14, further comprising a plurality of transparent traces, wherein the plurality of transparent traces electrically connect the light emitting elements of the second group of the plurality of first pixel units and the pixel circuits connected to the light emitting elements of the second group of the plurality of first pixel units in a one-to-one correspondence.
The display substrate of claim 13, wherein the display substrate further has a peripheral region at least partially surrounding the display region, the plurality of pixel circuits being at least partially disposed in the peripheral region.
The display substrate of any one of claims 13-16, further comprising a sensor, wherein the sensor is disposed on a non-display side of the display substrate, overlaps the first display region in a direction normal to a display surface of the display substrate, and is configured to receive and process an optical signal passing through the first display region.
A display device comprising a pixel circuit according to any one of claims 1 to 11 or a display substrate according to any one of claims 12 to 17.