JP2004309846A - Electro-optic device, its driving method, and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the electric power consumption of a liquid crystal display device. <P>SOLUTION: A sampling circuit 140 is equipped with (n) pieces of transistor (TR) groups U1 to Un. Each of the TRs groups U1 to Un has three TRs Tr1 to Tr3 of different sizes. The respective TRs Tr1 to Tr3 are selected based on selection signals SS1 to SS3 supplied through control lines L1 to L3. The selection signals SS1 to SS3 are so determined that a potential change of a data line 114 is reflected based on gradation data. As a result, the changing of the sizes of the TRs according to the driving load condition of the data line 114 is made possible. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an electro-optical device, a driving method thereof, and an electronic apparatus.
[0002]
[Prior art]
2. Description of the Related Art Electro-optical devices, for example, liquid crystal display devices using liquid crystal as an electro-optical material are widely used as display devices in place of cathode ray tubes (CRTs) for display units of various information processing apparatuses and liquid crystal televisions.
[0003]
Here, the conventional electro-optical device is configured as follows, for example. That is, a conventional electro-optical device includes a pixel electrode arranged in a matrix, an element substrate provided with a switching element such as a TFT (Thin Film Transistor) connected to the pixel electrode, and a pixel electrode. It comprises an opposing substrate on which opposing opposing electrodes are formed, and a liquid crystal as an electro-optical material filled between the opposing substrates. Then, in such a configuration, when a scanning signal is applied to the switching element via the scanning line, the switching element becomes conductive. When an image signal of a voltage corresponding to the gradation is applied to the pixel electrode via the data line in the conductive state, a charge corresponding to the voltage of the image signal is applied to the liquid crystal layer between the pixel electrode and the counter electrode. Stored. After the charge storage, even if the switching element is turned off, the charge storage in the liquid crystal layer is maintained by the capacitance of the liquid crystal layer itself, the storage capacitance, and the like. As described above, when the switching elements are driven and the amount of charge to be stored is controlled according to the gradation, the alignment state of the liquid crystal changes for each pixel, so that the density changes for each pixel. Therefore, it is possible to perform gradation display.
[0004]
In the above-described electro-optical device, a TFT is generally provided to sample and supply an image signal to a data line. In order to suppress the offset voltage of the TFT for sampling, there is known a technique in which two TFTs having different sizes are provided in parallel for one data line (for example, Patent Document 1).
[0005]
[Patent Document 1]
JP-A-5-75957 (FIG. 3)
[0006]
[Problems to be solved by the invention]
By the way, since the data line is a capacitive load, the potential of the data line changes slowly. For this reason, the size of the TFT for sampling has been determined according to the period during which one data line is selected and the maximum value of the potential change to be written to the data line. That is, the size of the TFT is determined in consideration of the driving ability to change the potential of the data line from the lowest potential to the highest potential in the selection period.
[0007]
However, it is not necessary to always change the potential to be written to the data line from the lowest potential to the highest potential, and such a case is rare. On the other hand, the gate current of the TFT increases as the size increases. For this reason, the conventional electro-optical device has a problem that the current consumption for driving the sampling transistor is large. In addition, this point is the same in the technology described in Patent Document 1.
[0008]
The present invention has been made in view of the above-described circumstances, and has an electro-optical device capable of reducing current consumption for driving a sampling transistor, a driving method thereof, and an electronic apparatus using the same. The task is to provide.
[0009]
[Means for Solving the Problems]
An electro-optical device according to the present invention includes a plurality of scanning lines, a plurality of data lines, and a plurality of pixels provided corresponding to intersections of the plurality of scanning lines and the plurality of data lines. A plurality of transistors provided corresponding to each of the plurality of data lines, and one or more transistors for supplying a data line signal to the data line from the group of transistors based on a selection signal; And a selection signal generating means for generating the selection signal in accordance with the driving load state of the data line.
[0010]
According to the present invention, one or more transistors are selected from the group of transistors according to the driving load state of the data line. Therefore, when the potential of the data line does not need to be largely changed, the driving capability can be kept low. On the other hand, when the potential of the data line needs to be largely changed, the driving capability can be enhanced. That is, the driving ability changes according to the driving load state. The sizes of the transistors constituting the transistor group may be different or the same. When the driving load state is light, a transistor having a small size is selected, or the number of selected transistors is small. Therefore, the current consumed for supplying the data line signal to the data line can be significantly reduced.
[0011]
Here, it is preferable that the selection signal generation unit detects a drive load state of the data line based on image information indicating a gray level to be displayed on the pixel, and generates the selection signal according to a detection result. . Since the data line signal is generated based on the image information, the driving load state of the data line can be detected based on the image information.
[0012]
More specifically, the selection signal generating means generates an evaluation value representing a potential change of the data line based on the image information, and the data line becomes larger as the potential change becomes larger based on the evaluation value. It is preferable to generate the selection signal so that the capability of driving the selection signal is enhanced. An increase in the ability to drive the data line means that, for example, if the transistor group includes a plurality of transistors having different sizes, a transistor having a larger size is selected.
[0013]
A data line driving circuit that generates the data line signal and supplies the data line signal to each of the transistor groups, wherein the selection signal generation unit drives the data line based on a current consumed by the data line driving circuit; Preferably, a load state is detected, and the selection signal is generated according to a detection result. Since the data line driving circuit drives the data lines, it is possible to detect the driving load state of the data lines based on the current consumed therein. Here, the current consumption may be detected directly or indirectly.
[0014]
More specifically, it is preferable that the selection signal generation unit detects a current consumption consumed in the data line driving circuit by detecting a power supply voltage supplied from a power supply to the data line driving circuit. Even a power supply has a predetermined output impedance, so if the current consumption of the data line drive circuit increases, the power supply voltage decreases. Therefore, by monitoring the power supply voltage, it is possible to detect the current consumption of the data line driving circuit, and thus to detect the driving load state of the data line.
[0015]
Here, it is preferable that the selection signal generation unit compares the power supply voltage with a plurality of reference voltages, and generates the selection signal based on a comparison result. Alternatively, the selection signal generation unit compares the power supply voltage with a first reference voltage and a second reference voltage lower than the first reference voltage, and when the power supply voltage exceeds the first reference voltage, The selection signal is generated such that the ability to drive the data line is reduced, and when the power supply voltage is between the first reference voltage and the second reference voltage, the selection signal is maintained to maintain the current state. Preferably, when a signal is generated and the power supply voltage is lower than the second reference voltage, the selection signal is generated so that the ability to drive the data line is higher than the current state.
[0016]
Further, it is preferable that the selection signal generation means switches the selection signal in units of one horizontal scanning period or in units of one frame. This is because, when the selection signal is frequently switched, the current consumption increases.
[0017]
Further, it is preferable that the selection signal generation means generates the selection signal in accordance with the length of a selection period of the data line as a driving load state of the data line. The driving load state of the data line is determined according to the potential change and the length of the selection period. When the selection period of the data line is long, even if a transistor having low driving capability is selected, a predetermined voltage is applied to the data line. This is because the potential can be sufficiently written.
[0018]
Further, in each of a plurality of subfields obtained by dividing one frame, the data line is selected and the data line signal is output, and the data line selection period varies according to the length of the subfield. If a circuit is provided, it is preferable that the selection signal generation means generates the selection signal by identifying the subfield.
[0019]
Further, it is preferable that the transistors constituting the transistor group have different sizes. Many data line driving capabilities can be switched with a small number of transistors.
[0020]
Next, an electronic apparatus according to an aspect of the invention includes the above-described electro-optical device, and includes, for example, a viewfinder, a mobile phone, and a notebook computer used for a video camera.
[0021]
Next, the driving method of the electro-optical device according to the present invention includes a plurality of scanning lines, a plurality of data lines, and a plurality of pixels provided corresponding to intersections of the plurality of scanning lines and the plurality of data lines. And a transistor group provided for each of the plurality of data lines, comprising: a transistor group including a plurality of transistors, wherein the transistor group is controlled according to a driving load state of the data line. And one or more transistors are selected from the above, and a data line signal is supplied to the data line via the selected transistor.
[0022]
According to the present invention, one or more transistors are selected from the group of transistors according to the driving load state of the data line. Therefore, when the potential of the data line does not need to be largely changed, the driving capability can be kept low. On the other hand, when the potential of the data line needs to be largely changed, the driving capability can be enhanced. This makes it possible to significantly reduce the current consumed for supplying the data line signal to the data line.
[0023]
In the electro-optical device driving method described above, the driving load state of the data line includes a potential change of the data line, and the potential of the data line is determined based on image information indicating a gray level to be displayed on a pixel. Generating an evaluation value indicating a change, and selecting one or more transistors from the transistor group such that the larger the potential change is based on the evaluation value, the higher the ability to drive the data line is. preferable.
[0024]
Further, in the above-described method of driving an electro-optical device, the electro-optical device includes a data line driving circuit that generates the data line signal and supplies the data line signal to each of the transistor groups, and consumes the data line driving circuit. Preferably, a driving load state of the data line is detected based on a current, and one or more transistors are selected from the transistor group according to a detection result.
[0025]
In the driving method of the electro-optical device described above, it is preferable that one or more transistors are selected from the transistor group according to a length of a selection period of the data line as a driving load state of the data line. .
[0026]
BEST MODE FOR CARRYING OUT THE INVENTION
<1. First Embodiment>
<1-1: Overall Configuration of Electro-Optical Device>
The electro-optical device according to the present embodiment is a liquid crystal device using liquid crystal as an electro-optical material. As will be described later, an element substrate and a counter substrate are adhered with a certain gap therebetween, and the electro-optical The structure is such that liquid crystal as a material is sandwiched. In addition, a peripheral driver circuit and the like are formed along with a transistor for driving a pixel. Note that the electro-optical device of this example drives a liquid crystal by dividing one frame into first to third subfields SF1 to SF3.
[0027]
FIG. 1 is a block diagram showing an electrical configuration of the electro-optical device. This electro-optical device includes an electro-optical panel AA, a timing signal generation circuit 200, a data conversion circuit 300, a power supply circuit 400, and a data line drive circuit 500. The power supply circuit 400 supplies the common electrode potential LCCOM to the common electrode of the liquid crystal panel AA and also supplies power to each component. In this example, the counter electrode potential LCCOM is a constant potential, but the polarity may be inverted at a predetermined cycle around the reference potential. The liquid crystal panel AA is a normally black panel that displays black when the absolute value of the effective voltage applied to the liquid crystal is low, and displays white when the absolute value of the effective voltage is high.
[0028]
The electro-optical device is supplied with 3-bit gradation data D0 to D2 (image information). The gradation data D0 to D2 represent gradation levels to be displayed on each pixel. Note that the least significant bit is represented by D0 and the most significant bit is represented by D2.
[0029]
The timing signal generation circuit 200 generates various timing signals and clock signals described below according to a vertical synchronization signal Vs, a horizontal synchronization signal Hs, and a dot clock signal DCLK supplied from a higher-level device (not shown). is there. First, the polarity inversion signal FR is a signal indicating the polarity of the voltage applied to the liquid crystal. The high-level polarity inversion signal FR instructs to apply a positive voltage based on the common electrode potential LCCOM, and the low-level polarity inversion signal FR applies a negative voltage based on the common electrode potential LCCOM. To do so. Second, the start pulse DY is a pulse signal output first in each subfield. Third, the clock signal CLY is a signal that defines a horizontal scanning period on the scanning side (Y side). Fourth, the latch pulse LP is a pulse signal output at the beginning of the horizontal scanning period, and is output when the level of the clock signal CLY changes (that is, rises and falls). Fifth, the clock signal CLX is a signal that defines a so-called dot clock.
[0030]
On the other hand, in the display area 101a on the element substrate, a plurality of scanning lines 112 are formed extending in the X (row) direction in the figure, and a plurality of data lines 114 are formed in the Y (column) direction. Are formed extending along. The pixels 110 are provided corresponding to the intersections of the scanning lines 112 and the data lines 114, and are arranged in a matrix. Here, for convenience of explanation, in this embodiment, the total number of the scanning lines 112 is m and the total number of the data lines 114 is n (m and n are integers of 2 or more), and m rows × n columns However, the present invention is not limited to this.
[0031]
The data conversion circuit 300 converts the grayscale data D0 to D2 into a binary signal Ds based on various timing signals, and generates the selection signals SS1 to SS3. The binary signal Ds instructs ON / OFF of each pixel. When the binary signal Ds is “1”, it is turned on (white), and when the binary signal Ds is “0”, it is turned off (black). Instruct. That is, in this example, the absolute value of the effective voltage applied to the liquid crystal is binary, and when Ds = 1, the effective voltage that maximizes the transmittance of the liquid crystal is written into the liquid crystal, while when Ds = 0, An effective voltage that minimizes the transmittance of the liquid crystal is written in the liquid crystal. The selection signals SS1 to SS3 are signals indicating a transistor to be selected in each of the transistor groups U1 to Un included in the sampling circuit 140 described later.
[0032]
The data line driving circuit 500 includes an X shift register. Then, the latch signal LP which becomes active at the beginning of the horizontal scanning period is sequentially transferred based on the clock signal CLX to generate the enable signals EN1 to ENn. The data line driving circuit 500 generates data line signals d1 to dn based on the binary signal Ds, the polarity inversion signal FR, and the enable signals EN1 to ENn.
[0033]
The scanning line driving circuit 130 is a so-called Y shift register, transfers a start pulse DY supplied at the beginning of each subfield in accordance with a clock signal CLY, and sends the scanning signals G1, G2, G3,..., Gm are sequentially and exclusively supplied.
[0034]
<1-2: Configuration of Pixel>
As a specific configuration of the pixel 110, for example, a configuration illustrated in FIG. In this configuration, the gate of the transistor (MOS type FET) 116 is connected to the scanning line 112, the source is connected to the data line 114, the drain is connected to the pixel electrode 118, respectively, and between the pixel electrode 118 and the counter electrode 108. A liquid crystal layer as an electro-optical material is sandwiched between the liquid crystal layers 105. Here, the counter electrode 108 is a transparent electrode formed on one surface of the counter substrate so as to actually face the pixel electrode 118 as described later. It is to be noted that a counter electrode potential LCCOM is applied to the counter electrode 108. In this example, the counter electrode potential LCCOM is a constant potential. However, the polarity may be inverted every frame around a predetermined reference potential. In addition, a storage capacitor 119 is formed between the pixel electrode 118 and the counter electrode 108 to prevent leakage of charges stored in the liquid crystal layer. In this embodiment, the storage capacitor 119 is formed between the pixel electrode 118 and the counter electrode 108, but may be formed between the pixel electrode 118 and the ground potential GND or between the pixel electrode 118 and the gate line.
[0035]
Here, in the configuration shown in FIG. 2A, since only one channel type is used as the transistor 116, an offset voltage is required. However, as shown in FIG. With a configuration in which a channel transistor and an N-channel transistor are complementarily combined, the influence of an offset voltage can be canceled. However, in this complementary configuration, it is necessary to supply mutually exclusive levels as scanning signals, so that two scanning lines 112a and 112b are required for one row of pixels 110. Note that these transistors are constituted by TFTs.
[0036]
<1-3: Sampling circuit>
FIG. 3 shows a detailed configuration of the sampling circuit 140. The sampling circuit 140 includes transistor groups U1 to Un, AND circuits A1 to A3 provided corresponding to the respective transistor groups U1 to Un, and control lines L1 to L3.
[0037]
Since the transistor groups U1 to Un have the same configuration, here, the transistor group U1 will be described. The transistor group U1 includes three transistors Tr1, Tr2, and Tr3. These transistors Tr1, Tr2, and Tr3 are formed of TFTs and are formed simultaneously with the transistor 116 and the like formed in the display area 101a in the same process. The sizes (gate widths) of the transistors Tr1, Tr2, and Tr3 are weighted at 1: 2: 4. Therefore, the driving capability and the gate current increase in the order of Tr1 → Tr2 → Tr3.
[0038]
The enable signal EN1 is supplied to one input terminal of the AND circuits A1 to A3, and the selection signals SS1 to SS3 are supplied to the other input terminals via control lines L1 to L3, respectively. Output signals of the AND circuits A1 to A3 are supplied to gates of the transistors Tr1 to Tr3, respectively.
[0039]
Therefore, when the enable signal EN1 becomes active (high level), the transistor that supplies the data line signal d1 to the data line 114 is selected from the transistor group U1 based on the selection signals SS1 to SS3, and the selected transistor is set to the selected transistor. The data line signal d1 is supplied to the data line 114 via the data line. The control lines L1 to L3 and the AND circuits A1 to A3 function as selection means for selecting a transistor that supplies the data line signals d1 to dn to the data line 114 from among the transistor groups U1 to Un.
[0040]
For example, when the selection signals SS1 and SS3 are active, the selection signal SS2 is inactive, and the enable signal EN1 becomes active, the transistors Tr1 and Tr3 are selected, and the data line signal d1 is supplied to the data line 114 via the transistors Tr1 and Tr3. Is done.
[0041]
As described above, the sampling circuit 140 can select the transistors Tr1 to Tr3 that supply the data line signals d1 to dn to the respective data lines 114 based on the selection signals SS1 to SS3. When the driving load state of the data line 114 is heavy and the potential needs to be largely changed, the transistors Tr1 to Tr3 are selected from the transistor groups U1 to Un so that the driving capability is increased. When the driving load state is light and its potential hardly needs to be changed, the transistors Tr1 to Tr3 can be selected from the transistor groups U1 to Un so that the driving capability is reduced. To turn on the transistors Tr1 to Tr3, it is necessary to supply a gate current. Generally, the gate current increases as the transistor size increases.
[0042]
According to the present embodiment, the transistors Tr1 to Tr3 can be selected according to the driving load state of the data line 114. Therefore, it is possible to prevent unnecessary consumption of the gate current and reduce power consumption. it can. Further, since the sizes of the transistors Tr1 to Tr3 constituting the transistor groups U1 to Un are weighted, a large number of driving capabilities can be realized using a small number of transistors. As a result, it is possible to finely control the value of the gate current.
[0043]
<1-4: Data conversion circuit>
In order to write a predetermined potential to the pixel electrode 118 for each of the first to third subfields SF1 to SF3, it is necessary to convert the gradation data D0 to D2 corresponding to the pixel in some form. Further, it is necessary to generate the selection signals SS1 to SS3 according to the driving load state of the data line 114.
[0044]
The data conversion circuit 300 shown in FIG. 4 is provided for this purpose. The data conversion circuit 300 includes a write address control unit 310, a decoder 320, a read address control unit 330, a memory 340, and a selection signal generation circuit 350.
[0045]
The decoder 320 converts the grayscale data D0 to D2 into subfield data SD1 to SD3. Subfield data SD1 indicates a potential to be selected in first subfield SF1, subfield data SD2 indicates a potential to be selected in second subfield SF2, and subfield data SD3 indicates a potential to be selected in third subfield SF3. Indicate the potential to be applied. The subfield data SD1 to SD3 are 1-bit data. In this example, each period of the first to third subfields SF1 to SF3 is weighted at 1: 2: 4. Therefore, the subfield data SD1 is composed of the gradation data D0, the subfield data SD2 is composed of the gradation data D1, and the subfield data SD3 is composed of the gradation data D2.
[0046]
The memory 340 has storage areas corresponding to the first to third subfields SF1 to SF3. Each storage area has an m × n memory space corresponding to each pixel (m rows × n columns) formed in the display area 101a of the element substrate.
[0047]
The write address control unit 310 supplies the write enable signal WE and the write address WAD to the memory 340 in synchronization with the vertical synchronization signal Vs, the horizontal synchronization signal Hs, and the dot clock signal DCLK. That is, the write address control unit 310 counts up the dot clock signal DCLK, outputs the count result as the write address signal WAD, and activates the write enable signal WE every time the value of the write address signal WAD is determined. . The count result of the write address control unit 310 is reset every time the vertical synchronization signal Vs becomes active. As a result, the write address WAD for sequentially accessing the m × n memory spaces of each storage area is supplied to the memory 340, and the subfield data SD1 to SD3 are stored in the memory corresponding to the display position in each corresponding storage area. Stored sequentially in space.
[0048]
When the first to third subfield periods are started, the read address control unit 330 outputs an address signal RAD for accessing the memory space of the corresponding display row. The address signal RAD is incremented "n-1" times in synchronization with the clock signal CLX according to the number of display columns. As a result, an address signal RAD for sequentially designating the first to n-th memory areas for the corresponding display row is generated. Also, the read enable signal RE becomes active in synchronization with the determination of the address signal RAD. As a result, the binary signals Ds are sequentially read from the memory 340.
[0049]
Next, the selection signal generation circuit 350 detects the drive load state of the data line 114 based on the subfield data SD1 to SD3 and the polarity inversion signal FR stored in the memory 340, and selects the selection signal according to the detection result. Generate SS1 to SS3.
[0050]
In the present embodiment, a change in the potential of the data line 114 is detected as a driving load state. More specifically, the potential change of the data line 114 is estimated from the subfield data SD1 to SD3 (image information) and the polarity inversion signal FR, and the selection signals SS1 to SS3 are generated based on the evaluation value according to the potential change. You. The scanning lines 112 are sequentially selected, and the data line signals d1 to dn are supplied to the respective data lines 114 during the selection period of a certain scanning line 112. Therefore, focusing on one data line 114, the potential is written to the data line 114 during the previous scanning line 112 selection period and the potential is written to the data line 114 during the current scanning line 112 selection period. It can be evaluated by comparing potentials.
[0051]
FIG. 5 shows the relationship among the evaluation value, the binary signal Ds, the polarity inversion signal FR, and the potential of the data line when the polarity is inverted for each data line and each frame. FIG. 6 shows a potential change in each column. In this example, the potential “VC”, the potential “VC”, the potential “VL”, and the potential “VH” are written in the first to fourth columns in the M line, and the first to fourth columns in the M + 1 line. Are written with potentials “VC”, “VH”, “VC”, and “VH”. The evaluation value corresponding to each data line 114 is “0” when there is no change in the potential, “1” when a change between the potential VC and the potential VL or the potential VH, and “1” when a change between the potential VL and the potential VH. Assume “2”. In this case, assuming a signal FR ′ that is “−1” when the polarity inversion signal FR is “0” and “+1” when the polarity inversion signal is “1”, the evaluation value P can be obtained according to the following equation. .
P = | Ds (M) * FR '(M) -Ds (M + 1) * FR' (M + 1) | Equation 1
In this equation, (M) represents M lines, and (M + 1) represents M + 1 lines.
[0052]
For example, focusing on the second column, Ds (M) = 0 and FR '(M) = 1 in the M line, Ds (M) = 1, FR' (M) = 1 in the M + 1 line, and P = 1 Get. Then, the selection signals SS1 to SS3 are generated by calculating the sum of the evaluation values for each horizontal period and comparing the sum with a plurality of reference values.
[0053]
The maximum load when the polarity is inverted for each data line and for each frame is when the value of the binary signal Ds is inverted for each line as shown in FIG. In this case, the selection signals SS1 to SS3 are all activated, and the data lines 114 are driven using all the transistors Tr1 to Tr3.
[0054]
FIG. 8 shows the relationship among the evaluation value, the binary signal Ds, the polarity inversion signal FR, and the data line potential when the polarity is inverted for each scanning line and each dot. FIG. 9 shows a potential change in each column. In this example, the potential “VC”, the potential “VC”, the potential “VL”, and the potential “VH” are written in the first to fourth columns in the M line, and the first to fourth columns in the M + 1 line. Are written with potentials “VC”, “VL”, “VC”, and “VL”. Also in this case, the evaluation value is calculated in accordance with Equation 1 described above.
[0055]
For example, focusing on the fourth column, Ds (M) = 1 and FR '(M) = 1 in the M line, Ds (M) = 1 and FR' (M) = 0 in the M + 1 line, and the evaluation value P = 2. Then, the selection signals SS1 to SS3 are generated by calculating the sum of the evaluation values for each horizontal period and comparing the sum with a plurality of reference values.
[0056]
In addition, the maximum load when the polarity is inverted for each scanning line and each dot is when the value of the binary signal Ds is all “1” as shown in FIG. In this case, the selection signals SS1 to SS3 are all activated, and the data lines 114 are driven using all the transistors Tr1 to Tr3. In this example, the polarity inversion is detected based on the polarity inversion signal FR, and the selection signals SS1 to SS3 are generated in consideration of the polarity inversion. However, the polarity inversion sequence is determined by the vertical synchronization signal Vs, the horizontal synchronization signal Hs, Of course, the detection may be performed based on the dot clock signal DCLK or the like according to a predetermined rule, and the selection signals SS1 to SS3 may be generated in consideration of the detection. Alternatively, a plurality of types of sequences may be stored and selected. Thereby, it is possible to easily cope with a plurality of polarity inversions.
[0057]
<1-5: Operation of electro-optical device>
FIG. 11 is a timing chart for explaining the operation of the electro-optical device. First, the start pulse DY is supplied at the start of each subfield.
[0058]
Here, in the frame (1F), when the start pulse DY is supplied, the scan signals G1, G2, G3,..., Gm are transferred in the period (t) by the transfer according to the clock signal CLY in the scan line drive circuit 130. They are sequentially and exclusively output. Note that the period (t) is set to a period shorter than the shortest first subfield SF1.
[0059]
The scanning signals G1, G2, G3,..., Gm each have a pulse width corresponding to a half cycle of the clock signal CLY, and the scanning signal G1 corresponding to the first scanning line 112 counted from the top is After the start pulse DY is supplied, the clock signal CLY first rises and is output with a delay of at least a half cycle of the clock signal CLY. Therefore, one shot (G0) of the latch pulse LP is supplied to the data line driving circuit 500 from the supply of the start pulse DY to the output of the scanning signal G1.
[0060]
Therefore, the case where one shot (G0) of the latch pulse LP is supplied will be examined. First, when one shot (G0) of the latch pulse LP is supplied to the data line driving circuit 500, the enable signal EN1, EN2, EN3,..., ENn is transferred by the data line driving circuit 500 in accordance with the clock signal CLX. Are sequentially and exclusively output during the horizontal scanning period (1H). Each of the enable signals EN1, EN2, EN3,..., ENn has a pulse width corresponding to a half cycle of the clock signal CLX.
[0061]
Then, in synchronization with the period in which each of the enable signals EN1, EN2, EN3,..., ENn becomes active, data line signals d1 to dn having potentials selected based on the binary signal Ds and the polarity inversion signal FR are generated. The data is supplied to the data line 114 via the transistor groups U1 to Un.
[0062]
Here, the selection signals SS1 to SS3 change every one horizontal scanning period. For example, in the period T1, the transistors Tr1 and Tr3 are selected, and in the period T2, the transistors Tr2 and Tr3 are selected. As a result, it is possible to determine which of the transistor groups U1 to Un is to be used for driving in each horizontal scanning period, and it is possible to change the transistor size according to the driving load state of the data line 114. Become. The cycle of switching the selection signals SS1 to SS3 is arbitrary, and may be switched in one frame cycle. However, since the potential of the data line 114 is inverted around the reference potential due to the polarity inversion, it is preferable to switch the selection signals SS1 to SS3 in synchronization with the polarity inversion cycle.
[0063]
<1-6: Configuration example of liquid crystal panel>
Next, the overall configuration of the liquid crystal panel according to the above-described electrical configuration will be described with reference to FIGS. Here, FIG. 12 is a perspective view showing a configuration of the liquid crystal panel AA, and FIG. 13 is a sectional view taken along line ZZ ′ in FIG.
[0064]
As shown in these drawings, the liquid crystal panel AA includes an element substrate 151 such as a glass or a semiconductor on which the pixel electrodes 118 and the like are formed, and a transparent counter substrate 152 such as a glass on which the counter electrodes 158 and the like are formed. A gap is maintained by a sealing material 154 mixed with a spacer 153 so that electrode forming surfaces are opposed to each other, and a liquid crystal 105 as an electro-optical material is sealed in the gap. Note that the sealant 154 is formed along the periphery of the counter substrate 152, but is partially open to seal the liquid crystal 105. Therefore, after the liquid crystal 105 is sealed, the opening is sealed by the sealing material 156.
[0065]
Here, a scanning line driving circuit 130 is formed on one side outside the sealing material 154 and one side opposite to the opposite side of the element substrate 151, and the scanning lines 112 extending in the X direction are formed on both sides. It is configured to be driven from. Further, the above-described sampling circuit 140 is formed on the element substrate 151 and drives the data lines 114 extending in the Y direction. Further, a plurality of connection electrodes 157 are formed on one side to input various signals from the timing signal generation circuit 200 and the binary signal Ds.
[0066]
On the other hand, the opposing electrode 158 of the opposing substrate 152 is electrically connected to the element substrate 151 by a conductive material provided in at least one of four corners of a portion bonded to the element substrate 151. In addition, the opposing substrate 152 is provided with, for example, first, color filters arranged in a stripe shape, a mosaic shape, a triangle shape, or the like according to the use of the liquid crystal panel AA. Thirdly, a black matrix such as resin black in which a metal material such as nickel or nickel or carbon or titanium is dispersed in a photoresist is provided. Third, a backlight for irradiating the liquid crystal panel AA with light is provided. In particular, in the case of application for color light modulation, a black matrix is provided on the counter substrate 152 without forming a color filter.
[0067]
In addition, on the opposing surfaces of the element substrate 151 and the opposing substrate 152, an alignment film or the like rubbed in a predetermined direction is provided, respectively, and on the back side thereof, a polarizing plate (not shown) corresponding to the alignment direction is provided. Are respectively provided. However, if a polymer-dispersed liquid crystal in which fine particles are dispersed in a polymer is used as the liquid crystal 105, the above-described alignment film, polarizing plate, and the like become unnecessary, and the light use efficiency is increased. This is advantageous in reducing power consumption.
[0068]
Note that a part or all of peripheral circuits such as the data line driving circuit 500 and the timing signal generating circuit 200 may be replaced with a driving IC chip mounted on a film using TAB (Tape Automated Bonding) technology, for example, using an element substrate 151. May be electrically and mechanically connected via an anisotropic conductive film provided at a predetermined position, or the driving IC chip itself may be mounted on the element substrate 151 by using COG (Chip On Grass) technology. It may be configured to be electrically and mechanically connected to a predetermined position via an anisotropic conductive film. Further, the timing signal generation circuit 200 and the data conversion circuit 300 may be formed on the element substrate 151.
[0069]
<2. Second Embodiment>
In the first embodiment, the driving load state of the data line 114 is detected based on the image information. However, the electro-optical device according to the second embodiment uses the current consumption of the data line driving circuit 500 to change the driving load state of the data line 114. Is to be detected.
[0070]
FIG. 14 is a block diagram illustrating an electrical configuration of the electro-optical device according to the second embodiment. The electro-optical device according to the second embodiment has the same configuration as that of FIG. 1 except that a data conversion circuit 301 having no selection signal generation circuit 350 is used instead of the data conversion circuit 300 and a load current detection circuit 600 is provided. Has the same configuration as the electro-optical device of the first embodiment shown in FIG.
[0071]
The load current detection circuit 600 detects the current consumption of the data line drive circuit 500 based on the power supply voltage VDDX, and generates the selection signals SS1 to SS3 according to the detection result. The output impedance of the power supply 400 is ideally preferably zero, but a real device has a constant output impedance. Therefore, when the current consumption of the data line driving circuit 500 increases, the power supply voltage VDDX decreases. In particular, in a portable electronic device such as a mobile phone, the driving capability of the power supply 400 is not so high, and when the current consumption increases, the power supply voltage may decrease. Therefore, the load current detection circuit 600 indirectly detects the current consumption by detecting the power supply voltage VDDX instead of detecting the current consumption of the data line drive circuit 500.
[0072]
Hereinafter, two embodiments will be described as specific examples of the configuration of the load current detection circuit 600. FIG. 15 is a circuit diagram of the load current detection circuit 600 according to the first embodiment, and FIG. 16 is a timing chart showing the operation. The load current detection circuit 600 includes comparators CP1 to CP6 and an arithmetic circuit 610. The power supply voltage VDDX is supplied to the positive input terminals of the comparators CP1 to CP6, while the reference voltages Vref1 to Vref6 are supplied to their negative input terminals.
[0073]
Reference voltages Vref1 to Vref6 have a relationship of Vref1>Vref2>...Vref5> Vref6, as shown in FIG. Therefore, the power supply voltage VDDX can be determined in seven stages based on the output signals C1 to C6 of the comparators CP1 to CP6. The arithmetic circuit 610 generates selection signals SS1 to SS3 based on the output signals C1 to C6. For example, when the output signals C1 to C6 are all “1”, the value of the power supply voltage VDDX is ranked as the highest voltage. In this case, the arithmetic circuit 610 sets the selection signal SS1 to high level (1) and sets the selection signals SS2 and SS3 to low level (0). As a result, the data line signals d1 to dn are supplied to each data line 114 using only the transistor Tr1 having the smallest size.
[0074]
For example, in the example shown in FIG. 16, in the period t1, the power supply voltage VDDX is between the reference voltage Vref4 and the reference voltage Vref3, and SS1 = SS2 = 0 and SS3 = 1. Thereafter, SS1 = SS2 = 1 and SS3 = 0 in the period t2, SS1 = SS3 = 0 and SS2 = 1 in the period t3, and SS1 = SS2 = SS3 = 1 in the period t7. In the first mode, a transistor can be selected from each of the transistor groups U1 to Un according to a change in the power supply voltage VDD.
[0075]
FIG. 17 is a circuit diagram of the load current detection circuit 600 according to the second embodiment, and FIG. 18 is a timing chart showing the operation. The load current detection circuit 600 includes comparators CP1 and CP2, flip-flops FF1 and FF2, and an arithmetic circuit 620. The negative input terminal of the comparator CP1 is supplied with a first reference voltage VrefD as a reference for decreasing the transistor size, while the negative input terminal of the comparator CP2 is supplied with a first reference voltage VrefU as a reference for increasing the transistor size. .
[0076]
Output signals C1 and C2 are supplied to data input terminals D of the flip-flops FF1 and FF2, and a latch pulse LP of one horizontal scanning cycle is supplied to a clock input terminal. The output signals C1 and C2 are latched by the latch pulse LP and supplied to the arithmetic circuit 620. The arithmetic circuit 620 generates the selection signals SS1 and SS2 based on the output signals Q1 and Q2 of the flip-flops FF1 and FF2.
[0077]
Specifically, when Q1 = 0, the transistors Tr1 to Tr3 are selected so as to be larger than the original transistor size. For example, if the selection signals SS1 to SS3 are SS1 = 1, SS2 = SS3 = 0, the transistor size is increased by one step by setting SS1 = 0, SS2 = 1, SS3 = 0.
[0078]
When Q1 = 1 and Q2 = 0, the selection signals SS1 to SS3 are generated so as to maintain the original transistor size. Further, when Q2 = 1, the transistors Tr1 to Tr3 are selected so as to be smaller than the original transistor size. For example, if the selection signals SS1 to SS3 are SS1 = 0 and SS2 = SS3 = 1, the transistor size is reduced by one step by setting SS1 = SS3 = 1 and SS2 = 0.
[0079]
For example, in the example shown in FIG. 18, if the selection stage in the period t1 is “4”, “4” in the period t2, “3” in the period t3, “2” in the period t4, and “2” in the period t5. 1 "," 1 "in the period t6 to t8," 2 "in the period t9, and" 3 "in the period t10.
[0080]
According to the second aspect, the transistor size can be gently switched based on the current consumption of the data line driving circuit 500. If the transistor size is suddenly switched from the minimum to the maximum, the driving ability of the data line signals d1 to dn suddenly changes greatly, so that a person may feel as if the brightness of the screen has changed. According to the second aspect, since the transistor size can be changed gradually, it is possible to prevent giving an unnatural impression to the user.
[0081]
<3. Third embodiment>
FIG. 19 is a block diagram illustrating a configuration of an electro-optical device according to the third embodiment. The electro-optical device according to the third embodiment uses a data conversion circuit 301 having no selection signal generation circuit 350 instead of the data conversion circuit 300, and uses the selection signals SS1 to SS3 instead of the timing signal generation circuit 200. The configuration is the same as that of the electro-optical device according to the first embodiment shown in FIG. 1 except that a timing signal generating circuit 201 for generating the signal is provided.
[0082]
Incidentally, the first to third subfields SF1 to SF3 have different periods. Therefore, the period for selecting the scanning line 112 and the period for selecting the data line 114 can be changed according to the length of each subfield.
[0083]
In the present embodiment, the selection period of the data line 114 is set to be longer in the order of the first subfield SF1 → the second subfield SF2 → the third subfield SF3. FIG. 20 shows the relationship between the selection period (the period during which the enable signals EN1 to ENn are active), the potential of the data line 114, and the selected transistors Tr1 to Tr3. As shown in this figure, the selection periods Ta to Tc become longer in the order of Ta → Tb → Tc. Then, in each of the selection periods Ta to Tc, it is necessary to write a predetermined potential to the data line 114. In order to change the potential of the data line 114 in a shorter time, it is necessary to supply the data line signals d1 to dn to the data line 114 using a transistor having a large driving capability. In other words, it can be said that the length of the selection period Ta to Tc is the driving load state of the data line 114.
[0084]
In this example, the transistor Tr3 is turned on during the selection period Ta of the first subfield SF1, the transistor Tr2 is turned on during the selection period Tb of the second subfield SF2, and the transistor Tr1 is turned on during the selection period Tc of the third subfield SF3. To generate the selection signals SS1 to SS3. That is, the timing signal generation circuit 200 generates the selection signals SS1 to SS3 according to the length of each subfield or the length of the selection period of the data line 114.
[0085]
Thereby, a transistor necessary and sufficient to change the potential of the data line 114 can be selected from the transistor groups U1 to Un in accordance with the driving load state, so that a predetermined potential is sufficiently written to the data line 114. In addition, current consumption can be reduced.
[0086]
<4. Application>
<4-1: Configuration of Element Substrate>
In each of the above-described embodiments, the element substrate 151 of the liquid crystal panel AA is formed of a transparent insulating substrate such as glass, a silicon thin film is formed on the substrate, and the source, drain, and channel are formed on the thin film. Although the formed TFT constitutes a pixel switching element, an element of the data line driving circuit 500, and an element of the scanning line driving circuit 130, the present invention is not limited to this.
[0087]
For example, the element substrate 151 is formed using a semiconductor substrate, and a switching element of a pixel or an element of various circuits is formed using an insulated gate field effect transistor in which a source, a drain, and a channel are formed on the surface of the semiconductor substrate. Is also good. When the element substrate 151 is formed using a semiconductor substrate as described above, it cannot be used as a transmissive display panel. Therefore, the pixel electrode 118 is formed of aluminum or the like and used as a reflective type. Alternatively, the element substrate 151 may simply be a transparent substrate and the pixel electrode 118 may be of a reflection type.
[0088]
Further, in the above-described embodiment, the switching element of the pixel is described as a three-terminal element represented by a TFT, but may be configured with a two-terminal element such as a diode. However, when a two-terminal element is used as a switching element of a pixel, the scanning line 112 is formed on one substrate, the data line 114 is formed on the other substrate, and the two-terminal element is connected to the scanning line 112 or the data line. It is necessary to form between any one of the pixel electrodes 114 and the pixel electrode. In this case, the pixel includes a liquid crystal and a two-terminal element connected in series between the scanning line 112 and the data line 114.
[0089]
Further, the present invention has been described as an active matrix type liquid crystal display device. However, the present invention is not limited to this, and is also applicable to a passive type using STN (Super Twisted Nematic) liquid crystal. Further, as the electro-optical material, in addition to liquid crystal, the present invention can be applied to a display device that uses an electroluminescence element or the like to perform display by the electro-optical effect. That is, the present invention is applicable to all electro-optical devices having a configuration similar to the above-described liquid crystal device.
[0090]
<4-2: Electronic device>
Next, some examples in which the above-described liquid crystal device is used in specific electronic devices will be described.
<4-2-1: Mobile computer>
First, an example in which this liquid crystal panel is applied to a mobile personal computer will be described. FIG. 21 is a perspective view showing the configuration of this personal computer. In the figure, a computer 1200 includes a main body 1204 having a keyboard 1202 and a liquid crystal display unit 1206. The liquid crystal display unit 1206 is configured by adding a backlight to the back of the liquid crystal panel 1005 described above.
[0091]
<4-2-2: Mobile phone>
Further, an example in which the liquid crystal panel is applied to a mobile phone will be described. FIG. 22 is a perspective view showing the configuration of the mobile phone. In the figure, a mobile phone 1300 includes a plurality of operation buttons 1302 and a reflective liquid crystal panel 1005. In this reflection type liquid crystal panel 1005, a front light is provided on the front surface as needed.
[0092]
Note that, in addition to the electronic devices described with reference to FIGS. 21 and 22, a liquid crystal television, a viewfinder type, a video tape recorder of a monitor direct-view type, a car navigation device, a pager, an electronic notebook, a calculator, a word processor, a work Stations, videophones, POS terminals, devices equipped with touch panels, and the like. Needless to say, the present invention can be applied to these various electronic devices.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating an electrical configuration of an electro-optical device according to a first embodiment of the invention.
FIGS. 2A and 2B are block diagrams each illustrating one mode of a pixel of the device. FIGS.
FIG. 3 is a circuit diagram showing a detailed configuration of a sampling circuit in the device.
FIG. 4 is a block diagram showing a configuration of a data conversion circuit in the device.
FIG. 5 is an explanatory diagram showing a relationship among an evaluation value, a binary signal Ds, a polarity inversion signal FR, and a potential of a data line when the polarity is inverted for each data line and each frame.
FIG. 6 is a timing chart of a potential change in each column shown in FIG.
FIG. 7 is an explanatory diagram showing a binary signal of a maximum load when the polarity is inverted for each data line and each frame.
FIG. 8 is an explanatory diagram showing a relationship among an evaluation value, a binary signal Ds, a polarity inversion signal FR, and a potential of a data line when the polarity is inverted for each scanning line and each dot.
FIG. 9 is a timing chart of a potential change in each column shown in FIG.
FIG. 10 is an explanatory diagram showing a binary signal of a maximum load when the polarity is inverted for each scanning line and each dot.
FIG. 11 is a timing chart showing the operation of the same device.
FIG. 12 is a perspective view showing a mechanical configuration of a liquid crystal panel used in the device.
FIG. 13 is a cross-sectional view of the panel of FIG. 12 cut along ZZ ′.
FIG. 14 is a block diagram illustrating an electrical configuration of an electro-optical device according to a second embodiment of the invention.
FIG. 15 is a block diagram showing a configuration example of a load current detection circuit used in the device.
16 is a timing chart of the load current detection circuit shown in FIG.
FIG. 17 is a block diagram showing another configuration example of the load current detection circuit used in the device.
18 is a timing chart of the load current detection circuit shown in FIG.
FIG. 19 is a block diagram illustrating an electrical configuration of an electro-optical device according to a third embodiment of the invention.
FIG. 20 is an explanatory diagram showing a relationship between a selection period, a potential of a data line 114, and selected transistors Tr1 to Tr3 in each subfield.
FIG. 21 is a perspective view illustrating a configuration of a personal computer as an example of an electronic apparatus to which the electro-optical device is applied.
FIG. 22 is a perspective view illustrating a configuration of a mobile phone as an example of an electronic apparatus to which the electro-optical device is applied.
[Explanation of symbols]
Reference numeral 105: liquid crystal, 108: counter electrode, 112: scanning line, 114: data line, Tr1 to Tr3: transistor, 118: pixel electrode, 130: scanning line driving circuit, 140: sampling circuit, 400: power supply circuit, 500: data Line drive circuit, 350: selection signal generation circuit, 600: load current detection circuit. 300, 301: data conversion circuit, Ds: binary signal.

Claims (16)

An electro-optical device including a plurality of scanning lines, a plurality of data lines, and a plurality of pixels provided corresponding to intersections of the plurality of scanning lines and the plurality of data lines,
A transistor group provided corresponding to each of the plurality of data lines and including a plurality of transistors;
Selecting means for selecting one or more transistors for supplying a data line signal to the data line from the group of transistors based on a selection signal;
An electro-optical device comprising: a selection signal generation unit configured to generate the selection signal according to a driving load state of the data line. The selection signal generation unit detects a driving load state of the data line based on image information indicating a gray level to be displayed on the pixel, and generates the selection signal according to a detection result. Item 2. The electro-optical device according to item 1. The selection signal generation unit generates an evaluation value representing a potential change of the data line based on the image information, and the higher the potential change based on the evaluation value, the higher the ability to drive the data line. The electro-optical device according to claim 2, wherein the selection signal is generated so as to be as follows. A data line driving circuit that generates the data line signal and supplies the data line signal to each of the transistor groups;
The method according to claim 1, wherein the selection signal generation unit detects a driving load state of the data line based on a current consumption consumed by the data line driving circuit, and generates the selection signal according to a detection result. 2. The electro-optical device according to 1. 5. The device according to claim 4, wherein the selection signal generation unit detects a current consumed by the data line driving circuit by detecting a power supply voltage supplied from a power supply to the data line driving circuit. 6. Electro-optical device. 6. The electro-optical device according to claim 5, wherein the selection signal generation unit compares the power supply voltage with a plurality of reference voltages and generates the selection signal based on a comparison result. The selection signal generation unit compares the power supply voltage with a first reference voltage and a second reference voltage lower than the first reference voltage, and when the power supply voltage exceeds the first reference voltage, Generating the selection signal so that the ability to drive the line is reduced; and when the power supply voltage is between the first reference voltage and the second reference voltage, the selection signal is generated so as to maintain the current state. The power supply according to claim 5, wherein when the power supply voltage is lower than the second reference voltage, the selection signal is generated such that the ability to drive the data line is higher than the current state. Optical device. 8. The electro-optical device according to claim 1, wherein the selection signal generation unit switches the selection signal in units of one horizontal scanning period or in units of one frame. 2. The electro-optical device according to claim 1, wherein the selection signal generation unit generates the selection signal in accordance with a length of a selection period of the data line as a driving load state of the data line. In each of a plurality of subfields obtained by dividing one frame, the data line is selected to output the data line signal, and a data line driving circuit in which the selection period of the data line is different according to the length of the subfield. Prepare,
10. The electro-optical device according to claim 9, wherein the selection signal generation unit generates the selection signal by identifying the subfield. The electro-optical device according to any one of claims 1 to 10, wherein each transistor constituting the transistor group has a different size. An electronic apparatus comprising the electro-optical device according to claim 1. A plurality of scanning lines, a plurality of data lines, a plurality of pixels provided corresponding to intersections of the plurality of scanning lines and the plurality of data lines, and a plurality of pixels provided corresponding to each of the plurality of data lines. A driving method of an electro-optical device including a transistor group including a plurality of transistors,
Selecting one or more transistors from the group of transistors according to a driving load state of the data line;
A method for driving an electro-optical device, comprising: supplying a data line signal to the data line via a selected transistor. The driving load state of the data line includes a potential change of the data line,
Based on image information representing a gray level to be displayed on a pixel, an evaluation value representing a potential change of the data line is generated,
14. The transistor according to claim 13, wherein one or more transistors are selected from the group of transistors so that the larger the potential change based on the evaluation value, the higher the ability to drive the data line. A driving method of the electro-optical device. The electro-optical device includes a data line driving circuit that generates the data line signal and supplies the data line signal to each of the transistor groups.
Detecting a driving load state of the data line based on current consumption consumed by the data line driving circuit,
14. The method of driving an electro-optical device according to claim 13, wherein one or more transistors are selected from the group of transistors according to a detection result. 14. The electro-optical device according to claim 13, wherein one or more transistors are selected from the transistor group according to a length of a selection period of the data line as a driving load state of the data line. Drive method.

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