KR20010105973A - A contact structure of a wires and a method of manufacturing the same, and thin film transistor substrate including the contact structure and a method of manufacturing the same - Google Patents

Abstract

The invention relates to a security element for security paper for banknotes and the like having both aesthetic and anti-counterfeitable qualities. The invention comprises a security element for wholly or partially embedding in security paper comprising an elongate strip of a light transmitting polymeric substrate. The substrate bears a reflective metallic layer on at least one surface thereof in the form of a design. The design comprises at least one repeating geometric pattern of which one or more of the frequency, instantaneous amplitude and/or maximum amplitude of the pattern varies along the length of the element, said design having at least one non-linear boundary.

Description

A contact structure of a wiring, a manufacturing method thereof, and a thin film transistor substrate including the same, and a method for manufacturing the same, and a method for manufacturing the same }

The present invention relates to a contact structure of a wiring, a method of manufacturing the same, a thin film transistor substrate including the same, and a method of manufacturing the same.

In general, the wiring in the semiconductor device is used as a means for transmitting a signal, it is required to minimize the signal delay.

In this case, in order to prevent signal delay, the wiring is generally made of a metal material having a low resistance, particularly an aluminum-based metal material such as aluminum (Al) or aluminum alloy (Al alloy). However, since the aluminum-based wiring has weak physical or chemical properties, corrosion occurs when connected to other conductive materials at the contact portion, thereby increasing contact resistance and deteriorating characteristics of the semiconductor device. In order to improve such contact characteristics, wiring may be interposed with other metals when forming an aluminum series. However, in order to form a multilayer wiring, not only different etching solutions are required but also multiple etching processes are required, which makes the manufacturing process complicated. .

On the other hand, the liquid crystal display device is one of the most widely used flat panel display devices, and consists of two substrates on which electrodes are formed and a liquid crystal layer inserted therebetween. The display device controls the amount of light transmitted by rearranging.

Among the liquid crystal display devices, a liquid crystal display device having a thin film transistor for forming an electrode on each of two substrates and switching a voltage applied to the electrode is generally used. The thin film transistor is generally formed on one of two substrates.

In such a liquid crystal display device, in order to prevent signal delay, the wiring generally uses a low resistance material such as aluminum (Al) or aluminum alloy (Al alloy) having a low resistance. However, in the case of forming a pixel electrode or securing pad part reliability using indium tin oxide (ITO) or indium zinc oxide (IZO), which is a transparent conductive material, as in a liquid crystal display device, an aluminum-based metal and ITO or IZO The contact properties are poor, but intervenes with other metals such as molybdenum series or chromium, but aluminum or aluminum alloys need to be removed from the contact portion, which causes a complicated manufacturing process.

On the other hand, in the manufacturing method of the liquid crystal display device, the substrate on which the thin film transistor is formed is generally manufactured through a photolithography process using a mask. At this time, it is preferable to reduce the number of masks in order to reduce the production cost.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a contact structure of a wiring made of a low resistance material and having a low resistance contact characteristic, and a method of manufacturing the same.

Another object of the present invention is to provide a thin film transistor substrate including a contact structure of a wiring having excellent contact characteristics and a method of manufacturing the same.

In addition, another object of the present invention is to simplify the manufacturing method of the thin film transistor substrate.

1 is a thin film transistor substrate for a liquid crystal display device according to a first embodiment of the present invention;

FIG. 2 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 1 taken along the line II-II.

3A, 4A, 5A, 6A, and 7A are layout views of a thin film transistor substrate in an intermediate process of manufacturing a thin film transistor substrate for a liquid crystal display device according to a first embodiment of the present invention;

3B is a cross-sectional view taken along the line IIIb-IIIb ′ in FIG. 3A;

4B is a cross-sectional view taken along the line IVb-IVb ′ in FIG. 4A and is a cross-sectional view showing the next step in FIG. 3B;

FIG. 5B is a cross-sectional view taken along the line Vb-Vb ′ in FIG. 5A and is a cross-sectional view showing the next step in FIG. 4B;

FIG. 6B is a cross-sectional view taken along the line VIb-VIb ′ in FIG. 6A and is a cross-sectional view showing the next step in FIG. 5B;

FIG. 7B is a cross-sectional view taken along the line VIIIb-VIIIb ′ in FIG. 7A, and is a cross-sectional view showing the next step in FIG. 6B;

8 is a layout view of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention.

9 and 10 are cross-sectional views of the thin film transistor substrate shown in FIG. 8 taken along lines VIII-VIII 'and IX-IX',

11A is a layout view of a thin film transistor substrate at a first stage of manufacture in accordance with a second embodiment of the present invention,

11B and 1C are cross-sectional views taken along the lines XIb-XIb 'and XIc-XIc' of FIG. 11A, respectively.

12A and 12B are cross-sectional views taken along the lines XIb-XIb 'and XIc-XIc' of FIG. 11A, respectively, and are cross-sectional views of the next steps of FIGS. 11B and 11C;

FIG. 13A is a layout view of a thin film transistor substrate at a next step of FIGS. 12A and 12B;

13B and 13C are cross-sectional views taken along the lines XIIIb-XIIIb 'and XIIIc-XIIIc' of FIG. 13A, respectively.

14A, 15A, 16A and 14B, 15B, 16B are cross-sectional views taken along the lines XIIIb-XIIIb 'and XIIIc-XIIIc' in FIG. 13A, respectively, illustrating the following steps in the order of the process. ,

17A is a layout view of a thin film transistor substrate in the next steps of FIGS. 16A and 16B,

17B and 17C are cross-sectional views taken along the lines XVIIb-XVIIb 'and XVIIc-XVIIc', respectively, in FIG. 17A.

In order to solve this problem, the present invention performs a heat treatment process to form a silicide layer on the upper interface of the wiring made of aluminum-based metal.

In the contact structure of the wiring according to the present invention and the method for forming the wiring, first, metal wiring is formed on the substrate, and a reaction layer is formed on the wiring. Subsequently, a conductive layer electrically connected to the wiring via the reaction layer is formed.

Here, the metal wiring is preferably formed of an aluminum-based metal, and may further include forming an insulating film having a contact hole between the wiring and the conductive layer.

In this case, the reaction layer may be formed by performing a heat treatment process by annealing.

The conductive layer may be a transparent conductive material, and may be formed of IZO, the reaction layer may be formed by laminating an amorphous silicon layer or a doped amorphous silicon layer to form a buffer layer and annealing, and may remove the buffer layer. It may not.

Such a contact structure of wirings and a method of forming the same can be applied to a method of manufacturing a thin film transistor substrate.

First, gate wirings, data wirings, and semiconductor layers are formed, and an insulating film covering them is formed. A reaction layer between layers including at least silicon is formed on the gate wiring and the data wiring, and an insulating layer is patterned to form a contact hole exposing the reaction layer on the gate wiring or the data wiring. Subsequently, a transparent conductive layer that is electrically connected to the gate wiring or the data wiring through the reaction layer is formed through the contact hole.

In this case, the gate wiring and the data wiring are preferably formed by including an aluminum-based conductive material. The conductive layer may be formed of IZO, and the reaction layer may include Al _x Si _y as a main component.

In more detail, a first conductive material is stacked and patterned on an insulating substrate to form a gate line including a gate line and a gate electrode connected to the gate line, and a reaction layer is formed on the gate line. Next, a gate insulating layer is stacked, a semiconductor layer is formed on the gate insulating layer, and a second conductive material is stacked and patterned thereon, the data line crossing the gate line, the source electrode connected to the data line and adjacent to the gate electrode; A data line including a drain electrode located opposite the source electrode is formed with respect to the gate electrode. Subsequently, after the reaction layer is formed on the data line, a protective layer is stacked and patterned to form a first contact hole on the drain electrode, and a pixel electrode electrically connected to the drain electrode on the protective layer.

Here, the reaction layer is preferably formed through a heat treatment process, and the first and second conductive materials preferably include an aluminum-based metal, and the pixel electrode may be formed of a transparent conductive material, and may be formed of IZO. Can be.

The gate wiring further includes a gate pad receiving a scan signal from the outside and transferring the scan signal to a gate line, and the data wiring further includes a data pad receiving an image signal from the outside and transferring the image signal to a data line, and the protective layer includes a data pad and a gate. It has a second and third contact hole to expose the gate pad with the insulating film, the reaction layer is formed to the upper portion of the gate pad and the data pad, and through the reaction layer through the second and third contact hole in the same layer as the pixel electrode The auxiliary gate pad and the auxiliary data pad electrically connected to the gate pad and the data pad may be further formed.

The data line and the semiconductor layer may be formed together by a photolithography process using a photoresist pattern having a different thickness, and the photoresist pattern has a first portion having a first thickness, a second portion thicker than the first thickness, and no thickness. It is preferred to include a third portion except for the first and second portions.

In the photolithography process, the photoresist pattern may be formed using an optical mask including a first region, a second region having a lower transmittance than the first region, and a third region having a higher transmittance than the first region. In the etching process, the first portion is preferably formed between the source electrode and the drain electrode, and the second portion is positioned above the data line.

In order to control the transmittance of the first to third regions differently, a slit pattern smaller than the resolution of the translucent film or the exposure machine may be formed in the photomask, and the thickness of the first portion is 1/2 or less with respect to the thickness of the second portion. It is preferable to form.

The method may further include forming an ohmic contact layer between the semiconductor layer and the data line, and the data line, the contact layer, and the semiconductor layer may be formed using one mask.

Next, a thin film transistor substrate for a liquid crystal display device and a method of manufacturing the same according to embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. do.

As a semiconductor device, particularly a wiring for transmitting a signal, an aluminum-based metal material having a low resistivity of 15 µΩcm or less is suitable to minimize signal delay. In this case, the wiring should be connected to another conductive layer in order to receive a signal from the outside or to transmit a signal to the outside, and should not be easily corroded when contacted with other materials in the manufacturing process. To this end, in the method for manufacturing a contact structure of a wiring according to an embodiment of the present invention, first, a wiring made of a metal having a low resistance is formed on an upper portion of a substrate, and then a buffer layer containing silicon is laminated and annealed to form an upper portion of the wiring. To form a reaction layer. In this case, the reaction layer may be formed by performing a heat treatment process through annealing. Subsequently, a conductive layer is electrically connected to the wiring via the reaction layer through the contact hole of the insulating film.

Here, the reaction layer may be formed after forming an insulating film, or may be formed after forming contact holes.

In addition, the conductive layer may be formed of a transparent conductive material, preferably indium tin oxide (ITO) or indium zinc oxide (IZO), and the wiring may be formed of an aluminum-based metal having low resistance.

Here, the reaction layer has a function of lowering the contact resistance of the aluminum-based wiring and ITO or IZO or blocking corrosion from contacting.

The wiring may be used as a gate wiring or a data wiring of a thin film transistor for a liquid crystal display device.

First, a structure of a thin film transistor substrate for a liquid crystal display according to a first embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a thin film transistor substrate for a liquid crystal display according to a first embodiment of the present invention, and FIG. 2 is a cross-sectional view of the thin film transistor substrate shown in FIG. 1 taken along the line II-II '.

A gate wiring made of an aluminum-based metal material having low resistance is formed on the insulating substrate 10. The gate wire is connected to the gate line 22 and the gate line 22 extending in the horizontal direction, and are connected to the gate pad 24 and the gate line 22 which receive a gate signal from the outside and transmit the gate signal to the gate line. A gate electrode 26 of the thin film transistor.

The first reaction layer 94 made of aluminum silicide (Al _x Si _y ) is formed on the gate wiring. In this case, the first reaction layer may further include an amorphous silicon layer or an n + amorphous silicon layer on the aluminum silicide layer.

On the substrate 10, a gate insulating film 30 made of silicon nitride (SiN _x ) covers the gate wirings 22, 24, and 26, and the gate insulating film 30 is provided with a gate pad along with a protective film 70 formed thereafter. It has a contact hole 74 that exposes 24.

A semiconductor layer 40 made of a semiconductor such as amorphous silicon is formed on the gate insulating film 30 of the gate electrode 24 in an island shape, and silicide or n-type impurities are doped with high concentration on the semiconductor layer 40. Resistive contact layers 54 and 56 made of a material such as n + hydrogenated amorphous silicon are formed, respectively.

On the resistive contact layers 54 and 56 and the gate insulating layer 30, aluminum (Al) or aluminum alloy (Al alloy), molybdenum (Mo) or molybdenum-tungsten (MoW) alloy, chromium (Cr), tantalum (Ta), etc. The data wirings 62, 64, 66, 68 made of metal or conductors are formed. The data line is formed in the vertical direction and crosses the gate line 22 to define a pixel, the data line 62 and the branch of the data line 62 and the source electrode 64 extending to the upper portion of the ohmic contact layer 54. ), Which is connected to one end of the data line 62 and is separated from the data pad 68 and the source electrode 64 to which an image signal from the outside is applied, and is opposite to the source electrode 64 with respect to the gate electrode 26. And a drain electrode 66 formed on the ohmic contact layer 56.

The data lines 62, 64, 66, and 68 may be formed of a single film made of aluminum or an aluminum alloy, or may be formed of two or more layers. In the case of forming more than two layers, it is preferable that one layer is made of a material having a low resistance and the other layer is made of a material having good contact properties with other materials. Examples thereof include Cr / Al (or Al alloy) or Al / Mo. In the embodiment of the present invention, the data lines 62, 64, 66, and 68 may be formed of the lower layer 601 of Cr and the aluminum alloy. The upper film 602 is formed.

Second reaction layers 94, 96, and 98 including at least Al _x Si _y are formed on the upper layer 602 of the data lines 62, 64, 66, and 68. Like the first reaction layer 92, the second reaction layers 94, 96, and 98 may further include an amorphous silicon layer or an n + amorphous silicon layer on the Al _x Si _y layer. Here, the second reaction layers 94, 96, and 98 may include the pixel electrode layers 82, 86, and 88 of indium zinc oxide (IZO), which are formed later, and the gate pad 24 and the drain electrode, which are made of an aluminum-based metal. 66 is a layer for improving the contact characteristics between the upper layer 602 of the data pad 68 and lowers the contact resistance of the contact portion or prevents impurities from entering the wirings 24, 66, 68 from the contact portion. It may have a function to prevent it from proceeding.

The passivation layer 70 is formed on the data lines 62, 64, 66, and 68 and the semiconductor layer 40 not covered by the data lines 62. The passivation layer 90 is provided with contact holes 76 and 78 respectively exposing the drain electrode 66 and the second reaction layers 96 and 98 of the data pad 68, respectively, and together with the gate insulating layer 30. A contact hole 74 is formed to expose the first reaction layer 94 in the portion of the gate pad 24. In this case, only Al _x Si _y layers are formed in portions of the first and second reaction layers 94, 96, and 98 exposed through the contact holes 74, 76, and 78, and an amorphous silicon layer or an n + amorphous silicon. The layer is removed.

On the passivation layer 70, the gate pad is connected to the reaction layer 96 on the drain electrode 66 through the contact hole 76 and through the pixel electrode 82 and the contact holes 74 and 78 positioned in the pixel, respectively. And an auxiliary gate pad 86 and an auxiliary data pad 88 connected to the reaction layers 94 and 98 on the data pad 68 and the pixel pad layers 82, 86, and 88 made of IZO. ) Is formed.

1 and 2, the pixel electrode 82 overlaps with the gate line 22 to form a storage capacitor. When the storage capacitor is insufficient, the pixel electrode 82 is disposed on the same layer as the gate wirings 22, 24, and 26. It is also possible to add a storage capacitor wiring.

The structure according to the exemplary embodiment of the present invention includes gate wirings 22, 24, and 26 and data wirings 62, 64, 66, and 68 made of aluminum-based metal having low resistance, so that a liquid crystal having a high screen resolution is provided. Applicable to the display device. At the same time, the gate pad 24, the data pad 68, and the drain electrode 66 and the auxiliary gate pad 86, the auxiliary data pad 88, and the pixel electrode 82 of IZO or ITO, respectively, have their contact characteristics. By contacting through the reaction layers 94, 98, and 96 to improve the resistance, the pad part can be prevented from being corroded, thereby ensuring the reliability of the pad part.

The reaction layers 94, 96, and 98 have been described as being made of Al _x Si _y , but may further include an amorphous silicon layer or a doped amorphous silicon layer on the Al _x Si _y layer.

Next, a method of manufacturing a thin film transistor substrate for a liquid crystal display device having a structure according to a first embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2 and FIGS. 3A to 7B.

First, as shown in FIGS. 3A and 3B, an aluminum-based conductive film having a low resistance is laminated on the substrate 10 to a thickness of about 2,500 GPa, and an amorphous silicon layer or an N + amorphous silicon layer is laminated on the conductive film to 50 GPa. Laminate the buffer layer to a thickness of about 1,000Å. Subsequently, after the annealing is performed to form a first reaction layer made of Al _X Si _y on the conductive film, the buffer layer is etched and removed using SF ₆ + O ₂ mixed gas. In this case, when the buffer layer is thin, wet etching may be used. The annealing is preferably performed at a temperature between 250 ° C. and 400 ° C. for about 30 minutes to 2 hours. At this time, the buffer layer is removed, but the first reaction layer formed through annealing remains. Meanwhile, the annealing process and the buffer layer removing process may be omitted. This is because the annealing may be naturally performed in a subsequent process, for example, a chemical vapor deposition (CVD) process, and the buffer layer may form only a contact hole in the protective film and then remove only the portion exposed through the contact hole.

Subsequently, the conductive film and the first reaction layer are patterned together to form a horizontal gate line including the gate line 22, the gate electrode 26, and the gate pad 24, and the first reaction layer pattern 94 thereon. Form.

Next, as shown in FIGS. 4A and 4B, a three-layer film of the gate insulating film 30, the semiconductor layer 40 made of amorphous silicon, and the doped amorphous silicon layer 50 is successively laminated and patterned using a mask. The semiconductor layer 40 and the doped amorphous silicon layer 50 are patterned to form an island-like semiconductor layer 40 and an ohmic contact layer 50 on the gate insulating layer 30 facing the gate electrode 24. .

Next, as shown in FIGS. 5A to 5B, the lower layer 601 made of molybdenum, molybdenum alloy, chromium, or the like has a thickness of about 300 GPa, and the upper layer 602 made of an aluminum-based metal having low resistance. After the stacking is sequentially performed at a thickness of about 2,500 mW, an amorphous silicon layer or an N + amorphous silicon layer is laminated on the upper layer 602, and a buffer layer is laminated at a thickness of 50 mW to 1,000 mW. Subsequently, annealing is performed under the same conditions as in the first reaction layer forming step to form a second reaction layer made of Al _x Si _y on the conductive layer, and then the buffer layer is entirely etched using SF ₆ + O ₂ mixed gas. To remove it. At this time, the buffer layer is removed, but the second reaction layer formed through annealing remains. In this case, the annealing and the buffer layer removing process may also be omitted.

Subsequently, the lower layer 601, the upper layer 602, and the reaction layer are patterned together by a photolithography process using a mask to be connected to the data line 62 and the data line 62 crossing the gate line 22. The source electrode 64 and the data line 62 extending to the upper portion of the 26 are separated from the data pad 68 and the source electrode 64 connected to one end, and the source electrode 64 is centered on the gate electrode 26. The data line including the drain electrode 66 facing the electrode 66 and the second reaction layer pattern 96 98 are formed. Here, both the upper layer 602 and the lower layer 601 may be etched by wet etching, the upper layer 602 may be etched by wet etching, and the lower layer 601 may be etched by dry etching.

Subsequently, the doped amorphous silicon layer pattern 50, which is not covered by the data lines 62, 64, 66, and 68, is etched and separated on both sides of the gate electrode 26, while both doped amorphous silicon layers ( The semiconductor layer pattern 40 between 54 and 56 is exposed. Subsequently, in order to stabilize the surface of the exposed semiconductor layer 40, it is preferable to perform oxygen plasma.

Next, as shown in FIGS. 6A and 6B, a protective film 70 made of silicon nitride or an organic insulating film is laminated.

Next, as shown in FIGS. 7A and 7B, the passivation layer 70 is patterned by dry etching together with the gate insulating layer 30 by a photolithography process using a mask to form the gate pad 24, the drain electrode 66, and the like. Contact holes 74, 76, 78 are formed in the data pad 68. The first and second reaction layers 94 and 96 and 98 over the gate pad 24, the drain electrode 66, and the data pad 68 are exposed through the contact holes 74, 76, and 78. do.

In the case where the buffer layer removing step is omitted in the above steps of forming the first and second reaction layer patterns 94, 96, and 98, the contact holes 74, 76, and 78 are formed, and then the contact holes 74, 76, and 78 are formed. ) To remove the exposed buffer layer.

Next, as shown in FIGS. 1 and 2, the pixel electrode connected to the reaction layer 96 on the drain electrode 66 through the contact hole 76 is formed by stacking IZO and performing patterning using a mask. The auxiliary gate pad 86 and the auxiliary data pad 88 connected to the gate pad 24 and the reaction layers 94 and 98 on the data pad 68 through the contact holes 74 and 78, respectively. Form each.

In the manufacturing method according to the exemplary embodiment of the present invention, the reaction layers 94, 96, and 98 are formed in order to improve contact characteristics between the CIZO and the aluminum-based metal before laminating the IZO film.

In the first embodiment, as described above, the present invention can be applied to a manufacturing method using five masks, but the same can be applied to the manufacturing method of a thin film transistor substrate for liquid crystal display devices using four masks. This will be described in detail with reference to the drawings.

First, a unit pixel structure of a thin film transistor substrate for a liquid crystal display device completed using four masks according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 8 to 10.

8 is a layout view of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention, and FIGS. 9 and 10 are along the IX-IX 'and XX' lines of the thin film transistor substrate shown in FIG. It is sectional drawing cut out.

First, a gate line including a gate line 22, a gate pad 24, and a gate electrode 26 made of an aluminum-based metal is formed on the insulating substrate 10 as in the first embodiment. The gate wiring includes a sustain electrode 28 that is parallel to the gate line 22 on the substrate 10 and receives a voltage such as a common electrode voltage input to the common electrode of the upper plate from the outside. The storage electrode 28 overlaps with the conductive capacitor conductor 68 for the storage capacitor connected to the pixel electrode 82, which will be described later, to form a storage capacitor which improves the charge retention capability of the pixel. The pixel electrode 82 and the gate line, which will be described later, If the holding capacity generated by the overlap of (22) is sufficient, it may not be formed.

The first reaction layer 92 made of aluminum silicide (Al _x Si _y ) is formed on the gate lines 22, 24, 26, and 28. The first reaction layer 92 may further include an amorphous silicon layer or an n + amorphous silicon layer on the aluminum silicide layer.

A gate insulating film 30 made of silicon nitride (SiN _x ) is formed on the first reaction layer 92 to cover the gate wires 22, 24, 26, and 28.

Semiconductor patterns 42 and 48 made of semiconductors such as hydrogenated amorphous silicon are formed on the gate insulating layer 30, and high concentrations of n-type impurities such as phosphorus (P) are formed on the semiconductor patterns 42 and 48. An ohmic contact layer pattern or an intermediate layer pattern 55, 56, 58 made of amorphous silicon doped with is formed.

On the ohmic contact layer patterns 55, 56, and 58, a data line made of an aluminum-based conductive material having low resistance is formed. The data line is a thin film transistor which is a branch of the data line 62 formed in the vertical direction, the data pad 64 connected to one end of the data line 62 to receive an image signal from the outside, and the data line 62. And a data line portion of the source electrode 65 of the source electrode 65, and separated from the data line portions 62, 64, and 65 and of the source electrode 65 with respect to the gate electrode 26 or the channel portion C of the thin film transistor. It also includes a conductive capacitor conductor 68 for the storage capacitor located on the drain electrode 66 and the storage electrode 28 of the thin film transistor located on the opposite side. When the sustain electrode 28 is not formed, the conductor pattern 68 for the storage capacitor is also not formed.

The data lines 62, 64, 65, 66 and 68 may also be formed in a single layer like the gate lines 22, 24, 26 and 28, but similarly to the first embodiment, they include chromium or molybdenum or molybdenum alloys. It may be formed as a double film.

The contact layer patterns 55, 56, and 58 serve to lower the contact resistance between the semiconductor patterns 42 and 48 below and the data lines 62, 64, 65, 66, and 68 above them. It has exactly the same form as (62, 64, 65, 66, 68). That is, the data line part intermediate layer pattern 55 is the same as the data line parts 62, 64 and 65, the drain electrode intermediate layer pattern 56 is the same as the drain electrode 66, and the storage capacitor intermediate layer pattern 58 is It is the same as the conductor pattern 68 for holding capacitors.

The semiconductor patterns 42 and 48 have the same shapes as the data lines 62, 64, 65, 66, and 68 and the ohmic contact layer patterns 55, 56, and 57 except for the channel portion C of the thin film transistor. Doing. Specifically, the semiconductor capacitor 48 for the storage capacitor, the conductor pattern 68 for the storage capacitor, and the contact layer pattern 58 for the storage capacitor have the same shape, but the semiconductor pattern 42 for the thin film transistor has data wiring and contact. Slightly different from the rest of the layer pattern. That is, the data line parts 62, 64, 65, in particular, the source electrode 65 and the drain electrode 66 are separated from the channel portion C of the thin film transistor, and the contact layer pattern for the data line intermediate layer 55 and the drain electrode is separated. Although 56 is also separated, the semiconductor pattern 42 for thin film transistors is not disconnected here and is connected to generate a channel of the thin film transistor.

Second reaction layers 91, 93, 94, and 95 made of Al _x Si _y are formed on the data lines 62, 64, 65, 66, and 68. The second reaction layers 91, 93, 94, and 95 may further include an amorphous silicon layer or an n + amorphous silicon layer on the aluminum silicide layer.

The passivation layer 70 is formed on the second reaction layers 91, 93, 94, and 95, and the passivation layer 70 is formed on the drain electrode 66, the data pad 64, and the conductive pattern 68 for the storage capacitor. Contact holes 71, 73, and 74 exposing the second reaction layers 91, 93, 94, and 95 of the second reaction layer, and the first reaction layer 92 on the gate pad 24 together with the gate insulating layer 30. Has a contact hole 72 exposing The passivation layer 70 may be made of an organic insulating material such as silicon nitride or acrylic.

On the passivation layer 70, a pixel electrode 82 that receives an image signal from a thin film transistor and generates an electric field together with the electrode of the upper plate is formed. The pixel electrode 82 is made of a transparent conductive material such as indium tin oxide (IZO). The pixel electrode 82 is electrically connected to the drain electrode 66 through the second reaction layer 91 through the contact hole 71 and is connected to the image signal. Received. The pixel electrode 82 also overlaps with the neighboring gate line 22 and the data line 62 to increase the aperture ratio, but may not overlap. In addition, the pixel electrode 82 is also connected to the second reaction layer 94 on the conductive capacitor pattern 68 for the storage capacitor through the contact hole 74 to transmit an image signal to the conductive pattern 68. On the other hand, the auxiliary gate pads connected to the first reaction layer 92 on the gate pad 24 and the second reaction layer 93 on the data pad 64 through the contact holes 72 and 73, respectively. 84) and auxiliary data pads 86 are formed, which are not essential to complement the adhesion of the pads 24 and 64 to the external circuitry and to protect the pads. to be.

Although transparent IZO is used as an example of the material of the pixel electrode 82, an opaque conductive material may be used for the reflective liquid crystal display device.

Next, a method of manufacturing a thin film transistor substrate for a liquid crystal display device having the structure of FIGS. 8 to 10 using four masks will be described in detail with reference to FIGS. 8 to 10 and FIGS. 11A to 18C. .

First, as shown in FIGS. 11A to 11C, a low-resistance aluminum-based conductive film is laminated on the substrate 10 to a thickness of about 2,500 mW, and an amorphous silicon layer or an N + amorphous silicon layer is laminated on the conductive film to 50 mW. Laminate the buffer layer to a thickness of between 1,000Å. Subsequently, after annealing is performed to form a first reaction layer made of Al _x Si _y on the conductive film, the buffer layer is etched and removed using SF ₆ + O ₂ mixed gas. At this time, the buffer layer is removed, but the first reaction layer formed through annealing remains. Meanwhile, the annealing process and the buffer layer removing process may be omitted. Subsequently, the conductive film and the first reaction layer are patterned together to form a horizontal gate wiring including the gate line 22, the gate electrode 26, the gate pad 24, and the storage electrode 28, and a first reaction thereon. The layer pattern 92 is formed.

Next, as shown in FIGS. 12A and 12B, the gate insulating film 30, the semiconductor layer 40, and the intermediate layer 50 are respectively 1,500 kV to 5,000 kV, 500 kV to 2,000 kV, and 300 kV using chemical vapor deposition. Continuously deposited to a thickness of 600 to 600 kV, and then depositing the conductor layer 60 to a thickness of 1,500 kPa to 3,000 kPa by a method such as sputtering with an aluminum-based metal having a low resistance, and then amorphous on the conductor layer 60 By laminating a silicon layer or an N + amorphous silicon layer, a buffer layer is laminated to a thickness of 50 mV to 1,000 mV. Subsequently, annealing is performed in the same manner as the first reaction layer forming method to form the second reaction layer 90, and then the buffer layer is removed by full etching using a SF ₆ + O ₂ mixed gas. At this time, the buffer layer is removed, but the second reaction layer 90 formed through annealing remains. Meanwhile, the annealing process and the buffer layer removing process may be omitted. Subsequently, the photosensitive film 110 is applied on the second reaction layer 90 to a thickness of 1 μm to 2 μm.

Thereafter, the photoresist film 110 is irradiated with light through a second mask and then developed to form photoresist patterns 112 and 114 as illustrated in FIGS. 13B and 13C. In this case, among the photoresist patterns 112 and 114, the channel portion C of the thin film transistor, that is, the first portion 114 positioned between the source electrode 65 and the drain electrode 66, is the data wiring portion A, that is, the data. The thickness of the wirings 62, 64, 65, 66, and 68 is smaller than that of the second part 112 positioned at the portion where the wirings 62, 64, 65, 66, and 68 are to be formed. At this time, the ratio of the thickness of the photoresist film 114 remaining in the channel portion C to the thickness of the photoresist film 112 remaining in the data wiring portion A should be different depending on the process conditions in the etching process described later. It is preferable to make the thickness of the 1st part 114 into 1/2 or less of the thickness of the 2nd part 112, for example, it is good that it is 4,000 Pa or less.

As such, there may be various methods of varying the thickness of the photoresist layer according to the position. In order to control the light transmittance in the A region, a slit or lattice-shaped pattern is mainly formed or a translucent film is used.

In this case, the line width of the pattern located between the slits, or the interval between the patterns, that is, the width of the slits, is preferably smaller than the resolution of the exposure apparatus used for exposure. A thin film having a thickness or a thin film may be used.

When the light is irradiated to the photosensitive film through such a mask, the polymers are completely decomposed at the part directly exposed to the light, and the polymers are not completely decomposed because the amount of light is small at the part where the slit pattern or the translucent film is formed. In the area covered by, the polymer is hardly decomposed. Subsequently, when the photoresist film is developed, only a portion where the polymer molecules are not decomposed is left, and a thin photoresist film is left at the center portion where the light is not irradiated at a portion less irradiated with light. In this case, if the exposure time is extended, all molecules are decomposed, so it should not be so.

The thin film 114 is formed by using a photoresist film made of a reflowable material, and is exposed to a conventional mask that is divided into a part that can completely transmit light and a part that cannot fully transmit light, and then develops and ripples. It can also be formed by letting a part of the photosensitive film flow to the part which does not remain by making it low.

Subsequently, etching is performed on the photoresist pattern 114 and the lower layers thereof, that is, the second reaction layer 90, the conductor layer 60, the intermediate layer 50, and the semiconductor layer 40. In this case, the data line and the layers under the data line remain in the data wiring portion A, only the semiconductor layer 40 should remain in the channel portion C, and the upper four layers 90 in the remaining portion B. , 60, 50, and 40 should be removed to expose the gate insulating film 30.

First, as shown in FIGS. 14A and 14B, the exposed second reaction layer 90 and the conductor layer 60 of the other portion B are removed to expose the lower intermediate layer 50. In this process, both a dry etching method and a wet etching method may be used. In this case, the second reaction layer 90 and the conductor layer 60 may be etched and the photoresist patterns 112 and 114 may be hardly etched. However, in the case of dry etching, it may be difficult to find a condition in which only the second reaction layer 90 and the conductor layer 60 are etched and the photoresist patterns 112 and 114 are not etched, so that the photoresist patterns 112 and 114 are also etched together. It can be performed under the conditions shown. In this case, the thickness of the first portion 114 is thicker than that of the wet etching so that the first portion 114 is removed in this process so that the lower second reaction layer 90 is not exposed.

When the conductor layer 60 is any one of Mo or MoW alloy, Al or Al alloy, and Ta, either dry etching or wet etching can be used. However, since Cr is not easily removed by the dry etching method, it is preferable to use only wet etching if the conductor layer 60 is Cr. In the case of wet etching in which the conductor layer 60 is Cr, CeNHO ₃ may be used as an etchant. In the case of dry etching in which the conductor layer 60 is Mo or MoW, the mixed gas or CF of CF ₄ and HCl may be used as the etching gas. A mixed gas of ₄ and O ₂ can be used, and in the latter case, the etching ratio to the photoresist film is almost the same.

In this way, as shown in FIGS. 14A and 14B, the conductor layer and the second reaction layer of the channel portion C and the data wiring portion B, that is, the conductor patterns 67 and the second conductor layer for the data line and the source / drain Only the reaction layers 93 and 95, the conductor pattern 68 for the storage capacitor, and the second reaction layer 94 remain, and the conductor layer 60 of the other part (B) is removed so that the intermediate layer 50 underneath is removed. Revealed. The remaining conductor patterns 67 and 68 have the same shape as the data lines 62, 64, 65, 66, and 68 except that the source and drain electrodes 65 and 66 are connected without being separated. In addition, when dry etching is used, the photoresist patterns 112 and 114 are also etched to a certain thickness.

Subsequently, as shown in FIGS. 15A and 15B, the exposed intermediate layer 50 of the other portion B and the semiconductor layer 40 below it are simultaneously removed together with the first portion 114 of the photosensitive film by a dry etching method. do. At this time, etching is performed under the condition that the photoresist patterns 112 and 114, the intermediate layer 50, and the semiconductor layer 40 (the semiconductor layer and the intermediate layer have almost no etching selectivity) are simultaneously etched, and the gate insulating layer 30 is not etched. In particular, it is preferable to etch under conditions in which the etch ratios of the photoresist patterns 112 and 114 and the semiconductor layer 40 are almost the same. For example, by using a mixed gas of SF ₆ and HCl or a mixed gas of SF ₆ and O ₂ , the two films can be etched to almost the same thickness. When the etching ratios of the photoresist patterns 112 and 114 and the semiconductor layer 40 are the same, the thickness of the first portion 114 should be equal to or smaller than the sum of the thicknesses of the semiconductor layer 40 and the intermediate layer 50.

This removes the first portion 114 of the channel portion C, revealing the source / drain conductor pattern 67, as shown in FIGS. 15A and 15B, and the intermediate layer 50 of the other portion B. And the semiconductor layer 40 is removed to expose the gate insulating layer 30 thereunder. On the other hand, since the second portion 112 of the data wiring portion A is also etched, the thickness becomes thin. In this step, the semiconductor patterns 42 and 48 are completed. Reference numerals 57 and 58 indicate the intermediate layer pattern under the source / drain conductor pattern 67 and the intermediate layer pattern under the storage capacitor conductor pattern 68, respectively.

Subsequently, ashing removes photoresist residue remaining on the surface of the source / drain conductor pattern 67 of the channel portion C.

Next, as shown in FIGS. 16A and 16B, the source / drain conductor pattern 67 of the channel part C and the source / drain interlayer pattern 57 below are etched and removed. In this case, the etching may be performed only by dry etching with respect to both the source / drain conductor pattern 67 and the intermediate layer pattern 57. The etching may be performed by wet etching on the source / drain conductor pattern 67. 57 may be performed by dry etching. In the former case, it is preferable to perform etching under the condition that the etching selectivity of the source / drain conductor pattern 67 and the interlayer pattern 57 is large. This is because it is not easy to adjust the thickness of the semiconductor pattern 42 remaining in Fig. 2). For example, those of etching the SF ₆ and O ₂ by using the mixed gas of the source / drain conductive pattern 67. In the latter case of alternating between wet etching and dry etching, the side surface of the conductive pattern 67 for wet etching of the source / drain is etched, but the intermediate layer pattern 57 which is dry etched is hardly etched, and thus is formed in a step shape. Examples of the etching gas used to etch the intermediate layer pattern 57 and the semiconductor pattern 42 include the aforementioned mixed gas of CF ₄ and HCl or mixed gas of CF ₄ and O ₂ , and CF ₄ and O _{Using 2} can leave the semiconductor pattern 42 in a uniform thickness. In this case, as shown in FIG. 15B, a part of the semiconductor pattern 42 may be removed to reduce the thickness, and the second part 112 of the photoresist pattern may also be etched to a certain thickness at this time. The etching may be performed under the condition that the gate insulating layer 30 is not etched, and the photoresist pattern may not be exposed by etching the second part 112. Of course, thick is preferable.

In this way, the source electrode 65 and the drain electrode 66 are separated, thereby completing the data lines 62, 64, 65, 66, and 68 and the contact layer patterns 55, 56, and 58 under the data lines.

Finally, the second photoresist layer 112 remaining in the data wiring portion A is removed. However, the removal of the second portion 112 may be made after removing the conductor pattern 67 for the channel portion C source / drain and before removing the intermediate layer pattern 57 thereunder.

As mentioned earlier, wet and dry etching can be alternately used or only dry etching can be used. In the latter case, since only one type of etching is used, the process is relatively easy, but it is difficult to find a suitable etching condition. On the other hand, in the former case, the etching conditions are relatively easy to find, but the process is more cumbersome than the latter.

After the data wirings 62, 64, 65, 66, and 68 are formed in this manner, as shown in FIGS. 17A to 17C, silicon nitride is deposited by CVD or spin-coated an organic insulating material to have a thickness of 3,000 Å or more. The protective film 70 is formed. Subsequently, the passivation layer 70 is etched together with the gate insulating layer 30 by using a third mask, and the upper portion of the drain electrode 66, the gate pad 24, the data pad 64, and the conductive pattern 68 for the storage capacitor is formed. Contact holes 71, 72, 73, and 74 are formed to expose the first and second reaction layers 92, 93, 94, 95, respectively.

In the case where the buffer layer removing process is omitted in the above-described first and second reaction layer patterns 92, 93, 94, and 95, the contact holes 71, 72, 73, and 74 are formed, and then the contact holes 71 are formed. , 72, 73, 74) to remove the exposed buffer layer.

Finally, as illustrated in FIGS. 11 to 13, the IZO layer having a thickness of 400 kHz to 500 kHz is deposited and etched using a fourth mask to etch the drain electrode 66 and the storage through the reaction layers 91 and 94. The data electrode through the pixel electrode 82 connected to the conductor pattern 68 for the capacitor, the auxiliary gate pad 84 connected to the gate pad 24 through the first reaction layer 92, and the second reaction layer 93. An auxiliary data pad 86 connected with 64 is formed.

In the third embodiment of the present invention, in addition to the effects according to the first embodiment, the data wirings 62, 64, 65, 66, and 68 and the contact layer patterns 55, 56, and 58 and the semiconductor patterns 42 thereunder. , 48) may be formed using one mask, and the source electrode 65 and the drain electrode 66 may be separated in this process to simplify the manufacturing process.

The contact resistance of the contact portion of the completed thin film transistor substrate according to the embodiment of the present invention was measured at about 10E4 kPa, and the contact resistance did not increase even after repeatedly annealing. At this time, the contact holes 71, 72, 73, and 74 were formed to be 7 mu m x 7 mu m.

In this embodiment of the present invention, in order to improve the contact characteristics between the aluminum-based metal and the IZO film, a reaction layer including Al _x Si _y was formed therebetween, but in the contact structure of another wiring, chromium or molybdenum or molybdenum alloy It is also possible to form a wiring with another metal such as a wire to form a reaction layer containing another metal and silicon. It is also possible to use other materials instead of silicon. In the exemplary embodiment of the present invention, the IZO film is used as the pixel electrode layer, but the contact characteristic is improved even when the ITO film is used.

As described above, according to the present invention, by forming a reaction layer between the layers including metal and silicon at the contact portion, the pad portion is secured and wires are formed of aluminum or aluminum alloy with low resistance, thereby improving the characteristics of the product having a high screen size. Can be improved. In addition, the manufacturing process may be simplified to manufacture a thin film transistor substrate for a liquid crystal display, thereby simplifying the manufacturing process and reducing the manufacturing cost.

Claims (23)

Forming a gate wiring, Forming a data line insulated from the gate line; Forming a reaction layer on at least one of the gate wiring and the data wiring; Forming a transparent conductive layer electrically connected to the gate wiring or the data wiring Method of manufacturing a thin film transistor substrate comprising a. In claim 1, And the reaction layer is formed on both the gate wiring and the data wiring. In claim 1, Forming the reaction layer Laminating the silicon layer, Annealing, Removing the silicon layer Method of manufacturing a thin film transistor substrate comprising a. In claim 1, The reaction layer is a method for manufacturing a thin film transistor substrate having Al _x Si _y as a main component. In claim 1, The said transparent conductive layer is a manufacturing method of the thin film transistor substrate which has IZO as a main component. Stacking and patterning a first conductive material on an insulating substrate to form a gate line including a gate line and a gate electrode connected to the gate line; Forming a reaction layer on the gate wiring; Stacking a gate insulating film, Forming a semiconductor layer, A data line stacked on and intersecting the gate line by stacking and patterning a second conductive material, a source electrode connected to the data line and adjacent to the gate electrode, and a drain electrode opposite to the source electrode with respect to the gate electrode; Forming a data wiring, Forming a reaction layer on the data line; Laminating a protective film, Patterning the passivation layer to form a first contact hole in the drain electrode; Forming a pixel electrode on the passivation layer, the pixel electrode being electrically connected to the drain electrode Method of manufacturing a thin film transistor substrate for a liquid crystal display device comprising a. In claim 6, The first and second conductive materials may include an aluminum-based metal. In claim 6, The pixel electrode is formed of a transparent conductive material. In claim 8, And the pixel electrode is formed of IZO. In claim 6, The gate line further includes a gate pad receiving a scan signal from the outside and transferring the scan signal to the gate line, The data line further includes a data pad which transfers an image signal from an external source to the data line. The passivation layer has second and third contact holes exposing the reaction layer on the gate pad together with the data pad and the gate insulating layer. And forming an auxiliary gate pad and an auxiliary data pad electrically connected to the gate pad and the data pad through the second and third contact holes on the same layer as the pixel electrode. . In claim 6, And the data line and the semiconductor layer are formed together in a single photolithography process using a photoresist pattern having a partially different thickness. In claim 11, The photoresist pattern may include a first part having a first thickness, a second part thicker than the first thickness, and a third part having no thickness and excluding the first and second parts. Manufacturing method. In claim 12, In the photolithography process, the photoresist pattern is formed using a photomask including a first region, a second region having a lower transmittance than the first region, and a third region having a higher transmittance than the first region. Method for manufacturing a thin film transistor substrate for a device. In claim 13, And forming the first portion between the source electrode and the drain electrode and the second portion over the data line in the photolithography process. The method of claim 14, A method of manufacturing a thin film transistor substrate for a liquid crystal display device, in which a slit pattern smaller than the resolution of a translucent film or an exposure machine is formed in the photomask in order to differently control the transmittance of the first to third regions. In claim 6, And forming an ohmic contact layer between the semiconductor layer and the data line. The method of claim 16, A method of manufacturing a thin film transistor substrate for a liquid crystal display device, wherein the data line, the contact layer, and the semiconductor layer are formed using one mask. A gate wiring made of a first conductive material on an insulating substrate, A gate insulating film covering the gate wiring, A semiconductor layer formed on the gate insulating film, A data line formed of a second conductive material and formed on the gate insulating layer; A protective film covering the data wiring, A reaction layer formed on at least one of the gate wiring and the data wiring; A transparent conductive film pattern electrically connected to the gate wiring or the data wiring via the reaction layer through a contact hole formed in the gate insulating film or the protective film Thin film transistor substrate comprising a. The method of claim 18, The thin film transistor substrate of which the first and second conductive materials include an aluminum-based metal. The method of claim 18, The thin film transistor substrate of which the gate insulating film and the protective film are made of silicon nitride. The method of claim 18, The transparent conductive film pattern is a thin film transistor substrate containing IZO as a main component. The method of claim 18, The gate line includes a gate line extending in a horizontal direction, a gate electrode connected to the gate line, and a gate pad receiving a scan signal from the outside and transferring the scan signal to the gate line, The data line may include a data line extending in a vertical direction, a source electrode connected to the data line, a drain electrode separated from the source electrode and facing the source electrode around the gate electrode, and receiving image signals from the outside. A thin film transistor substrate comprising a data pad to transfer to the data line. The method of claim 18, The reaction layer is a thin film transistor substrate having Al _x Si _y as a main component.