KR20010059013A - A method for forming a capacitor of a semiconductor device - Google Patents
A method for forming a capacitor of a semiconductor device Download PDFInfo
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- KR20010059013A KR20010059013A KR1019990066391A KR19990066391A KR20010059013A KR 20010059013 A KR20010059013 A KR 20010059013A KR 1019990066391 A KR1019990066391 A KR 1019990066391A KR 19990066391 A KR19990066391 A KR 19990066391A KR 20010059013 A KR20010059013 A KR 20010059013A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
Abstract
Description
본 발명은 반도체소자의 캐패시터 형성방법에 관한 것으로, 특히 반도체소자의 고집적화에 따른 리소그래피 ( lithograpy ) 공정의 한계로 인하여 캐패시터 간의 최소거리를 확보하기 어려운 문제점을 해결하기 위하는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a capacitor of a semiconductor device, and more particularly, to a technique for solving a problem that it is difficult to secure a minimum distance between capacitors due to a limitation of a lithography process due to high integration of a semiconductor device.
반도체소자가 고집적화되어 셀 크기가 감소됨에따라 저장전극의 표면적에 비례하는 정전용량을 충분히 확보하기가 어려워지고 있다.As semiconductor devices are highly integrated and cell size is reduced, it is difficult to secure a capacitance that is proportional to the surface area of the storage electrode.
특히, 단위셀이 하나의 모스 트랜지스터와 캐패시터로 구성되는 디램 소자는 칩에서 많은 면적을 차지하는 캐패시터의 정전용량을 크게하면서, 면적을 줄이는 것이 디램 소자의 고집적화에 중요한 요인이 된다.In particular, in a DRAM device having a unit cell composed of one MOS transistor and a capacitor, it is important to reduce the area while increasing the capacitance of a capacitor that occupies a large area on a chip, which is an important factor for high integration of the DRAM device.
그래서, ( εo × εr × A ) / T ( 단, 상기 εo 는 진공유전율, 상기 εr 은 유전막의 유전율, 상기 A 는 캐패시터의 면적 그리고 상기 T 는 유전막의 두께 ) 로 표시되는 캐패시터의 정전용량 C 를 증가시키기 위하여, 유전상수가 높은 물질을 유전체막으로 사용하거나, 유전체막을 얇게 형성하거나 또는 저장전극의 표면적을 증가시키는 등의 방법을 사용하였다.Thus, εo × εr × A) / T (where, εo is the vacuum dielectric constant, εr is the dielectric constant of the dielectric film, A is the area of the capacitor and T is the thickness of the dielectric film) of the capacitor C In order to increase, a method of using a material having a high dielectric constant as a dielectric film, forming a thin dielectric film, or increasing the surface area of a storage electrode has been used.
그리고, 상기 저장전극의 표면적을 증가시키기 위하여 삼차원적인 구조를 갖는 저장전극을 형성하였다.In addition, a storage electrode having a three-dimensional structure was formed to increase the surface area of the storage electrode.
그리고, 가장 보편적으로 사용하는 형상이 실린더형 저장전극이다.The most commonly used shape is a cylindrical storage electrode.
도시되지않았으나, 종래기술에 따른 반도체소자의 캐패시터 형성방법을 설명하면 다음과 같다.Although not shown, a method of forming a capacitor of a semiconductor device according to the prior art will be described.
먼저, 반도체기판 상부에 하부절연층을 형성한다. 이때, 상기 하부절연층은 소자분리막, 워드라인 및 비트라인 등의 단위소자들이 형성된 것이다.First, a lower insulating layer is formed on the semiconductor substrate. In this case, the lower insulating layer is formed of unit devices such as an isolation layer, a word line, and a bit line.
그리고, 상기 하부절연층은 비.피.에스.지. ( boro phospho silicate glass, 이하에서 BSPG 라 함 ) 절연막과 같이 유동성이 우수한 절연물질로 형성한다.The lower insulating layer is made of B.S.G. (Brophospho silicate glass, hereinafter referred to as BSPG) It is formed of an insulating material with excellent fluidity such as an insulating film.
그리고, 상기 반도체기판의 불순물 접합영역에 접속되는 제1도전체를 전체표면상부에 형성하고 그 상부에 희생산화막을 형성한다.A first conductor connected to the impurity junction region of the semiconductor substrate is formed on the entire surface, and a sacrificial oxide film is formed thereon.
그리고, 저장전극 마스크를 이용하여 상기 희생산화막과 제1도전체를 패터닝한다.The sacrificial oxide film and the first conductor are patterned using a storage electrode mask.
그 다음, 상기 희생산화막과 제1도전체의 식각 측벽에 제2도전체로 스페이서를 형성한다. 그리고, 상기 희생산화막을 제거함으로써 실린더형 저장전극을 형성한다.Next, spacers are formed on the etch sidewalls of the sacrificial oxide layer and the first conductor. The cylindrical storage electrode is formed by removing the sacrificial oxide film.
상기한 바와같이 종래기술에 따른 반도체소자의 캐패시터 형성방법은, 캐패시터가 형성되는 영역에 희생산화막을 패터닝하고 이 측벽에 스페이서를 형성하는 공정으로 실리더형 저장전극을 형성함으로써 반도체소자의 고집적화로 인하여 스페이서와 스페이서 간의 최소 거리를 노광하기가 어려워 실린더형 저장전극의 측벽에 스페이서 간에 쇼트 ( short ) 가 유발될 수 있고 그에 따른 반도체소자의 특성 및 신뢰성이 저하될 수 있는 문제점이 있다.As described above, the method of forming a capacitor of a semiconductor device according to the related art is formed by forming a cylinder-type storage electrode in a process of patterning a sacrificial oxide film on a region where a capacitor is formed and forming a spacer on the sidewalls, resulting in high integration of the semiconductor device. Since it is difficult to expose the minimum distance between the spacers, a short may be generated between the spacers on the sidewalls of the cylindrical storage electrodes, thereby degrading characteristics and reliability of the semiconductor device.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 저장전극이 형성되지않는 부분에 절연막을 패터닝하되, 저장전극이 형성되는 영역으로 상측이 휘어지도록 형성함으로써 후속공정으로 형성되는 실린더형 저장전극 간의 절연특성을 향상시키고, 특히 가장 취약한 특성을 갖는 실린더 측벽 상측을 타부분보다 간격이 크게 형성하여 반도체소자의 특성 및 신뢰성을 향상시킬 수 있는 반도체소자의 캐패시터 형성방법을 제공하는데 그 목적이 있다.In order to solve the above problems of the prior art, the insulating film is patterned on a portion where the storage electrode is not formed, and the upper side is bent to a region where the storage electrode is formed. It is an object of the present invention to provide a method for forming a capacitor of a semiconductor device which improves the characteristics and reliability of the semiconductor device by improving the insulating properties, and in particular, forming a larger gap than the other part of the upper side of the cylinder sidewall having the weakest characteristic.
도 1a 내지 도 1g 는 본 발명의 실시예에 따른 반도체소자의 캐패시터 형성방법을 나타낸 단면도.1A to 1G are cross-sectional views illustrating a method of forming a capacitor of a semiconductor device in accordance with an embodiment of the present invention.
<도면의 주요주분에 대한 부호의 설명〉<Explanation of symbols for main parts of drawing>
11 : 하부절연층 13 : 제1절연막11: lower insulating layer 13: first insulating film
15 : 저장전극 콘택플러그 17 : 제2절연막15: storage electrode contact plug 17: second insulating film
19 : 제3절연막 21 : 제4절연막19: third insulating film 21: fourth insulating film
23 : 저장전극용 도전층 25 : 제5절연막23 conductive layer for storage electrode 25 fifth insulating film
상기한 목적 달성을 위해 본 발명에 따른 반도체소자의 캐패시터 형성방법은,Capacitor forming method of a semiconductor device according to the present invention for achieving the above object,
반도체기판 상의 하부절연층 상부에 제1절연막을 형성하는 공정과,Forming a first insulating film on the lower insulating layer on the semiconductor substrate;
상기 제1절연막과 하부절연층을 식각하여 저장전극 콘택플러그를 형성하는 공정과,Forming a storage electrode contact plug by etching the first insulating layer and the lower insulating layer;
상기 콘택플러그에 상부에 저장전극마스크를 이용한 사진식각공정으로 제2절연막패턴을 형성하는 공정과,Forming a second insulating film pattern on the contact plug by a photolithography process using a storage electrode mask thereon;
상기 제2절연막패턴 측벽에 제3절연막 스페이서를 형성하고 전체표면상부에 제4절연막을 형성하는 공정과,Forming a third insulating film spacer on the sidewalls of the second insulating film pattern and forming a fourth insulating film on an entire surface thereof;
상기 제4절연막을 평탄화식각공정으로 식각하여 상기 제2절연막패턴을 노출시키는 공정과,Etching the fourth insulating layer by a planarization etching process to expose the second insulating layer pattern;
상기 제3절연막 스페이서 간의 제4절연막을 남기고 상기 제2,4절연막을 제거하는 공정과,Removing the second and fourth insulating films while leaving a fourth insulating film between the third insulating film spacers;
상기 콘택플러그에 접속되는 저장전극용 도전층을 전체표면상부에 형성하고 그 상부를 평탄화시키는 제5절연막을 형성하는 공정과,Forming a fifth insulating film for forming a conductive layer for a storage electrode connected to the contact plug on the entire surface and planarizing an upper portion thereof;
상기 제4절연막이 노출될때까지 평탄화식각하고 상기 제5절연막을 제거하여 실린더형 측벽 상측 끝부분이 실린더 내측으로 휘어진 실린더형 저장전극을 형성하는 공정을 포함하는 것을 특징으로한다.And flattening etching until the fourth insulating layer is exposed and removing the fifth insulating layer to form a cylindrical storage electrode having an upper end portion of the cylindrical sidewall bent into the cylinder.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 1a 내지 도 1g 는 본 발명의 실시예에 따른 반도체소자의 캐패시터 형성방법을 도시한 단면도이다.1A to 1G are cross-sectional views illustrating a method of forming a capacitor of a semiconductor device in accordance with an embodiment of the present invention.
먼저, 반도체기판(도시안됨) 상부에 하부절연층(11)을 형성한다. 이때, 상기하부절연층(11)은 소자분리막, 워드라인 및 비트라인 등의 단위소자들이 형성된 것이다.First, a lower insulating layer 11 is formed on a semiconductor substrate (not shown). In this case, the lower insulating layer 11 is formed of unit devices such as an isolation layer, a word line and a bit line.
그리고, 상기 하부절연층(11)은 비.피.에스.지. ( boro phospho silicate glass, 이하에서 BSPG 라 함 ) 절연막과 같이 유동성이 우수한 절연물질로 형성한다.The lower insulating layer 11 is made of B.S.G. (Brophospho silicate glass, hereinafter referred to as BSPG) It is formed of an insulating material with excellent fluidity such as an insulating film.
그 다음, 상기 하부절연층(11) 상부에 제1절연막(13)을 일정두께 형성하고 저장전극 콘택마스크(도시안됨)를 이용한 식각공정으로 상기 제1절연막(13)과 하부절연층(11)을 식각하여 상기 반도체기판의 예정된 영역을 노출시키는 콘택홀을 형성한다.Next, a first thickness of the first insulating layer 13 is formed on the lower insulating layer 11, and the first insulating layer 13 and the lower insulating layer 11 are formed by an etching process using a storage electrode contact mask (not shown). Etching to form a contact hole for exposing a predetermined region of the semiconductor substrate.
그리고, 상기 콘택홀을 매립하는 콘택플러그(15)를 형성한다. 이때, 상기 콘택플러그(15)는 텅스텐, 폴리실리콘 등과 같은 도전층으로 형성한다. (도 1a)In addition, a contact plug 15 filling the contact hole is formed. In this case, the contact plug 15 is formed of a conductive layer such as tungsten or polysilicon. (FIG. 1A)
그 다음, 전체표면상부에 제2절연막(17)을 형성하되, 후속공정으로 형성될 실린더형 저장전극의 높이만큼 두껍게 형성한다.Next, a second insulating film 17 is formed over the entire surface, and as thick as the height of the cylindrical storage electrode to be formed in a subsequent process.
그리고, 저장전극 마스크(도시안됨)를 이용한 사진식각공정으로 패터닝한다.(도 1b)Then, patterning is performed by a photolithography process using a storage electrode mask (not shown) (FIG. 1B).
그 다음, 상기 제2절연막(17)패턴 측벽에 제3절연막(19)으로 스페이서를 형성한다. (도 1c)Next, spacers are formed on the sidewalls of the second insulating layer 17 as the third insulating layer 19. (FIG. 1C)
그리고, 전체표면상부에 제4절연막(21)을 형성하고 상기 제1절연막(17)이 노출될때까지 평탄화식각한다.A fourth insulating film 21 is formed over the entire surface and planarized etching is performed until the first insulating film 17 is exposed.
이때, 상기 평탄화식각공정은 화학기계연마 ( chemical mechenicalpolishing, 이하에서 CMP 라 함 ) 방법으로 실시하거나 전면식각공정으로 실시한다. (도 1d, 도 1e)In this case, the planarization etching process may be performed by chemical mechanical polishing (hereinafter referred to as CMP) method or by a full surface etching process. (FIG. 1D, FIG. 1E)
그 다음, 상기 제2절연막(17)과 제3절연막(19)을 제거하고 상기 제3절연막(19) 스페이서 사이의 상기 제4절연막(21)을 남기는 동시에, 상기 저장전극의 콘택플러그(15)를 노출시킨다.Next, the second insulating layer 17 and the third insulating layer 19 are removed and the fourth insulating layer 21 is left between the spacers of the third insulating layer 19, and at the same time, the contact plug 15 of the storage electrode 15 is removed. Expose
그리고, 상기 콘택플러그(15)를 통하여 상기 반도체기판에 접속되는 저장전극용 도전층(13)을 전체표면상부에 일정두께 형성한다.Then, the conductive electrode 13 for the storage electrode, which is connected to the semiconductor substrate through the contact plug 15, is formed to have a predetermined thickness on the entire surface.
그 다음, 전체표면상부를 평탄화시키는 제5절연막(25)을 형성한다. 이대, 상기 제5절연막(25)은 감광막을 대신 사용할 수 있다. (도 1f)Next, a fifth insulating film 25 is formed to planarize the entire upper surface portion. In this case, the fifth insulating film 25 may use a photosensitive film instead. (FIG. 1F)
그리고, 상기 제4절연막(21)이 노출되도록 CMP 방법으로 평탄화식각하여 실린더형 저장전극의 측벽 상측이 실린더형의 안측으로 기울어진 형태로 형성함으로써 절연특성을 향상시킨다.In addition, the planar etching is performed by the CMP method so that the fourth insulating layer 21 is exposed, and the upper sidewall of the cylindrical storage electrode is formed to be inclined to the inner side of the cylindrical shape, thereby improving insulation characteristics.
이때, 상기 CMP 방법은 전면건식식각공정으로 대신할 수 있다. (도 1g)In this case, the CMP method may be replaced by a full dry etching process. (Fig. 1g)
이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 캐패시터 형성방법은, 실린더형 저장전극 영역 간에 절연막 패턴을 형성하고 이를 이용하여 실린더형 저장전극의 측벽 스페이서를 형성함으로써 저장전극 간의 절연특성을 용이하게 향상시킬 수 있어 반도체소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 생산성 및 수율을 향상시킬 수 있는 효과를 제공한다.As described above, in the method of forming the capacitor of the semiconductor device according to the present invention, an insulating pattern is formed between the cylindrical storage electrode regions and the sidewall spacers of the cylindrical storage electrode are formed using the same, thereby easily improving the insulation characteristics between the storage electrodes. It is possible to improve the characteristics and reliability of the semiconductor device, thereby providing an effect that can improve the productivity and yield of the semiconductor device.
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KR100682192B1 (en) * | 2000-06-23 | 2007-02-12 | 주식회사 하이닉스반도체 | A method for forming a capacitor of a semiconductor device |
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KR950021644A (en) * | 1993-12-31 | 1995-07-26 | 김주용 | Semiconductor Memory and Manufacturing Method |
KR0161196B1 (en) * | 1995-06-30 | 1998-12-01 | 김주용 | Fabricating method of capacitor storage node |
KR970024178A (en) * | 1995-10-11 | 1997-05-30 | 김주용 | Method for forming charge storage electrode of capacitor |
KR19990001772A (en) * | 1997-06-17 | 1999-01-15 | 윤종용 | Capacitor Manufacturing Method of Semiconductor Device with Cylindrical Bottom Electrode |
KR20000003633A (en) * | 1998-06-29 | 2000-01-25 | 김영환 | Method for forming storage electrode of semiconductor devices |
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Publication number | Priority date | Publication date | Assignee | Title |
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KR100682192B1 (en) * | 2000-06-23 | 2007-02-12 | 주식회사 하이닉스반도체 | A method for forming a capacitor of a semiconductor device |
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