KR20010092874A - Method of fabricating a capacitor in a semiconductor device - Google Patents

Abstract

PURPOSE: A capacitor fabrication method is provided to increase a surface area of a lower electrode and to prevent a short between the lower electrodes by forming the lower electrode having a dual cylindrical structure. CONSTITUTION: After forming an interlayer dielectric(32) having a contact hole on a silicon substrate(30), a contact plug(33) is formed in the contact hole. Then, a polysilicon layer(37) for forming an outer wall of an outer cylinder of a lower electrode is formed on the resultant structure, and an amorphous silicon layer(38) for forming an inner wall of the outer cylinder is formed on the polysilicon layer(37). After forming sidewall spacers made of a second sacrificial layer, a second amorphous silicon layer(40) for forming an inner cylinder of the lower electrode is formed. By removing the remaining sidewall spacers and sacrificial layers, the lower electrode is formed. The lower electrode includes the outer cylinder having the remaining polysilicon layer(37) and the remaining first amorphous silicon layer(38) and the inner cylinder having the remaining second amorphous silicon layer(40). Adjacent outer cylinders are isolated each other to an etch stopping layer(340).

Description

Method of fabricating a capacitor in a semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a capacitor of a semiconductor device. In particular, when a hemispherical silicon grain is employed to expand the surface area of a lower electrode, the lower electrode is formed in a double cylinder structure and the outer cylinder is a double layer of a polysilicon layer / amorphous silicon layer. The outer layer of the outer cylinder is formed of a polysilicon layer so that hemispherical silicon grains are not formed on the outer wall of the outer cylinder, thereby preventing short circuits due to hemispherical silicon grains between neighboring lower electrodes, and extending the surface area of the lower electrode required. The present invention relates to a method for manufacturing a capacitor having a cylindrical lower electrode of a semiconductor device so as to omit further doping.

As the semiconductor devices are highly integrated, the area occupied by the capacitor also decreases as the size of the cell decreases. Therefore, the surface of the lower electrode is irregularly formed to secure the required capacitance.

In order to secure the necessary surface area of the lower electrode to the maximum, the technique of forming protrusions on the surface of the lower electrode with HSG (hemisphere silicon grain) is called a surface area enhanced silicon (SAES) formation method. In order to form HSG (hemispherical silicon grain) is formed on the lower electrode surface.

That is, the SAES process is used as a general process for increasing the surface area of the lower electrode. The key to this process is to secure the maximum capacitance by maximizing the density and grain size of the SAES while maintaining the electrical characteristics of the capacitor.

However, when maximizing the size of the silicon grain, the silicon grains formed on the peaks of the lower electrode are vulnerable to physical stress, and thus, from the lower electrode pattern of the cylindrical form in the subsequent processes such as pre-doping cleaning and pre-dielectric film deposition cleaning. This can lead to reduced capacitance and short circuits of neighboring devices.

The conventional technique employing SAES removes a predetermined portion of the interlayer insulating layer to form a contact hole exposing a predetermined impurity diffusion region, and then forms polysilicon and amorphous silicon on the interlayer insulating layer including the contact hole. After forming a thickness, a hard mask is formed on the oxide film and patterned thereon to form a basic skeleton of the lower electrode, and then a plurality of hemispherical silicon grains are formed thereon to maximize the surface area of the lower electrode.

The dielectric film and the upper electrode are sequentially formed on the lower electrode to complete the capacitor element used in the DRAM of the semiconductor device.

1A to 1D are cross-sectional views of a capacitor manufacturing process of a semiconductor device having a lower electrode having a hemispherical grain formed according to the prior art.

Referring to FIG. 1A, an interlayer insulating layer is formed on a silicon substrate 10, which is a p-type semiconductor substrate having an impurity diffusion region 11 doped with n-type impurities such as acene or phosphorus (P). An oxide film 12 is formed of (12), and then a photoresist film (not shown) is applied over the 12.

After the photoresist film is exposed and developed to form a photoresist pattern (not shown) for exposing the impurity diffusion region 11, the exposed portion of the interlayer insulating layer 12 is used as an etching mask. The contact hole exposing the impurity region 11 is formed by removing by anisotropic etching such as dry etching.

After removing the photoresist pattern, the polysilicon layer 13 doped with P ions as a p-type impurity as the first conductive layer 13 on the interlayer insulating layer 12 including the contact hole has a predetermined thickness. After deposition by chemical vapor deposition (CVD), the surface of the interlayer insulating layer 12 is etched back to form a contact plug 13 made of polysilicon remaining only in the contact hole.

The nitride film 14 is deposited on the interlayer insulating layer 12 including the upper surface of the contact plug 13 by the etching stop layer 14 by chemical vapor deposition to a predetermined thickness.

Subsequently, the first sacrificial layer 15 is formed by thickly depositing an oxide film 15 having excellent etching property to a predetermined thickness as a sacrificial film for forming a cylindrical lower electrode.

An etch mask 16 is formed on the sacrificial layer 15 to pattern the first sacrificial layer 15 to be used as the cylindrical lower electrode support layer. In this case, the etching mask 16 is formed by forming polysilicon on the first sacrificial layer 15 and then patterning the photolithography with photolithography.

Referring to FIG. 1B, the first sacrificial layer made of the oxide film not protected by the etch mask and the etch stop layer made of the nitride film are sequentially removed to form the supporting film 150 made of the remaining first sacrificial layer 150.

Then, the etching mask is removed by a wet etching method.

Next, an amorphous silicon layer 17 for forming a lower electrode is deposited on the entire surface of the substrate including the supporting layer 150 by chemical vapor deposition.

Then, the second sacrificial layer 18 is formed on the amorphous silicon layer 17 with an oxide film so as to sufficiently fill the valleys between the supporting films 150.

Referring to FIG. 1C, a predetermined portion of the second sacrificial layer 18, the amorphous silicon layer 17, and the support layer 150 may be removed by a method such as chemical mechanical polishing to form a support layer formed of an oxide film ( 150 surface is exposed. At this time, the removed portion is as much as the cutting line I-I 'of FIG.

Referring to FIG. 1D, the surface of the cylindrical lower electrode of the capacitor including the remaining amorphous silicon layer 17 is exposed by wet etching by removing the second sacrificial layer, which is made of the oxide film and the exposed support film and also the oxide film.

Then, SiH ₄ gas is flowed to the exposed surface of the amorphous silicon layer 17 to form a hemispherical silicon grain layer 19 for extending the surface area of the lower electrode.

At this time, as shown in the figure, the amorphous silicon layer 17 in which the hemispherical silicon grains grow is easily separated from the chartering process before doping, because the gap between adjacent portions S is narrow, and thus, the lower electrodes may be shorted to each other. have.

Then, in order to improve the electrical characteristics such as conductivity of the lower electrode, hemispherical silicon grain layer 19 and amorphous silicon layer 17 are further doped with phosphorus ions.

Although not shown, a cylindrical capacitor used in DRAM of a semiconductor device is formed by depositing a dielectric film on the surfaces of the lower electrodes 17 and 19 and then forming an upper electrode covering the dielectric film with a conductor such as doped polysilicon or metal. Complete the manufacture of

However, in the above-described method of manufacturing a capacitor according to the related art, since the hemispherical silicon grains formed at the corners of the lower electrode pattern are easily detached from the lower electrode pattern due to external physical impact, the silicon grains separated are short-circuited between adjacent cylinders. (Bridge phenomenon) decreases the yield of the device, and since hemispherical silicon grains are formed on both the outer and inner walls of the cylindrical lower electrode, a short circuit between the silicon grains of the neighboring lower electrodes can also occur, and the hemispherical silicon grain Since the concentration of amorphous silicon should be low to facilitate growth, additional doping of the amorphous silicon layer to improve the depletion phenomenon after the formation of hemispherical silicon grains is required, and since the lower electrode of a simple cylinder structure is formed, the dielectric film deposition of the lower electrode is performed. There is a limit to improving the site. There are problems.

Accordingly, an object of the present invention is to form the lower electrode in a double cylinder structure when the hemispherical silicon grain is adopted to expand the surface area of the lower electrode, and the outer cylinder is formed of a double layer of a polysilicon layer / amorphous silicon layer to form an outer layer of the outer cylinder. By forming a silicon layer, hemispherical silicon grains are not formed on the outer wall of the outer cylinder to prevent short-circuit by hemispherical silicon grains between neighboring lower electrodes, to extend the surface area of the lower electrode, and to omit additional doping to the lower electrode. A capacitor manufacturing method having a cylindrical lower electrode of a semiconductor device is provided.

According to the present invention, there is provided a method of manufacturing a capacitor of a semiconductor device, the method including: forming a contact plug in an insulating layer formed on a semiconductor substrate and contacting a surface of the semiconductor substrate through a predetermined portion of the insulating layer; Forming an etch stop layer and a first sacrificial layer on the insulating layer including a contact plug, and patterning the first sacrificial layer and the etch stop layer to the first sacrificial layer remaining on the etch stop layer remaining Forming a support layer and exposing the remaining surface of the insulating layer and the contact plug; and forming a polysilicon layer, a first amorphous silicon layer, and a second sacrificial layer on the exposed insulating layer including the exposed etch stop layer and the support layer. Sequentially forming the second sacrificial layer and leaving only the sidewalls of the first amorphous silicon layer to form sidewall spacers. Forming a second amorphous silicon layer on the exposed sidewall spacer and the surface of the first amorphous silicon layer, and filling a space between the second amorphous silicon layer and the third sacrificial layer to form the second amorphous silicon layer. Forming on the silicon layer, and removing a predetermined portion of the third sacrificial layer, the second amorphous silicon layer, the first amorphous silicon layer, the sidewall spacer, the polysilicon layer, and the support film by a chemical mechanical polishing by a predetermined height. Exposing the surface of the support film, removing the remaining third sacrificial layer, sidewall spacers and support film, and forming a hemispherical silicon grain layer on the exposed second amorphous silicon layer and the first amorphous silicon layer. And sequentially forming a dielectric film and an upper electrode on the hemispherical silicon grain layer, the remaining second and second amorphous silicon layers, and the polysilicon layer. It comprise.

1A to 1D are cross-sectional views of a capacitor manufacturing process of a semiconductor device having a lower electrode having hemispherical grains according to the prior art.

2A to 2F are cross-sectional views of a capacitor manufacturing process of a semiconductor device according to the present invention.

According to the present invention, when a hemispherical silicon grain is employed to enlarge the lower electrode surface area of the capacitor, it is possible to prevent a short circuit between neighboring lower electrodes of the capacitor and to omit additional doping of the lower electrode formed of amorphous silicon, and the lower electrode may be internally sealed. Since it is formed in the form of a double cylinder consisting of you and the outer cylinder, it is possible to maximize the surface area of the lower electrode on which the dielectric film is deposited.

That is, in the present invention, the outer surface of the lower electrode in the form of a cylinder, which causes short circuit between the lower electrodes, is formed of polysilicon doped with high concentration of phosphorus ions, which is difficult to grow, and the hemispherical silicon grain is formed on the outer surface of the lower electrode. Prevent formation. Therefore, a short circuit between adjacent lower electrodes is prevented.

In addition, in the present invention, since the outer wall of the outer cylinder is formed of polysilicon doped with a high concentration of phosphorus ions, the dopant (inion) of polysilicon is an amorphous hemispherical silicon grain growth region, without any additional doping, unlike the prior art. Diffusion to the silicon layer ensures the electrical characteristics of the lower electrode.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2A to 2F are cross-sectional views of a capacitor manufacturing process of a semiconductor device having a lower electrode having a double cylinder structure consisting of an inner cylinder and an outer cylinder according to the present invention.

Referring to FIG. 2A, a transistor (not shown) is formed in a DRAM cell of a semiconductor device, and an n-type impurity, which is a second conductive type such as an ashen (As) or a phosphorus (P), which is a source / drain region of a transistor, has a high concentration. An oxide film 32 is formed on the p-type silicon substrate 30, which is the first conductivity type semiconductor substrate having the doped impurity diffusion region 31 formed therein, as an interlayer insulating layer 32, and then a photoresist is formed thereon. A film (not shown) is applied.

After the photoresist film is exposed and developed to form a photoresist pattern (not shown) for exposing the impurity diffusion region 31, the exposed portion of the interlayer insulating layer 32 is used as an etching mask. The contact hole exposing the impurity region 31 is formed by removing by anisotropic etching such as dry etching.

After the photoresist pattern is removed, the chemical vapor deposition is performed on the interlayer insulating layer 32 including the contact hole to form a polysilicon layer 33 doped with P ions as a p-type impurity as a conductive layer 33 to have a predetermined thickness. Chemical Vapor Deposition (hereinafter, referred to as CVD), and then etched back to expose the surface of the interlayer insulating layer 32 to form a contact plug 33 made of polysilicon remaining only in the contact hole.

The nitride film 34 is formed on the interlayer insulating layer 32 including the upper surface of the contact plug 33 by the etching stop layer 34 by chemical vapor deposition to a predetermined thickness. In this case, the etch stop layer 34 is formed of polysilicon and an oxide layer and an insulating material having a large etching selectivity.

Subsequently, the first sacrificial layer 35 is formed by thickly depositing an oxide film 35 having excellent etching property to a predetermined thickness as a sacrificial film for forming a cylindrical lower electrode.

An etch mask 36 is formed on the sacrificial layer 35 to pattern the first sacrificial layer 35 to be used as the cylindrical lower electrode support layer. In this case, the etching mask 36 is formed by forming polysilicon on the first sacrificial layer 35 and then patterning the photolithography.

Referring to FIG. 2B, the first sacrificial layer made of the oxide film not protected by the etch mask and the etch stop layer made of the nitride film are sequentially removed to form the supporting film 350 made of the remaining first sacrificial layer 350.

Then, the etching mask is removed by a wet etching method.

Next, a polysilicon layer 37 for forming an outer cylinder outer wall of the lower electrode on the entire surface of the substrate including the supporting film 350 is formed by chemical vapor deposition. In this case, the polysilicon layer is formed such that phosphorus ions are doped at a high concentration.

Then, the first amorphous silicon layer 38 for forming the outer cylinder inner wall is formed on the surface of the polysilicon layer 37 by a predetermined thickness.

Then, in order to form the inner cylinder support film, the second sacrificial layer 39 is formed by depositing a predetermined thickness on the first amorphous silicon layer 38 with an oxide film. At this time, the thickness of the second sacrificial layer 39 is determined in consideration of the distance between the outer cylinder wall and the inner cylinder wall.

Referring to FIG. 2C, the sidewall spacer 390 including the second sacrificial layer 390 is formed by performing etch back to expose the surface of the first amorphous silicon layer 38 to the second sacrificial layer. Thus, the side thickness of the sidewall spacers 390 becomes the gap between the outer cylinder wall and the inner cylinder wall.

Subsequently, a second amorphous silicon layer 40 for forming an inner cylinder is formed on the surface of the exposed first amorphous silicon layer 38 and the surface of the sidewall spacer 390 by chemical vapor deposition.

The third sacrificial layer 410 is formed by depositing an oxide film having an excellent etching property on the second amorphous silicon layer 49 to sufficiently fill the valleys between the second amorphous silicon layer 40.

Referring to FIG. 2D, the third sacrificial layer 41, the second amorphous silicon layer 40, the first amorphous silicon layer 38, the sidewall spacer 390, the polysilicon layer 37, and the support layer 350 are provided. As much as a predetermined portion of is removed by a method such as chemical mechanical polishing to expose the surface of the support film 350 made of an oxide film. At this time, the cut line of the portion to be removed is indicated at II-II 'of FIG. 2C.

Therefore, as a result of the chemical mechanical polishing, the third sacrificial layer 41, the second amorphous silicon layer 40, the first amorphous silicon layer 38, the sidewall spacer 390, the polysilicon layer 37, the support film 350 ) Surface is exposed.

Referring to FIG. 2E, the lower portion of the capacitor including the polysilicon layer 37 and the first amorphous silicon layer 38 remaining by removing the third sacrificial layer, the sidewall spacer, and the support layer 350 formed of an oxide film by wet etching. The surface of the inner cylinder for the lower electrode composed of the outer cylinder for the electrode and the remaining second amorphous silicon layer 40 is exposed.

Therefore, the lower electrode of one capacitor includes an outer cylinder 38 and 37 composed of an inner wall 38 of amorphous silicon and an outer wall 37 of polysilicon, and an inner cylinder 40 formed of only amorphous silicon.

In addition, the external cylinders are insulated from each other by an etch stop film 340 formed of a neighboring external cylinder and the remaining nitride film.

Referring to FIG. 2F, the SiH ₄ gas is flowed on the exposed outer cylinder 38 and the inner cylinder 40 including only amorphous silicon to form a hemispherical silicon grain layer 42 for extending the surface area of the lower electrode.

At this time, as shown, since the hemispherical silicon grains are formed on the amorphous silicon site due to the deposition characteristics, hemispherical silicon grains are not formed on the surface of the outer wall 37 of the outer cylinder made of polysilicon doped with phosphorus ions. Therefore, there is a fear that adjacent lower electrodes may be shorted to each other by hemispherical silicon grains.

Then, annealing or the like undergoes a thermal process to crystallize the amorphous silicon. At this time, phosphorus ions of the heavily doped polysilicon forming the outer wall 37 are diffused into the inner wall 38 and the inner cylinder 40, so that The doping concentration of the lower electrode is increased to improve the electrical characteristics of the lower electrode.

Therefore, in the exemplary embodiment of the present invention, indium ion doping of the separate hemispherical silicon grain layer 42 and the first to second amorphous silicon layers 38 and 40 is required to improve electrical characteristics such as conductivity of the lower electrode. I never do that.

Subsequently, although not shown, the dielectric film 43 is deposited on the surfaces of the lower electrodes 37, 38, 40, and 42, and then the upper electrode 44 is formed to cover the dielectric film with a conductor such as doped polysilicon or metal. This completes the manufacture of the cylindrical capacitor used in the DRAM of the semiconductor device.

Therefore, the present invention does not form hemispherical silicon grains on the outer cylinder outer wall of the lower electrode, thereby preventing short circuits between neighboring lower electrodes, and forming the outer wall of polysilicon doped with difficulty so that diffusion into the remaining amorphous silicon in subsequent thermal processes is prevented. As a result of the magnetic doping, no additional doping to the lower electrode is required, and since the lower electrode is formed of a double structure consisting of an outer cylinder and an inner cylinder, the dielectric film deposition portion of the lower electrode is greatly increased to improve the capacitance of the capacitor. have.

Claims (5)

Forming a contact plug in an insulating layer formed on the semiconductor substrate and penetrating a predetermined portion of the insulating layer and in contact with the surface of the semiconductor substrate; Forming an etch stop layer and a first sacrificial layer on the insulating layer including the contact plug; Patterning the first sacrificial layer and the etch stop layer to form a support layer formed of the first sacrificial layer remaining on the etch stop layer and exposing the remaining insulating layer and the contact plug surface; Sequentially forming a polysilicon layer, a first amorphous silicon layer, and a second sacrificial layer on the insulating layer including the exposed etch stop layer and the support layer; Leaving the second sacrificial layer only on the side of the first amorphous silicon layer to form a sidewall spacer; Forming a second amorphous silicon layer on the exposed sidewall spacers and the first amorphous silicon layer surface; Forming a third sacrificial layer on the second amorphous silicon layer to sufficiently fill a space between the second amorphous silicon layer; Removing a predetermined portion of the third sacrificial layer, the second amorphous silicon layer, the first amorphous silicon layer, the sidewall spacer, the polysilicon layer, and the support layer by a chemical mechanical polishing to expose the remaining surface of the support layer; , Removing the remaining third sacrificial layer, the sidewall spacers and the support film; Forming a hemispherical silicon grain layer on the exposed surfaces of the second amorphous silicon layer and the first amorphous silicon layer; And sequentially forming a dielectric film and an upper electrode on the hemispherical silicon grain layer, the remaining second, the amorphous silicon layer, and the polysilicon layer. The method according to claim 1, And the first to third sacrificial layers are formed of an oxide film and the etch stop layer is formed of a nitride film. The method according to claim 1, Wherein said polysilicon layer is formed to be heavily doped with phosphorus ions. The method according to claim 1, Wherein the remaining second amorphous silicon becomes an inner cylinder structure in the lower electrode of the double cylinder structure, and the remaining polysilicon layer and the first amorphous silicon layer form an outer cylinder structure. . The method according to claim 1, And removing the remaining third sacrificial layer, the sidewall spacers and the support layer by wet etching at the same time.