JP2005019741A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device, excellent in transistor characteristics and high in reliability, in the semiconductor device having a vertical type transistor. <P>SOLUTION: In the semiconductor device having a first periodical structure wherein vertical type transistors are arranged periodically on the main plane of a silicon substrate, at least one piece or more and preferably three pieces or more of vertical type dummy transistors are formed at the end part of the first periodical structure with a period same as that of the first periodical structure, since the stresses of the vertical type transistors in the first periodical structure become uniform, the semiconductor device, wherein the characteristics of vertical type transistors in the first periodical structure are uniform, can be obtained. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a vertical field effect transistor.
[0002]
[Prior art]
In recent years, with the development of information communication equipment, higher integration of semiconductor devices such as LSIs has been promoted. In particular, a planar field effect transistor has been widely used because of its low power consumption. However, its high integration has been promoted mainly by miniaturization of the structure, which is an advancement of lithography technology for processing semiconductor elements. It has been supported. However, recently, the required minimum processing size (minimum processing size of the gate length) has become below the wavelength level of light used for lithography, and further miniaturization processing is becoming difficult.
[0003]
Thus, a vertical field effect transistor (hereinafter referred to as a vertical transistor) has been proposed as means for highly integrating field effect transistors. A vertical transistor has a columnar structure in which a source layer, a channel layer, and a drain layer are formed in a direction perpendicular to the substrate surface. Therefore, compared with a planar field effect transistor that uses a conventional silicon (Si) substrate as a surface, the Si substrate surface The area occupied by can be reduced (the projected area on the Si substrate surface is small). Further, the vertical transistor has a feature that the operation speed of the transistor can be increased without depending on the lithography technique because the gate length of the vertical transistor can be controlled by the film thickness of the film formation technique. The vertical transistor is disclosed in, for example, Patent Document 1.
[0004]
[Patent Document 1]
JP 2002-83945 A
[Non-Patent Document 1]
Akemi Hamada et al. Vol., "IE Trans. Electron Devices", 1991, vol. 38, no. 4, p. 895-900
[0005]
[Problems to be solved by the invention]
Since the vertical transistor described above is a columnar transistor in which the drain layer, the channel layer, and the source layer are stacked in the vertical direction (vertical direction of the substrate surface), the height in the vertical direction is planar compared to the horizontal direction of the substrate surface. Compared to other transistors, it has the feature of becoming larger. In a semiconductor device, there is a portion where transistors are periodically arranged adjacent to each other on an electric circuit. In the conventional planar field effect transistor, the step ratio between the top surface of the transistor array and the surface where the transistor is not formed is small even at the end of the transistor array having a small aspect ratio and periodically formed. The collapse of the symmetry of the directional structure was small. However, at the end of the portion where the vertical transistors are continuously arranged adjacent to each other, the step becomes large, and the symmetry of the structure with the portion where the vertical transistor is not formed is greatly broken.
[0006]
In general, in a semiconductor device manufacturing process, stress is generated inside an element due to a difference in linear expansion coefficient between materials, a difference in lattice constant, and film shrinkage in a heat treatment process.
[0007]
The inventors of the present application conducted a stress analysis of a portion where a plurality of vertical transistors are periodically formed continuously. As a result, it has been clarified that the stress at the end of the transistor is different from the transistor near the center due to the discontinuity of the structure.
[0008]
It has been conventionally studied that stress changes the characteristics of a transistor (see, for example, Non-Patent Document 1). Even in a vertical transistor formed of silicon, it is considered that the characteristics change due to stress.
[0009]
Therefore, from the results of the stress analysis described above, in the case of the vertically arranged vertical transistors, the stress is different at the end and the center, so that the plurality of transistor characteristics at the ends of the vertical transistor array are It was clarified that there is a problem that it is different from the characteristics near the part. As a portion where a plurality of vertical transistors are periodically formed continuously, for example, there is a memory mat in the case where a SRAM (Static Random Access Memory) memory cell is formed using vertical transistors.
[0010]
Also, since the vertical transistor has a higher aspect ratio structure than the planar type that has been widely used as described above, the vertical transistor is formed in a portion other than, for example, a planar transistor. In a peripheral circuit in which a type transistor or a resistance element is formed, a difference in height occurs in the height of the element. In the manufacturing process of a semiconductor device, a layer in which a vertical transistor is formed is filled with an interlayer insulating film made of, for example, silicon oxide, and then the surface is planarized by a CMP (Chemical Mechanical Polishing) process. Move on to the process. However, CMP in a portion with a large difference in height is difficult to flatten after polishing, and there are problems such as an increase in manufacturing cost and productivity not being improved.
[0011]
In general, in a semiconductor device, a parallel plate type MOS capacitor is used for an inter-power source capacitance or an analog capacitance. The MOS capacitor occupies a large area in the semiconductor device, and there is a problem that miniaturization and high integration of the semiconductor device are hindered.
In general, a resistance element is used in a semiconductor device. However, since the resistance element is also formed in the surface of the Si substrate, there is a problem that the semiconductor device is hindered from being downsized and highly integrated.
[0012]
The present invention has been made to solve at least one of the above problems. A first object of the present invention is to provide a semiconductor device having a vertical transistor, which is excellent in characteristics of the vertical transistor. A second object of the present invention is to provide a semiconductor device that is excellent in manufacturing cost. It is a third object of the present invention to provide a semiconductor device that achieves miniaturization and high integration of MOS capacitors. A fourth object of the present invention is to provide a semiconductor device in which a resistance element is miniaturized and highly integrated. A fifth object of the present invention is to provide a semiconductor device having excellent mechanical reliability.
[0013]
[Means for Solving the Problems]
In the semiconductor device having the first periodic structure in which the vertical transistors are periodically arranged on the main plane of the silicon substrate, the first periodic structure and the first periodic structure are arranged at the end of the first periodic structure. This is solved by forming at least one dummy vertical transistor, more preferably three or more dummy vertical transistors in the same cycle. Thereby, since the stress of the vertical transistor in the first periodic structure becomes uniform, a semiconductor device in which the characteristics of the vertical transistor in the first periodic structure are uniform can be obtained.
[0014]
Further, in the semiconductor device having a vertical transistor formed on the main surface of the silicon substrate and a peripheral circuit formed around the vertical transistor, a dummy vertical transistor is formed on the upper surface of the peripheral circuit. It is solved by doing. Thereby, the same height as that of the vertical transistor is obtained on the peripheral circuit by the dummy vertical transistor, so that the effect of preventing dishing in the CMP process can be obtained.
[0015]
Further, in the above-described semiconductor device, the above problem is solved by forming a capacitive element between the channel of the dummy vertical transistor and a gate electrode adjacent to the dummy vertical transistor through a gate insulating film. As a result, the capacitance formed by the conventional plate capacitor can be three-dimensionally formed, so that the semiconductor device can be highly integrated.
[0016]
Further, the above problem can be solved by using the source, channel and drain of the dummy vertical transistor as a resistance element in the semiconductor device described above. As a result, the dummy vertical field effect transistor can be effectively used, and the semiconductor device can be highly integrated.
[0017]
Further, in the above semiconductor device, the above problem is solved by forming a contact plug at the lower end of the dummy vertical transistor. Thereby, the mechanical strength in the manufacturing process of the dummy vertical transistor can be increased.
[0018]
Further, in the above-described semiconductor device, the above problem can be solved by making the diameter of the dummy vertical transistor larger than that of the vertical transistor. Thereby, the mask data used in the manufacturing process can be reduced, and the mechanical strength in the manufacturing process of the dummy vertical transistor can be increased.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
<Example 1>
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. 1 to 3 are schematic cross-sectional views of the semiconductor device of this embodiment (cross-sections A to B, C to D, and E to F of FIG. 4), and FIG. 4 is a plan layout of the semiconductor device of this embodiment. FIG. 5 is an electric circuit diagram showing a part of the semiconductor device of this embodiment, FIG. 6 is a stress analysis result of the channel portion stress generated by the manufacturing process of the vertical transistor, and FIGS. 7 to 60 are this embodiment. It is a cross-sectional schematic diagram showing a part of manufacturing process of the semiconductor device.
[0020]
As shown in FIG. 1 (A-B cross section in FIG. 4), FIG. 2 (C-D cross section in FIG. 4), and FIG. 3 (E-F cross section in FIG. 4), A vertical field effect transistor 100 formed on the main plane side of the substrate 1, a planar field effect transistor 10 which is electrically connected to the vertical field effect transistor 100 and constitutes an SRAM cell, and the SRAM cell periodically. The dummy vertical field effect transistor d100 formed adjacent to the end of the vertical transistor row formed in the memory mat arranged in the memory mat and its peripheral circuit.
[0021]
An electric circuit diagram of the SRAM cell is shown in FIG. In this embodiment, the transistors P1 and P2 are formed by vertical field effect transistors, and the transistors N1, N2, N3, and N4 are formed by planar field effect transistors.
[0022]
The planar field effect transistor 10 includes an n-type source / drain (12, 13) formed in a p-type well 11 formed on a Si substrate main plane, a gate insulating film 14, and a gate electrode 15. Silicides 17 and 18 are formed on the upper surface of the transistor and the upper surfaces of the source / drain (12, 13). These planar field effect transistors are composed of a silicon oxide film (SiO 2). ₂ ) And the shallow trench isolation 2 made of silicon nitride (SiN) is insulated from other transistors.
[0023]
The gate insulating film 14 is, for example, a silicon oxide film (SiO ₂ ), Silicon nitride film (SiN), oxynitride film (SiON), titanium oxide (TiO) ₂ ), Zirconium oxide (ZrO) ₂ ), Hafnium oxide (HfO) ₂ ), Tantalum pentoxide (Ta ₂ O ₅ Etc.) or a laminated structure thereof. The gate electrode 15 is made of, for example, a polycrystalline silicon film, a metal film such as tungsten (W), platinum (Pt), ruthenium (Ru), or a laminated structure thereof. On the side walls of the gate insulating film 14, the gate electrode 15, and the silicides 17 and 18, silicon nitride (SiN) or silicon oxide film (SiO ₂ ) Is formed.
[0024]
On the upper surface of the planar type field effect transistor 10, for example, a BPSG (Boron-doped Phospho Silicate Glass) film, an SOG (Spin On Glass) film, a TEOS (Tetra-Ethyl-Ortho-Silicate) film, or a chemical gas is used. It is covered with a silicon oxide film formed by a phase growth method or a sputtering method, or an interlayer insulating film 3 having a laminated structure of a silicon oxide film and a silicon nitride film. The planar transistor 10 covered with the interlayer insulating film 3 is electrically connected to the upper vertical field effect transistor 100, the contact plug 118, and the like through the contact plug 4 and the wiring 6. The contact plug 4 and the wiring 6 are made of, for example, tungsten (W). As the barrier metal, tungsten nitride (WN), titanium nitride (TiN), titanium (Ti), or a laminated structure thereof may be used. .
[0025]
The vertical field effect transistor 100 is a columnar field effect transistor formed perpendicular to the main surface of the Si substrate, and is formed so as to cover the source 108, the channel 107, the drain 106, and the channel 108 processed into a columnar shape. And the gate electrodes 110 and 111 adjacent to the gate insulating film 109.
[0026]
The source 108, the channel 107, and the drain 106 are made of, for example, polycrystalline silicon. The gate insulating film 109 is formed of, for example, a silicon oxide film (SiO ₂ ), A silicon nitride film (SiN), an oxynitride film (SiON), or a stacked structure thereof, or a gate insulating film material used in the planar field effect transistor 10. The gate electrodes 110 and 111 are made of, for example, polycrystalline silicon, a metal film such as tungsten (W), or a laminated structure thereof.
[0027]
A contact plug 105 made of, for example, polycrystalline silicon is connected to the drain 106 side of the vertical field effect transistor 100, and is connected to the lower wiring 6 through the barrier metal 101. The barrier metal 101 is, for example, tungsten silicide (WSi). ₂ ), Tungsten nitride (WN), titanium nitride (TiN), titanium (Ti), or a laminated structure thereof.
[0028]
A wiring 103 and a contact plug 115 are connected to the gate electrode 111. The wiring 103 is made of, for example, polycrystalline silicon. The contact plug 115 is formed of, for example, tungsten silicide (WSi) on a barrier metal. ₂ ), Tungsten nitride (WN), titanium nitride (TiN), titanium (Ti), or tungsten (W) using a laminated structure thereof.
[0029]
A contact plug 117 is formed on the source 108 side of the vertical field effect transistor 100, and further connected to an upper layer wiring and element. The contact plug 117 is made of, for example, tungsten silicide (WSi), tungsten nitride (WN), titanium nitride (TiN), titanium (Ti), or tungsten (W) using a stacked structure thereof as a barrier metal.
[0030]
The semiconductor device of this embodiment is characterized in that a dummy vertical field effect transistor d100 that is not used as an SRAM memory cell is formed adjacent to the vertical field effect transistor 100a located at the end of the SRAM memory mat. To do.
[0031]
The dummy vertical field effect transistor d100 of this embodiment includes a dummy source d108, a channel d107, a drain d106, a gate insulating film d109, gate electrodes d110 and d111, an interlayer insulating film d104, and a barrier metal d101. This is different from the vertical field effect transistor 100 in that the contact plug 117 is not formed.
[0032]
In the semiconductor device of this embodiment, the lower layer of the dummy vertical field effect transistor d100 has a dummy wiring d6, a dummy contact plug d4, a dummy gate electrode d15, a sidewall d16, and a silicide d17. A dummy planar field effect transistor is also formed. The material and the manufacturing method may be the same as those of the planar transistor 10 of the SRAM cell.
[0033]
Similar to the interlayer insulating film 3, interlayer insulating films 112, 114, and 116 are formed around the vertical transistor 100 and the dummy vertical transistor d100 and on the entire upper surface, and the contact plug 117 is formed at a desired position. 118, 119, and wirings are formed.
[0034]
FIG. 4 is a plan layout diagram showing the arrangement of dummy vertical transistors dSV (d100). In this embodiment, three dummy vertical transistors dSV (d100) are formed at the end of the vertical transistor SV (100) column formed in the memory mat with the same repetition period as the vertical transistor column. In FIG. 4, in order to simplify the drawing, the vertical field effect transistor SV (100), the dummy vertical field effect transistor dSV (d100), the contact plug MSCT (117), MLCT (118), and SVGC (115). Only the active ACT and the gate electrode FG of the peripheral circuit are shown.
[0035]
Here, it is desirable that at least one dummy vertical transistor dSV (d100) is formed at the end of one column of the vertical transistor SV (100), more preferably three or more.
[0036]
A part of the manufacturing process of the semiconductor device of the present embodiment is as follows, for example. Note that the method of manufacturing the semiconductor device of this embodiment is not necessarily limited to the following.
(1) A shallow planar element isolation 2 is formed on the main plane of the silicon substrate 1 and is a dummy planar type comprising an SRAM cell planar transistor 10 and dummy gate electrodes d15, sidewalls d16, silicides d17, and the like. A peripheral circuit around the transistor and the memory mat is formed. Thereafter, an interlayer insulating film 3 made of, for example, a silicon oxide film is formed on the entire upper surface of the memory mat portion and the peripheral circuit portion, and after removing the interlayer insulating film 4 where the contact plug 4 is disposed by etching, the contact For example, tungsten (W) using titanium (Ti) or titanium nitride (TiN) as a barrier metal is formed on the entire upper surface by CVD, sputtering, or the like, and then CMP (chemical The contact plug 4 is formed by planarizing the upper surface by a mechanical polishing method (FIGS. 7, 8, and 9).
(2) Further, the interlayer insulating film 5 is formed on the entire upper surface, and the portion where the wiring 6 is disposed is removed by etching, and then the wiring 6 is formed. For example, titanium (Ti) or titanium nitride (TiN) is used as a barrier metal. The tungsten (W) used is formed on the entire upper surface by CVD or sputtering, and then the upper surface is flattened by CMP to form wiring 6 (FIGS. 10, 11, and 12).
(3) For example, titanium (Ti), titanium nitride (TiN), tungsten nitride (WN), tungsten silicide, or a laminated film thereof, which becomes the barrier metal 101, d101, is formed by CVD or sputtering. After formation on the entire upper surface, unnecessary portions are removed by etching to form barrier metals 101 and d101. Thereafter, an etch stopper 102 made of, for example, silicon nitride is formed on the entire upper surface by CVD or sputtering, and an interlayer insulating film 121 made of, for example, silicon oxide is further formed on the upper surface. (Fig. 13, 14, 15)
(4) The gate electrode lead-out wiring 103 of the vertical transistor is formed, for example, by forming a polycrystalline or amorphous silicon film doped with boron (B) over the entire upper surface, and then etching unnecessary portions by etching. The wiring 103 is formed by removing. (Fig. 16, 17, 18)
(5) After the interlayer insulating film 104 made of a silicon oxide film is formed on the entire upper surface, the portions of the interlayer insulating films 104 and 121 and the etch stopper 102 where the contact plugs 105 and d105 are to be formed are removed by etching. (Fig. 19, 20, 21)
(6) A silicon oxide film to be the interlayer insulating films 120 and d120 is formed on the entire upper surface and then etched to form the interlayer insulating films 120 and d120. (Figs. 22, 23 and 24)
(7) For example, a polycrystalline or amorphous silicon film to which boron (B) is added is formed on the entire upper surface, and then planarized by CMP to form contact plugs 105 and d105. (Fig. 25, 26, 27)
(8) A polycrystalline silicon layer to which, for example, boron (B) or the like, which becomes the drains 106 and d106 of the vertical transistors 100 and d100, the channels 107 and d107, and the sources 108 and d108, for example, boron (B) or the like is added in a desired concentration is formed on the entire surface To do. Each layer may be formed by forming amorphous silicon over the entire surface, implanting impurities such as boron (B) at a desired concentration over the entire upper surface, and then crystallizing by heat treatment. Alternatively, polycrystalline silicon to which impurities are added in advance or amorphous silicon to which impurities are added in advance may be crystallized later. After these are formed, a silicon oxide film 109 is formed on the entire upper surface, and an etch stopper 113 made of, for example, silicon nitride is further formed on the upper surface. (Fig. 28, 29, 30)
(9) The etch stopper 113 is processed into a vertical transistor shape, and the underlying silicon oxide film 109, source 108, channel 107, and drain 106 are processed by etching to form the source 108 of the vertical transistor 100, The channel 107 and the drain 106 are formed, and the source d108, the channel d107, and the drain d106 of the dummy vertical transistor d100 are formed. (Fig. 31, 32, 33)
(10) Gate insulating films 109 and d109 are formed on the source 108, channel 107, and drain 106 of the vertical transistor 100, and on the source d108, channel d107, and drain d106 of the dummy vertical transistor d100. The gate insulating film is, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a stacked structure thereof, and is formed by thermal oxidation, a CVD method, a sputtering method, or the like. Note that the cross-sectional schematic diagram in the present invention includes a silicon oxide film on the upper surface of the source 108 and d108 formed in step (8), an oxide film or a nitride film on the side walls of the source, channel, and drain formed in this step. Alternatively, the gate insulating films such as a stacked structure of an oxide film and a nitride film are collectively referred to as gate insulating films 109 and d109. (Fig. 34, 35, 36)
(11) For example, an amorphous or polycrystalline silicon film to which boron (B) is added is formed on the entire upper surface, which is to be the gate electrodes 110 and d110, and then etching is performed, so that the source 108, d108, channel 107, The gate electrodes 110 and d110 are formed on the side walls of the d107 drain 106 and d106 columnar structures. (Fig. 37, 38, 39)
(12) The interlayer insulating film 104 is etched to expose the wiring 103. (Fig. 40, 41, 42)
(13) Amorphous or polycrystalline silicon to which the gate electrodes 111 and d111 are added, for example, boron (B) added, is formed on the entire upper surface, and then etched to form the gate electrodes 111 and d111. . (Fig. 43, 44, 45)
(14) For example, after the interlayer insulating film 112 made of a silicon oxide film is formed on the entire upper surface, the upper surface is planarized by CMP. (Fig. 46, 47, 48)
(15) The interlayer insulating film 112 is etched to expose the upper surfaces of the vertical transistors 100 and d100 and the upper ends of the gate electrodes 110, 111, d110, and d111. (Fig. 49, 50, 51)
(16) The upper ends of the gate electrodes 110, 111, d110, d111 are retracted by etching. (Fig. 52, 53, 54)
(17) For example, a silicon nitride film serving as an etch stopper is formed on the entire upper surface, and etch stoppers 113 and d113 at the upper end of the vertical transistor are formed by etching. The etch stopper film formed in this step and the etch stopper formed in step (8) are combined to be etch stoppers 113 and d113. (Fig. 55, 56, 57)
(18) An interlayer insulating film 114 made of, for example, a silicon oxide film is formed on the entire upper surface, and a portion of the interlayer insulating film 114 in which the contact plugs 115 and 118 are disposed is removed by etching, for example, tungsten (W) is replaced with titanium. Then, titanium nitride is formed as a barrier metal over the entire upper surface, and the upper surface is planarized by CMP to form contact plugs 115 and 118. (Fig. 58, 59, 60)
(19) Similarly to the step (18), the interlayer insulating film 116 is formed on the entire upper surface, and the portion of the interlayer insulating film 116 where the contact plugs 117 and 119 are disposed is removed by etching, and tungsten, for example, titanium, for example, is removed. Then, titanium nitride is formed as a barrier metal over the entire upper surface, and planarized by CMP to form contact plugs 117 and 119. (Figure 1)
Hereinafter, the function and effect of the semiconductor device of this embodiment will be described. In recent years, with the development of information communication equipment, higher integration and larger capacity of semiconductor devices such as SRAM have been promoted. For this reason, miniaturization of transistors is being promoted. Conventionally, a planar type field effect transistor has been generally used as a transistor. However, use of a vertical type field effect transistor has been studied for high integration. The vertical field effect transistor is a columnar transistor in which a source, a channel, and a drain are formed in a direction perpendicular to the Si substrate surface.
[0037]
A vertical field effect transistor is a transistor having a larger aspect ratio in the height direction than a conventional planar field effect transistor. The inventors of the present application have clarified that in a portion where a plurality of vertical field effect transistors are periodically formed, the vertical field effect transistor located at the end of the transistor has different electrical characteristics from those of other transistors. We found a way to stabilize the characteristics.
[0038]
In general, in a semiconductor device manufacturing process, thermal stress due to a difference in linear expansion coefficient of a material constituting an element, intrinsic stress due to shrinkage of a film unique to the material, stress due to the structure of the element, etc. Occurs inside the device.
[0039]
The inventors of the present application analyzed the stress generated in the transistor in the manufacturing process of the vertical field effect transistor array by the finite element method. FIG. 6 shows a stress analysis result in which stress generated in the channel portion of the vertical field effect transistor in the process of forming the vertical field effect transistor column is evaluated in order from the end of the column. The horizontal axis in the figure is the position of the vertical field effect transistor from the end of the column, and the vertical axis is the stress in the normal direction of the channel surface. From the figure, it is clear that the stress is relaxed at the edge, and the influence of this edge reaches about the third.
[0040]
It has been known that the mobility of electrons and holes in Si has stress (strain) dependence, and it is known that the stress (strain) affects the electrical characteristics of conventional planar transistors. (For example, Akemi Hamada, et al., IEEE Trans. Electron Devices, vol. 38, No. 4, pp. 895-900, 1991). Even in the vertical field effect transistor, since Si is used for the channel portion, it is clear that the electrical characteristics fluctuate due to the stress (strain) generated in the channel. According to the analysis by the inventors of the present invention shown in FIG. 6, the channel stress of the vertical field effect transistor from the third end to the third is different from that near the center. It has been clarified that the electrical characteristics of the vertical field effect transistors are different from those in the vicinity of the center.
[0041]
As shown in FIGS. 1 to 4, in the semiconductor device of this embodiment, at least one dummy vertical field effect transistor not used as an electric circuit is provided at the end of the vertical field effect transistor row of the memory mat. One or more, more preferably three or more are formed. As a result, the vertical field effect transistor used as the electric circuit of the memory mat has an effect that a stable characteristic without variation in electric characteristics due to stress can be obtained.
[0042]
Further, by forming a dummy vertical field effect transistor in the vertical field effect transistor array, it is possible to obtain an effect that density correction can be performed in the photo process and the etching process.
Further, the method for stabilizing the vertical field effect transistor characteristics in the present embodiment utilizes the vertical transistor process of SRAM cell formation. Therefore, there is no need for an additional manufacturing process, and an effect that a highly reliable semiconductor device with excellent manufacturing cost can be manufactured.
[0043]
In this embodiment, in addition to the vertical transistor, a dummy is also formed for the lower planar transistor. As a result, the continuity from the center of the memory mat can be maintained for the planar transistor and the wiring structure below the vertical transistor, so that the stress can be stabilized. With respect to the wiring structure, the effect that the mechanical reliability can be improved is obtained.
[0044]
Note that the structure of the dummy vertical transistor in this embodiment is not necessarily the same as the vertical transistor of the memory cell. It is only necessary that the source d108, the channel d107, and the drain d106, which are the main structural factors of the vertical transistor, be formed, and a dummy planar transistor including the barrier metal d101, the wiring d6, or the dummy gate electrode d15 in the lower layer. Etc. are not necessarily formed.
[0045]
This embodiment describes a circuit in which vertical transistors are formed periodically. Therefore, the application of the present embodiment is not limited to the SRAM memory mat, and may be another circuit in which vertical transistors are periodically formed.
[0046]
<Example 2>
Next, a second embodiment of the present invention will be described with reference to FIGS. 61 is a schematic cross-sectional view of the semiconductor device of the present invention (A-B-G-H cross-section of FIG. 62), FIG. 62 is a schematic plan view of the semiconductor device of the present invention, and FIGS. 63 to 65 are semiconductor devices of the present invention. FIG. 66 to FIG. 69 are plan layout views showing a method for arranging dummy on the peripheral circuit in the present invention, and FIG. 70 to FIG. 73 are diagrams showing one of the conventional semiconductor device manufacturing steps. It is a cross-sectional schematic diagram showing a part.
[0047]
The difference from the first embodiment is that, as shown in FIGS. 61 and 62, shallow groove element isolation structures 2b and 2c in the peripheral portion of the SRAM memory mat made of the vertical transistor 100 (SV), and the planar of the peripheral circuit. A dummy vertical transistor d500 (d5SV) is also formed in the upper layer of the type transistor 50. The dummy vertical transistor d500 includes an interlayer insulating film d504, a source d508, a channel d507, a drain d506, a gate insulating film d509, and gate electrodes d510 and d511, and the dummy vertical transistor d500 is not used as an electric circuit. It is a dummy transistor. These are formed by the same material and manufacturing method as the vertical transistor 100 described in the first embodiment. A part of the manufacturing process of the semiconductor device of this embodiment is shown below.
(1) The steps up to the step of forming the contact plugs 105 and d105 are performed in the same steps as in the first embodiment. In this embodiment, the portion corresponding to the contact plug 105 connected to the vertical transistor 100, the barrier metal 101, and the interlayer insulating film 120 is not formed in the dummy vertical transistor d500. (Fig. 63)
(2) A portion that becomes the drain, channel, and source of the vertical transistors 100, d100, and d500, for example, a polycrystalline silicon film to which boron (B) is added is sequentially formed on the entire upper surface, and then the silicon oxide film 109 and Further, an etch stopper 113 made of, for example, silicon nitride is formed on the upper surface. (Fig. 64)
(3) The etch stopper 113 is processed into a vertical transistor shape, and the underlying silicon oxide film 109, source 108, channel 107, and drain 106 are processed by etching to form the source 108 of the vertical transistor 100, The channels 107 and the drains 106, the sources d108 and d508 of the dummy vertical transistors d100 and d500, the channels d107 and d507, the drains d106 and d506 are formed. (Fig. 65)
(4) The vertical transistor 100, the dummy vertical transistors d100 and d500, the interlayer insulating films 112, 114 and 116, and the contact plugs 115 and 119 are formed by the same process as in the first embodiment. (Fig. 61)
The dummy circuit layout method in the present embodiment is performed as follows, for example.
(1) A planar layout (FIG. 66) of a circuit including peripheral circuits and a planar layout in which dummy vertical transistors d5SV are arranged at equal intervals are produced (FIG. 67). Here, in the planar layout of the peripheral circuit, a layout of wiring and elements such as the contact plug MLCT (118) formed in the same layer as the vertical transistor SV (100) is described.
(2) The planar layout (FIG. 66) of the circuit including the peripheral circuit and the planar layout (FIG. 67) in which the dummy vertical transistors d5SV are arranged at equal intervals are overlapped (FIG. 68).
(3) Contact plug MLCT (118) and wiring formed in the same layer as vertical transistor SV (100), vertical transistor SV (100), dummy vertical transistor dSV (d100) around the memory mat, The overlapping dummy vertical transistor d5SV is removed (FIG. 69).
(4) Further, contact plug MLCT (118) and wiring formed in the same layer as the vertical transistors 100 and SV, the vertical transistor SV (100), and the dummy vertical transistor dSV (d100) around the memory mat. On the other hand, the dummy vertical transistor d5SV adjacent to the layout rule or less is removed. The layout rule is determined by the minimum interval between two vertical transistors used as an electric circuit in the semiconductor device, for example, the minimum interval between two adjacent vertical transistors in the SRAM memory mat. (Fig. 62)
The above is an example of the arrangement method of the dummy vertical transistors d5SV (d500) in the peripheral circuit portion. Examples of other arrangement methods include contact plug MLCT (118) and wiring formed in the same layer as the vertical transistor SV (100), the vertical transistor SV (100), and a dummy vertical transistor around the memory mat. In the layer where dSV (d100) is formed, when the contact plugs and the like are located with a space larger than the layout rule, a dummy vertical transistor d5SV (d500) is arranged between them. There may be.
[0048]
Hereinafter, the function and effect of the semiconductor device of this embodiment will be described. In a conventional semiconductor device using a vertical transistor, the density of the vertical transistor is coarse. In the case of such a conventional semiconductor device, when the vertical transistor layer is embedded with an interlayer insulating film and chemical mechanical polishing (CMP) is performed, dishing in which a portion where the vertical transistor is not formed is more deeply polished. The problem arises. 70 to 73 show a part of the manufacturing process of the conventional semiconductor device.
(1) A planar field effect transistor 10 and a structure below the vertical transistor SV such as the wiring ML and the vertical transistor SV are formed on the main surface of the silicon substrate 1, and an interlayer insulating film 112 is formed. An etch stopper 113 is formed (FIG. 70).
(2) An interlayer insulating film 114 made of, for example, a silicon oxide film is formed on the entire upper surface of the vertical transistor SV and its peripheral circuit, and a portion where the contact plug 118 is formed is removed by etching (FIG. 71).
(3) A contact plug 118 made of, for example, tungsten is formed on the entire upper surface, and the surface is planarized by chemical mechanical polishing (CMP) (FIG. 72).
(4) Thereafter, as in the step (3), an interlayer insulating film 116 and a contact plug 119 are formed (FIG. 73).
[0049]
As described above, in the conventional semiconductor device, in the CMP process shown in the above step (3), the portion where the vertical transistor is not formed is polished deeper and a step is generated, which affects the subsequent steps. was there.
[0050]
In contrast, the semiconductor device of this embodiment can secure the same height as the portion where the vertical transistor 100 is formed by forming the dummy vertical transistor d500 on the peripheral circuit. The effect that dishing in the CMP process can be prevented is obtained.
[0051]
Further, since the dishing prevention method shown in this embodiment is a part of the manufacturing process of the vertical transistor, there is no need to add a new manufacturing process, and the effect of excellent manufacturing cost can be obtained.
[0052]
In this embodiment, the dummy vertical transistor d500 is for preventing dishing of peripheral circuits in the CMP process. Therefore, it is sufficient that the vertical transistor 100 is formed to have the same height, and preferably, the source d508, the channel d507, the drain d506 portion, and more preferably, the interlayer insulating film d504 is formed. The gate insulating film d509 and the gate electrodes d510 and d511 are not necessarily formed.
[0053]
<Example 3>
Next, a third embodiment of the present invention will be described with reference to FIGS. 74 is a schematic cross-sectional view of a semiconductor device of the present invention, FIG. 75 is a schematic cross-sectional view of a conventional MOS capacitor, and FIG. 76 is a schematic cross-sectional view showing another embodiment of the semiconductor device of the present invention.
The difference between this embodiment and other embodiments is that the dummy vertical transistor d500 formed in the peripheral circuit shown in the second embodiment is used as a capacitor. As shown in FIG. 74, the dummy vertical transistor d500 of this embodiment includes interlayer insulating films d504 and d520, contact plugs d505, barrier metal d501, source d508, channel d507, drain d506, gate insulating film d509, and gate electrode. d510 and d511. The dummy vertical transistor d500 of this embodiment is formed in the same process as the vertical transistor 100.
Hereinafter, the effect of the present embodiment will be described. According to the semiconductor device of this embodiment, electrical connection can be established from the lower end of the drain to the lower layer wiring 6, for example, an element such as the transistor 50, and the wiring 103 is formed in the gate electrode d511. Since the contact plug 118 is electrically connected to another wiring, a MOS capacitor can be formed through the gate insulating film d509. Therefore, according to this embodiment, it is possible to effectively use the dummy vertical transistor not only for preventing dishing but also as a MOS capacitor. The MOS capacitor according to the present embodiment can be used as, for example, a capacity between power supplies or an analog capacity.
Further, since the MOS capacitor of this embodiment uses the side wall portion of the columnar structure, it has a three-dimensional structure, and an effect that the area can be increased as compared with a normal flat plate type MOS capacitor is obtained. FIG. 75 is a schematic sectional view of a conventional MOS capacitor. The conventional MOS capacitor is constituted by a gate insulating film 54 formed on the silicon substrate 1 and a gate electrode 55, and is insulated from other elements by the shallow groove element isolation 2. As shown in the figure, since the conventional MOS capacitor is formed in a two-dimensional parallel plate type, the area occupancy inside the semiconductor device is considerably larger than other circuits when the shallow trench isolation 2 is included. End up.
For example, the dummy vertical transistor d500 is a cylinder having a channel portion diameter of 0.2 μm and a channel length of 0.4 μm, and the distance between the centers of adjacent vertical transistors of the dummy vertical transistor d500 is 0.4 μm. Suppose that In this case, the area that can be used as a MOS capacitor of one vertical transistor is π × 0.2 μm × 0.4 μm = 0.25 (μm). ² It is. The area occupied by the vertical transistor with respect to the main surface of the silicon substrate is 0.4 μm × 0.4 μm = 0.16 (μm) even if the repetition period is taken into consideration. ² Therefore, the area can be enlarged about 1.6 times by using the vertical transistor. The normal MOS capacitor shown in FIG. ** is, for example, 30 μm × 4 μm = 120 (μm) ² It is formed with the size at. By applying this embodiment, the same capacitor can be formed with a size of, for example, about 19 μm × 4 μm with respect to the main surface of the silicon substrate, and the area can be reduced.
FIG. 76 shows another form of the present embodiment. The present embodiment is characterized in that electrical connection is made from the source d508 side to other wirings and elements via the contact plug 117.
In the present embodiment, since the wiring for electrically connecting the dummy vertical transistors is not formed in the lower wiring 6 layer, the wiring 6 layer and the peripheral circuit such as the lower transistor 50 are in electrical contact. Therefore, an effect that a peripheral circuit can be freely formed is obtained.
[0054]
<Example 4>
Next, a fourth embodiment of the present invention will be described with reference to FIGS. 77 is a schematic cross-sectional view of the semiconductor device of the present invention, and FIGS. 78 to 80 are schematic cross-sectional views showing a part of the manufacturing process of the semiconductor device of the present invention.
The difference between this embodiment and other embodiments is that a dummy vertical transistor d500 formed in the peripheral circuit shown in the second embodiment is used as a resistor.
The dummy vertical transistor d500 of this embodiment includes interlayer insulating films d504 and d520, a contact plug d505, a barrier metal d501, a source d508, a channel d507, a drain d506, a gate insulating film d509, and gate electrodes d510 and d511.
A part of the manufacturing process of this example is shown below.
(1) By the same method as in the second embodiment, the drain layers of the vertical transistors 100 and d500 are formed, and thereafter, amorphous silicon that will be the channel layers of the vertical transistors 100 and d100 is formed on the entire surface. Thereafter, an impurity such as boron (B) is ion-implanted at a desired concentration over the entire surface, so that a portion to be a channel layer of the vertical transistor 100 is formed. (Fig. 78)
(2) A mask 900 made of, for example, a silicon oxide film is formed on the upper surface of the vertical transistor 100, and impurities such as boron (B) are ion-implanted at a desired concentration to form a channel layer of the dummy vertical transistor d500. The part which becomes becomes. (Fig. 79)
(3) The mask 900 is removed. (Fig. 80)
Step (1) may be the reverse of step (2). In the following processes, the vertical transistor 100, the dummy vertical transistor d500, and the like are formed in the same process as in the second embodiment.
[0055]
Hereinafter, the effect of the present embodiment will be described. According to the semiconductor device of the present embodiment, electrical connection can be established from the lower end of the drain d506 of the dummy vertical transistor d500 to the lower layer wiring 6, for example, an element such as the transistor 50, and the upper end of the source d508. Is electrically connected to other wiring via the contact plug 117, so that the effect that the source, the channel, and the drain can be used as a resistance element is obtained.
[0056]
Further, according to this embodiment, the impurity addition to the channel d507 of the dummy vertical transistor d500 is performed in a separate process from the vertical transistor 100. Therefore, it is possible to obtain an effect that a desired resistance value can be obtained by adjusting the impurity addition amount.
[0057]
In this embodiment, the resistance value is controlled by changing the impurity addition to the channel layer. However, ion implantation may be performed for the source and drain layers.
[0058]
<Example 5>
Next, a fifth embodiment of the present invention will be described with reference to FIGS. 81 is a schematic cross-sectional view of the semiconductor device of the present invention, and FIG. 82 is a result of analyzing the stress generated at the lower end of the columnar structure when an external force is applied to the columnar structure including the source, channel, and drain.
The difference between this embodiment and the other embodiments is that a contact plug d505 is formed in a dummy vertical transistor d500 formed on the peripheral circuit shown in the second embodiment. The dummy vertical transistor d500 of this embodiment includes interlayer insulating films d504 and d520, a contact plug d505, a barrier metal d501, a source d508, a channel d507, a drain d506, a gate insulating film d509, and gate electrodes d510 and d511. The dummy vertical transistor d500 is formed in the same process as the vertical transistor 100.
[0059]
Hereinafter, the function and effect of the semiconductor device of this embodiment will be described. In the manufacturing process of the vertical transistor, as shown in FIG. 65 of the second embodiment, after the source, channel, and drain are processed into a columnar structure by etching, etching residues are removed and the gate insulating film 109 is formed. Cleaning is performed for the purpose of surface treatment.
[0060]
The columnar sources 108 and d508, the channels 107 and d507, the drains 106 and d506 have a high aspect ratio structure in which the dimension in the height direction is larger than the dimension in the width direction. Therefore, there is a possibility of collapse due to the flow of the cleaning liquid in the cleaning process. The inventors of the present application conducted stress analysis on the strength of the columnar structure of the source, channel, and drain portions, and revealed that the strength changes depending on the presence or absence of the contact plug. FIG. 82 shows a result of comparing the stress generated at the lower end of the drain when an external force is applied in the lateral direction with respect to the columnar structure in the step of FIG. From this analysis result, it became clear that the stress generated can be reduced by about 10% by forming the contact plug.
[0061]
According to the present embodiment, since the contact plug is formed also in the dummy vertical transistor d500 portion, the effect of ensuring the strength of the columnar structure of the source d508, the channel d507, and the drain d506 in the dummy portion is obtained.
[0062]
In this embodiment, it is important that a contact plug is formed, and the barrier metal d501 is not necessarily formed. However, by forming the barrier metal d501, the interlayer insulating films d504 and d520 are formed. Can be used as an etch stopper when processing is performed by etching.
[0063]
<Example 6>
Next, a sixth embodiment of the present invention will be described with reference to FIG. FIG. 83 is a schematic cross-sectional view of the semiconductor device of the present invention.
The difference between this embodiment and the other embodiments is that the diameter of the dummy vertical transistor d500 formed on the peripheral circuit shown in the second embodiment is larger than that of the vertical transistor 100. . Similar to the second embodiment, the dummy vertical transistor d500 of this embodiment includes interlayer insulating films d504 and d520, a source d508, a channel d507, a drain d506, a gate insulating film d509, and gate electrodes d510 and d511. The dummy vertical transistor d500 is formed in the same process as the vertical transistor 100.
[0064]
Hereinafter, the function and effect of the semiconductor device of this embodiment will be described. The formation of dummy vertical transistors in the peripheral circuit described in the second embodiment may increase the number of dummy vertical transistors if the area of the peripheral circuit portion is large. According to this embodiment, the diameter of one dummy vertical transistor can be increased, and the number of dummy vertical transistors formed per unit area can be reduced. As a result, it is possible to reduce the mask data.
[0065]
Further, as described in the fifth embodiment, the diameter can be increased and the height aspect ratio can be decreased. For this reason, since the intensity | strength with respect to an external force can be improved, the effect that collapse of the columnar structure under washing | cleaning can be acquired is acquired.
[0066]
【The invention's effect】
In a semiconductor device having a vertical field effect transistor formed in a semiconductor main plane, and a plurality of the vertical field effect transistors are periodically arranged, a dummy field is formed at an end of the vertical field effect transistor array. By forming at least one vertical field effect transistor, there is an effect that the characteristic variation due to stress of the plurality of vertical field effect transistors can be reduced.
[Brief description of the drawings]
FIG. 1 is a schematic view showing a cross section of a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a schematic view showing a cross section of the semiconductor device according to the first embodiment of the present invention;
FIG. 3 is a schematic view showing a cross section of the semiconductor device according to the first embodiment of the present invention;
FIG. 4 is a schematic diagram showing a planar layout of the semiconductor device according to the first embodiment of the present invention;
FIG. 5 is an electric circuit diagram showing a part of an SRAM memory cell to which the present invention is applied;
FIG. 6 is a result of analyzing a stress generated in a vertical field effect transistor array.
FIG. 7 is a schematic cross-sectional view showing a part of the manufacturing process of the semiconductor device according to the first example of the present invention.
FIG. 8 is a schematic cross-sectional view showing a part of the manufacturing process of the semiconductor device according to the first example of the present invention.
FIG. 9 is a schematic cross-sectional view showing a part of the manufacturing process of the semiconductor device according to the first example of the present invention.
FIG. 10 is a schematic cross-sectional view showing a part of the manufacturing process of the semiconductor device according to the first example of the present invention.
FIG. 11 is a schematic cross-sectional view showing a part of the manufacturing process of the semiconductor device according to the first example of the present invention.
FIG. 12 is a schematic cross-sectional view showing a part of the manufacturing process of the semiconductor device according to the first example of the present invention.
FIG. 13 is a schematic cross-sectional view showing a part of the manufacturing process of the semiconductor device according to the first example of the present invention.
FIG. 14 is a schematic cross-sectional view showing a part of the manufacturing process of the semiconductor device according to the first example of the present invention.
FIG. 15 is a schematic cross sectional view showing a part of the manufacturing process for the semiconductor device according to the first example of the present invention;
FIG. 16 is a schematic cross-sectional view showing a part of the manufacturing process of the semiconductor device according to the first example of the present invention.
FIG. 17 is a schematic cross sectional view showing a part of the manufacturing process for the semiconductor device according to the first example of the present invention;
FIG. 18 is a schematic cross sectional view showing a part of the manufacturing process for the semiconductor device according to the first example of the present invention;
FIG. 19 is a schematic cross-sectional view showing a part of the manufacturing process of the semiconductor device according to the first example of the present invention.
FIG. 20 is a schematic cross-sectional view showing a part of the manufacturing process of the semiconductor device according to the first example of the present invention.
FIG. 21 is a schematic cross sectional view showing a part of the manufacturing process for the semiconductor device according to the first example of the present invention;
FIG. 22 is a schematic cross sectional view showing a part of the manufacturing process for the semiconductor device according to the first example of the present invention;
FIG. 23 is a schematic cross-sectional view showing a part of the manufacturing process of the semiconductor device according to the first example of the present invention.
FIG. 24 is a schematic cross-sectional view showing a part of the manufacturing process of the semiconductor device according to the first example of the present invention.
FIG. 25 is a schematic cross sectional view showing a part of the manufacturing process for the semiconductor device according to the first example of the present invention;
FIG. 26 is a schematic cross sectional view showing a part of the manufacturing process for the semiconductor device according to the first example of the present invention;
FIG. 27 is a schematic cross sectional view showing a part of the manufacturing process for the semiconductor device according to the first example of the present invention;
FIG. 28 is a schematic cross sectional view showing a part of the manufacturing process for the semiconductor device according to the first example of the present invention;
FIG. 29 is a schematic cross sectional view showing a part of the manufacturing process for the semiconductor device according to the first example of the present invention;
30 is a schematic cross-sectional view showing a part of the manufacturing process of the semiconductor device according to the first example of the present invention. FIG.
FIG. 31 is a schematic cross-sectional view showing a part of the manufacturing process of the semiconductor device according to the first example of the present invention;
FIG. 32 is a schematic cross sectional view showing a part of the manufacturing process for the semiconductor device according to the first example of the present invention;
FIG. 33 is a schematic cross sectional view showing a part of the manufacturing process for the semiconductor device according to the first example of the present invention;
FIG. 34 is a schematic cross-sectional view showing a part of the manufacturing process of the semiconductor device according to the first example of the present invention.
FIG. 35 is a schematic cross sectional view showing a part of the manufacturing process for the semiconductor device according to the first example of the present invention;
FIG. 36 is a schematic cross sectional view showing a part of the manufacturing process for the semiconductor device according to the first example of the present invention;
FIG. 37 is a schematic cross sectional view showing a part of the manufacturing process for the semiconductor device according to the first example of the present invention;
FIG. 38 is a schematic cross sectional view showing a part of the manufacturing process for the semiconductor device according to the first example of the present invention;
FIG. 39 is a schematic cross sectional view showing a part of the manufacturing process for the semiconductor device according to the first example of the present invention;
FIG. 40 is a schematic cross sectional view showing a part of the manufacturing process for the semiconductor device according to the first example of the present invention;
FIG. 41 is a schematic cross sectional view showing a part of the manufacturing process for the semiconductor device according to the first example of the present invention;
FIG. 42 is a schematic cross sectional view showing a part of the manufacturing process for the semiconductor device according to the first example of the present invention;
FIG. 43 is a schematic cross sectional view showing a part of the manufacturing process for the semiconductor device according to the first example of the present invention;
44 is a schematic cross-sectional view showing a part of the manufacturing process of the semiconductor device according to the first example of the present invention. FIG.
FIG. 45 is a schematic cross sectional view showing a part of the manufacturing process for the semiconductor device according to the first example of the present invention;
FIG. 46 is a schematic cross sectional view showing a part of the manufacturing process for the semiconductor device according to the first example of the present invention;
FIG. 47 is a schematic cross sectional view showing a part of the manufacturing process for the semiconductor device according to the first example of the present invention;
FIG. 48 is a schematic cross sectional view showing a part of the manufacturing process for the semiconductor device according to the first example of the present invention;
FIG. 49 is a schematic cross-sectional view showing a part of the manufacturing process of the semiconductor device according to the first example of the present invention.
FIG. 50 is a schematic cross sectional view showing a part of the manufacturing process for the semiconductor device according to the first example of the present invention;
FIG. 51 is a schematic cross sectional view showing a part of the manufacturing process for the semiconductor device according to the first example of the present invention;
FIG. 52 is a schematic cross sectional view showing a part of the manufacturing process for the semiconductor device according to the first example of the present invention;
FIG. 53 is a schematic cross sectional view showing a part of the manufacturing process for the semiconductor device according to the first example of the present invention;
FIG. 54 is a schematic cross sectional view showing a part of the manufacturing process for the semiconductor device according to the first example of the present invention;
FIG. 55 is a schematic cross sectional view showing a part of the manufacturing process for the semiconductor device according to the first example of the present invention;
FIG. 56 is a schematic cross sectional view showing a part of the manufacturing process for the semiconductor device according to the first example of the present invention;
FIG. 57 is a schematic cross sectional view showing a part of the manufacturing process for the semiconductor device according to the first example of the present invention;
FIG. 58 is a schematic cross sectional view showing a part of the manufacturing process for the semiconductor device according to the first example of the present invention;
FIG. 59 is a schematic cross-sectional view showing a part of the manufacturing process of the semiconductor device according to the first example of the present invention.
FIG. 60 is a schematic cross sectional view showing a part of the manufacturing process for the semiconductor device according to the first example of the present invention;
FIG. 61 is a schematic view showing a cross section of a semiconductor device according to a second embodiment of the present invention;
FIG. 62 is a schematic view showing a planar layout of a semiconductor device according to a second embodiment of the present invention.
FIG. 63 is a schematic cross-sectional view showing a part of the manufacturing process of the semiconductor device according to the second example of the present invention.
FIG. 64 is a schematic cross-sectional view showing a part of the manufacturing process of the semiconductor device according to the second example of the present invention.
FIG. 65 is a schematic cross-sectional view showing a part of the manufacturing process of the semiconductor device according to the second example of the present invention.
FIG. 66 is a plan layout view showing a method for arranging dummy vertical field effect transistors in the semiconductor device according to the second embodiment of the present invention;
FIG. 67 is a plan layout view showing a method for arranging dummy vertical field effect transistors in the semiconductor device according to the second embodiment of the present invention;
FIG. 68 is a plan layout view showing a method for arranging dummy vertical field effect transistors in the semiconductor device according to the second embodiment of the present invention;
FIG. 69 is a plan layout view showing a method for arranging dummy vertical field effect transistors in the semiconductor device according to the second embodiment of the present invention;
FIG. 70 is a schematic cross-sectional view showing a part of the manufacturing process of the conventional semiconductor device of the second example of the present invention.
FIG. 71 is a schematic cross-sectional view showing a part of the manufacturing process of the conventional semiconductor device according to the second embodiment of the present invention.
FIG. 72 is a schematic cross-sectional view showing a part of the manufacturing process of the conventional semiconductor device of the second example of the present invention.
FIG. 73 is a schematic cross-sectional view showing a part of the manufacturing process of the conventional semiconductor device of the second example of the present invention.
74 is a schematic view showing a cross section of a semiconductor device according to a third embodiment of the present invention; FIG.
FIG. 75 is a schematic view showing a cross section of a conventional semiconductor device according to a third embodiment of the present invention.
FIG. 76 is a schematic view showing another mode of the semiconductor device according to the third embodiment of the present invention;
FIG. 77 is a schematic view showing a cross section of a semiconductor device according to a fourth embodiment of the present invention;
FIG. 78 is a schematic cross-sectional view showing a part of the manufacturing process of the semiconductor device according to the fourth example of the present invention.
FIG. 79 is a schematic cross-sectional view showing a part of the manufacturing process of the semiconductor device according to the fourth example of the present invention.
FIG. 80 is a schematic cross-sectional view showing a part of the manufacturing process of the semiconductor device according to the fourth example of the present invention.
FIG. 81 is a schematic view showing a cross section of a semiconductor device according to a fifth embodiment of the present invention;
FIG. 82 is a result of analyzing a stress generated in a columnar structure when an external force is applied to the columnar structure including a source, a channel, and a drain of a vertical field effect transistor.
FIG. 83 is a schematic view showing a cross section of a semiconductor device according to a sixth embodiment of the present invention;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Shallow groove element isolation | separation, 3, 5, 104, 112, 114, 116, 120, 121, d104, d120, d520, d504 ... Interlayer insulation film, 4,105, 115, 117, 118, 119, d105, d505, CONT, MLCT, SVGC ... contact plug,
6, 103 ... wiring, 7, 17, 18 ... silicide, 10 ... planar field effect transistor, 11 ... p-type well, 12, 13 ... n-type source / drain,
1, 109, d109, d509 ... gate insulating film, 15, 110, 111, d110, d111, d510, d511,
FG... Gate electrode, 16 .. sidewall, 101, d101, d501 .. barrier metal,
102: etch stopper, 106, d106, d506 ... drain, 107, d107, d507 ... channel, 108, d108, d508 ... source, 113 ... etch stopper, 900 ... mask, 100,
SV ... vertical field effect transistor, d100, d500, dSV ... dummy vertical field effect transistor, ACT ... active.

Claims (9)

A first semiconductor layer having a columnar shape is provided on a main surface side of the semiconductor substrate;
A gate electrode formed through a gate insulating film so as to surround a side surface of the first semiconductor layer, and a source and drain layer formed adjacent to one end and the other end of the first semiconductor layer, respectively A vertical field effect transistor comprising:
In the first region where the vertical field effect transistors are two-dimensionally arranged with a predetermined interval,
When the region having the predetermined interval where the periodicity is not maintained is an end portion, at least one row closest to the end portion among the vertical field effect transistors arranged around the first region. And a semiconductor device wherein the operation of the vertical field effect transistors arranged in a column is deactivated. The semiconductor device according to claim 1, wherein the first semiconductor layer has a high aspect ratio. In the first region in which the vertical field effect transistors provided in the first semiconductor layer having a columnar shape on the main surface side of the semiconductor substrate are arranged two-dimensionally and periodically,
When the region where the periodicity is not maintained is an end portion, one to three rows and columns closest to the end portion of the vertical field effect transistors arranged around the first region are arranged. A semiconductor device using the arranged vertical field effect transistor as a dummy element. A first semiconductor layer having a columnar shape is provided on a main surface side of the semiconductor substrate;
A gate electrode formed through a gate insulating film so as to surround a side surface of the first semiconductor layer, and a source and drain layer formed adjacent to the upper end portion and the lower end portion of the first semiconductor layer, respectively. A first region in which vertical field effect transistors are arranged two-dimensionally and periodically;
In a region other than the first region, the peripheral region of the semiconductor substrate,
A second region in which a field effect transistor having a source and drain layer formed in the semiconductor substrate and a gate portion formed so as to cover one end of each of the source and drain layers is disposed;
A semiconductor device, wherein the vertical field effect transistors are two-dimensionally arranged with a predetermined interval on the second region via an interlayer insulating film. A first semiconductor layer having a columnar shape is provided on a main surface side of the semiconductor substrate;
A gate electrode formed through a gate insulating film so as to surround a side surface of the first semiconductor layer, and a source and drain layer formed adjacent to the upper end portion and the lower end portion of the first semiconductor layer, respectively. A vertical field effect transistor
In a second region where a field effect transistor having a source and drain layer formed in the semiconductor substrate and a gate part formed to cover one end of each of the source and drain layers is disposed,
A semiconductor device, wherein the vertical field effect transistors are two-dimensionally arranged with a predetermined interval on the second region via an interlayer insulating film. The vertical field effect transistor formed on the second region is used as a capacitive element having the gate electrode as one electrode end, the semiconductor layer as the other electrode end, and the gate insulating film as a charge storage portion. The semiconductor device according to claim 4, wherein: The vertical field effect transistor formed on the second region is used as a resistance element having the source layer as one electrode end, the drain layer as the other electrode end, and the first semiconductor as a resistance layer. The semiconductor device according to claim 4, wherein: One end of the vertical field effect transistor formed on the second region is connected to a contact plug formed so as to fill a through hole formed through the interlayer insulating film with a polycrystalline silicon film. The semiconductor device according to claim 4, wherein: The diameter of the first semiconductor layer constituting the vertical field effect transistor formed on the second region is larger than the diameter of the first semiconductor layer constituting the vertical field effect transistor formed on the first region. A semiconductor device characterized by being large.

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