KR20010047252A - Method for fabricating contact of semiconductor device - Google Patents

Method for fabricating contact of semiconductor device Download PDF

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Publication number
KR20010047252A
KR20010047252A KR1019990051377A KR19990051377A KR20010047252A KR 20010047252 A KR20010047252 A KR 20010047252A KR 1019990051377 A KR1019990051377 A KR 1019990051377A KR 19990051377 A KR19990051377 A KR 19990051377A KR 20010047252 A KR20010047252 A KR 20010047252A
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South Korea
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contact hole
contact
insulating film
forming
semiconductor substrate
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KR1019990051377A
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Korean (ko)
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이영준
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박종섭
주식회사 하이닉스반도체
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Priority to KR1019990051377A priority Critical patent/KR20010047252A/en
Publication of KR20010047252A publication Critical patent/KR20010047252A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for forming a contact of a semiconductor device is provided to allow a reduction in contact resistance. CONSTITUTION: In the method, the first insulating layer(22) is formed on a semiconductor substrate(21), and the second insulating layer(23) is formed on the first insulating layer(22). Here the second insulating layer(23) has a lower wet-etch rate than the first insulating layer(22) has. Next, the second and first insulating layers(23,22) are selectively removed to form a contact hole, and then the first insulating layer(22) is selectively removed again by wet-etch to enlarge a lower part of the contact hole. Next, a barrier layer(25) is formed on entire surfaces including a surface of the contact hole, and a conductive plug(26) is then formed on the barrier layer(25) in the contact hole.

Description

반도체 소자의 콘택 형성방법{Method for fabricating contact of semiconductor device}Method for fabricating contact of semiconductor device

본 발명은 반도체 소자의 제조공정에 관한 것으로, 특히 콘택(Contact) 저항을 감소하는데 적당한 반도체 소자의 콘택 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing process of a semiconductor device, and more particularly to a method for forming a contact of a semiconductor device suitable for reducing contact resistance.

이하, 첨부된 도면을 참고하여 종래의 반도체 소자의 콘택 형성방법을 설명하면 다음과 같다.Hereinafter, a method for forming a contact of a conventional semiconductor device will be described with reference to the accompanying drawings.

도 1a 내지 도 1c는 종래의 반도체 소자의 콘택 형성방법을 나타낸 공정단면도이다.1A to 1C are cross-sectional views illustrating a method for forming a contact of a conventional semiconductor device.

도 1a에 도시한 바와 같이, 반도체 기판(11)상에 절연막(12)을 형성하고, 포토 및 식각공정을 통하여 상기 반도체 기판(11)의 표면이 소정부분 노출되도록 상기 절연막(12)을 선택적으로 제거하여 콘택홀(13)을 형성한다.As shown in FIG. 1A, an insulating film 12 is formed on the semiconductor substrate 11, and the insulating film 12 is selectively exposed to expose a predetermined portion of the surface of the semiconductor substrate 11 through photo and etching processes. To form a contact hole 13.

도 1b에 도시한 바와 같이, 상기 노출된 반도체 기판(11)의 표면에 형성된 자연산화막(도시되지 않음)을 제거하기 위하여 반도체 기판(11)에 습식식각(Wet Etch)을 실시한다.As shown in FIG. 1B, wet etching is performed on the semiconductor substrate 11 to remove the native oxide film (not shown) formed on the exposed surface of the semiconductor substrate 11.

이때 상기 콘택홀(13)의 폭이 넓어진다.At this time, the width of the contact hole 13 is widened.

이어, 상기 콘택홀(13)을 포함한 반도체 기판(11)의 전면에 스퍼터(Sputter)법으로 티타늄/질화 티타늄(Ti/TiN)막 등과 같은 베리어(Barrier)막(14)을 형성한다.Subsequently, a barrier film 14 such as a titanium / titanium nitride (Ti / TiN) film or the like is formed on the entire surface of the semiconductor substrate 11 including the contact hole 13 by a sputter method.

도 1c에 도시한 바와 같이, 상기 베리어막(14)을 포함한 반도체 기판(11)의 전면에 티타늄(Ti), 실리콘(Si), 텅스텐(W)과 같은 금속막을 형성한 후, 상기 콘택홀(13)의 내부에만 남도록 전면에 에치백 공정을 실시하여 금속 플러그(15)를 형성한다.As shown in FIG. 1C, a metal film such as titanium (Ti), silicon (Si), and tungsten (W) is formed on the entire surface of the semiconductor substrate 11 including the barrier film 14. The metal plug 15 is formed by performing an etch back process on the front surface so that only the inside of the 13) remains.

그러나 상기와 같은 종래의 반도체 소자의 콘택 형성방법에 있어서 다음과 같은 문제점이 있었다.However, the above-described conventional method for forming a contact of a semiconductor device has the following problems.

첫째, 소자가 집적화되면서 요구되는 콘택 사이즈가 감소하게 됨에 따라 제한된 콘택 사이즈에서는 콘택 저항이 증가한다.First, as the integration of devices reduces the required contact size, the contact resistance increases at limited contact sizes.

둘째, 요구되는 콘택 저항을 만족시키기 위하여 콘택 사이즈를 증가시켜야 하며, 이 때문에 소자의 집적화에 제약을 받는다.Second, the contact size must be increased to satisfy the required contact resistance, which limits the integration of the device.

본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출한 것으로 제한된 콘택홀의 사이즈에서 콘택 저항을 줄이도록 한 반도체 소자의 콘택 형성방법을 제공하는데 그 목적이 있다.An object of the present invention is to provide a method for forming a contact of a semiconductor device to reduce the contact resistance in the size of the contact hole limited to solve the conventional problems as described above.

도 1a 내지 도 1c는 종래의 반도체 소자의 콘택 형성방법을 나타낸 공정단면도1A to 1C are cross-sectional views illustrating a method for forming a contact of a conventional semiconductor device.

도 2a 내지 도 2d는 본 발명에 의한 반도체 소자의 콘택 형성방법을 나타낸 공정단면도2A to 2D are cross-sectional views illustrating a method of forming a contact for a semiconductor device according to the present invention.

도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings

21 : 반도체 기판 22 : 제 1 절연막21 semiconductor substrate 22 first insulating film

23 : 제 2 절연막 24 : 콘택홀23: second insulating film 24: contact hole

25 : 베리어막 26 : 금속 플러그25: barrier film 26: metal plug

상기와 같은 목적을 달성하기 위한 본 발명에 의한 반도체 소자의 콘택 형성방법은 반도체 기판상에 제 1 절연막을 형성하는 단계와, 상기 제 1 절연막상에 제 1 절연막보다 식각속도가 느린 제 2 절연막을 형성하는 단계와, 상기 반도체 기판의 표면이 소정부분 노출되도록 제 2 절연막 및 제 1 절연막을 선택적으로 제거하여 콘택홀을 형성하는 단계와, 상기 제 1 절연막을 선택적으로 제거하여 콘택홀의 하부면적을 넓히는 단계와, 상기 콘택홀을 포함한 전면에 베리어막을 형성하는 단계와, 상기 콘택홀내부의 베리어막상에 도전성 플러그를 형성하는 단계를 포함하여 형성함을 특징으로 한다.The contact forming method of the semiconductor device according to the present invention for achieving the above object comprises the steps of forming a first insulating film on the semiconductor substrate, and a second insulating film having a lower etching speed than the first insulating film on the first insulating film Forming a contact hole by selectively removing the second insulating film and the first insulating film so as to expose a predetermined portion of the surface of the semiconductor substrate, and selectively removing the first insulating film to widen the lower area of the contact hole. And forming a barrier film on the entire surface including the contact hole, and forming a conductive plug on the barrier film inside the contact hole.

이하, 첨부된 도면을 참고하여 본 발명에 의한 반도체 소자의 콘택 형성방법을 상세히 설명하면 다음과 같다.Hereinafter, a method for forming a contact of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2d는 본 발명에 의한 반도체 소자의 콘택 형성방법을 나타낸 공정단면도이다.2A to 2D are cross-sectional views illustrating a method of forming a contact for a semiconductor device according to the present invention.

도 2a에 도시한 바와 같이, 반도체 기판(21)상에 특정화학물질에 대한 습식식각 속도가 상대적으로 빠른 제 1 절연막(22)을 형성하고, 상기 제 1 절연막(22)상에 제 1 절연막(22)보다 특정화학물질에 대한 습식식각 속도가 느린 제 2 절연막(23)을 형성한다.As shown in FIG. 2A, a first insulating film 22 having a relatively high wet etching rate with respect to a specific chemical is formed on the semiconductor substrate 21, and a first insulating film is formed on the first insulating film 22. The second insulating film 23 having a slower wet etching rate with respect to a specific chemical is formed.

이어, 상기 제 1, 제 2 절연막(22,23)이 형성된 반도체 기판(21)에 포토 및 식각공정을 통하여 상기 반도체 기판(21)의 표면이 소정부분 노출되도록 제 2 절연막(23)과 제 1 절연막(22)을 선택적으로 제거하여 콘택홀(24)을 형성한다.Subsequently, the surface of the semiconductor substrate 21 is exposed to a predetermined portion through the photolithography and etching processes on the semiconductor substrate 21 on which the first and second insulating layers 22 and 23 are formed. The insulating film 22 is selectively removed to form the contact hole 24.

도 2b에 도시한 바와 같이, 상기 반도체 기판(21)의 표면에 형성된 자연산화막(도시되지 않음)을 제거하기 위하여 반도체 기판(21)에 습식식각을 실시한다.As shown in FIG. 2B, a wet etching is performed on the semiconductor substrate 21 to remove a natural oxide film (not shown) formed on the surface of the semiconductor substrate 21.

이어, 상기 반도체 기판(21)에 습식식각을 실시하여 제 1 절연막(22)을 선택적으로 제거한다.Subsequently, the first insulating layer 22 is selectively removed by performing wet etching on the semiconductor substrate 21.

이때 상기 제 2 절연막(23)과 제 1 절연막(22)은 습식식각 차이로 인하여 제 2 절연막(23)은 거의 식각되지 않는 반면에 제 1 절연막(22)의 식각량은 많아 콘택홀(24) 하부의 면적이 넓어진다.At this time, the second insulating film 23 and the first insulating film 22 are hardly etched due to the difference in wet etching, while the etching amount of the first insulating film 22 is large, so that the contact hole 24 is formed. The lower area becomes wider.

도 2c에 도시한 바와 같이, 상기 콘택홀(24)을 포함한 반도체 기판(21)의 전면에 단차 피복성(Step Coverage)이 좋은 Ti/TiN 등과 같은 베리어막(25)을 CVD법으로 형성한다.As shown in FIG. 2C, a barrier film 25 such as Ti / TiN having good step coverage is formed on the entire surface of the semiconductor substrate 21 including the contact hole 24 by CVD.

즉, 상기 베리어막(25)은 티타늄(Ti), 실리콘(Si), 텅스텐(W)중에나 하나를 사용하거나 그 화합물을 사용한다.That is, the barrier layer 25 may be made of one of titanium (Ti), silicon (Si), tungsten (W), or a compound thereof.

도 2d에 도시한 바와 같이, 상기 베리어막(25)상에 티타늄(Ti), 실리콘(Si), 텅스텐(W) 혹은 그 화합물의 금속막을 형성한 후, 상기 콘택홀(24)의 내부에만 남도록 전면에 에치백 공정을 실시하여 콘택홀(24)의 내부에 금속 플러그(26)를 형성한다.As shown in FIG. 2D, after forming a metal film of titanium (Ti), silicon (Si), tungsten (W) or a compound thereof on the barrier film 25, the metal film remains only inside the contact hole 24. An etch back process is performed on the entire surface to form a metal plug 26 in the contact hole 24.

여기서 상기 금속 플러그(26)는 제 1 절연막(22)이 선택적으로 제거되어 콘택홀(24)의 넓어져 있기 때문에 종래 보다 반도체 기판(21)과 금속 플러그(26)가 콘택되는 부분이 넓어지기 때문에 콘택 저항을 줄일 수 있다.In this case, since the first insulating layer 22 is selectively removed and the contact hole 24 is widened, the metal plug 26 is wider in contact with the semiconductor substrate 21 and the metal plug 26 than in the prior art. Contact resistance can be reduced.

이상에서 설명한 바와 같이 본 발명에 의한 반도체 소자의 콘택 형성방법은 다음과 같은 효과가 있다.As described above, the method for forming a contact of a semiconductor device according to the present invention has the following effects.

첫째, 종래와 동일한 콘택홀의 사이즈에서 그 하부의 콘택부분의 면적을 넓힘으로서 콘택 저항값을 줄일 수 있다.First, the contact resistance value can be reduced by widening the area of the lower contact portion at the same size of the contact hole as in the prior art.

둘째, 종래의 동일한 콘택 저항 값을 갖는 소자 형성시 보다 작은 콘택홀을 형성할 수 있으므로 소자를 집적화할 수 있다.Second, since a smaller contact hole can be formed when a device having the same contact resistance value is conventionally formed, the device can be integrated.

Claims (3)

반도체 기판상에 제 1 절연막을 형성하는 단계;Forming a first insulating film on the semiconductor substrate; 상기 제 1 절연막상에 제 1 절연막보다 식각속도가 느린 제 2 절연막을 형성하는 단계;Forming a second insulating film on the first insulating film, the etching speed of which is lower than that of the first insulating film; 상기 반도체 기판의 표면이 소정부분 노출되도록 제 2 절연막 및 제 1 절연막을 선택적으로 제거하여 콘택홀을 형성하는 단계;Forming a contact hole by selectively removing the second insulating film and the first insulating film so that the surface of the semiconductor substrate is partially exposed; 상기 제 1 절연막을 선택적으로 제거하여 콘택홀의 하부면적을 넓히는 단계;Selectively removing the first insulating layer to widen the lower area of the contact hole; 상기 콘택홀을 포함한 전면에 베리어막을 형성하는 단계;Forming a barrier film on the entire surface including the contact hole; 상기 콘택홀내부의 베리어막상에 도전성 플러그를 형성하는 단계를 포함하여 형성함을 특징으로 하는 반도체 소자의 콘택 형성방법.And forming a conductive plug on the barrier film inside the contact hole. 제 1 항에 있어서, 상기 베리어막은 티타늄, 실리콘, 텅스텐 중에 그 하나로 형성하거나 그 화합물로 형성하는 것을 특징으로 하는 반도체 소자의 콘택 형성방법.The method of claim 1, wherein the barrier layer is formed of one of titanium, silicon, and tungsten or a compound thereof. 제 1 항에 있어서, 상기 도전성 플러그는 티타늄, 실리콘, 텅스텐 중의 하나로 형성하거나 그 화합물의 금속막으로 형성하는 것을 특징으로 하는 반도체 소자의 콘택 형성방법.The method of claim 1, wherein the conductive plug is formed of one of titanium, silicon, and tungsten, or a metal film of a compound thereof.
KR1019990051377A 1999-11-18 1999-11-18 Method for fabricating contact of semiconductor device KR20010047252A (en)

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