KR20010041519A - 브리지에서의 성능 최적화를 위한 트리거 포인트 - Google Patents

브리지에서의 성능 최적화를 위한 트리거 포인트 Download PDF

Info

Publication number
KR20010041519A
KR20010041519A KR1020007009689A KR20007009689A KR20010041519A KR 20010041519 A KR20010041519 A KR 20010041519A KR 1020007009689 A KR1020007009689 A KR 1020007009689A KR 20007009689 A KR20007009689 A KR 20007009689A KR 20010041519 A KR20010041519 A KR 20010041519A
Authority
KR
South Korea
Prior art keywords
bridge
bus
queue
data
target
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
KR1020007009689A
Other languages
English (en)
Korean (ko)
Inventor
데이비스베리알.
에스칸데리닉지.
Original Assignee
피터 엔. 데트킨
인텔 코오퍼레이션
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 피터 엔. 데트킨, 인텔 코오퍼레이션 filed Critical 피터 엔. 데트킨
Publication of KR20010041519A publication Critical patent/KR20010041519A/ko
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
    • G06F13/4054—Coupling between buses using bus bridges where the bridge performs a synchronising function where the function is bus cycle extension, e.g. to meet the timing requirements of the target bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Bus Control (AREA)
KR1020007009689A 1998-03-04 1999-02-26 브리지에서의 성능 최적화를 위한 트리거 포인트 Ceased KR20010041519A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US9/034,624 1998-03-04
US09/034,624 US6298407B1 (en) 1998-03-04 1998-03-04 Trigger points for performance optimization in bus-to-bus bridges
PCT/US1999/004234 WO1999045470A2 (en) 1998-03-04 1999-02-26 Trigger points for performance optimization in bridges

Publications (1)

Publication Number Publication Date
KR20010041519A true KR20010041519A (ko) 2001-05-25

Family

ID=21877567

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020007009689A Ceased KR20010041519A (ko) 1998-03-04 1999-02-26 브리지에서의 성능 최적화를 위한 트리거 포인트

Country Status (6)

Country Link
US (1) US6298407B1 (enExample)
JP (1) JP2002506250A (enExample)
KR (1) KR20010041519A (enExample)
AU (1) AU2793599A (enExample)
DE (1) DE19983026B4 (enExample)
WO (1) WO1999045470A2 (enExample)

Families Citing this family (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6584539B1 (en) * 1999-03-19 2003-06-24 Sony Corporation Method and system for message broadcast flow control on a bus bridge interconnect
US6581125B1 (en) * 1999-05-14 2003-06-17 Koninklijke Philips Electronics N.V. PCI bridge having latency inducing serial bus
US6625683B1 (en) * 1999-08-23 2003-09-23 Advanced Micro Devices, Inc. Automatic early PCI transaction retry
US6742074B2 (en) * 1999-08-31 2004-05-25 Micron Technology, Inc. Bus to system memory delayed read processing
US6801954B1 (en) * 2000-02-25 2004-10-05 Hewlett-Packard Development Company, L.P. Method and apparatus to concurrently operate on multiple data movement transactions in a disk array subsystem
US6807590B1 (en) * 2000-04-04 2004-10-19 Hewlett-Packard Development Company, L.P. Disconnecting a device on a cache line boundary in response to a write command
US6965939B2 (en) * 2001-01-05 2005-11-15 International Business Machines Corporation Method and apparatus for processing requests in a network data processing system based on a trust association between servers
US8041739B2 (en) * 2001-08-31 2011-10-18 Jinan Glasgow Automated system and method for patent drafting and technology assessment
JP2003108514A (ja) * 2001-10-01 2003-04-11 Matsushita Electric Ind Co Ltd バスブリッジ
ATE367610T1 (de) * 2001-12-07 2007-08-15 Renesas Technology Europ Ltd Busbrücke mit einem burst-übertragungsmodebus und einem einzel-übertragungsmodebus
US20040003164A1 (en) * 2002-06-27 2004-01-01 Patrick Boily PCI bridge and data transfer methods
US7103701B2 (en) * 2002-09-23 2006-09-05 Hewlett-Packard Development Company, L.P. Memory bus interface
US6950905B2 (en) * 2003-02-20 2005-09-27 Sun Microsystems, Inc. Write posting memory interface with block-based read-ahead mechanism
WO2004081803A1 (en) * 2003-03-12 2004-09-23 Koninklijke Philips Electronics N. V. Data processing device and method for transferring data
US8386648B1 (en) * 2003-06-26 2013-02-26 Nvidia Corporation Hardware support system for accelerated disk I/O
US8683132B1 (en) 2003-09-29 2014-03-25 Nvidia Corporation Memory controller for sequentially prefetching data for a processor of a computer system
US8356142B1 (en) 2003-11-12 2013-01-15 Nvidia Corporation Memory controller for non-sequentially prefetching data for a processor of a computer system
US8700808B2 (en) * 2003-12-01 2014-04-15 Nvidia Corporation Hardware support system for accelerated disk I/O
US7213094B2 (en) * 2004-02-17 2007-05-01 Intel Corporation Method and apparatus for managing buffers in PCI bridges
US8356143B1 (en) 2004-10-22 2013-01-15 NVIDIA Corporatin Prefetch mechanism for bus master memory access
US7593345B2 (en) * 2004-12-30 2009-09-22 Finisar Corporation Altering latency for network testing
US7487274B2 (en) * 2005-08-01 2009-02-03 Asic Architect, Inc. Method and apparatus for generating unique identification numbers for PCI express transactions with substantially increased performance
US7698493B2 (en) * 2005-08-31 2010-04-13 Ati Technologies, Inc. Methods and apparatus for translating write request messages in a computing system
JP4362135B2 (ja) * 2007-02-13 2009-11-11 富士通株式会社 データ転送装置およびデータ転送方法
WO2009028494A1 (ja) 2007-08-28 2009-03-05 Nikon Corporation 位置検出装置、位置検出方法、露光装置、およびデバイス製造方法
JP5112138B2 (ja) * 2008-03-28 2013-01-09 株式会社日立製作所 セッション管理方法、ストレージ装置、及び、計算機システム
US8356128B2 (en) * 2008-09-16 2013-01-15 Nvidia Corporation Method and system of reducing latencies associated with resource allocation by using multiple arbiters
US8370552B2 (en) * 2008-10-14 2013-02-05 Nvidia Corporation Priority based bus arbiters avoiding deadlock and starvation on buses that support retrying of transactions
US8698823B2 (en) 2009-04-08 2014-04-15 Nvidia Corporation System and method for deadlock-free pipelining
JP2011182314A (ja) * 2010-03-03 2011-09-15 Oki Semiconductor Co Ltd データ中継装置及び方法
US8566496B2 (en) * 2010-12-03 2013-10-22 Lsi Corporation Data prefetch in SAS expanders
US8677031B2 (en) 2011-03-31 2014-03-18 Intel Corporation Facilitating, at least in part, by circuitry, accessing of at least one controller command interface
JP5564019B2 (ja) * 2011-08-26 2014-07-30 株式会社東芝 ファイル転送装置およびその方法
US10425456B2 (en) 2017-11-29 2019-09-24 Bank Of America Corporation Request processing system using a splitting engine
US10419265B2 (en) 2017-11-29 2019-09-17 Bank Of America Corporation Request processing system using a combining engine
US11226910B2 (en) * 2019-03-04 2022-01-18 Qualcomm Incorporated Ticket based request flow control

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4727537A (en) * 1985-12-24 1988-02-23 American Telephone And Telegraph Company Flow control arrangement for the transmission of data packets to a communication network
US5117486A (en) * 1989-04-21 1992-05-26 International Business Machines Corp. Buffer for packetizing block of data with different sizes and rates received from first processor before transferring to second processor
US5101477A (en) * 1990-02-16 1992-03-31 International Business Machines Corp. System for high speed transfer of data frames between a channel and an input/output device with request and backup request count registers
JP3132509B2 (ja) * 1990-07-06 2001-02-05 富士通株式会社 データ受信処理装置
JP2798107B2 (ja) * 1992-04-15 1998-09-17 日本電気株式会社 データ転送方法
US5941964A (en) * 1992-05-21 1999-08-24 Intel Corporation Bridge buffer management by bridge interception of synchronization events
US5434872A (en) * 1992-07-28 1995-07-18 3Com Corporation Apparatus for automatic initiation of data transmission
US5546546A (en) * 1994-05-20 1996-08-13 Intel Corporation Method and apparatus for maintaining transaction ordering and arbitrating in a bus bridge
US5687316A (en) * 1994-07-29 1997-11-11 International Business Machines Corporation Communication apparatus and methods having P-MAC, I-MAC engines and buffer bypass for simultaneously transmitting multimedia and packet data
US5548730A (en) * 1994-09-20 1996-08-20 Intel Corporation Intelligent bus bridge for input/output subsystems in a computer system
JPH08272735A (ja) * 1995-03-29 1996-10-18 Fujitsu Ltd 情報処理装置
US5848249A (en) * 1995-06-15 1998-12-08 Intel Corporation Method and apparatus for enabling intelligent I/O subsystems using PCI I/O devices
JP3519182B2 (ja) * 1995-09-05 2004-04-12 株式会社日立製作所 情報処理システムおよびバスアービタならびにバス制御方法
US5828865A (en) * 1995-12-27 1998-10-27 Intel Corporation Dual mode bus bridge for interfacing a host bus and a personal computer interface bus
US6072781A (en) * 1996-10-22 2000-06-06 International Business Machines Corporation Multi-tasking adapter for parallel network applications

Also Published As

Publication number Publication date
WO1999045470A2 (en) 1999-09-10
AU2793599A (en) 1999-09-20
WO1999045470A3 (en) 2000-03-02
DE19983026T1 (de) 2001-02-22
JP2002506250A (ja) 2002-02-26
US6298407B1 (en) 2001-10-02
DE19983026B4 (de) 2010-12-23

Similar Documents

Publication Publication Date Title
KR20010041519A (ko) 브리지에서의 성능 최적화를 위한 트리거 포인트
US5579530A (en) Method and apparatus for dynamically allocating access time to a resource shared between a peripheral bus and a host bus by dynamically controlling the size of burst data transfers on the peripheral bus
US5884050A (en) Mechanism for high bandwidth DMA transfers in a PCI environment
US6170030B1 (en) Method and apparatus for restreaming data that has been queued in a bus bridging device
US6336150B1 (en) Apparatus and method for enhancing data transfer rates using transfer control blocks
US7865652B2 (en) Power control by a multi-port bridge device
US6148359A (en) Bus-to-bus bridge in computer system, with fast burst memory range
US5740466A (en) Flexible processor-driven SCSI controller with buffer memory and local processor memory coupled via separate buses
US6324597B2 (en) Host controller interface descriptor fetching unit
US5870567A (en) Delayed transaction protocol for computer system bus
US6460108B1 (en) Low cost data streaming mechanism
US6092141A (en) Selective data read-ahead in bus-to-bus bridge architecture
US6286074B1 (en) Method and system for reading prefetched data across a bridge system
US20050114559A1 (en) Method for efficiently processing DMA transactions
US5269005A (en) Method and apparatus for transferring data within a computer system
US6477610B1 (en) Reordering responses on a data bus based on size of response
US6256684B1 (en) System for transferring data in high speed between host computer and peripheral device utilizing peripheral interface with accelerated mode
JPS6122333B2 (enExample)
US5416907A (en) Method and apparatus for transferring data processing data transfer sizes
US6631437B1 (en) Method and apparatus for promoting memory read commands
US6782463B2 (en) Shared memory array
US6425023B1 (en) Method and system for gathering and buffering sequential data for a transaction comprising multiple data access requests
US6532507B1 (en) Digital signal processor and method for prioritized access by multiple core processors to shared device
US6269102B1 (en) Bus control device
JP2001282631A (ja) 書き込みデータの破壊を制限する方法及びシステムとｐｃｉバス・システム

Legal Events

Date Code Title Description
A201 Request for examination
PA0105 International application

Patent event date: 20000901

Patent event code: PA01051R01D

Comment text: International Patent Application

PA0201 Request for examination
PG1501 Laying open of application
E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

Comment text: Notification of reason for refusal

Patent event date: 20020730

Patent event code: PE09021S01D

E601 Decision to refuse application
PE0601 Decision on rejection of patent

Patent event date: 20030422

Comment text: Decision to Refuse Application

Patent event code: PE06012S01D

Patent event date: 20020730

Comment text: Notification of reason for refusal

Patent event code: PE06011S01I

J201 Request for trial against refusal decision
PJ0201 Trial against decision of rejection

Patent event date: 20030721

Comment text: Request for Trial against Decision on Refusal

Patent event code: PJ02012R01D

Patent event date: 20030422

Comment text: Decision to Refuse Application

Patent event code: PJ02011S01I

Appeal kind category: Appeal against decision to decline refusal

Decision date: 20050629

Appeal identifier: 2003101002837

Request date: 20030721

J301 Trial decision

Free format text: TRIAL DECISION FOR APPEAL AGAINST DECISION TO DECLINE REFUSAL REQUESTED 20030721

Effective date: 20050629

PJ1301 Trial decision

Patent event code: PJ13011S01D

Patent event date: 20050629

Comment text: Trial Decision on Objection to Decision on Refusal

Appeal kind category: Appeal against decision to decline refusal

Request date: 20030721

Decision date: 20050629

Appeal identifier: 2003101002837